CN104638004B

CN104638004B - The structure of super junction MOSFET element

Info

Publication number: CN104638004B
Application number: CN201310574061.4A
Authority: CN
Inventors: 刘继全
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2013-11-15
Filing date: 2013-11-15
Publication date: 2018-04-17
Anticipated expiration: 2033-11-15
Also published as: CN104638004A

Abstract

The invention discloses a kind of structure of super junction MOSFET element, width of the width of its first semiconductor layer of active area and the second semiconductor layer than S1, the first semiconductor layer of termination environment and the second semiconductor layer meets condition than the doping concentration n of the second semiconductor layer of the doping concentration m of the first semiconductor layer of S2, active area and termination environment, active area and termination environment：0<1 S1m/n≤0.1 and 0.1≤1 S2m/n<0；Or 0.1≤1 S1m/n<0 and 0<1‑S2m/n≤0.1.The present invention carries out reasonable design by the width ratio and doping concentration ratio of the first semiconductor layer to active area and termination environment and the second semiconductor layer, make the breakdown voltage distribution of active area and termination environment in certain disparity range, the very poor of breakdown voltage is reduced, improves the uniformity of breakdown voltage and the uniformity of super junction MOSFET element.

Description

The structure of super junction MOSFET element

Technical field

The present invention relates to IC manufacturing field, more particularly to the structure of super junction MOSFET element.

Background technology

VDMOSFET（Vertical double-diffused MOS transistor）Electric conduction can be reduced using the thickness that drain terminal drift region is thinned Resistance, however, the thickness of drain terminal drift region, which is thinned, will reduce the breakdown voltage of device, therefore in VDMOS, improves hitting for device It is conflict that voltage, which is worn, with the conducting resistance for reducing device.

Super junction MOSFET employs new structure of voltage-sustaining layer, thin using a series of p-types being alternately arranged and N-type semiconductor Layer, p-type, N-type region are exhausted, realize that electric charge mutually compensates for, under relatively low backward voltage so that p-type, N-type region are highly doped High breakdown voltage can be realized under concentration, can thus obtain low on-resistance and high-breakdown-voltage at the same time, breaks traditional work( The theoretical limit of rate MOSFET.

But the stability control of the doping concentration of super junction MOSFET is relatively difficult.Under normal conditions, device is active Area is consistent with the P/N width ratio of termination environment, and active area is also consistent with the breakdown voltage distribution of termination environment（See Fig. 1）, device hits Wear voltage and depend on the breakdown voltage of one of them, be t3 to t1, the fluctuation that this causes punch through voltage is bigger, device it is steady It is qualitative poor.

The content of the invention

The technical problem to be solved in the present invention is to provide a kind of structure of super junction MOSFET element, it can improve breakdown The uniformity of voltage, reduces the very poor of breakdown voltage.

In order to solve the above technical problems, the structure of the super junction MOSFET element of the present invention, its first semiconductor of active area Width ratio S2, active area of the width than S1, the first semiconductor layer of termination environment and the second semiconductor layer of layer and the second semiconductor layer The second semiconductor layer doped concentration n of the first semiconductor layer doped concentration m, active area and termination environment with termination environment, meet bar Part：0<1-S1m/n≤0.1 and -0.1≤1-S2m/n<0；Or -0.1≤1-S1m/n<0 and 0<1-S2m/n≤0.1.

The present invention passes through the first semiconductor layer to active area and termination environment and the width ratio of the second semiconductor layer and doping Concentration ratio carries out reasonable design, makes the breakdown voltage distribution of active area and the breakdown voltage distribution of termination environment in certain difference In the range of, the very poor of breakdown voltage is reduced, improves the uniformity of breakdown voltage and the uniformity of super junction MOSFET element.

Brief description of the drawings

Fig. 1 is the active area and termination environment breakdown voltage distribution figure of conventional Super junction structure.

Fig. 2-5 is the formation process flow diagram of the super-junction structures of the embodiment of the present invention.Wherein, Fig. 5 is the present invention The schematic cross-section for the super-junction structures that embodiment makes.

Fig. 6 is the active area and termination environment breakdown voltage distribution curve map of the super-junction structures of the embodiment of the present invention.

The reference numerals are as follows in figure：

1：Semiconductor base

2：First semiconductor layer

3：Second semiconductor layer

4：First electrode

5：Second electrode

6：Source area

7：Base region

8：Before-metal medium layer

9：Grid

10：Gate dielectric layer

Embodiment

To have and more specifically understanding to technology contents, feature and effect of the present invention, in conjunction with embodiment illustrated, in detail State as follows：

Refer to shown in Fig. 2-5, super junction MOSFET element of the invention, its specific manufacturing process steps is：

Step 1, the first semiconductor layer that a layer thickness is 10~100 microns is grown on a semiconductor substrate, such as Fig. 2 institutes Show, and grow a layer dielectric on the first semiconductor layer（It is not drawn into figure）.

First semiconductor layer and semiconductor base have the first doping type.Typical first semiconductor layer is outside N-type silicon Prolong layer, typical semiconductor base is N-type silicon base.The doping concentration of first semiconductor layer is set as m.The load of semiconductor base Flow sub- concentration and be more than the first semiconductor layer.

Deielectric-coating is at least one of silica, silicon nitride or silicon oxynitride.

Step 2, with photoetching and dry etching method, groove is etched inside the first semiconductor layer, as shown in Figure 3.

The width of groove is 1.0~10 microns, and depth is 8~90 microns, and spacing is 1.0~20 microns.

Groove is distributed in active area and termination environment.The width and depth of active area and the groove of termination environment can be identical, Can be different, but trench spacing differs.The ratio between width of the spacing of the groove of active area and groove is set as S1 by us, will The ratio between the spacing of termination environment groove and the width of groove are set as S2.

Step 3, with selective silicon epitaxy technique, the second semiconductor layer is filled in portion in the trench, then uses chemical mechanical grinding Technique planarizes the top of the groove, as shown in Figure 4.

Second semiconductor layer has the second doping type（First, second doping type is on the contrary, for example the first doping type is N-type, then the second doping type is p-type；First doping type is p-type, then the second doping type is N-type）.Typical the second half lead Body layer is P-type silicon epitaxial layer.The doping concentration of second semiconductor layer is set as n.

Step 4, with conventional MOSFET techniques formed base region, source area, gate dielectric layer, grid, before-metal medium layer, Second electrode, semiconductor base are thinned and back side first electrode is formed etc., as shown in Figure 5.

In order to obtain preferable BV uniformities, reduce the very poor of device, the present invention to active area and termination environment the first half The width of conductor layer and the second semiconductor layer ratio（S1、S2）And doping concentration（m、n）Designed, S1, S2, m, n need full Foot：

0<1-S1m/n≤0.1, and -0.1≤1-S2m/n<0；

Or -0.1≤1-S1m/n<0, and 0<1-S2m/n≤0.1.

The derivation of above-mentioned formula is as follows：

Setting Fig. 5 in the width of spaced first semiconductor layer of active area and the second semiconductor layer be respectively a1 and The width of b1, spaced first semiconductor layer in termination environment and the second semiconductor layer is respectively a2 and b2, then：

S1=a1/b1

S2=a2/b2

When the difference of the first semiconductor layer and the carrier total amount of the second semiconductor layer accounts for the second semiconductor layer carrier total amount Ratio when within ± 10%, breakdown voltage change unobvious, but when this ratio more than ± 10% when, BV declines rapidly, therefore, This ratio should be controlled within ± 10%.It is possible thereby to release：

0<(nb1-ma1)/nb1≤0.1（Active area）

And -0.1≤(nb2-ma2)/nb2<0（Termination environment）

Or

-0.1≤(nb1-ma1)/nb1<0（Active area）

And 0<(nb2-ma2)/nb2≤0.1（Termination environment）

I.e.：

0<1-S1m/n≤0.1 and -0.1≤1-S2m/n<0；Or -0.1≤1-S1m/n<0 and 0<1-S2m/n≤0.1.

In this way, by the width ratio of the first semiconductor layer to active area and termination environment and the second semiconductor layer and adulterate dense Degree is than carrying out reasonable design, so that it may so that the breakdown voltage distribution of active area and the breakdown voltage distribution of termination environment are certain In disparity range, work as P（N）When the carrier concentration of column changes within the specific limits（As changed in Fig. 6 between X1-X2）, hit The peak for wearing voltage is exactly the crosspoint of two curves, and minimum point is exactly value of a certain bar curve in X1 or X2（Active area Or the minimum of the breakdown voltage of termination environment）, i.e. the fluctuation range of breakdown voltage is t2 to t1.It is obvious that t3-t1>T2-t1, Therefore, BV can substantially be reduced compared to the structure of conventional MOS FET, super junction MOSFET element structure of the invention（Breakdown potential Pressure）Excursion, improve the uniformity of device.

Claims

1. the structure of super junction MOSFET element, it is characterised in that the first semiconductor layer of active area of super junction MOSFET and Width ratio S2, active area and end of the width of second semiconductor layer than S1, the first semiconductor layer of termination environment and the second semiconductor layer The doping concentration n of the second semiconductor layer of doping concentration m, active area and termination environment of the first semiconductor layer of petiolarea, meets condition：0< 1-S1m/n≤0.1 and -0.1≤1-S2m/n<0；Or -0.1≤1-S1m/n<0 and 0<1-S2m/n≤0.1.