CN117832277A - Silicon carbide MOSFET device and preparation method thereof - Google Patents
Silicon carbide MOSFET device and preparation method thereof Download PDFInfo
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- CN117832277A CN117832277A CN202410008588.9A CN202410008588A CN117832277A CN 117832277 A CN117832277 A CN 117832277A CN 202410008588 A CN202410008588 A CN 202410008588A CN 117832277 A CN117832277 A CN 117832277A
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 85
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 84
- 238000002360 preparation method Methods 0.000 title abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 238000002513 implantation Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 3
- 239000007943 implant Substances 0.000 claims description 2
- 238000005530 etching Methods 0.000 description 8
- 238000002347 injection Methods 0.000 description 7
- 239000007924 injection Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 239000000969 carrier Substances 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- -1 aluminum ion Chemical class 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 230000003252 repetitive effect Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Abstract
The invention provides a silicon carbide MOSFET device and a preparation method thereof. The method comprises the following steps: providing a first conductivity type heavily doped silicon carbide substrate comprising a first surface and a second surface; forming a first conductive type lightly doped epitaxial layer on the first surface; forming a second conductivity type well region, a source region and a second conductivity type heavily doped contact region in the first conductivity type lightly doped epitaxial layer; forming a first conductive type lightly doped region on one side of the first conductive type lightly doped epitaxial layer away from the silicon carbide substrate; forming a gate oxide layer on a side of the lightly doped region of the first conductivity type, which is away from the silicon carbide substrate; forming a gate electrode on one side of the gate oxide layer away from the silicon carbide substrate; and forming a source region metal electrode on one side of the source region and the second conductive type heavily doped contact region, which is away from the silicon carbide substrate, and forming a drain region metal electrode on the second surface. The invention can improve the mobility of the current carrier in the channel when the MOSFET device is conducted, and improve the performance of the device.
Description
Technical Field
The invention relates to the technical field of silicon carbide devices, in particular to a silicon carbide MOSFET device and a preparation method thereof.
Background
Silicon carbide (SiC) has a wide forbidden band, high thermal conductivity, high breakdown voltage, and high electron saturation drift rate, and has good prospects in the fields of high power, high temperature, high frequency, and radiation-resistant electron power. Compared with Si MOSFETs of the same power class, the SiC MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) have the advantages of greatly reduced on-resistance and switching loss, applicability to higher operating frequencies and greatly improved high-temperature stability. The channel mobility is a key parameter of the performance of the SiC MOSFET device, and the improvement of the channel mobility can effectively reduce the starting voltage and the on-resistance, so that the loss under large current is reduced, and the conductivity of the device is improved. In other words, to increase the channel mobility of a SiC MOSFET device, the on-resistance when it is turned on needs to be reduced.
Fig. 1 shows a prior art planar gate SiC MOSFET device. Taking a planar gate SiC MOSFET device as an example, the overall on-resistance Ron when the SiC device is on will be described. As shown in fig. 1, the resistance when the SiC MOSFET is on is:
Ron＝Rs+Rch+RJFET+Repi+Rsubs+Rcd；
wherein Rs is a source resistor; rch is the channel resistance; the RJFET is a junction field effect transistor resistor; repi is the epitaxial layer resistance; rsubs is the substrate resistance; rcd is the drain contact resistance.
At present, the main material of the gate oxide layer of the SiC MOSFET is SiO generated by thermal oxidation 2 But SiC and SiO 2 The contact interface quality is poor, the channel resistance Rch of the device is large due to the interface state with high density and interface roughness, the channel mobility of SiC is low, and the development of the SiC power device is severely restricted.
Disclosure of Invention
Aiming at the problems in the prior art, the invention aims to provide a silicon carbide MOSFET and a preparation method thereof, wherein a layer of impurities is shallow injected on a silicon carbide substrate before a gate oxide layer is formed, so that the formed gate oxide layer has the same conductivity type as a channel, the mobility of carriers of the channel is further improved, the channel resistance is reduced, the total resistance of the silicon carbide MOSFET is reduced, and the performance of a device is improved.
The embodiment of the invention provides a preparation method of a silicon carbide MOSFET device, which comprises the following steps:
providing a first conductivity type heavily doped silicon carbide substrate, the first conductivity type heavily doped silicon carbide substrate comprising a first surface and a second surface;
forming a first conductive type lightly doped epitaxial layer on a first surface of the first conductive type heavily doped silicon carbide substrate;
forming a second conductivity type well region, a source region and a second conductivity type heavily doped contact region in the first conductivity type lightly doped epitaxial layer;
forming a first conductive type lightly doped region on one side of the first conductive type lightly doped epitaxial layer away from the first conductive type heavily doped silicon carbide substrate;
forming a gate oxide layer on one side of the first conductive type lightly doped region away from the first conductive type heavily doped silicon carbide substrate;
forming a gate electrode on one side of the gate oxide layer away from the first conductive type heavily doped silicon carbide substrate;
and forming a source region metal electrode on one side of the source region and the second conductive type heavily doped contact region, which is away from the first conductive type heavily doped silicon carbide substrate, and forming a drain region metal electrode on the second surface of the silicon carbide substrate.
In some embodiments, the lightly doped region of the first conductivity type is formed using an ion implantation process with an implantation energy of 20keV to 40keV.
In some embodiments, the first conductivity type lightly doped region is formed with an implant dose of less than 5×10 11 atm/cm 2 。
In some embodiments, the gate oxide layer is formed by a thermal oxidation process.
In some embodiments, forming a second conductivity type well region, a source region, and a second conductivity type heavily doped contact region within the first conductivity type lightly doped epitaxial layer comprises:
doping the lightly doped epitaxial layer of the first conductivity type to form a well region of the second conductivity type;
heavy doping is carried out in the second conduction type well region, and the second conduction type heavy doping contact region is formed;
and carrying out heavy doping in the second conductive type well region to form a source region.
In some embodiments, the depth of the heavily doped contact region of the second conductivity type is less than the depth of the well region, and a predetermined distance is provided between the inner wall of the source region and the inner wall of the well region.
In some embodiments, the lightly doped epitaxial layer of the first conductivity type is formed by an epitaxial process.
In some embodiments, the gate electrode is polysilicon.
In some embodiments, one of the first conductivity type and the second conductivity type is n-type conductivity and the other of the first conductivity type and the second conductivity type is P-type conductivity.
The embodiment of the invention provides a silicon carbide MOSFET device, which is prepared by the silicon carbide MOSFET preparation method.
The silicon carbide MOSFET device and the preparation method thereof have the following advantages:
forming a first conductive type lightly doped region on one surface of a silicon carbide epitaxial wafer, on which the gate oxide layer is formed, before forming the gate oxide layer; forming the gate oxide layer on the surface of the first conductive type lightly doped region; gate, source and drain metal electrodes are prepared to form the silicon carbide MOSFET device. According to the invention, the first conductive type lightly doped region is formed before the gate oxide layer is formed, so that the carrier concentration in the channel is increased, and when the device is conducted, the channel resistance is reduced, and the carrier mobility in the channel of the MOSFET device is further improved, and the device performance is improved.
Drawings
Other features, objects and advantages of the present invention will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the following drawings.
FIG. 1 is a schematic diagram of a prior art silicon carbide MOSFET;
FIG. 2 is a detailed flow chart of a method of making a silicon carbide MOSFE in accordance with one embodiment of the present invention;
fig. 3 to 10 are schematic structural views of a process of a silicon carbide MOSFET according to an embodiment of the present invention.
Reference numerals:
1. heavily doped silicon carbide substrate of first conductivity type
2. Lightly doped epitaxial layer of first conductivity type
3. Doped regions of the second conductivity type
4. Source region
5. Heavily doped region of the second conductivity type
6. Lightly doped region of first conductivity type
7. Gate oxide layer
8. Gate electrode
9. Source electrode metal electrode
10. Drain metal electrode
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus a repetitive description thereof will be omitted. "or", "or" in the specification may each mean "and" or ".
Furthermore, the drawings are merely schematic illustrations of the present invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software or in one or more hardware modules or integrated circuits or in different networks and/or processor devices and/or microcontroller devices.
The flow diagrams depicted in the figures are exemplary only and not necessarily all steps are included. For example, some steps may be decomposed, and some steps may be combined or partially combined, so that the order of actual execution may be changed according to actual situations.
The description modes "first conductivity type" and "second conductivity type" used herein refer to n-type conductivity (i.e., electron conductivity) or p-type conductivity (i.e., hole conductivity), which are different, specifically, the first conductivity type is n-type conductivity and the second conductivity type is p-type conductivity; or the second conductivity type is n-type conductivity and the first conductivity type is p-type conductivity.
FIG. 2 illustrates a specific flow chart for preparing a silicon carbide MOSFET in accordance with an embodiment of the present invention; fig. 3 to 10 are schematic process diagrams of a silicon carbide MOSFET device according to an embodiment of the present invention. The following describes in detail the method for manufacturing the silicon carbide MOSFET device according to the present invention with reference to fig. 2 to 10.
The preparation method of the silicon carbide MOSFET device comprises the following steps:
step S11: providing a first conductivity type heavily doped silicon carbide substrate 1;
step S12: a first conductive type lightly doped epitaxial layer 2 is formed on a first conductive type heavily doped silicon carbide substrate 1 through an epitaxial process to obtain a structural diagram as shown in fig. 3.
In some embodiments, the first conductivity type heavily doped silicon carbide substrate 1 may be an n+ type silicon carbide substrate, the first conductivity type lightly doped epitaxial layer 2 may be an N-type epitaxial layer, and the first conductivity type doped impurities include, but are not limited to, nitrogen (N) or phosphorus (P), etc., and the impurity types of the first conductivity type heavily doped silicon carbide substrate 1 and the first conductivity type lightly doped epitaxial layer 2 may be the same or different, which is not particularly limited herein.
The epitaxial layer may be formed by deposition, including, for example, but not limited to, chemical vapor deposition and the like, particularly metal organic vapor deposition and the like.
Step S20: as shown in fig. 5, the second conductivity type doped region 3 and the source region 4 are formed using an implantation process;
as shown in fig. 4, in some embodiments, the second conductive-type doped region 3 may be formed by ion implantation of the first conductive-type lightly doped epitaxial layer 2. In some embodiments, the second conductivity type doped region 3 may be a P-type doped region, also referred to as a P-well, doped with impurities including, but not limited to, aluminum (Al), boron (B), and the like.
In one embodiment, the specific process is as follows: first, a mask is deposited on the surface of the first conductive type lightly doped epitaxial layer 2, then a second conductive type doped region injection region is formed through photoetching and etching the mask, and aluminum ion selective injection is carried out on the second conductive type doped region injection region for a plurality of times, so that a second conductive type doped region 3, namely a P well, is formed as shown in fig. 4.
And depositing a mask on the second conductive type doped region 3, forming a source region injection region through photoetching and etching the mask, and performing nitrogen ions on the source region injection region for a plurality of times to form an N+ source region.
Step S30: a second-conductivity-type heavily doped region 5 is formed on the second-conductivity-type doped region 3, resulting in the structure shown in fig. 5.
In one embodiment, the specific process is as follows: masking the second conductive type doped region 3, forming a second conductive type heavily doped injection region by photoetching and etching the masking, and injecting Al ions into the second conductive type heavily doped injection region for a plurality of times to form a second conductive type heavily doped region 5.
Step S110: as shown in fig. 6, an implantation process is adopted to perform a light doping process on the surface of the current silicon carbide epitaxial wafer, so as to form a light doping region 6 of the first conductivity type, and the structure shown in fig. 7 is obtained.
In one embodiment, the implantation energy of 20-40 keV may be used in a specific process flow, and the implantation dose is 5×10 11 atm/cm 2 P ions of (c) are implanted into the surface of the silicon carbide epitaxial wafer. The first conductive type lightly doped region 6 can more effectively increase the carrier concentration of the channel surface region, thereby effectively improving the channel mobility and reducing the channel resistance.
Step S120: forming a gate oxide layer 7 on the surface of the first conductive type lightly doped region 6 to obtain a structure as shown in fig. 8;
in the embodiment of the present invention, the gate oxide layer 7 may be formed by thermal oxidation growth, for example, a dry oxidation method or a wet oxidation method, and specific oxidation conditions and parameters may be flexibly selected by those skilled in the art according to actual requirements, which are not described herein. A mask is provided on the gate oxide layer 7, and the gate oxide layer 7 is made to cover the channel by photolithography and etching. In the embodiment of the invention, the specific etching method can be at least one of wet etching and dry etching, for example, a mask with a pattern can be formed on the gate oxide layer, then the surface of the gate oxide layer which is not covered by the mask is etched, and the specific etching gas can be flexibly selected according to the specific components of the etching object.
In some embodiments, the material forming the gate oxide layer 7 may be silicon dioxide, silicon nitride, or the like.
Step S210: forming a gate electrode 8 on the surface of the gate oxide layer 7 to obtain a structure shown in fig. 9;
in some embodiments, the gate-forming material includes, but is not limited to, polysilicon or the like. Specifically, a polysilicon layer is deposited and grown on the surface of the epitaxial wafer by a chemical vapor deposition method. And forming a polysilicon gate by photoetching and etching the polysilicon remained on the surface of the gate oxide layer.
Step S310: forming a source metal electrode 9 in the source region 4 and the second conductive type heavily doped region 5 to obtain a structure shown in fig. 9;
the materials forming the source metal electrodes may each be a conventional metal electrode, including, but not limited to, at least one of copper, silver, and gold in some embodiments.
Step 320: a drain metal electrode 10 is formed on the back side of the first conductivity type heavily doped silicon carbide substrate 1 to obtain the structure shown in fig. 10, and the silicon carbide MOSFET device is completed.
The gate electrode and the metal electrode can be formed by a deposition method, such as chemical vapor deposition, physical vapor deposition and the like, and specific parameter conditions can be flexibly selected by a person skilled in the art according to needs, and are not described herein.
The embodiment of the invention also provides a silicon carbide MOSFET device which is manufactured by the manufacturing method, and the first conductive type lightly doped region is formed on the surface of the silicon carbide epitaxial wafer before the gate oxide layer is formed, so that the carrier concentration in a channel formed by the silicon carbide epitaxial wafer is increased, and when the device is conducted, the channel mobility of the device is improved, and the channel resistance is reduced.
In order to explore the progress of the silicon carbide MOSFET device provided by the embodiment of the invention, the applicant compares the threshold voltage Vth and the on-time resistance Ron of the silicon carbide MOSFET device provided by the embodiment of the invention with those of the existing silicon carbide MOSFET device, and finds that the threshold voltage and the on-resistance of the silicon carbide MOSFET device provided by the invention are obviously reduced compared with those of the existing MOSFET, the threshold voltage Vth of the silicon carbide MOSFET device provided by the invention is reduced to 74% of the existing MOSFET, and the on-resistance Ron is reduced to 93.9% of the existing MOSFET.
The silicon carbide MOSFET device and the preparation method thereof have the following advantages:
according to the preparation method of the silicon carbide MOSFET device, the first conductive type lightly doped region is formed on the surface of the silicon carbide epitaxial wafer before the gate oxide layer of the MOSFET device is formed, so that the concentration of carriers in a channel is improved, the concentration of carriers is increased when the MOSFET device is conducted, the channel resistance is reduced, the mobility of carriers in the channel is improved, and the device performance is improved.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
Claims (10)
1. A method of fabricating a silicon carbide MOSFET device, the method comprising:
providing a first conductivity type heavily doped silicon carbide substrate, the first conductivity type heavily doped silicon carbide substrate comprising a first surface and a second surface;
forming a first conductive type lightly doped epitaxial layer on a first surface of the first conductive type heavily doped silicon carbide substrate;
forming a second conductivity type well region, a source region and a second conductivity type heavily doped contact region in the first conductivity type lightly doped epitaxial layer;
forming a first conductive type lightly doped region on one side of the first conductive type lightly doped epitaxial layer away from the first conductive type heavily doped silicon carbide substrate;
forming a gate oxide layer on one side of the first conductive type lightly doped region away from the first conductive type heavily doped silicon carbide substrate;
forming a gate electrode on one side of the gate oxide layer away from the first conductive type heavily doped silicon carbide substrate;
and forming a source region metal electrode on one side of the source region and the second conductive type heavily doped contact region, which is away from the first conductive type heavily doped silicon carbide substrate, and forming a drain region metal electrode on the second surface of the silicon carbide substrate.
2. The method of manufacturing a silicon carbide MOSFET device according to claim 1, wherein the lightly doped region of the first conductivity type is formed by an ion implantation process with an implantation energy of 20keV to 40keV.
3. The method of manufacturing a silicon carbide MOSFET device according to claim 2, wherein forming the lightly doped region of the first conductivity type has an implant dose of less than 5 x 10 11 atm/cm 2 。
4. The method of fabricating a silicon carbide MOSFET device according to claim 1, wherein the gate oxide layer is formed by a thermal oxidation process.
5. The method of manufacturing a silicon carbide MOSFET device of claim 1, wherein forming a well region of a second conductivity type, a source region, and a heavily doped contact region of a second conductivity type within the lightly doped epitaxial layer of the first conductivity type comprises:
doping the lightly doped epitaxial layer of the first conductivity type to form a well region of the second conductivity type;
heavy doping is carried out in the second conduction type well region, and the second conduction type heavy doping contact region is formed;
and carrying out heavy doping in the second conductive type well region to form a source region.
6. The method of manufacturing a silicon carbide MOSFET device of claim 5, wherein the depth of the heavily doped contact region of the second conductivity type is less than the depth of the well region, and wherein a predetermined distance is provided between an inner wall of the source region and an inner wall of the well region.
7. The method of fabricating a silicon carbide MOSFET device of claim 1, wherein said lightly doped epitaxial layer of the first conductivity type is formed by an epitaxial process.
8. The method of fabricating a silicon carbide MOSFET device according to claim 1 wherein the gate electrode is polysilicon.
9. The method of manufacturing a silicon carbide MOSFET device of claim 8, wherein one of the first conductivity type and the second conductivity type is n-type conductivity and the other of the first conductivity type and the second conductivity type is P-type conductivity.
10. A silicon carbide MOSFET device prepared by the method of any one of claims 1 to 9.
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| CN202410008588.9A CN117832277A (en) | 2024-01-02 | 2024-01-02 | Silicon carbide MOSFET device and preparation method thereof |
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| CN202410008588.9A CN117832277A (en) | 2024-01-02 | 2024-01-02 | Silicon carbide MOSFET device and preparation method thereof |
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