CN111029398A - Groove type MOSFET power device and preparation method thereof - Google Patents
Groove type MOSFET power device and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 238000002161 passivation Methods 0.000 claims abstract description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 21
- 238000011049 filling Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 22
- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 230000008569 process Effects 0.000 claims description 14
- 238000000137 annealing Methods 0.000 claims description 13
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- 230000007480 spreading Effects 0.000 claims description 8
- 238000003892 spreading Methods 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 7
- -1 aluminum ions Chemical class 0.000 claims description 6
- 230000004888 barrier function Effects 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- 238000002347 injection Methods 0.000 claims description 5
- 239000007924 injection Substances 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 description 23
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 18
- 229910010271 silicon carbide Inorganic materials 0.000 description 18
- 229920005591 polysilicon Polymers 0.000 description 10
- 239000010408 film Substances 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 239000007789 gas Substances 0.000 description 6
- 230000005684 electric field Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000004134 energy conservation Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
Abstract
The invention discloses a trench type MOSFET power device and a preparation method thereof, wherein the preparation method comprises the following steps: providing a substrate, and forming an epitaxial layer on the surface of the substrate; forming a current expansion layer, a well region, an anode contact region, a source region and a heavily doped contact region in the epitaxial layer; forming a groove in the epitaxial layer, and forming a shielding region in the epitaxial layer below the bottom of the groove; forming a gate dielectric layer on the side wall and the bottom of the groove; filling a polycrystalline silicon layer in the groove; forming a passivation layer on the surface of the epitaxial layer; forming a source electrode window in the passivation layer, forming a source electrode ohmic contact layer in the source electrode window, and forming a drain electrode ohmic contact layer on the bottom surface of the substrate; forming a gate window in the passivation layer; a gate electrode, a source electrode and a drain electrode are separately prepared. According to the invention, the SBD structure is embedded into the groove type MOSFET device, so that the reverse conduction capability of the MOSFET device is improved, and the overall size and economic cost of the SiC power module are reduced.
Description
Technical Field
The invention relates to a semiconductor component manufacturing technology, in particular to a trench type MOSFET power device and a manufacturing method thereof.
Background
With the increasing increase of energy crisis and the increasing prominence of environmental problems, technologies with energy conservation and emission reduction as the core are emerging, and the technical field of improving the energy utilization rate by improving the existing power system is most concerned. Statistically, 60% to 70% of the electrical energy is used in low energy systems, where most of the energy is wasted in power conversion and power driving. A key role in improving power utilization efficiency is the power device, also known as a power electronic device. How to reduce the power consumption of power devices has become an important issue worldwide. In this context, silicon carbide devices, which have far superior performance to conventional silicon devices, are favored. SiC has a series of excellent characteristics such as a large forbidden band width, a high critical breakdown field strength, and a high thermal conductivity as a third-generation semiconductor material. The SiC power switch device can simultaneously realize excellent performances of high breakdown voltage, low on-resistance, high switching speed, easy heat dissipation and the like, has obvious competitiveness in the power electronic technology with high energy efficiency, high power and high temperature, and becomes a research hotspot of the current power semiconductor technology. The SiC device has higher breakdown voltage, high current density and high working frequency, has the advantages of high temperature resistance and radiation resistance, and is suitable for working under severe conditions.
In a conventional planar gate SiC MOSFET device, the on-resistance of the device increases due to the presence of a parasitic Junction Field Effect Transistor (JFET) structure. The groove type SiC MOSFET has no JFET area, the on-resistance of the device can be obviously reduced, and the side wall of the gate groove is the (11-20) crystal face of the SiC crystal, so that the higher channel carrier mobility can be realized, the on-current of the device is further improved, and the on-resistance of the device is reduced. However, due to the limitation of the turn-on voltage of the SiC PN junction, the trench SiC MOSFET device also has the problems of poor reverse conduction capability and long reverse recovery time, as with the planar gate. Therefore, when the SiC power switch module is assembled, a SiC SBD needs to be matched at the periphery of the SiC MOSFET device to improve the reverse conduction capability thereof, thereby increasing the overall size and economic cost of the power module.
Disclosure of Invention
The invention aims to provide a trench type MOSFET power device and a preparation method thereof, wherein an SBD structure is embedded in the trench type MOSFET device, the good conduction performance of the SBD is utilized, the reverse conduction capability of the MOSFET device is improved, the overall size and the economic cost of a SiC power module are reduced, and the miniaturization of an electronic power device is realized; in addition, the invention also utilizes the shielding region structure at the bottom of the groove, can reduce the electric field intensity in the gate oxide, avoid the breakdown of the gate oxide and improve the reliability of the gate oxide.
The technical solution for realizing the purpose of the invention is as follows: a preparation method of a trench type MOSFET power device comprises the following steps:
1) providing a heavily doped substrate of a first doping type, and forming a lightly doped epitaxial layer of the first doping type on the upper surface of the substrate;
2) forming a current extension layer of a first doping type in the epitaxial layer, forming a well region of a second doping type in the epitaxial layer, wherein the well region extends from the surface of the epitaxial layer to the upper surface of the current extension layer, forming an anode contact region embedded with an SBD structure in the epitaxial layer between the well regions of the second doping type, forming a heavily doped source region of the first doping type in the well region of the second doping type, and forming a heavily doped contact region of the second doping type in the well region of the second doping type;
3) forming a groove in the epitaxial layer, and forming a shielding region of a second doping type in the epitaxial layer below the bottom of the groove;
4) forming a gate dielectric layer on the side wall and the bottom of the groove obtained in the step 3);
5) filling a first doping type polycrystalline silicon layer in the groove with the gate dielectric layer obtained in the step 4);
6) forming a passivation layer on the surface of the epitaxial layer;
7) forming a source electrode window in the passivation layer, wherein the source electrode window exposes the source region, the anode contact region and the heavily doped contact region, a source electrode ohmic contact layer is formed in the source electrode window, and a drain electrode ohmic contact layer is formed on the bottom surface of the substrate;
8) forming a grid window in the passivation layer at a position corresponding to the polycrystalline silicon layer;
9) and forming a grid electrode in the grid window, forming a source electrode on the surface of the source ohmic contact layer, and forming a drain electrode on the surface of the drain ohmic contact layer.
Preferably, the first doping type is N-type, and the second doping type is P-type.
In another preferred embodiment, the first doping type is P-type, and the second doping type is N-type.
Preferably, in the step 1), before forming the epitaxial layer on the upper surface of the substrate, a step of forming a buffer layer on the upper surface of the substrate is further included, and the epitaxial layer is formed on the upper surface of the buffer layer.
Preferably, the step 3) of forming a trench in the epitaxial layer and forming a shielding region of the second doping type in the epitaxial layer below the bottom of the trench includes the following steps:
3-1) forming a first mask layer on the upper surface of the epitaxial layer;
3-2) coating photoresist on the upper surface of the first mask layer, and carrying out patterning treatment on the photoresist by adopting a photoetching process to form patterned photoresist;
3-3) simultaneously etching the first mask layer and the epitaxial layer according to the patterned photoresist to form the groove in the epitaxial layer;
3-4) removing the patterned photoresist and reserving the etched first mask layer;
3-5) forming an injection barrier layer on the surface of the etched first mask layer and the surface of the groove;
3-6) injecting aluminum ions into the surface of the injection barrier layer so as to form a shielding region of a second doping type in the epitaxial layer at the bottom of the groove;
3-7) removing the first mask layer and the implantation barrier layer.
Preferably, the step 4) of forming a gate dielectric layer on the sidewall and the bottom of the trench obtained by the step 3) includes the following steps:
4-1) forming a layer of film on the side wall and the bottom surface of the groove;
4-2) annealing the film to form the gate dielectric layer.
Preferably, the forming of the source ohmic contact layer and the drain ohmic contact layer in the step 7) includes:
7-1) depositing more than 2 metal layers which are sequentially stacked in the source window and on the surface of the bottom of the substrate respectively;
7-2) carrying out high-temperature annealing treatment on the deposited metal layer to form the source ohmic contact layer and the drain ohmic contact layer respectively.
The present invention also provides a trench MOSFET power device, comprising:
a heavily doped substrate of a first doping type;
a lightly doped epitaxial layer of a first doping type on an upper surface of the substrate;
a heavily doped current spreading layer of a first doping type located within the epitaxial layer;
the well region of the second doping type is positioned in the upper surface of the current extension layer extending from the surface of the epitaxial layer;
a heavily doped source region of a first doping type located in the well region;
a heavily doped contact region of a second doping type located in the well region;
an anode contact region embedded with an SBD structure is positioned in the epitaxial layer between the well regions;
a trench located within the epitaxial layer;
the shielding region of the second doping type is positioned in the epitaxial layer below the groove;
the gate dielectric layer is positioned on the side wall and the bottom surface of the groove;
a polycrystalline silicon layer filled on the surface of the gate dielectric layer in the groove;
the source ohmic contact layer is positioned on the upper surfaces of the heavily doped source region of the first doping type, the heavily doped contact region of the second doping type and the anode contact region embedded with the SBD structure;
the passivation layer is positioned on the upper surface of the epitaxial layer between the source ohmic contact layer and the grid electrode;
the drain electrode ohmic contact layer is positioned on the lower surface of the substrate;
the drain electrode is positioned on the lower surface of the drain ohmic contact layer;
the grid electrode is positioned on the upper surface of the polycrystalline silicon layer;
and the source electrode is positioned on the upper surface of the source ohmic contact layer.
Preferably, the trench MOSFET power device structure further comprises a buffer layer, and the buffer layer is located between the substrate and the epitaxial layer.
Preferably, the first doping type is N-type, and the second doping type is P-type.
In another preferred embodiment, the first doping type is P-type, and the second doping type is N-type.
Preferably, the length of the shielding region of the second doping type at the bottom of the trench is smaller than the width of the trench.
Compared with the prior art, the invention has the following remarkable advantages: (1) the invention optimizes the device structure, particularly embeds the SBD structure into the groove type silicon carbide MOSFET device, can utilize the good conduction performance of the SBD, improve the reverse conduction capability of the MOSFET device, reduce the overall size and economic cost of the SiC power module, and realize the miniaturization of the electronic power device; in addition, the invention also utilizes the shielding region structure at the bottom of the trench, can reduce the electric field intensity in the gate oxide, avoid the breakdown of the gate oxide and improve the reliability of the gate oxide; (2) the device structure and the preparation process are simple, the effect is obvious, and the device structure and the preparation method have wide application prospects in the novel MOSFET power device structure and the preparation method.
Drawings
Fig. 1 is a schematic flow chart of a method for manufacturing a trench MOSFET power device according to the present invention.
Fig. 2 is a schematic view of a lightly doped epitaxial layer with a first doping type formed on the upper surface of the substrate.
Fig. 3 is a schematic diagram of preparing a current spreading layer, a well region of a second doping type, an anode contact region, a heavily doped source region of a first doping type, and a heavily doped contact region of a second doping type.
Fig. 4 is a schematic diagram of forming trenches in an epitaxial layer.
Fig. 5 is a schematic diagram of a second doping type shielding region formed in the epitaxial layer under the bottom of the trench.
Fig. 6 is a schematic diagram of forming a gate dielectric layer.
Fig. 7 is a schematic view of filling a first doping type polysilicon layer in a trench having a gate dielectric layer.
Fig. 8 is a schematic diagram of forming a passivation layer.
FIG. 9 is a schematic view of forming a source window.
FIG. 10 is a schematic view of forming a source ohmic contact layer in the source window and a drain ohmic contact layer on the bottom surface of the substrate.
Fig. 11 is a schematic view of a gate window formed in a passivation layer at a location corresponding to a polysilicon layer.
Fig. 12 is a schematic view of forming a gate electrode, a source electrode, and a drain electrode.
Fig. 13 is a schematic cross-sectional structure diagram of the prepared MOSFET power device.
Reference symbol of element:
101 substrate
102 buffer layer
103 epitaxial layer
104 current spreading layer
105 well region
106 source region
107 heavily doped contact region
108 anode contact region
109 groove
110 shield region
111 gate dielectric layer
112 grid
113 passivation layer
114 source window
115 source ohmic contact layer
116 drain ohmic contact layer
117 gate window
118 gate electrode
119 source electrode
120 drain electrode
Detailed Description
The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will become apparent to those skilled in the art from the present disclosure.
Please refer to fig. 1 to 13. It should be understood that the structures, ratios, sizes, and the like shown in the drawings and described in the specification are only used for matching with the disclosure of the specification, so as to be understood and read by those skilled in the art, and are not used to limit the conditions under which the present invention can be implemented, so that the present invention has no technical significance, and any structural modification, ratio relationship change, or size adjustment should still fall within the scope of the present invention without affecting the efficacy and the achievable purpose of the present invention. In addition, the terms "upper", "lower", "left", "right", "middle" and "one" used in the present specification are for clarity of description, and are not intended to limit the scope of the present invention, and the relative relationship between the terms and the terms is not to be construed as a scope of the present invention.
Example 1
As shown in fig. 1 to fig. 13, the present invention provides a method for manufacturing a trench MOSFET power device, which at least comprises the following steps:
1) providing a heavily doped substrate 101 of a first doping type, and forming a lightly doped epitaxial layer 103 of the first doping type on the upper surface of the substrate;
2) forming a current extension layer 104 of a first doping type in the epitaxial layer 103, forming a well region 105 of a second doping type in the epitaxial layer, wherein the well region 105 of the second doping type extends from the surface of the epitaxial layer 103 to the upper surface of the current extension layer 104, forming an anode contact region 108 with an embedded SBD structure in the epitaxial layer 103 between the well regions 105 of the second doping type, forming a heavily doped source region 106 of the first doping type in the well region 105 of the second doping type, and forming a heavily doped contact region 107 of the second doping type in the well region 105 of the second doping type;
3) forming a trench 109 in the epitaxial layer 103, and forming a shielding region 110 of a second doping type in the epitaxial layer below the bottom of the trench 109;
4) forming a gate dielectric layer 111 on the side wall and the bottom of the trench 109 obtained in the step 3);
5) filling a first doping type polycrystalline silicon layer in the groove with the gate dielectric layer obtained in the step 4);
6) forming a passivation layer on the surface of the epitaxial layer;
7) forming a source electrode window in the passivation layer, wherein the source electrode window exposes the source region, the anode contact region and the heavily doped contact region, a source electrode ohmic contact layer is formed in the source electrode window, and a drain electrode ohmic contact layer is formed on the bottom surface of the substrate;
8) forming a grid window in the passivation layer at a position corresponding to the polycrystalline silicon layer;
9) and forming a grid electrode in the grid window, forming a source electrode on the surface of the source ohmic contact layer, and forming a drain electrode on the surface of the drain ohmic contact layer.
In step 1), please refer to step S01 in fig. 1 and fig. 2, a heavily doped substrate 101 of a first doping type is provided, and a lightly doped epitaxial layer 103 of the first doping type is formed on the upper surface of the substrate 101.
In this embodiment, the step 1) further includes a step of forming a buffer layer 102 between the substrate 101 and the epitaxial layer 103, and the epitaxial layer 103 is formed on an upper surface of the buffer layer 102.
It should be noted that the buffer layer 102 is used to help the epitaxial layer 103 and the substrate 101 to be better matched, so as to achieve the purposes of improving the device performance and prolonging the service life of the device. For example, the material of the buffer layer 102 is generally the same as the material of the epitaxial layer 103 and the material of the substrate 101, or at least the same as one of the material of the epitaxial layer 103 and the material of the substrate 101. Of course, in other examples, the material of the buffer layer 102, the material of the epitaxial layer 103, and the material of the substrate 101 may be different. Specifically, in this embodiment, the material of the buffer layer 102, the material of the epitaxial layer 103, and the material of the substrate 101 are the same.
As an example, the material of the epitaxial layer 103 and the material of the substrate 101 may be the same, for example, the material of the substrate 101 and the material of the epitaxial layer 103 are both one of 4H-SIC, 6H-SIC, 3C-SIC, or 15R-SIC; in this embodiment, the substrate 101 and the epitaxial layer 103 are both 4H-SIC; further, in the present embodiment, the crystal orientation of the material of the substrate 101 is deviated to a (11-20) direction (4 ± 0.5) ° tilt angle.
In other examples, the material of the epitaxial layer 103 may be different from the material of the substrate 101, for example, the material of the substrate 101 may be one of single crystal silicon, polysilicon, sapphire and gallium arsenide, and the material of the epitaxial layer 103 may be one of 4H-SIC, 6H-SIC, 3C-SIC or 15R-SIC.
In step 2), please refer to step S02 in fig. 1 and fig. 3, forming a current spreading layer 104 of a first doping type in the epitaxial layer 103, forming a well 105 of a second doping type in the epitaxial layer 103 extending from the surface of the epitaxial layer 103 to the upper surface of the current spreading layer 104, forming an anode contact region 108 with an embedded SBD structure in the epitaxial layer 103 between the well regions of the second doping type, forming a heavily doped source region 106 of the first doping type in the well 105 of the second doping type, and forming a heavily doped contact region 107 of the second doping type in the well 105 of the second doping type;
in step 3), referring to step S03 in fig. 1 and fig. 4 and 5, a trench 109 is formed in the epitaxial layer 103, and a shielding region 110 of the second doping type is formed in the epitaxial layer 103 under the bottom of the trench 109.
As an example, in the step 3), forming a trench 109 in the epitaxial layer 103, and forming a shielding region 110 of the second doping type in the epitaxial layer 103 under the bottom of the trench 109, includes the following steps:
3-1) forming a first mask layer on the upper surface of the epitaxial layer 103;
3-2) coating photoresist on the upper surface of the first mask layer, and carrying out patterning treatment on the photoresist by adopting a photoetching process to form patterned photoresist;
3-3) etching the first mask layer and the epitaxial layer 103 simultaneously according to the patterned photoresist to form the trench 109 in the epitaxial layer 103;
3-4) removing the patterned photoresist and reserving the etched first mask layer;
3-5) forming an injection masking layer on the surface of the etched first masking layer and the surface of the groove 109;
3-6) implanting aluminum ions into the surface of the implantation mask layer to form a shielding region 110 of the second doping type in the epitaxial layer 103 at the bottom of the trench 109;
3-7) removing the first mask layer and the implantation masking layer.
It should be noted that the first mask layer serves as an implantation blocking layer to block the implanted aluminum ions and prevent the epitaxial layer region outside the shielding region 110 from being implanted with aluminum ions.
As an example, in the step 3-1), the process of forming the first mask layer may be a chemical vapor deposition process, and the first mask layer may be polysilicon or SiO2，Si3N4And a film, further, in the present embodiment, a thickness of the first mask layerIs 1.0-1.5 um.
As an example, in the step 3-3), the first mask layer and the epitaxial layer 103 are simultaneously etched according to the patterned photoresist, so that the process for forming the trench 109 in the epitaxial layer 103 may be a plasma etching process, and further, an etching gas used in the plasma etching process adopted in this embodiment is SF6And O2The flow ratio of the mixed gas (2) is 5:1 to 3:1, and the total flow of the gas is 5 to 20 sccm.
In addition to the above etching gas, the etching gas may be CF4、O2、N2、SF6、CHF3、NF3、He、C2F6And the like.
As an example, in the step 3-6), aluminum ions are implanted into the surface of the implantation mask layer to form a shielding region 110 of the second doping type in the epitaxial layer 103 at the bottom of the trench 109, and the depth of the shielding region 110 is 0.1 to 0.3 um.
It should be noted that the shielding region 110 is used to shield the high electric field strength in the bulk of the device in the blocking state, so as to reduce the electric field in the gate oxide, especially in the gate oxide at the bottom of the trench 109, and prevent the gate oxide from breaking down.
As an example, the first doping type is N-type and the second doping type is P-type.
In other examples, the first doping type may be P-type and the second doping type may be N-type.
In step 4), referring to step S04 in fig. 1 and fig. 6, a gate dielectric layer 111 is formed on the surface of the structure obtained by the step 3).
As an example, forming the gate dielectric layer 111 includes the following steps:
4-1) forming a layer of film on the surface of the epitaxial layer 103;
4-2) annealing the film to form the gate dielectric layer 111.
As an example, the process used to form a thin film on the surface of the epitaxial layer 103 is thermal oxygenFurthermore, in the present embodiment, the formed film is a silicon dioxide film, the thickness of the silicon dioxide film is 50-80 nm, and the used thermal oxidation gas is O2The thermal oxidation temperature is 1200-1400 ℃.
As an example, the annealing process is at N2O or N2/O2The annealing treatment is carried out in an atmosphere, and further, in the embodiment, the annealing treatment temperature is 1200-1350 ℃, and the annealing treatment time is 30-60 min.
As an example, the gate dielectric layer 111 may also be made of Si3N4And non-metallic or non-metallic compounds such as polysilicon.
In other examples, the gate dielectric layer 111 may also be made of a high-k material, such as Al2O3、HfO2、HfAlO3And the like.
In step 5), referring to step S05 in fig. 1 and fig. 7, the trench 109 with the gate dielectric layer 111 obtained by the step 4) is filled with the polysilicon layer 112 of the first doping type.
As an example, the process of forming the polysilicon layer 112 of the first doping type may be an in-situ doping chemical vapor deposition process.
In step 6), referring to step S06 in fig. 1 and fig. 8, a passivation layer 113 is formed on the surface of the structure obtained by step 4).
It should be noted that the passivation layer 113 mainly functions to form a device surface protection film, overcome device surface defects, and enhance the stability and reliability of the device, and the passivation layer 113 may be made of silicon dioxide or nitride, for example.
In step 7), referring to step S07 in fig. 1 and fig. 9 and 10, a source window 114 is formed in the passivation layer 113, the source window 114 exposes the source region 106, the heavily doped contact region 107 and the anode contact region 108, a source ohmic contact layer 115 is formed in the source window 114, and a drain ohmic contact layer 116 is formed on the bottom surface of the substrate 101.
As an example, the method for forming the source window 114 in the passivation layer 113 in the step 7) may be dry etching or wet etching.
As an example, forming the source ohmic contact layer 115 and the drain ohmic contact layer 116 includes the steps of:
7-1) depositing more than 2 metal layers which are sequentially stacked in the source window 114 and on the bottom surface of the substrate 101 respectively;
7-2) performing a high temperature annealing process on the deposited metal layer to form the source ohmic contact layer 115 and the drain ohmic contact layer 116, respectively.
As an example, in the step 7-1), the process of depositing the metal layer may be one and/or more of vacuum evaporation, sputter coating, arc plasma coating, ion coating, molecular beam epitaxy, ion implantation, and the like.
It should be noted that the main function of the source ohmic contact layer 115 and the drain ohmic contact layer 116 is to reduce the contact resistance between SiC and the metal electrode, so as to improve the on-state capability of the device. For example, the material of the metal layer may be one or more of metals such as Ti, Ni, Au, Ta, W, Mo, Pt, and Co, and the metal layer may be two or more layers.
In this embodiment, a Ti layer, a Ni layer and an Au layer are sequentially stacked, and further, in this embodiment, the Ti layer has a thickness of 15 to 25nm, the Ni layer has a thickness of 100 to 150nm, and the Au layer has a thickness of 200 to 300 nm.
In other examples, the Ti layer, Ni layer, and Au layer may be deposited in other orders.
In the step 7-2), the high-temperature annealing treatment is performed in a nitrogen atmosphere, and further, in this embodiment, the annealing temperature is 950 to 1050 ℃ and the annealing time is 30 to 60 seconds.
In step 8), referring to step S08 in fig. 1 and fig. 11, a gate window 117 is formed in the passivation layer 113 at a position corresponding to the polysilicon layer 112.
As an example, the method for forming the gate window 117 in the step 8) may be dry etching or wet etching.
In step 9), referring to step S09 in fig. 1 and fig. 12 and 13, a gate electrode 118 is formed in the gate window 117, a source electrode 119 is formed on the surface of the source ohmic contact layer 115, and a drain electrode 120 is formed on the surface of the drain ohmic contact layer 116.
As an example, the gate electrode 118, the source electrode 119, and the drain electrode 120 may be metal electrodes, and the metal material may be one or more of metals such as Ti, Ni, Au, Ta, W, Mo, Pt, Co, Cu, Al, Cr, Ag, and Sn.
Example 2
As shown in fig. 13, the present invention provides a trench MOSFET power device structure, the device structure comprising:
a heavily doped substrate 101 of a first doping type;
a lightly doped epitaxial layer 103 of a first doping type on the upper surface of the substrate 101;
a heavily doped current spreading layer 104 of a first doping type located within the epitaxial layer 103;
a well region 105 of the second doping type, located in a region extending from the surface of the epitaxial layer 103 to the upper surface of the current spreading layer 104;
a heavily doped source region 106 of the first doping type located in the well region 105;
a heavily doped contact region 107 of a second doping type located in the well region 105;
an anode contact region 108 embedded with an SBD structure is positioned in the epitaxial layer 103 between the well regions 105;
a trench 109 located within the epitaxial layer 103;
a screening region 110 of the second doping type located in the epitaxial layer below said trench 109;
a gate dielectric layer 111 located on the sidewall and bottom surface of the trench 109;
a polysilicon layer 112 filled on the surface of the gate dielectric layer 111 in the trench 109;
a source ohmic contact layer 115 on the upper surfaces of the heavily doped source region 106 of the first doping type, the heavily doped contact region 107 of the second doping type, and the anode contact region 108 of the embedded SBD structure;
a passivation layer 113 on an upper surface of the SiC epitaxial layer 103 between the source ohmic contact layer 115 and the gate electrode 118;
a drain ohmic contact layer 116 on a lower surface of the substrate 101;
a drain electrode 120 on a lower surface of the drain ohmic contact layer 116;
a gate electrode 118 on an upper surface of the polysilicon layer 112;
and a source electrode 119 on an upper surface of the source ohmic contact layer 115.
As an example, the device structure of this embodiment further includes a buffer layer 102, where the buffer layer 102 is located between the substrate 101 and the epitaxial layer 103, and further, the thickness of the buffer layer 102 is 0.5 to 1 μm.
As an example, the first doping type is N-type and the second doping type is P-type.
In other examples, the first doping type may also be P-type, and the second doping type may be N-type.
As an example, the depth of the annular groove 109 is 1.0-1.4 um, and the width is 1.2-1.6 um.
For example, the thickness of the gate dielectric layer 111 is 50 to 80 nm.
For example, the gate electrode 118, the source electrode 119, and the drain electrode 120 may be made of one or more metals selected from Ti, Ni, Au, Ta, W, Mo, Pt, Co, Cu, Al, Cr, Ag, and Sn.
According to the invention, the SBD structure is embedded into the groove type MOSFET device, so that the good conduction performance of the SBD can be utilized, the reverse conduction capability of the MOSFET device is improved, the overall size and economic cost of the SiC power module are reduced, and the miniaturization of an electronic power device is realized. In addition, the invention also utilizes the shielding region structure at the bottom of the groove, can reduce the electric field intensity in the gate oxide, avoid the breakdown of the gate oxide and improve the reliability of the gate oxide. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A preparation method of a trench type MOSFET power device is characterized by comprising the following steps:
1) providing a heavily doped substrate of a first doping type, and forming a lightly doped epitaxial layer of the first doping type on the upper surface of the substrate;
2) forming a current extension layer of a first doping type in the epitaxial layer, forming a well region of a second doping type in the epitaxial layer, wherein the well region extends from the surface of the epitaxial layer to the upper surface of the current extension layer, forming an anode contact region embedded with an SBD structure in the epitaxial layer between the well regions of the second doping type, forming a heavily doped source region of the first doping type in the well region of the second doping type, and forming a heavily doped contact region of the second doping type in the well region of the second doping type;
3) forming a groove in the epitaxial layer, and forming a shielding region of a second doping type in the epitaxial layer below the bottom of the groove;
4) forming a gate dielectric layer on the side wall and the bottom of the groove obtained in the step 3);
5) filling a first doping type polycrystalline silicon layer in the groove with the gate dielectric layer obtained in the step 4);
6) forming a passivation layer on the surface of the epitaxial layer;
7) forming a source electrode window in the passivation layer, wherein the source electrode window exposes the source region, the anode contact region and the heavily doped contact region, a source electrode ohmic contact layer is formed in the source electrode window, and a drain electrode ohmic contact layer is formed on the bottom surface of the substrate;
8) forming a grid window in the passivation layer at a position corresponding to the polycrystalline silicon layer;
9) and forming a grid electrode in the grid window, forming a source electrode on the surface of the source ohmic contact layer, and forming a drain electrode on the surface of the drain ohmic contact layer.
2. The method of claim 1, wherein the first doping type is N-type or P-type and the corresponding second doping type is P-type or N-type.
3. The method of manufacturing a trench MOSFET power device as claimed in claim 1, wherein the step 1) further comprises a step of forming a buffer layer on the upper surface of the substrate before forming an epitaxial layer on the upper surface of the substrate, wherein the epitaxial layer is formed on the upper surface of the buffer layer.
4. The method of claim 1, wherein the step 3) of forming a trench in the epitaxial layer and forming a shielding region of the second doping type in the epitaxial layer below the bottom of the trench comprises the steps of:
3-1) forming a first mask layer on the upper surface of the epitaxial layer;
3-2) coating photoresist on the upper surface of the first mask layer, and carrying out patterning treatment on the photoresist by adopting a photoetching process to form patterned photoresist;
3-3) simultaneously etching the first mask layer and the epitaxial layer according to the patterned photoresist to form the groove in the epitaxial layer;
3-4) removing the patterned photoresist and reserving the etched first mask layer;
3-5) forming an injection barrier layer on the surface of the etched first mask layer and the surface of the groove;
3-6) injecting aluminum ions into the surface of the injection barrier layer so as to form a shielding region of a second doping type in the epitaxial layer at the bottom of the groove;
3-7) removing the first mask layer and the implantation barrier layer.
5. The method of manufacturing a trench MOSFET power device of claim 1, wherein: in the step 4), a gate dielectric layer is formed on the side wall and the bottom of the trench obtained in the step 3), and the method comprises the following steps:
4-1) forming a layer of film on the side wall and the bottom surface of the groove;
4-2) annealing the film to form a gate dielectric layer.
6. The method for manufacturing the trench MOSFET power device according to claim 1, wherein the step 7) of forming the source ohmic contact layer and the drain ohmic contact layer comprises the steps of:
7-1) depositing more than 2 metal layers which are sequentially stacked in the source window and on the surface of the bottom of the substrate respectively;
7-2) carrying out high-temperature annealing treatment on the deposited metal layer to form the source ohmic contact layer and the drain ohmic contact layer respectively.
7. A trench MOSFET power device, comprising:
a heavily doped substrate of a first doping type;
a lightly doped epitaxial layer of a first doping type on an upper surface of the substrate;
a heavily doped current spreading layer of a first doping type located within the epitaxial layer;
the well region of the second doping type is positioned in the upper surface of the current extension layer extending from the surface of the epitaxial layer;
a heavily doped source region of a first doping type located in the well region;
a heavily doped contact region of a second doping type located in the well region;
an anode contact region embedded with an SBD structure is positioned in the epitaxial layer between the well regions;
a trench located within the epitaxial layer;
the shielding region of the second doping type is positioned in the epitaxial layer below the groove;
the gate dielectric layer is positioned on the side wall and the bottom surface of the groove;
a polycrystalline silicon layer filled on the surface of the gate dielectric layer in the groove;
the source ohmic contact layer is positioned on the upper surfaces of the heavily doped source region of the first doping type, the heavily doped contact region of the second doping type and the anode contact region embedded with the SBD structure;
the passivation layer is positioned on the upper surface of the epitaxial layer between the source ohmic contact layer and the grid electrode;
the drain electrode ohmic contact layer is positioned on the lower surface of the substrate;
the drain electrode is positioned on the lower surface of the drain ohmic contact layer;
the grid electrode is positioned on the upper surface of the polycrystalline silicon layer;
and the source electrode is positioned on the upper surface of the source ohmic contact layer.
8. The trench MOSFET power device of claim 7 wherein the trench MOSFET power device structure further comprises a buffer layer between the substrate and the epitaxial layer.
9. The trench MOSFET power device of claim 7 wherein the first doping type is N-type or P-type and the corresponding second doping type is P-type or N-type.
10. The trench MOSFET power device of claim 7 wherein the length of the shielding region of the second doping type at the bottom of the trench is less than the width of the trench.
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