CN111986991B - Groove etching method, silicon carbide device manufacturing method and silicon carbide device - Google Patents

Groove etching method, silicon carbide device manufacturing method and silicon carbide device Download PDF

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CN111986991B
CN111986991B CN202010838550.6A CN202010838550A CN111986991B CN 111986991 B CN111986991 B CN 111986991B CN 202010838550 A CN202010838550 A CN 202010838550A CN 111986991 B CN111986991 B CN 111986991B
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layer
etching
etching window
forming
groove
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CN111986991A (en
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刘启军
王亚飞
李诚瞻
陈喜明
赵艳黎
郑昌伟
张超
罗海辉
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Zhuzhou CRRC Times Semiconductor Co Ltd
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Abstract

The disclosure provides a trench etching method, a silicon carbide device manufacturing method and a silicon carbide device, wherein the silicon carbide device manufacturing method comprises the following steps: forming a third etching window on the oxide layer on the drift layer at the corresponding position of the shielding region through a wet etching process and chemical mechanical planarization; the inclination angle of the side wall of the third etching window relative to the bottom of the third etching window is 130-140 degrees; forming a groove in an isosceles trapezoid shape at a corresponding position of the shielding region in the surface of the drift layer through the third etching window by adopting a dry etching process, wherein the rest part of the shielding region is positioned below the groove; the inclination angle of the side wall of the groove relative to the bottom of the groove is equal to the inclination angle of the side wall of the third etching window relative to the bottom of the third etching window; and forming a Schottky metal layer which forms Schottky contact with the drift layer on the side wall and the bottom of the groove. The method realizes the optimal compromise relationship between on-state current and blocking voltage after the integration of the MOSFET and the SBD.

Description

Groove etching method, silicon carbide device manufacturing method and silicon carbide device
Technical Field
The disclosure relates to the technical field of semiconductor devices, and in particular relates to a trench etching method, a silicon carbide device manufacturing method and a silicon carbide device.
Background
Silicon carbide (SiC) is a novel wide forbidden band semiconductor material, has the advantages of high heat conductivity, high breakdown field strength, high saturation speed and the like, and is very suitable for manufacturing high-temperature high-power semiconductor devices. The silicon carbide-based power device can greatly exert the characteristics of high temperature, high frequency and low loss, so that the silicon carbide-based power device has great application prospect in the aspects of high voltage, high temperature, high frequency, high power, strong radiation and the like. The silicon carbide Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) has the characteristics of low on-resistance, high switching speed, high temperature resistance and the like, and has great application advantages in the fields of high-voltage frequency conversion, new energy automobiles, rail transit and the like.
However, in the SiC MOSFET device with the conventional planar gate structure, a PIN diode is parasitic in the cell structure in addition to the MOS structure, and the turn-on of the PIN diode may cause a "bipolar degradation" phenomenon, which seriously affects the reliability of the MOSFET device in long-term use. In order to suppress the turn-on of the PIN diode in the SiC MOSFET device, a schottky barrier diode (Schottky Barrier Diode, SBD) is conventionally used in anti-parallel with the MOSFET device as its freewheel diode. However, in the chip manufacturing process, the anti-parallel MOSFET and the SBD increase manufacturing procedures, prolong manufacturing time and increase manufacturing cost; in addition, the increase of working procedures increases the risk of the manufacturing process and reduces the yield of products; in addition, conventional anti-parallel coupling introduces redundant bond wires into the device, which increases redundant stray inductance during device use, resulting in degradation of the device electrical performance. However, in the existing silicon carbide device integrated with the SBD, it is difficult to realize the optimal trade-off relationship between on-state current and blocking voltage after the integration of the MOSFET device and the SBD.
Disclosure of Invention
In view of the above problems, the present disclosure provides a trench etching method, a silicon carbide device manufacturing method, and a silicon carbide device, which solve the technical problem in the prior art that it is difficult to realize a trade-off relationship between on-state current and blocking voltage after the integration of an optimal MOSFET device and an SBD.
In a first aspect, the present disclosure provides a method for etching a trench, including:
providing a first conductivity type silicon carbide substrate, and forming a first conductivity type drift layer over the substrate;
forming an oxide layer over the drift layer;
forming a photoresist mask layer above the oxide layer, and performing patterning treatment on the photoresist mask layer to form a first etching window on the photoresist mask layer;
etching the oxide layer below the first etching window by adopting a wet etching process through the first etching window so as to form a second etching window on the oxide layer;
removing the photoresist mask layer, performing chemical mechanical planarization on the oxide layer to remove the oxide layer with preset thickness and optimize the second etching window, so as to form a third isosceles trapezoid etching window on the rest oxide layer; the inclination angle of the side wall of the third etching window relative to the bottom of the third etching window is 130-140 degrees;
etching the drift layer below the third etching window through the third etching window by adopting a dry etching process so as to form a groove in an isosceles trapezoid shape in the surface of the drift layer; the inclination angle of the side wall of the groove relative to the bottom of the groove is equal to the inclination angle of the side wall of the third etching window relative to the bottom of the third etching window;
and removing the rest oxide layer.
According to an embodiment of the present disclosure, preferably, the depth of the trench is 1 to 2um.
In accordance with an embodiment of the present disclosure, preferably,
the width of the bottom of the first etching window is 0.8 mu m;
the bottom width of the third etching window is smaller than or equal to 1.5 mu m.
In a second aspect, the present disclosure provides a method of making a silicon carbide device, comprising:
providing a first conductivity type silicon carbide substrate, and forming a first conductivity type drift layer over the substrate;
forming a plurality of well regions of a second conductivity type arranged at intervals in the surface of the drift layer, and forming a shielding region of the second conductivity type in the surface of the drift layer between two adjacent well regions; wherein the shielding region is not in contact with the well region;
forming an oxide layer over the drift layer;
forming a photoresist mask layer above the oxide layer, and performing patterning treatment on the photoresist mask layer to form a first etching window on the photoresist mask layer at a corresponding position of the shielding region;
etching the oxide layer below the first etching window through the first etching window by adopting a wet etching process so as to form a second etching window on the oxide layer at a corresponding position of the shielding region;
removing the photoresist mask layer, performing chemical mechanical planarization on the oxide layer to remove the oxide layer with preset thickness and optimize the second etching window, so as to form a third isosceles trapezoid etching window on the rest of the oxide layer at the corresponding position of the shielding region; the inclination angle of the side wall of the third etching window relative to the bottom of the third etching window is 130-140 degrees;
etching the drift layer below the third etching window through the third etching window by adopting a dry etching process so as to etch away part of the shielding region and form a isosceles trapezoid groove at the corresponding position of the shielding region in the surface of the drift layer; the inclination angle of the side wall of the groove relative to the bottom of the groove is equal to the inclination angle of the side wall of the third etching window relative to the bottom of the groove, the side wall of the groove is not in contact with the well region, and the rest part of the shielding region is positioned below the groove;
removing the rest oxide layer;
and forming a Schottky metal layer which forms Schottky contact with the drift layers at two sides of the groove at the side wall and the bottom of the groove.
According to an embodiment of the present disclosure, preferably, the depth of the trench is 1 to 2um.
In accordance with an embodiment of the present disclosure, preferably,
the width of the bottom of the first etching window is 0.8 mu m;
the bottom width of the third etching window is smaller than or equal to 1.5 mu m.
According to an embodiment of the present disclosure, preferably, after the step of forming a plurality of well regions of the second conductivity type disposed at intervals in the drift layer surface and forming a shield region of the second conductivity type in the drift layer surface between two adjacent well regions, the method further comprises the steps of:
forming a first source region of a second conductivity type in the well region surface;
forming a first conductive type second source region on two sides of the first source region in the surface of the well region; wherein both sides of the well region surface are not completely covered by the first source region and the second source region.
According to an embodiment of the present disclosure, preferably, before the step of forming the schottky metal layer forming schottky contacts with the drift layers at both sides of the trench on the side wall and the bottom of the trench, the method further includes the steps of:
forming gate insulation layers on the two sides of the groove and above the well region, the second source region and the drift layer, wherein the gate insulation layers are in contact with the well region and the second source region;
forming a gate electrode over the gate insulating layer;
forming an interlayer dielectric layer above the grid electrode;
forming a source metal layer over the first and second source regions while being in ohmic contact with the first and second source regions; the grid electrode is isolated from the source electrode metal layer through the interlayer dielectric layer.
According to an embodiment of the present disclosure, preferably, after the step of forming the schottky metal layer forming schottky contacts with the drift layers at both sides of the trench on the side wall and the bottom of the trench, the method further includes the steps of:
forming a source briquetting metal layer above the source metal layer and above the Schottky metal layer and in the groove; the Schottky metal layer and the source metal layer are electrically connected through the source pressing block metal layer, and the grid is isolated from the source pressing block metal layer through the interlayer dielectric layer;
a drain metal layer is formed under the substrate in ohmic contact with the substrate.
In a third aspect, the present disclosure provides a silicon carbide device prepared by the method of preparing a silicon carbide device according to any one of the second aspects.
By adopting the technical scheme, at least the following technical effects can be achieved:
(1) Forming a groove which is in an isosceles trapezoid and has an inclination angle of 130-140 degrees in the surface of the drift layer by an etching method combining wet etching, chemical mechanical planarization and dry etching;
(2) The Schottky metal layer is formed in the isosceles trapezoid groove with the inclination angle of 130-140 degrees between two adjacent well regions, the Schottky contact effect of the Schottky metal layer and the drift layer can be improved, and the optimal compromise relationship between on-state current and blocking voltage after the MOSFET and the SBD are integrated is realized;
(3) The SBD is integrated in the silicon carbide device, so that the module does not need to be additionally packaged when packaged, the cost is reduced, and the parasitic inductance is reduced;
(4) And a second conduction type shielding region is arranged in a local area where the Schottky metal is in contact with the drift layer, so that leakage current of the Schottky junction in reverse bias is reduced, and the electrical performance of the device is improved.
Drawings
The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification, illustrate the disclosure and together with the description serve to explain, but do not limit the disclosure. In the drawings:
FIG. 1 is a flow chart of a method of etching a trench according to an exemplary embodiment of the disclosure;
FIGS. 2-6 are schematic cross-sectional views illustrating steps associated with a trench etching method according to an exemplary embodiment of the present disclosure;
FIG. 7 is a flow chart illustrating a method of fabricating a silicon carbide device according to an exemplary embodiment of the present disclosure;
fig. 8-16 are schematic cross-sectional structures formed by the relevant steps of a method of fabricating a silicon carbide device according to an exemplary embodiment of the present disclosure.
Detailed Description
The embodiments of the present disclosure will be described in detail below with reference to the drawings and examples, so as to solve the technical problem by applying technical means to the present disclosure, and the implementation process for achieving the corresponding technical effects can be fully understood and implemented accordingly. The embodiments of the present disclosure and various features in the embodiments may be combined with each other without conflict, and the formed technical solutions are all within the protection scope of the present disclosure. In the drawings, the size of layers and regions, as well as the relative sizes, may be exaggerated for clarity. Like numbers refer to like elements throughout.
It will be understood that, although the terms "first," "second," "third," etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.
It will be understood that spatially relative terms, such as "above," "located above," "below," "located below," and the like, may be used herein for convenience of description to describe one element or feature as illustrated in the figures as connected with another element or feature. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the present disclosure are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure. In this way, variations from the illustrated shape due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present disclosure should not be limited to the particular shapes of the regions illustrated herein, but include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.
For a thorough understanding of the present disclosure, detailed structures and steps will be presented in the following description in order to illustrate the technical solutions presented by the present disclosure. Preferred embodiments of the present disclosure are described in detail below, however, the present disclosure may have other implementations in addition to these detailed descriptions.
Example 1
The embodiment provides a trench etching method. Fig. 1 is a flow chart illustrating a method for etching a trench according to an embodiment of the disclosure. Fig. 2 to 6 are schematic cross-sectional structures formed by relevant steps of a trench etching method according to an embodiment of the present disclosure. Detailed steps of an exemplary method for etching a trench according to an embodiment of the present disclosure will be described with reference to fig. 1 and 2 to 6.
As shown in fig. 1, the method for etching a trench in this embodiment includes the following steps:
step S101: as shown in fig. 2, a first conductivity-type silicon carbide substrate 101 is provided, and a first conductivity-type drift layer 102 is formed over the substrate 101.
Step S102: an oxide layer 103 is formed over the drift layer 102.
The oxide layer 103 is made of TEOS-SiO 2 The thickness was 2. Mu.m.
Specifically, TEOS-SiO having a thickness of 2 μm is first prepared by low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD) over the drift layer 102 2 And N is carried out on it 2 And (3) annealing densification treatment, wherein the annealing condition temperature is 1000 ℃.
Step S103: a photoresist mask layer 104 is formed over the oxide layer 103, and the photoresist mask layer 104 is subjected to patterning process to form a first etching window 105 on the photoresist mask layer 104.
Specifically, the photoresist mask layer 104 is patterned by an exposure and development process, wherein the photoresist thickness is 1.6 to 1.8 μm, and the width of the first etching window 105 is 0.8 μm. After development, a hardening process is also required to pattern the photoresist mask layer 104.
Step S104: as shown in fig. 3, through the first etching window 105, the oxide layer 103 under the first etching window 105 is etched using a wet etching process to form a second etching window 106 on the oxide layer 103.
Specifically, in the wet etching process, the etching solution used is a BOE solution, and in the wet etching process, the second etching window 106 formed has no certain inclination angle and has a side corrosion phenomenon because the BOE solution is corroded to have isotropy.
Step S105: as shown in fig. 4, the photoresist mask layer 104 is removed, chemical mechanical planarization is performed on the oxide layer 103, so as to remove the oxide layer 103 with a preset thickness and optimize the second etching window 106, thereby forming a third etching window 107 with an isosceles trapezoid shape on the remaining oxide layer 103; wherein the sidewall of the third etching window 107 has an inclination angle of 130 ° to 140 ° with respect to the bottom thereof.
Specifically, in order to form an etching window of a predetermined inclination angle at a predetermined position, after removing the photoresist mask layer 104, the oxide layer 103 of a predetermined thickness (about 1.2 μm) of the surface layer of the oxide layer 103 is then removed by a chemical mechanical planarization (Chemical Mechanical Planarization, CMP) technique, while an effect of optimizing the second etching window 106 is achieved, and an upper portion (irregular portion) of the second etching window 106 is removed, thereby forming a third etching window 107 of an isosceles trapezoid shape having a predetermined inclination angle on the remaining oxide layer 103 (about 0.8 μm).
The sidewall of the third etching window 107 has an inclination angle θ of 130 ° to 140 ° with respect to the bottom thereof.
Note that, in order to ensure the quality of the sidewall of the third etching window 107, the BOE etching time may be appropriately adjusted, but the width of the third etching window 107 needs to be less than or equal to 1.5 μm.
Step S106: as shown in fig. 5, through the third etching window 107, the drift layer 102 under the third etching window 107 is etched by a dry etching process to form a trench 108 having an isosceles trapezoid shape in the surface of the drift layer 102; wherein the inclination angle of the side wall of the trench 108 with respect to the bottom thereof is equal to the inclination angle of the side wall of the third etching window 107 with respect to the bottom thereof.
Since the dry etching is anisotropic etching, the drift layer 102 is etched through the third etching window 107, so that the trench 108 having an isosceles trapezoid shape with an inclination angle identical to that of the third etching window 107 can be obtained, the inclination angle θ of the side wall of the trench 108 with respect to the bottom thereof is also 130 ° to 140 °, and the depth of the trench 108 is 1 to 2 μm. That is, the pattern on the oxide layer 103 can be transferred onto the drift layer 102 by a dry etching process.
Such an etching method by combining wet etching, chemical mechanical planarization, and dry etching may form isosceles trapezoid trenches 108 having a predetermined inclination angle at predetermined positions in the surface of the drift layer 102.
Step S107: as shown in fig. 6, the remaining oxide layer 103 is removed.
Specifically, a wet etch process may be used to remove the remaining oxide layer 103 (about 0.8 μm).
The present embodiment provides a method for manufacturing a silicon carbide device, in which a trench 108 having an inclination angle of 130 ° to 140 ° in the form of an isosceles trapezoid is formed in the surface of a drift layer 102 by an etching method combining wet etching, chemical mechanical planarization and dry etching.
Example two
On the basis of the first embodiment, this embodiment provides a method for manufacturing a silicon carbide device. Fig. 7 is a flow chart illustrating a method of fabricating a silicon carbide device according to an embodiment of the present disclosure. Fig. 8-16 are schematic cross-sectional structures formed by the relevant steps of a method for fabricating a silicon carbide device according to embodiments of the present disclosure. The detailed steps of one exemplary method of the method of fabricating a silicon carbide device according to embodiments of the present disclosure are described below with reference to fig. 7 and 8-16.
As shown in fig. 7, the method for manufacturing the silicon carbide device of the present embodiment includes the following steps:
step S201: as shown in fig. 8, a first conductivity-type silicon carbide substrate 201 is provided, and a first conductivity-type drift layer 202 is formed over the substrate 201.
The thickness of the substrate 201 is thicker, the thickness of the substrate 201 is 180 to 400 μm, the thickness of the drift layer 202 is 6 to 30 μm, the thickness of the drift layer 202 isIon doping concentration of 1E13 to 1E17cm -3 In particular, it is necessary to optimize the device voltage resistance.
Step S202: forming a plurality of well regions 203 of the second conductivity type arranged at intervals in the surface of the drift layer 202, and forming a shield region 206 of the second conductivity type in the surface of the drift layer 202 between two adjacent well regions 203; wherein the shielding region 206 is not in contact with the well region 203.
Specifically, the second conductive type energetic ions are implanted into the surface of the drift layer 202 to form a plurality of well regions 203 of the second conductive type disposed at intervals, and then the second conductive type energetic ions are implanted into the surface of the drift layer 202 between the adjacent two well regions 203 to form a shield region 206 of the second conductive type.
The upper surfaces of the well region 203 and the shield region 206 are flush with the upper surface of the drift layer 202.
Wherein the ion implantation dose of the well region 203 is 1E15 to 1E18 atoms/cm 2 The implantation energy is 100 to 900KeV. The ion implantation dose of the shielding region 206 is 1E14 to 9E19 atoms/cm 2 The implantation energy is 100 to 1000KeV. And during the ion implantation, a layer of at least one of polysilicon, silicon oxide and silicon nitride is deposited over the drift layer 202 in the ion implantation region (the well region 203 and/or the shielding region 206), and the thickness of the protection layer is 10 to 200nm.
It should be noted that, in order to further shorten the process flow and save the manufacturing cost, the ion implantation of the well region 203 and the shielding region 206 may be performed simultaneously.
After step S202, the method further includes the following steps:
(a) Forming a second conductive type first source region 205 in the surface of the well region 203;
(b) Forming second source regions 204 of the first conductivity type on both sides of the first source region 205 in the surface of the well region 203; wherein both sides of the surface of the well region 203 are not completely covered by the first source region 205 and the second source region 204.
Specifically, a photolithography process is used to selectively mask a portion of the surface of the well region 203 by photoresist, and second conductivity type energetic ions are implanted into the well region 203 by ion implantation to form a second conductivity type first source region 205 in the surface of the well region 203. Then, a photolithography process is used to selectively shield the surface of the first source region 205 and a portion of the surface of the well region 203 by photoresist, and then, high-energy ions of the first conductivity type are implanted into the well region 203 by ion implantation to form second source regions 204 of the first conductivity type on both sides of the first source region 205 in the surface of the well region 203.
The upper surface of the first source region 205 is flush with the upper surface of the well region 203. The width of the first source region 205 is smaller than the width of the well region 203, the ion implantation dose of the first source region 205 is larger than the ion implantation dose of the well region 203, the depth of the first source region 205 is smaller than or equal to the depth of the well region 203, and both ends of the first source region 205 are in contact with the second source region 204. The ion implantation dose of the first source region 205 is equal to or greater than 5E18 atoms/cm 2 The implantation energy is 100 to 1000KeV. And in the ion implantation process, the implantation region is required to deposit at least one layer of polysilicon, silicon oxide and silicon nitride, and the thickness of the implantation damage protection layer is 10-200 nm.
The upper surface of the second source region 204 is flush with the upper surface of the well region 203. The ion implantation dose of the second source region 204 is larger than the ion implantation dose of the substrate 201 and the drift layer 202. The width of the second source region 204 is smaller than the width of the well region 203, and both sides of the surface of the well region 203 are not completely covered by the first source region 205 and the second source region 204, so that a planar gate conduction channel (not labeled in the figure) is formed on both sides of the well region 203. The ion implantation dose of the second source region 204 is greater than or equal to 5E18 atoms/cm 2 The implantation energy is 100 to 1000KeV. And in the ion implantation process, the implantation region is required to deposit a layer of at least one of polysilicon, silicon oxide and silicon nitride as an implantation damage protection layer, and the thickness of the implantation damage protection layer is 10-200 nm.
After the ion implantation of each doped region is completed, high-temperature activation annealing is required to be performed on the implanted ions at a temperature of 1200-2000 ℃ so that the implanted ions form a continuous and stable implanted doped layer. And a dense carbon film is formed above the drift layer 202 as a protective layer before high temperature annealing, wherein the thickness of the carbon film is 500-1100 nm.
Step S203: as shown in fig. 9, an oxide layer 207 is formed over the drift layer 202.
The oxide layer 207 is made of TEOS-SiO 2 The thickness was 2. Mu.m.
Specifically, TEOS-SiO having a thickness of 2 μm is first prepared by low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD) over the drift layer 202 2 And N is carried out on it 2 And (3) annealing densification treatment, wherein the annealing condition temperature is 1000 ℃.
Step S204: a photoresist mask layer 208 is formed over the oxide layer 207, and the photoresist mask layer 208 is patterned to form first etch windows 209 on the photoresist mask layer 208 at corresponding locations of the shield regions 206.
Specifically, the photoresist mask layer 208 is patterned by an exposure and development process, wherein the photoresist thickness is 1.6 to 1.8 μm, and the width of the first etching window 209 is 0.8 μm. After development, a hardening process is also required to pattern the photoresist mask layer 208.
Step S205: as shown in fig. 10, through the first etching window 209, the oxide layer 207 under the first etching window 209 is etched using a wet etching process to form a second etching window 210 on the oxide layer 207 at a corresponding position of the shielding region 206.
Specifically, in the wet etching process, the etching solution used is a BOE solution, and in the wet etching process, the second etching window 210 formed has no certain inclination angle and has a side corrosion phenomenon because the BOE solution is corroded to have isotropy.
Step S206: as shown in fig. 11, the photoresist mask layer 208 is removed, chemical mechanical planarization is performed on the oxide layer 207 to remove the oxide layer 207 with a preset thickness and optimize the second etching window 210, so that a third etching window 211 with an isosceles trapezoid shape is formed on the remaining oxide layer 207 at a corresponding position of the shielding region 206; wherein, the inclination angle of the side wall of the third etching window 211 relative to the bottom thereof is 130 ° to 140 °.
Specifically, in order to form an etching window with a predetermined inclination angle at a corresponding position of the shielding region 206, after removing the photoresist mask layer 208, the oxide layer 207 is removed by a chemical mechanical planarization (Chemical Mechanical Planarization, CMP) technique to a predetermined thickness (about 1.2 μm) on the surface layer of the oxide layer 207, and simultaneously, to optimize the second etching window 210, an upper portion (irregular portion) of the second etching window 106 is removed, thereby forming a third etching window 211 with a predetermined inclination angle in an isosceles trapezoid shape on the remaining oxide layer 207 (about 0.8 μm) at a corresponding position of the shielding region 206.
The sidewall of the third etching window 211 has an inclination angle θ of 130 ° to 140 ° with respect to the bottom thereof.
Note that, in order to ensure the quality of the sidewall of the third etching window 211, the BOE etching time may be properly adjusted, but the width of the third etching window 211 needs to be less than or equal to 1.5 μm.
Step S207: as shown in fig. 12, through the third etching window 211, the drift layer 202 below the third etching window 211 is etched by a dry etching process, so as to etch away part of the shielding region 206 and form a groove 212 in an isosceles trapezoid shape at a corresponding position of the shielding region 206 in the surface of the drift layer 202; wherein the inclination angle of the sidewall of the trench 212 with respect to the bottom thereof is equal to the inclination angle of the sidewall of the third etching window 211 with respect to the bottom thereof, the sidewall of the trench 212 is not in contact with the well region 203, and the remaining portion of the shielding region 206 is located under the trench 212.
Since the dry etching is anisotropic etching, the drift layer 202 is etched through the third etching window 211, so that the trench 212 having an isosceles trapezoid shape with an inclination angle identical to that of the third etching window 211 can be obtained, the inclination angle θ of the sidewall of the trench 212 with respect to the bottom thereof is also 130 ° to 140 °, and the depth of the trench 212 is 1 to 2 μm. That is, the pattern on the oxide layer 207 can be transferred onto the drift layer 202 by a dry etching process.
Such an etching method by combining wet etching, chemical mechanical planarization, and dry etching may form a trench 212 having a predetermined inclination angle in an isosceles trapezoid shape at a predetermined position (a position where the shielding region 206 is located) in the surface of the drift layer 202.
Step S208: as shown in fig. 13, the remaining oxide layer 207 is removed.
Specifically, a wet etch process may be used to remove the remaining oxide layer 207 (about 0.8 μm).
After step S208, as shown in fig. 14, the method further includes the steps of:
(a) Forming a gate insulating layer 213 contacting the well region 203 and the second source region 204 over the well region 203, the second source region 204, and the drift layer 202 at both sides of the trench 212;
(b) Forming a gate electrode 214 over the gate insulating layer 213;
(c) Forming an interlayer dielectric layer 215 over the gate 214;
(d) Forming a source metal layer 216 over the first and second source regions 205 and 204 while making ohmic contact with the first and second source regions 205 and 204; wherein the gate 214 is isolated from the source metal layer 216 by an interlayer dielectric layer 215.
Specifically, the thickness of the gate insulating layer 213 is 30 to 100nm, and the gate insulating layer 213 is not in contact with the trench 212 and is spaced apart from the trench 212.
The gate 214 is a polysilicon gate with a thickness of 300 to 700nm, as shown in fig. 14, in this embodiment, one planar gate structure (including the gate insulating layer 213 and the gate 214) is corresponding to each planar gate channel, that is, one JFET region corresponds to two planar gate structures, which is different from one JFET region corresponding to one planar gate structure. The split gate structure in the embodiment reduces parasitic capacitance of the gate structure of the MOSFET device and further reduces switching loss of the device.
The interlayer dielectric layer 215 has a thickness of 400 to 2000nm, and the interlayer dielectric layer 215 realizes isolation between the source metal layers 216 of the gate 214.
The source metal layer 216 is Ni metal and has a thickness of 100 to 400nm. The source metal layer 216 is prepared by sputtering Ni metal on the drift layer 202 and performing a high temperature annealing process to form a good ohmic contact.
Step S209: as shown in fig. 15, a schottky metal layer 217 forming a schottky contact with the drift layer 202 on both sides of the trench 212 is formed on the sidewalls and bottom of the trench 212.
Specifically, ti metal is sputtered on the drift layer 202 to form a schottky metal layer 217 on the sidewalls and bottom of the trench 212, and then a high temperature annealing process is performed to form schottky contacts between the schottky metal layer 217 and the drift layer 202 on both sides of the trench 212. Wherein the thickness of the schottky metal layer 217 is 100 to 300nm and the annealing temperature is 450 to 650 ℃.
In this embodiment, the schottky metal layer 217 is formed in the isosceles trapezoid trench 212 with a preset inclination angle between two adjacent well regions 203 (JFET regions), so that the schottky contact effect between the schottky metal layer 217 and the drift layer 202 can be improved, and an optimal trade-off relationship between on-state current and blocking voltage after the MOSFET and the SBD are integrated is realized.
And because the rest of the shielding region 206 is located below the trench 212, the second conductivity type shielding region 206 is arranged in the local area where the schottky metal layer 217 contacts with the drift layer 202, so that the leakage current of the schottky junction in reverse bias is reduced, and the electrical performance of the device is improved.
Step S210: as shown in fig. 16, a source briquette metal layer 218 is formed over source metal layer 216, and over schottky metal layer 217 and within trench 212; wherein the schottky metal layer 217 and the source metal layer 216 form an electrical connection through the source briquette metal layer 218, and the gate 214 is isolated from the source briquette metal layer 218 by the interlayer dielectric layer 215.
Specifically, an AlSi alloy layer is sputtered on the front side of the silicon carbide wafer to form a source briquetting metal layer 218 over the source metal layer 216, over the schottky metal layer 217 and within the trench 212, so that the schottky metal layer 217 and the source metal layer 216 are electrically connected through the source briquetting metal layer 218, even though the schottky metal layer 217 of the SBD and the source metal layer 216 of the MOSFET are effectively connected, achieving the technical effect of integrating the SBD in the MOSFET device.
In the embodiment, the SBD is integrated in the silicon carbide device, so that the module is packaged without additionally packaging the SBD, the cost is reduced, and the parasitic inductance is reduced.
The thickness of the source compact metal layer 218 is 2-6 μm.
After step S210, the method further includes the following steps: the substrate 201 is subjected to thinning processing.
Specifically, the front surface of the wafer needs to be glued or waxed for protection before the thinning process. The thinned wafer has a thickness of 120-280 μm, the thinned substrate 201 has a roughness of 4-10 nm, and the absolute value of the thinned wafer warpage is less than 80 μm.
Step S211: a drain metal layer 219 is formed under the substrate 201 in ohmic contact with the substrate 201.
Specifically, ni metal is sputtered as the drain metal layer 219 on the thinned substrate 201, and laser annealing treatment is performed to form good ohmic contact between the drain metal layer 219 and the substrate 201. Wherein the thickness of the drain metal layer 219 is 50 to 500nm.
After step S211, the method further includes the steps of: on the basis of the drain metal layer 219, metal thickening is performed.
The specific thickening metal is at least one of Ti, ni, ag, au, al, generally Ti/Ni/Ag combination, and the thickness of the thickening metal is 0.2-3 mu m.
Correspondingly, the first conductivity type is opposite to the second conductivity type. For example, when the first conductivity type is N-type, the second conductivity type is P-type; when the first conductivity type is P type, the second conductivity type is N type. The N-type high-energy ions are at least one of N, P, as, sb and the P-type high-energy ions are at least one of B, al, ga, in.
The present embodiment provides a method for manufacturing a silicon carbide device by forming a second conductivity type shielding region 206 in the surface of the drift layer 202 between two adjacent well regions 203; by combining the etching method of wet etching, chemical mechanical planarization and dry etching, the isosceles trapezoid groove 212 with the inclination angle of 130-140 degrees is formed in the surface of the drift layer 202, and the schottky metal layer 217 is formed in the isosceles trapezoid groove 212 with the inclination angle of 130-140 degrees between two adjacent well regions 203, the schottky contact effect of the schottky metal layer 217 and the drift layer 202 can be improved, and the optimal compromise relationship between on-state current and blocking voltage after the integration of the MOSFET and the SBD is realized. The SBD is integrated in the silicon carbide device, so that the module is packaged without extra SBD, the cost is reduced, the parasitic inductance is reduced, and the electrical performance of the device is improved.
The foregoing is merely a preferred embodiment of the present disclosure, and is not intended to limit the present disclosure, so that various modifications and changes may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure. While the embodiments of the present disclosure are described above, the disclosure is not limited to the embodiments employed for the convenience of understanding the present disclosure. Any person skilled in the art to which this disclosure pertains will appreciate that numerous modifications and variations in form and detail can be made without departing from the spirit and scope of the disclosure, but the scope of the disclosure is still subject to the scope of the appended claims.

Claims (10)

1. The etching method of the groove is characterized by comprising the following steps:
providing a first conductivity type silicon carbide substrate, and forming a first conductivity type drift layer over the substrate;
forming an oxide layer over the drift layer;
forming a photoresist mask layer above the oxide layer, and performing patterning treatment on the photoresist mask layer to form a first etching window on the photoresist mask layer;
etching the oxide layer below the first etching window by adopting a wet etching process through the first etching window so as to form a second etching window on the oxide layer;
removing the photoresist mask layer, performing chemical mechanical planarization on the oxide layer to remove the oxide layer with preset thickness and optimize the second etching window, so as to form a third isosceles trapezoid etching window on the rest oxide layer; the inclination angle of the side wall of the third etching window relative to the bottom of the third etching window is 130-140 degrees;
etching the drift layer below the third etching window through the third etching window by adopting a dry etching process so as to form a groove in an isosceles trapezoid shape in the surface of the drift layer; the inclination angle of the side wall of the groove relative to the bottom of the groove is equal to the inclination angle of the side wall of the third etching window relative to the bottom of the third etching window;
and removing the rest oxide layer.
2. The method of etching a trench of claim 1, wherein the depth of the trench is 1 to 2um.
3. The method for etching a trench as claimed in claim 1, wherein,
the width of the bottom of the first etching window is 0.8 mu m;
the bottom width of the third etching window is smaller than or equal to 1.5 mu m.
4. A method of making a silicon carbide device, comprising:
providing a first conductivity type silicon carbide substrate, and forming a first conductivity type drift layer over the substrate;
forming a plurality of well regions of a second conductivity type arranged at intervals in the surface of the drift layer, and forming a shielding region of the second conductivity type in the surface of the drift layer between two adjacent well regions; wherein the shielding region is not in contact with the well region;
forming an oxide layer over the drift layer;
forming a photoresist mask layer above the oxide layer, and performing patterning treatment on the photoresist mask layer to form a first etching window on the photoresist mask layer at a corresponding position of the shielding region;
etching the oxide layer below the first etching window through the first etching window by adopting a wet etching process so as to form a second etching window on the oxide layer at a corresponding position of the shielding region;
removing the photoresist mask layer, performing chemical mechanical planarization on the oxide layer to remove the oxide layer with preset thickness and optimize the second etching window, so as to form a third isosceles trapezoid etching window on the rest of the oxide layer at the corresponding position of the shielding region; the inclination angle of the side wall of the third etching window relative to the bottom of the third etching window is 130-140 degrees;
etching the drift layer below the third etching window through the third etching window by adopting a dry etching process so as to etch away part of the shielding region and form a isosceles trapezoid groove at the corresponding position of the shielding region in the surface of the drift layer; the inclination angle of the side wall of the groove relative to the bottom of the groove is equal to the inclination angle of the side wall of the third etching window relative to the bottom of the groove, the side wall of the groove is not in contact with the well region, and the rest part of the shielding region is positioned below the groove;
removing the rest oxide layer;
and forming a Schottky metal layer which forms Schottky contact with the drift layers at two sides of the groove at the side wall and the bottom of the groove.
5. The method of manufacturing a silicon carbide device according to claim 4, wherein the trench has a depth of 1 to 2um.
6. The method of manufacturing a silicon carbide device as claimed in claim 4,
the width of the bottom of the first etching window is 0.8 mu m;
the bottom width of the third etching window is smaller than or equal to 1.5 mu m.
7. The method of manufacturing a silicon carbide device according to claim 4, wherein after the step of forming a plurality of well regions of the second conductivity type in the drift layer surface at intervals and forming a shield region of the second conductivity type in the drift layer surface between adjacent two of the well regions, further comprising the steps of:
forming a first source region of a second conductivity type in the well region surface;
forming a first conductive type second source region on two sides of the first source region in the surface of the well region; wherein both sides of the well region surface are not completely covered by the first source region and the second source region.
8. The method of manufacturing a silicon carbide device according to claim 7, further comprising, before the step of forming schottky metal layers forming schottky contacts with the drift layers on both sides of the trench on the side walls and bottom of the trench, the steps of:
forming gate insulation layers on the two sides of the groove and above the well region, the second source region and the drift layer, wherein the gate insulation layers are in contact with the well region and the second source region;
forming a gate electrode over the gate insulating layer;
forming an interlayer dielectric layer above the grid electrode;
forming a source metal layer over the first and second source regions while being in ohmic contact with the first and second source regions; the grid electrode is isolated from the source electrode metal layer through the interlayer dielectric layer.
9. The method of manufacturing a silicon carbide device according to claim 8, further comprising, after the step of forming schottky metal layers forming schottky contacts with the drift layers on both sides of the trench on the side walls and bottom of the trench, the steps of:
forming a source briquetting metal layer above the source metal layer and above the Schottky metal layer and in the groove; the Schottky metal layer and the source metal layer are electrically connected through the source pressing block metal layer, and the grid is isolated from the source pressing block metal layer through the interlayer dielectric layer;
a drain metal layer is formed under the substrate in ohmic contact with the substrate.
10. A silicon carbide device prepared by the method of any one of claims 4 to 9.
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