CN117410322B - Groove type super junction silicon MOSFET and preparation method - Google Patents
Groove type super junction silicon MOSFET and preparation method Download PDFInfo
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- CN117410322B CN117410322B CN202311724573.4A CN202311724573A CN117410322B CN 117410322 B CN117410322 B CN 117410322B CN 202311724573 A CN202311724573 A CN 202311724573A CN 117410322 B CN117410322 B CN 117410322B
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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Abstract
The invention discloses a groove type super junction silicon MOSFET and a preparation method thereof, wherein the MOSFET comprises the following components: trench gate, P-pillar and N-pillar; the trench gate comprises a first extension part and a second extension part; the first extension part is positioned between and adjacent to the Pwell layers; the second extension part is positioned between and adjacent to the Pwell layer, the first extension part, the P column and the N column; the first end of the first extension part is connected with the second extension part; the first extension part and the second extension part form an inverted T shape; the P column is positioned among the Pwell layer, the second extension part, the N column and the substrate; the P column is adjacent to the Pwell layer, the N column and the substrate; the N column is positioned between the second extension part, the P column and the substrate; the N pillars are adjacent to the substrate. According to the invention, the trench is extended on the basis of the traditional vertical trench, so that the length of the grid electrode positioned in the trench is increased, the channel length of the super-junction silicon MOSFET is increased due to the increase of the length of the grid electrode, and the thermal stability of the super-junction silicon MOSFET device is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a trench type super-junction silicon MOSFET and a preparation method thereof.
Background
The trench MOSFET device is a novel MOSFET device with a vertical structure, and is optimized and developed on the basis of the traditional planar MOSFET structure. Compared with a planar MOSFET device, the trench MOSFET device has the advantages that a channel formed by constructing a trench structure penetrating through the bottommost end of the body region is positioned between the source region and the drift region, the JFET region is eliminated, and the JFET resistance is also eliminated; meanwhile, the groove grid structure of the groove type MOSFET device enables the interval of cells to be smaller than that of the plane type MOSFET device, more cells can be connected in parallel in design, and the total resistance is further reduced, so that the groove type MOSFET device can obtain smaller on-resistance.
In the transfer characteristic curve, when the threshold voltage does not change with a change in temperature at a certain gate-source voltage, this point is referred to as point a. When the actual gate-source voltage is smaller than the gate-source voltage at the point A, the threshold voltage of the trench super-junction silicon MOSFET is inversely related to the temperature, namely, the higher the temperature is, the lower the threshold voltage of the super-junction silicon MOSFET is. The wider and shallower the conduction channel of the super-junction silicon MOSFET is opened, the larger the generated channel current is; the increase of the channel current can lead to the heating temperature of the MOSFET device to be increased, the threshold voltage to be reduced due to the temperature increase, and the output current of the super-junction silicon MOSFET is increased, so that positive feedback is formed, and the super-junction silicon MOSFET device is in thermal failure.
Disclosure of Invention
In order to solve at least one technical problem, the present invention provides a trench type super-junction silicon MOSFET and a method for manufacturing the same, so as to solve the problem of thermal instability of the trench type super-junction silicon MOSFET.
The aim of the invention is realized by adopting the following technical modes:
In a first aspect, the present invention provides a trench super junction silicon MOSFET comprising: trench gate, P-pillar and N-pillar;
The trench gate includes a first extension and a second extension;
The first extension is positioned between and adjacent to the Pwell layers;
the second extension is located between and adjacent to the Pwell layer, the first extension, the P-pillar, and the N-pillar;
The first end of the first extension part is connected with the second extension part;
the first extension part and the second extension part form an inverted T shape;
The P column is positioned among the Pwell layer, the second extension part, the N column and the substrate;
the P-pillars are adjacent to the Pwell layer, the N-pillars, and the substrate;
the N column is positioned among the second extension part, the P column and the substrate;
The N-pillar is contiguous with the substrate.
Preferably, the trench gate further comprises a third extension;
the third extension is positioned above the Pwell layer and the first extension and is adjacent to the Pwell layer;
the third extension part is connected with the second end of the first extension part;
The first extension portion, the second extension portion and the third extension portion form an I shape.
Preferably, the length of the second extension is 300-600nm.
Preferably, the thickness of the second extension is 300nm.
Preferably, the length of the third extension is 300-600nm.
Preferably, the thickness of the third extension is 300nm.
Preferably, the width of the P column is 3.5um;
the width of the N column is 3.5um.
Preferably, the doping concentration of the P column is 6×10 15cm-3;
the doping concentration of the N column is 6×10 15cm-3.
Preferably, the method further comprises: a drain, a substrate, a Pwell layer, a p+ layer, an n+ layer, and a source;
The drain electrode is positioned below the substrate;
the substrate is positioned below the P column and the N column;
The Pwell layer is positioned above the P column;
the P+ layer and the N+ layer are positioned above the Pwell layer;
the source is located above the n+ layer.
In a second aspect, the invention provides a method for preparing a trench super junction silicon MOSFET, comprising the following steps:
epitaxially forming a P column and an N column above the substrate;
Depositing a first oxide layer and a polycrystalline material over the P and N pillars;
Etching the first oxide layer and the polycrystalline material;
depositing a second oxide layer over and on the side walls of the polycrystalline material to form second extension portions;
Extending the P column to the height of the second extension part;
depositing an active layer over the P-pillars and the second extension;
etching the active layer above the second oxide layer to form a trench;
Ion implantation is carried out on the active layer at two sides of the groove to form a Pwell layer;
Depositing a third oxide layer over the Pwell layer and on the sidewalls of the trench;
etching the second oxide layer and the third oxide layer;
depositing the polycrystalline material along the third oxide layer to form a first extension and a third extension;
forming an N+ layer and a P+ layer by ion implantation on the upper layer of the Pwell layer;
Depositing a fourth oxide layer over the third extension, the n+ layer, and the p+ layer;
and etching the fourth oxide layer above the N+ layer to form a contact hole.
Compared with the prior art, the invention has the beneficial effects that:
according to the invention, the trench is extended on the basis of the traditional vertical trench, so that the length of the gate positioned in the trench is increased, the channel length of the super-junction silicon MOSFET is increased due to the increase of the gate length, the source voltage corresponding to the point A is reduced due to the increase of the channel length, the negative feedback range is reduced, the threshold voltage is increased due to the increase of the temperature, and therefore, the channel current is reduced, and the thermal stability of the super-junction silicon MOSFET device is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
In order to more clearly describe the embodiments of the present application or the technical solutions in the background art, the following description will describe the drawings that are required to be used in the embodiments of the present application or the background art.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the technical aspects of the disclosure.
Fig. 1 is a schematic structural diagram of a trench super-junction silicon MOSFET according to an embodiment of the present invention;
fig. 2 is a schematic flow chart of a method for manufacturing a trench super-junction silicon MOSFET according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram a of a method for manufacturing a trench super-junction silicon MOSFET according to an embodiment of the present invention;
Fig. 4 is a schematic structural diagram B of a method for manufacturing a trench super-junction silicon MOSFET according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram C of a method for manufacturing a trench super-junction silicon MOSFET according to an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present application, a technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The terms first, second and the like in the description and in the claims and in the above-described figures are used for distinguishing between different objects and not necessarily for describing a sequential or chronological order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
The term "and/or" is herein merely an association relationship describing an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, C, may mean including any one or more elements selected from the group consisting of A, B and C.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better illustration of the invention. It will be understood by those skilled in the art that the present invention may be practiced without some of these specific details. In some instances, well known methods, procedures, components, and circuits have not been described in detail so as not to obscure the present invention.
In the transfer characteristic curve, when the threshold voltage does not change with a change in temperature at a certain gate-source voltage, this point is referred to as point a. When the actual gate-source voltage is smaller than the gate-source voltage at the point A, the threshold voltage of the super-junction silicon MOSFET is inversely related to the temperature, namely, the higher the temperature is, the lower the threshold voltage of the super-junction silicon MOSFET is. The wider and shallower the conduction channel of the super-junction silicon MOSFET is opened, the larger the generated channel current is; the increase of the channel current can lead to the heating temperature of the MOSFET device to be increased, the threshold voltage to be reduced due to the temperature increase, and the output current of the super-junction silicon MOSFET is increased, so that positive feedback is formed, and the super-junction silicon MOSFET device is in thermal failure.
According to the invention, the trench is extended on the basis of the traditional vertical trench, so that the length of the gate positioned in the trench is increased, the channel length of the super-junction silicon MOSFET is increased due to the increase of the gate length, the source voltage corresponding to the point A is reduced due to the increase of the channel length, the negative feedback range is reduced, the threshold voltage is increased due to the increase of the temperature, and therefore, the channel current is reduced, and the thermal stability of the super-junction silicon MOSFET device is improved.
Example 1
There is provided a trench superjunction silicon MOSFET, see fig. 1, comprising: trench gate, P-pillar and N-pillar;
the trench gate comprises a first extension part and a second extension part;
The first extension part is positioned between and adjacent to the Pwell layers;
the second extension part is positioned between and adjacent to the Pwell layer, the first extension part, the P column and the N column;
the first end of the first extension part is connected with the second extension part;
the first extension part and the second extension part form an inverted T shape;
The channel is a thin semiconductor layer between the source and drain of a MOSFET, and applying an external electric field to the MOSFET is a common method of turning on the channel of a MOSFET. When a voltage is applied to the MOSFET gate, an inversion layer is formed in the MOSFET in the direction of the electric field, in which current flows and is gate controlled. The thermal failure refers to the phenomenon that the performance of the MOSFET is reduced or the MOSFET is completely failed in a high-temperature environment, the channel current is inversely related to the length of the channel, and the excessive channel current can cause the heating temperature of the MOSFET device to be increased, so that the MOSFET device is thermally failed.
In this embodiment, the first extension portion is a vertical portion in the middle of the trench gate, and the second extension portion is a horizontal portion at the bottom of the trench gate, and the second extension portion is obtained by extending the bottom of the first extension portion on the basis of the first extension portion. The inverted T-shaped trench gate formed by the first extension part and the second extension part has the gate length increased compared with the vertical trench gate, so that the trench length of the super-junction silicon MOSFET is increased, and the thermal stability of the super-junction silicon MOSFET device is improved.
The P column is positioned among the Pwell layer, the second extension part, the N column and the substrate;
the P column is adjacent to the Pwell layer, the N column and the substrate;
The N column is positioned between the second extension part, the P column and the substrate;
The N pillars are adjacent to the substrate.
For a MOSFET device of a traditional structure, the reverse voltage resistance is mainly realized by a single N-type doped drift region. From the PN junction, the electric field gradually decreases. In order to increase the breakdown voltage, it is necessary to increase the thickness of the drift region or decrease the doping concentration of the drift region, but such a condition leads to an increase in on-resistance. Superjunction structures have been proposed to address the silicon limit issue. The super junction structure can introduce an additional electric field in the body of the device, so that the on-resistance of the device under the same breakdown voltage is greatly reduced. Compared with the traditional structure, the super junction structure greatly reduces the energy loss and realizes more efficient energy use efficiency. The super junction structure is characterized in that an original single doped N-type drift region is changed into a doped N-type drift region and a doped P-type drift region, two charges are mutually compensated transversely and the longitudinal electric field becomes quite uniform when the super junction structure is subjected to reverse voltage resistance, so that the breakdown voltage of the device is increased. In addition, the doping concentration of the super-junction structure drift region is higher than that of the traditional structure drift region, so that the breakdown voltage is improved, and meanwhile, the on-resistance of the MOSFET device is reduced.
To ensure that the high voltage power MOSFET has sufficient breakdown voltage, the most straightforward way to reduce on-resistance is to separate the reverse blocking voltage from the on-resistance function, and design them in different regions. In this embodiment, the N pillars are sandwiched between the P pillars on both sides, and when the trench MOSFET device is turned off, two reverse biased PN junctions are formed, P and N pillars and P-well and N pillars, respectively. The P-well cannot form an inversion layer to generate a conductive channel, the P column and the N column are reversely biased, the PN junction depletion layer is increased, and a transverse electric field is established; the PN junction formed by the P-well and N columns is also reverse biased, creating a wide depletion layer and establishing a vertical electric field. The entire region of the N pillar becomes substantially the depletion layer with a very high vertical blocking voltage. When the groove type MOSFET device is conducted, the electric field of the grid electrode and the source electrode is inverted to form a P-well type conduction channel, electrons in the source electrode area enter the N column through the conduction channel, holes in the N column are neutralized, and therefore the doping concentration of the N column is recovered, and therefore the conduction channel is formed. The doping concentration of the N column is increased, so that the N column has lower resistivity, and the on-resistance is reduced.
Preferably, the trench gate further comprises a third extension;
The third extension is positioned above and adjacent to the Pwell layer and the first extension;
The third extension part is connected with the second end of the first extension part;
The first extension part, the second extension part and the third extension part form an I shape.
There is a limitation in extending the bottom of the first extension to obtain the second extension to increase the length of the trench gate. The second extension portion occupies the space of the N-drift layer in the horizontal direction, and in the actual manufacturing process, the area of the super-junction silicon MOSFET device can be increased due to the fact that the length of the second extension portion is too long. In some embodiments, the third extension is a horizontal portion at the top of the trench gate, and the second extension and the third extension are obtained by respectively extending the bottom and the top of the first extension on the basis of the first extension. The H-shaped trench gate formed by the first extension part, the second extension part and the third extension part has the gate length increased compared with the vertical trench gate, so that the trench length of the super-junction silicon MOSFET is increased, and the thermal stability of the super-junction silicon MOSFET device is improved.
Preferably, the length of the second extension is 300-600nm.
The gate acts as a control element of the MOSFET for controlling the opening and closing of the channel, the length of which depends on the length of the gate. The increase of the channel length can reduce the channel current, thereby reducing the heating temperature of the MOSFET and improving the thermal stability of the MOSFET device. However, the excessively long length of the groove can increase the on-resistance of the MOSFET, and the working efficiency and the power processing capacity of the MOSFET are reduced; too long a trench length can also reduce the switching speed of the MOSFET, and reduce the response speed of the MOSFET; too long a trench length can also increase the leakage current of the MOSFET, increasing the power consumption of the MOSFET. In designing a MOSFET, the choice of channel length needs to be balanced to balance the performance and stability of the MOSFET. In this embodiment, the length of the second extension is set to 300-600nm, and as a preferred embodiment, the present invention sets the length of the second extension to 500nm. The length of the second extension portion refers to the length in the horizontal direction.
Preferably, the thickness of the second extension is 300nm.
The thickness of the gate can affect the performance of the MOSFET device. The larger gate thickness can provide a larger current path, so that the switching speed of the MOSFET device is improved, and meanwhile, the MOSFET device is not easily influenced by charge accumulation and heat accumulation, and the reliability of the MOSFET device is improved; but a larger gate thickness results in greater power and heat generation, increasing the power consumption of the MOSFET device. In designing a MOSFET, it is necessary to select an appropriate gate thickness to ensure that the MOSFET device operates reliably and reliably. In the present embodiment, the thickness of the second extension portion is set to 300nm, and the thickness of the third extension portion is set to 300nm.
Preferably, the length of the third extension is 300-600nm.
There is a limitation in extending the bottom of the first extension to obtain the second extension to increase the length of the trench gate. The second extension portion occupies the space of the N-drift layer in the horizontal direction, and in the actual manufacturing process, the area of the super-junction silicon MOSFET device can be increased due to the fact that the length of the second extension portion is too long. And the top of the first extension part is extended to obtain a third extension part, and the second extension part and the third extension part jointly increase the length of the grid electrode. In some embodiments, the length of the third extension is set to 300-600nm, and as a preferred embodiment, the present invention sets the length of the second extension to 300nm and the length of the third extension to 300nm. The length of the third extension portion refers to the length in the horizontal direction thereof.
Preferably, the thickness of the third extension is 300nm.
The thickness of the gate can affect the performance of the MOSFET device. The larger gate thickness can provide a larger current path, so that the switching speed of the MOSFET device is improved, and meanwhile, the MOSFET device is not easily influenced by charge accumulation and heat accumulation, and the reliability of the MOSFET device is improved; but a larger gate thickness results in greater power and heat generation, increasing the power consumption of the MOSFET device. In designing a MOSFET, it is necessary to select an appropriate gate thickness to ensure that the MOSFET device operates reliably and reliably. In some embodiments, the thickness of the third extension is set to 300nm.
Preferably, the width of the P-pillars is 3.5um;
the width of the N pillars is 3.5um.
When the widths of the P column and the N column are properly controlled, the N column can be completely depleted, so that free charges are not generated in the N column, the middle transverse electric field is very high, and only if the external voltage is larger than the internal transverse electric field, the region can be broken down. The widths of the P column and the N column are set at larger widths, when the groove type MOSFET is in an off state, a depletion layer formed between the P column and the N column is thinner, the N column cannot be completely depleted, and the breakdown voltage of the groove type MOSFET is reduced compared with that of the MOSFET with the completely depleted N column; when the trench MOSFET is in an on state, the N column has a lower doping concentration and a higher resistivity, resulting in an increase in the on-resistance of the trench MOSFET. While the widths of the P and N pillars are set to be smaller, the on-resistance of the trench MOSFET can be reduced, but the breakdown voltage reduction problem needs to be considered. In this embodiment, the width of the P column is set to 3.5um, and the width of the n column is set to 3.5um.
Preferably, the doping concentration of the P column is 6×10 15cm-3;
The doping concentration of the N column was 6×10 15cm-3.
Complete depletion of the N-pillars can also be achieved by adjusting the doping concentrations of the P-pillars and N-pillars. When the doping concentrations of the P column and the N column are properly controlled, the N column can be completely depleted, so that free charges are not generated in the N column, the middle transverse electric field is very high, and only if the external voltage is larger than the internal transverse electric field, the region can be broken down. The doping concentrations of the P column and the N column are set at lower concentrations, when the groove type MOSFET is in an off state, a depletion layer formed between the P column and the N column is thinner, the N column cannot be completely depleted, and the breakdown voltage of the groove type MOSFET is reduced compared with that of the MOSFET with the completely depleted N column; when the trench MOSFET is in an on state, the N column has a lower doping concentration and a higher resistivity, resulting in an increase in the on-resistance of the trench MOSFET. The doping concentrations of the P-pillar and the N-pillar are set at higher concentrations, which can reduce the on-resistance of the trench MOSFET device, but also take into consideration the problems of reduced breakdown voltage and high cost. In the present embodiment, the doping concentration of the P column is set to 6×10 15cm-3, and the doping concentration of the N column is set to 6×10 15cm-3.
Preferably, the method further comprises: a drain, a substrate, a Pwell layer, a p+ layer, an n+ layer, and a source;
The drain electrode is positioned below the substrate;
the substrate is positioned below the P column and the N column;
The Pwell layer is positioned above the P column;
the P+ layer and the N+ layer are positioned above the Pwell layer;
The source electrode is located above the n+ layer.
Example 2
A preparation method of a trench type super junction silicon MOSFET is provided, see fig. 2, 3, 4 and 5, comprising:
S100, epitaxially forming a P column and an N column above a substrate;
The epitaxial process refers to a process of growing a single crystal layer in complete alignment on a substrate, and the epitaxial process is a process of growing a crystal layer in the same lattice orientation as the original substrate on a single crystal substrate. Epitaxial processes are widely used in semiconductor manufacturing, such as epitaxial silicon wafers in the integrated circuit industry. The epitaxial growth modes are classified into solid phase epitaxy, liquid phase epitaxy and gas phase epitaxy according to the different phase states of the growth source. In integrated circuit fabrication, common epitaxy methods are solid phase epitaxy and vapor phase epitaxy.
Solid phase epitaxy refers to the process of growing a single crystal layer on a substrate by a solid source, such as thermal annealing after ion implantation, which is essentially a solid phase epitaxy process. During ion implantation processing, silicon atoms of the silicon wafer are bombarded by high-energy implantation ions and are separated from the original lattice positions, amorphization occurs, and a surface amorphous silicon layer is formed; and then, after high-temperature thermal annealing, the amorphous atoms return to the lattice positions again and keep consistent with the crystal orientation of the atoms in the substrate.
The growth method of vapor phase epitaxy includes chemical vapor phase epitaxy (CVE), molecular beam epitaxy (MBD), atomic Layer Epitaxy (ALE), and the like. The principle of chemical vapor epitaxy is basically the same as that of Chemical Vapor Deposition (CVD), and the process of depositing a film is carried out by mixing gases and then carrying out chemical reaction on the surface of a wafer; in contrast, since the single crystal layer is grown by chemical vapor epitaxy, the impurity content in the apparatus and the cleanliness of the silicon wafer surface are both higher. CVE can also be used in epitaxial silicon wafer processes and MOS transistor embedded source drain epitaxial processes in integrated circuit fabrication. The epitaxial silicon wafer process is to epitaxial a layer of monocrystalline silicon on the surface of the silicon wafer, and compared with the original substrate, the epitaxial silicon layer has higher purity and fewer lattice defects, so that the yield of semiconductor manufacture is improved. In addition, the growth thickness and doping concentration of the epitaxial silicon layer grown on the silicon wafer can be flexibly designed, which brings flexibility to the design of the device, such as being used for reducing the substrate resistance, enhancing the substrate isolation and the like. The embedded source-drain epitaxy process refers to a process of growing doped silicon germanium or silicon outside the source-drain region of the transistor. The main advantages of introducing the embedded source drain epitaxy process include: a pseudomorphic layer containing stress due to lattice adaptation can be grown, and channel carrier mobility is improved; the source and drain can be doped in situ, the parasitic resistance of the source and drain junction is reduced, and the defect of high-energy ion implantation is reduced.
S200, depositing a first oxide layer and polycrystalline material above the P column and the N column;
S300, etching the first oxide layer and the polycrystalline material;
Etching is a process of selectively removing unwanted material from the surface of a silicon wafer by chemical or physical means, and is a generic term for stripping and removing material by solution, reactive ions or other mechanical means. The etching technology is mainly divided into dry etching and wet etching. The dry etching mainly uses the reaction gas and the plasma for etching; the wet etching mainly uses chemical reagents to chemically react with the etched material for etching.
Ion beam etching is a physical dry etching process. Thereby, argon ions are irradiated onto the surface with an ion beam of about 1 to 3 keV. Due to the energy of the ions, they strike the material of the surface. The wafer is vertically or obliquely directed into the ion beam and the etching process is absolutely anisotropic. The selectivity is low because it is not different for each layer. The gases and abraded material are evacuated by the vacuum pump, but since the reaction products are not gaseous, particles can deposit on the wafer or chamber walls. All materials can be etched in this way and the wear on the vertical walls is low due to the vertical radiation.
Plasma etching is a chemical etching process and has the advantage that the wafer surface is not damaged by accelerated ions. The method is used to remove the entire film (e.g., backside cleaning after thermal oxidation) because the etch profile is isotropic due to the movable particles of the etch gas. One type of reactor used for plasma etching is a downstream reactor whereby the plasma is ignited at a high frequency of 2.45GHz by impact ionization, the location of which is separated from the wafer.
The etch rate depends on the pressure, the power of the high frequency generator, the process gas, the actual gas flow and the wafer temperature. Anisotropy increases with an increase in high-frequency power, a decrease in pressure, and a decrease in temperature. The uniformity of the etching process depends on the gas, the distance between the two electrodes and the material of the electrodes. If the distance is too small, the plasma cannot be unevenly dispersed, resulting in non-uniformity. If the distance of the electrodes is increased, the etch rate is reduced because the plasma is distributed in the enlarged volume. Carbon has proven to be the material of choice for electrodes. Since fluorine and chlorine also attack carbon, the electrodes produce a uniformly strained plasma and the wafer edge is affected by the same effect as the wafer center. The selectivity and etch rate are largely dependent on the process gas. For silicon and silicon compounds, fluorine gas and chlorine gas are mainly used.
S400, depositing a second oxide layer on the upper side and the side wall of the polycrystalline material to form a second extension part;
s500, extending the height from the P column to the second extension part;
s600 depositing an active layer over the P pillars and the second extension;
S700, etching the active layer above the second oxide layer to form a groove;
s800, forming a Pwell layer by ion implantation of active layers at two sides of the groove;
Ion implantation is the emission of an ion beam in vacuum towards a solid material, which, after being directed towards the solid material, is slowly slowed down by the resistance of the solid material and finally stays in the solid material. Ions of one element are accelerated into a solid target, thereby altering the physical, chemical or electrical properties of the target. Ion implantation is commonly used in the fabrication of semiconductor devices, metal surface treatment, and materials science research. If the ions stop and remain in the target, the ions change the elemental composition of the target (if the ions differ from the composition of the target). The ion implantation beam line design includes a common set of functional elements. The main part of the ion beam line comprises an apparatus called ion source for generating ion species. The source is tightly coupled to a bias electrode to extract ions into the beam line and most commonly to some way of selecting a particular ion species for transmission into the main accelerator section. The mass selection is accompanied by the extracted ion beam passing through a region of the magnetic field whose exit path is limited by a blocking aperture or slit which only allows ions to have mass and velocity/charge to continue along the beam line. If the target surface is larger than the ion beam diameter and the implant dose is uniformly distributed over the target surface, some combination of beam scanning and wafer motion may be used. Finally, the implanted surface is combined with some method for collecting the accumulated charge of the implanted ions so that the delivered dose can be measured in a continuous manner and the implantation process stopped at the desired dose level.
Doping semiconductors with boron, phosphorus or arsenic is a common application of ion implantation. When implanted into a semiconductor, each doping atom may generate charge carriers in the semiconductor after annealing. A hole may be created for the P-type dopant and an electron may be created for the N-type dopant. The conductivity of the semiconductor near the doped region is changed.
S900, depositing a third oxide layer above the Pwell layer and on the side wall of the groove;
S1000, etching the second oxide layer and the third oxide layer;
The gate oxide layer is a critical part of the semiconductor device structure and its growth process refers to the process of depositing an oxide layer on a substrate. The principle of gate oxide formation mainly involves two processes, namely oxidation and diffusion. In the oxidation reaction, oxygen chemically reacts with silicon atoms on the substrate surface to form silicon dioxide. During diffusion, oxygen diffuses downward through the already formed silicon dioxide, increasing the thickness of the oxide layer. In the integrated circuit manufacturing process, the method for forming the gate oxide layer mainly comprises a thermal oxidation method and a chemical vapor deposition method. The thermal oxidation method is a method of growing an oxide layer by thermal oxidation reaction in a high temperature oxygen atmosphere, and the chemical vapor deposition method is a method of forming silicon dioxide deposited on a substrate by heating and decomposing a chemical gas in a gas phase. The oxidation process refers to a process of forming silicon dioxide on the surface of a substrate by a thermal oxidation method. The oxidation process is divided into dry oxidation and wet oxidation. Dry oxygen oxidation is to take dry pure oxygen as an oxidation atmosphere, directly react with silicon at a high temperature of about 1000 ℃, the dry oxygen oxidation rate is lower than that of wet oxygen oxidation, the time of the dry oxygen oxidation is usually as long as 2 hours, and the time of the wet oxygen oxidation is shortened to about 12 minutes, but the quality of an oxidized film is higher than that of the wet oxygen oxidation, so that the growth of a shielding oxide layer, a substrate oxide layer and a gate oxide layer with thinner thickness is generally oxidized by dry oxygen. Wet oxygen oxidation is the replacement of oxygen with water, which at high temperatures decomposes to HO, which diffuses at a higher rate in silica than dry oxygen oxidation. Wet oxygen oxidation is used to grow thicker oxide layers such as shadow oxide, full area coverage oxide, LOCOS oxide, etc. In the wet oxygen oxidation method, oxygen firstly passes through deionized water at 95-98 ℃ to bring water vapor into an oxidation furnace, and the oxygen and the water vapor are subjected to oxidation reaction with silicon at the same time. The quality of the silicon dioxide film produced by the oxidation method is slightly poorer than that of the silicon dioxide film produced by the dry oxidation method, but the silicon dioxide film has better effect than that of the water vapor oxidation method, and the growth speed is faster. Therefore, in the case where the thickness of the oxide layer is thick and the electrical properties of the oxide layer are not required, such a method is often employed for productivity. The equipment of the thermal oxidation method mainly comprises two types of horizontal type equipment and vertical type equipment. Wafers with a size below 6 inches all use a horizontal oxidation oven and wafers with a size above 8 inches all use a vertical oxidation oven. Both the oxidation furnace and the wafer boat carrying the wafers are made of quartz materials. In the oxidation process, to prevent impurity pollution and metal pollution, in order to reduce human factors, automatic control is mostly adopted in modern manufacturing.
In this embodiment, the deposited first oxide layer, second oxide layer, and third oxide layer together form the gate oxide layer.
S1100, depositing polycrystalline material along the third oxide layer to form a first extension part and a third extension part;
Chemical vapor deposition is a commonly used method for preparing polysilicon. Chemical vapor deposition is performed by decomposing a silicon source gas into silicon atoms at a high temperature and depositing a polysilicon film on the surface of a substrate. In the chemical vapor deposition method, the deposition process is realized by controlling parameters such as gas flow, temperature, pressure and the like. The prepared silicon source gas is first introduced into the reaction chamber through a gas inlet and mixed with an inert carrier gas such as hydrogen. And then brought to an appropriate temperature, typically between 600 and 700 degrees celsius, by heating the reaction. Under high temperature conditions, the silicon source gas will decompose to form silicon atoms and deposit on the substrate surface. Deposition rate and film quality can be controlled by adjusting reaction temperature, gas flow rate, pressure, and other parameters.
In this embodiment, the trench gate is formed by depositing a polycrystalline material on the first oxide layer, the second oxide layer, and the third oxide layer.
S1200, forming an N+ layer and a P+ layer by ion implantation on the upper layer of the Pwell layer;
s1300, depositing a fourth oxide layer above the third extension part, the N+ layer and the P+ layer;
and S1400, etching the fourth oxide layer above the N+ layer to form a contact hole.
According to the embodiment, the trench is extended on the basis of the traditional vertical trench, so that the length of a gate positioned in the trench is increased, the channel length of the super-junction silicon MOSFET is increased due to the increase of the length of the gate, the source voltage of the gate corresponding to the point A is reduced due to the increase of the channel length, the range of negative feedback is reduced, the threshold voltage is increased due to the increase of the temperature, the channel current is reduced, and the thermal stability of the super-junction silicon MOSFET device is improved.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (5)
1. A trench superjunction silicon MOSFET comprising: trench gate, P-pillar and N-pillar;
The trench gate includes a first extension and a second extension;
The first extension is positioned between and adjacent to the Pwell layers;
The depth of the first extension is the same as the depth of the Pwell layer;
the second extension is located between and adjacent to the Pwell layer, the first extension, the P-pillar, and the N-pillar;
The first end of the first extension part is connected with the second extension part;
the first extension part and the second extension part form an inverted T shape;
The P column is positioned among the Pwell layer, the second extension part, the N column and the substrate;
the P-pillars are adjacent to the Pwell layer, the N-pillars, and the substrate;
the N column is positioned among the second extension part, the P column and the substrate;
the N column is adjacent to the substrate;
the trench gate further includes a third extension;
the third extension is positioned above the Pwell layer and the first extension and is adjacent to the Pwell layer;
the third extension part is connected with the second end of the first extension part;
the first extension part, the second extension part and the third extension part form an I shape;
The length of the second extension part is 300-600nm;
The thickness of the second extension part is 300nm;
the length of the third extension part is 300-600nm;
The thickness of the third extension is 300nm.
2. The trench super junction silicon MOSFET of claim 1, wherein said P-pillar has a width of 3.5um;
the width of the N column is 3.5um.
3. The trench super-junction silicon MOSFET of claim 1, wherein said P-pillar has a doping concentration of 6 x 10 15cm-3;
the doping concentration of the N column is 6×10 15cm-3.
4. The trench super-junction silicon MOSFET of claim 1, further comprising: a drain, a substrate, a Pwell layer, a p+ layer, an n+ layer, and a source;
The drain electrode is positioned below the substrate;
the substrate is positioned below the P column and the N column;
The Pwell layer is positioned above the P column;
the P+ layer and the N+ layer are positioned above the Pwell layer;
the source is located above the n+ layer.
5. A method for preparing a trench super-junction silicon MOSFET, applied to a trench super-junction silicon MOSFET as set forth in any one of claims 1 to 4, comprising:
epitaxially forming a P column and an N column above the substrate;
Depositing a first oxide layer and a polycrystalline material over the P and N pillars;
Etching the first oxide layer and the polycrystalline material;
depositing a second oxide layer over and on the side walls of the polycrystalline material to form second extension portions;
Extending the P column to the height of the second extension part;
depositing an active layer over the P-pillars and the second extension;
etching the active layer above the second oxide layer to form a trench;
Ion implantation is carried out on the active layer at two sides of the groove to form a Pwell layer;
Depositing a third oxide layer over the Pwell layer and on the sidewalls of the trench;
etching the second oxide layer and the third oxide layer;
depositing the polycrystalline material along the third oxide layer to form a first extension and a third extension;
forming an N+ layer and a P+ layer by ion implantation on the upper layer of the Pwell layer;
Depositing a fourth oxide layer over the third extension, the n+ layer, and the p+ layer;
and etching the fourth oxide layer above the N+ layer to form a contact hole.
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