CN116978954A - Groove type MOSFET device and manufacturing method - Google Patents

Abstract

The invention discloses a trench type MOSFET device and a manufacturing method. The trench type MOSFET device includes a source, a gate, a drain, a source region and a substrate. The drain, the source and the substrate The gate is located on the same side of the source region; the drain is in contact with the substrate through TSV. In the present invention, the drain originally located at the bottom of the trench MOSFET device is connected to one side of the source and gate through the TSV and in contact with the substrate. No additional device is required to lead out the drain pin during packaging, which reduces the The area and thickness of the package.

Description

Trench MOSFET device and manufacturing method

Technical field

The present invention relates to the field of semiconductor technology, and in particular to a trench MOSFET device and a manufacturing method.

Background technique

An example of a semiconductor device is a metal oxide silicon field effect transistor device, known as a MOSFET device, which is used in many electronic devices, including power supplies, automotive electronics, computers, and disk drives. MOSFET devices can be used in many applications, such as switches that connect power to specific electronic devices with loads. MOSFET devices can be formed in trenches that have been etched into the substrate or etched into the epitaxial layer. MOSFET devices operate by applying an appropriate voltage to the MOSFET device's gate electrode, which turns the device on and forms a channel connecting the source and drain of the MOSFET device, allowing current to flow.

As the core power electronic device of power control, power semiconductor devices are used in the conversion and control of electric energy. In recent years, the demand for power semiconductor devices in various fields such as new energy vehicles, high-speed trains, photovoltaics, wind power, mobile phones, computers, televisions, and air conditioners has greatly increased, promoting the rapid development of this field. As an important power semiconductor device, MOSFET's gate can both turn on and turn off the device through voltage control. It has the advantages of high input impedance and low conduction loss. It is currently widely used in switching power supplies, Motor control, mobile communications and other fields.

With the development of electronic manufacturing, MOSFETs are developing in the direction of ultra-thin and miniaturization. Trench MOSFET is a new vertical structure MOSFET device optimized and developed from the traditional planar MOSFET structure. The source and gate of existing trench MOSFET devices are located at the top of the device, and their drain is located at the bottom of the device and in contact with the substrate. The device structure in which the source metal, gate metal and drain metal are located on different sides results in the trench MOSFET device needing to use a lead frame or copper clip to connect the drain to the front of the device during the packaging process, and then bond it to the PCB. The processing and packaging method increases the packaging area and packaging thickness of MOSFET.

Contents of the invention

In order to solve at least one of the technical problems raised above, the purpose of the present invention is to provide a trench MOSFET device and a manufacturing method. The drain originally located at the bottom of the trench MOSFET device is connected to the source and gate through a TSV. Side and in contact with the substrate, no additional device is required to lead out the drain pin during packaging, which reduces the area and thickness of the package.

The purpose of the present invention is achieved by adopting the following technical solutions:

In a first aspect, the present invention provides a trench MOSFET device, including a source electrode, a gate electrode, a drain electrode, a source electrode region and a substrate, and the drain electrode, the source electrode and the gate electrode are located on the The same side of the source region; the drain is in contact with the substrate through the TSV.

Preferably, it also includes an epitaxial layer and a body region, and the body region is located above the epitaxial layer;

The epitaxial layer is located above the substrate;

The body region is located below the source region;

The source region is in contact with the source.

Preferably, it also includes a trench that passes through the source region and the body region, the bottom of the trench is located inside the epitaxial layer, the inner wall of the trench has a gate oxide layer, and the gate The oxygen layer is in contact with the gate.

Preferably, the substrate is an N+ type substrate;

The epitaxial layer is an N-type epitaxial layer;

The body region is a P-type body region;

The source region is an N+ type source region.

Preferably, the substrate is a P+ type substrate;

The epitaxial layer is a P-type epitaxial layer;

The body region is an N-type body region;

The source region is a P+ type source region.

Preferably, the through hole diameter of the TSV is 2-10um.

Preferably, the aspect ratio of the TSV is 3:1-15:1.

Preferably, the filling material of the TSV is copper.

In a second aspect, the present invention provides a method for manufacturing a trench MOSFET device, including:

Deposit an epitaxial layer over the substrate;

forming a body region and a source region above the epitaxial layer;

A first through hole is opened in the source region and the body region, a trench is opened in the upper layer of the epitaxial layer, and the first through hole is connected to the trench;

Perform TSV processing.

Preferably, performing TSV processing includes:

A second through hole is opened in the source region, and the bottom of the second through hole is located inside the substrate;

Deposit and form an insulating layer on the sidewall of the second through hole;

Deposit and form a barrier layer on the sidewall of the second through hole;

Fill the second through hole;

The metal above the second through hole is connected to the substrate through the second through hole to form a drain electrode.

Compared with the existing technology, the beneficial effects of the present invention are:

In the present invention, the drain originally located at the bottom of the trench MOSFET device is connected to one side of the source and gate through TSV and in contact with the substrate. No additional device is required to lead out the drain pin during packaging, which reduces the cost The area and thickness of the package.

It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not restrictive of the disclosure.

Description of the drawings

In order to more clearly explain the technical solutions in the embodiments of the present application or the background technology, the drawings required to be used in the embodiments or the background technology of the present application will be described below.

The accompanying drawings herein are incorporated into and constitute a part of this specification. They illustrate embodiments consistent with the disclosure and, together with the description, serve to explain the technical solutions of the disclosure.

Figure 1 is a schematic structural diagram of a trench MOSFET device provided by an embodiment of the present invention;

FIG. 2 is a flow chart of a manufacturing method of a trench MOSFET device provided by an embodiment of the present invention.

Detailed ways

In order to enable those in the technical field to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only These are part of the embodiments of this application, but not all of them. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

The terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish different objects, rather than describing a specific sequence. Furthermore, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units that are not listed, or optionally also includes Other steps or units inherent to such processes, methods, products or devices.

The term "and/or" in this article is just an association relationship that describes related objects, indicating that three relationships can exist. For example, A and/or B can mean: A exists alone, A and B exist simultaneously, and they exist alone. B these three situations. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, and C, which can mean including from A, Any one or more elements selected from the set composed of B and C.

Reference herein to "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The appearances of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those skilled in the art understand, both explicitly and implicitly, that the embodiments described herein may be combined with other embodiments.

In addition, in order to better explain the present invention, numerous specific details are given in the following detailed description. It will be understood by those skilled in the art that the present invention may be practiced without certain specific details. In some instances, methods, means, components and circuits that are well known to those skilled in the art are not described in detail in order to emphasize the gist of the present invention.

As the core power electronic device of power control, power semiconductor devices are used in the conversion and control of electric energy. In recent years, the demand for power semiconductor devices in various fields such as new energy vehicles, high-speed trains, photovoltaics, wind power, mobile phones, computers, televisions, and air conditioners has greatly increased, promoting the rapid development of this field. As an important power semiconductor device, MOSFET's gate can both turn on and turn off the device through voltage control. It has the advantages of high input impedance and low conduction loss. It is currently widely used in switching power supplies, Motor control, mobile communications and other fields.

With the development of electronic manufacturing, MOSFETs are developing in the direction of ultra-thin and miniaturization. Trench MOSFET is a new vertical structure MOSFET device optimized and developed from the traditional planar MOSFET structure. The source and gate of existing trench MOSFET devices are located at the top of the device, and their drain is located at the bottom of the device and in contact with the substrate. The device structure in which the source metal, gate metal and drain metal are located on different sides results in the trench MOSFET device needing to use a lead frame or copper clip to connect the drain to the front of the device during the packaging process, and then bond it to the PCB. The processing and packaging method increases the packaging area and packaging thickness of MOSFET. In the present invention, the drain originally located at the bottom of the trench MOSFET device is connected to one side of the source and gate through TSV and in contact with the substrate. No additional device is required to lead out the drain pin during packaging, which reduces the cost The area and thickness of the package.

Example 1

The invention provides a trench type MOSFET device, which includes a source, a gate, a drain, a source region and a substrate. The drain, the source and the gate are located on the same side of the source region; the drain is connected to the source region through TSV. substrate contact.

Trench MOSFET is a common field effect transistor. The basic structure of trench MOSFET includes source, drain, gate and channel. Among them, the channel between the source and drain is the channel for current flow, and the gate is the switch that controls the current in the channel. The source metal and gate metal of the trench MOSFET are located above the silicon wafer, the lower part of the silicon wafer is the substrate, and the drain is located below the silicon wafer in contact with the substrate. Trench MOSFET, also known as surface effect transistor, buries the gate into the substrate to form a vertical channel. Although the process is complex, the unit consistency is worse than that of the planar structure. However, the trench structure can increase the cell density, has no JFET effect, smaller parasitic capacitance, fast switching speed, and very low switching loss; moreover, by selecting the appropriate channel crystal plane and optimizing the designed structure, the best channel can be achieved mobility, significantly reducing on-resistance. The trench MOSFET provided in this embodiment is different from the traditional trench MOSFET. The drain originally located at the bottom of the trench MOSFET device is connected to one side of the source and gate through the TSV and is in contact with the substrate.

Preferably, it also includes an epitaxial layer and a body region, and the body region is located above the epitaxial layer;

The epitaxial layer is located above the substrate;

The body region is located below the source region;

The source region is in contact with the source.

Epitaxy refers to the process of growing a new layer of single crystal on a single crystal substrate that has been carefully processed by cutting, grinding, polishing, etc. The new single crystal can be the same material as the substrate, or it can be a different material (homoepitaxial or heteroepitaxy). Because the new single crystal layer extends and grows according to the crystal phase of the substrate, it is called an epitaxial layer. The thickness of the epitaxial layer is usually a few microns. Taking silicon as an example: The meaning of silicon epitaxial growth is to grow a layer of crystal with the same crystal orientation as the substrate and different resistivity and thickness on a silicon single crystal substrate with a certain crystal orientation. A crystal with good lattice structure integrity, and a substrate with an epitaxial layer is called an epitaxial wafer, that is, epitaxial wafer = epitaxial layer + substrate. The fabrication of MOSFET devices is carried out on the epitaxial layer.

For the traditional silicon semiconductor industry chain, manufacturing devices on silicon wafers cannot meet the requirements of high breakdown voltage, small series resistance, and small saturation voltage drop in the collector area. The development of epitaxy technology has successfully solved this difficulty. Epitaxy technology grows a high-resistivity epitaxial layer on an extremely low-resistance silicon substrate, and the device is fabricated on the epitaxial layer. This high-resistivity epitaxial layer ensures that the tube has a high breakdown voltage, while the low-resistance substrate It also reduces the resistance of the substrate, thereby reducing the saturation voltage drop, thus resolving the contradiction between the two. In addition, epitaxy technologies such as vapor phase epitaxy and liquid phase epitaxy of GaAs and other III-V, II-VI and other molecular compound semiconductor materials have also been greatly developed and have become the basis for most microwave devices, optoelectronic devices and power devices. Indispensable process technologies for production, especially the successful application of molecular beam and metal-organic vapor phase epitaxy technology in thin layers, superlattices, quantum wells, strained superlattices, and atomic-level thin-layer epitaxy have become a new field of semiconductor research. The development of "Energy Belt Project" has laid a solid foundation.

Preferably, it also includes a trench, the trench passes through the source region and the body region, the bottom of the trench is located inside the epitaxial layer, the inner wall of the trench has a gate oxide layer, and the gate oxide layer is in contact with the gate electrode.

The trench refers to the channel area. Trench MOSFET can change the performance and characteristics of the transistor by adjusting the size of the trench. In order to form a vertical channel structure, a trench MOSFET is opened in the epitaxial layer. After an oxide layer is made on the surface of the trench, polysilicon is filled inside the trench to form a gate electrode. In this structure, the gate is buried in the matrix to form a vertical channel. The current path flows vertically from the drain electrode of the lower substrate through the epitaxial layer, channel and source area, and the channel is parallel to the current direction. The difference between the trench MOSFET provided in this embodiment and the traditional trench MOSFET is that the drain metal is provided in contact with the substrate through the TSV. The drain metal and the source metal and the second gate metal are located on the same plane. In this embodiment The current path of the trench MOSFET provided is from the drain metal through the TSV fill metal to the lower substrate, and then flows vertically through the epitaxial layer, channel and source region.

Gate oxide is the dielectric layer that separates the MOSFET's gate from the source and drain and the conductive path that connects the source and drain when the transistor is on. The gate oxide layer is formed by thermally oxidizing the silicon in the channel to form a thin silicon dioxide insulating layer. The insulating silicon dioxide layer is formed through a self-limiting oxidation process, which is described by the Deal–Grove model. A conductive gate material is then deposited over the gate oxide to form the transistor. The gate oxide serves as a dielectric layer so the gate can withstand lateral electric fields of up to 1 to 5MV/cm to strongly modulate the conductance of the channel. Above the gate oxide is a thin electrode layer made of a conductor, which can be aluminum, highly doped silicon, a refractory metal such as tungsten, a suicide (TiSi, MoSi2, TaSi or WSi2) or a sandwich of these layers. This gate electrode is often called the gate metal or gate conductor. The geometric width of the gate conductor electrode (transverse to the direction of current flow) is called the physical gate width. The physical gate width may differ slightly from the electrical channel width used to simulate the transistor because fringing electric fields have an effect on conductors that are not directly beneath the gate.

The electrical properties of the gate oxide are critical to the formation of the conductive channel region beneath the gate. In NMOS-type devices, the area beneath the gate oxide is a thin n-type inversion layer on the surface of the p-type semiconductor substrate. It is caused by the oxide electric field of the applied gate voltage VG. This is called a reversal channel. It is the conductive channel that allows electrons to flow from source to drain.

Preferably, the substrate is an N+ type substrate;

The epitaxial layer is an N-type epitaxial layer;

The body region is a P-type body region;

The source region is an N+ type source region.

Preferably, the substrate is a P+ type substrate;

The epitaxial layer is a P-type epitaxial layer;

The body region is an N-type body region;

The source region is a P+ type source region.

+ is heavily doped (high doping concentration), - is lightly doped (low doping concentration), P-type doped IIIA group elements, such as boron, aluminum, gallium, indium, and thallium. N-type doping with Group VA elements such as nitrogen, phosphorus, arsenic, antimony, bismuth and enrium. Heavily doped semiconductors can be used to manufacture high-performance electronic devices. The doping concentration of heavy doping is above 10 ¹⁹ cm ^-3 . The methods for preparing P+ doping include diffusion and ion implantation. The diffusion method mixes impurity ions with the semiconductor material, and then heats the mixture to a high temperature to diffuse the impurity ions into the semiconductor material. Ion implantation accelerates the impurity ions to high speed and then injects them into the semiconductor material. Lightly doped semiconductor refers to a type of semiconductor material in which a low concentration of impurity atoms is added during the preparation of semiconductor materials. Doped impurity atoms can change the electrical properties of semiconductor materials, thereby improving their performance and functionality. In lightly doped semiconductors, the concentration of doped impurity atoms is usually lower than the intrinsic concentration of the semiconductor material (intrinsic concentration refers to the concentration of impurity atoms in a pure semiconductor). The doped impurity atoms must also have a similar lattice size and electronic structure to the semiconductor material atoms to ensure that they can successfully combine with the semiconductor material and move in the semiconductor material. After doping impurity atoms, the electrical properties of lightly doped semiconductors will change accordingly. The most important change is the increase in electrical conductivity. This is because the added impurity atoms can form additional free electrons or holes in the semiconductor, thereby enhancing the conductive properties of the semiconductor material. In addition, lightly doped semiconductors can also change the bandgap width, carrier mobility, optical absorption spectrum and other properties of semiconductor materials, thus expanding their applications in electronics, optoelectronics, chemistry and other fields. The preparation of lightly doped semiconductors usually uses techniques such as ion implantation and melt diffusion. Ion implantation is to accelerate doping elements to high speed through a high-voltage electric field, and then bombard the semiconductor surface to inject them into the semiconductor lattice. Melting diffusion places the semiconductor chip on a doped material block and then heats it to a high temperature. The doped atoms are melted and diffused into the semiconductor material. In practical applications, lightly doped semiconductors are widely used in circuits, solar cells, nanomaterials and other fields. For example, after silicon is doped with aluminum, n-type silicon can be formed, whose conductivity is significantly improved and can be used to manufacture pn junction solar cells. In addition, lightly doped semiconductors can also be used to prepare microelectronic devices such as metal oxide semiconductor field effect transistors (MOSFETs) and low-noise power amplifiers. In the field of nanotechnology, lightly doped semiconductors can be used to prepare various optoelectronic and biochemical sensors and have broad application prospects.

Preferably, the through hole diameter of the TSV is 2-10um.

The expansion coefficient of commonly used filler metal copper is much larger than that of materials such as silicon and arsenic, which can easily lead to reliability problems. In order to improve reliability, the smaller the diameter of the TSV through hole, the better, and it should be less than 10um. When the size of the TSV through hole drops below 5um, the processing cost and processing difficulty also need to be considered. The through hole diameter of the TSV in this embodiment is 2-10um.

Preferably, the aspect ratio of the TSV is 3:1-15:1.

The aspect ratio of TSV is too large, which makes process engineering difficult and the resistance value also increases. The transmission performance of TSV is better when the aspect ratio is 10:1. The aspect ratio of the TSV in this embodiment is 3:1-15:1.

Preferably, the filling material of the TSV is copper.

TSV filling materials include metals such as copper, tungsten, and nickel or non-metals such as doped polysilicon. As a metal with good electrical conductivity, low electromigration and low cost, copper is usually used as TSV via filling material.

Example 2

The invention provides a method for manufacturing a trench MOSFET device, which includes:

S100, deposit an epitaxial layer on top of the substrate;

The epitaxial process refers to the process of growing a fully ordered single crystal layer on a substrate. Generally speaking, the epitaxial process is to grow a crystal layer with the same lattice orientation as the original substrate on a single crystal substrate. Epitaxial processes are widely used in semiconductor manufacturing, such as epitaxial silicon wafers in the integrated circuit industry. Embedded source-drain epitaxial growth of MOS transistors, epitaxial growth on LED substrates, etc. According to the different phase states of the growth source, epitaxial growth methods are divided into solid phase epitaxy, liquid phase epitaxy, and vapor phase epitaxy. In integrated circuit manufacturing, the commonly used epitaxy methods are solid-phase epitaxy and vapor-phase epitaxy.

Solid-phase epitaxy refers to the process of epitaxial recrystallization of the amorphous layer on a semiconductor single crystal at a temperature lower than the melting point or eutectic point of the material. The recrystallization process without epitaxy does not belong to solid phase epitaxy. There are two main growth methods in solid-phase epitaxy: one is that the amorphous layer is directly in contact with the single crystal substrate for epitaxial growth; the other is that a layer of metal or carbide is sandwiched between the amorphous layer and the single crystal silicon substrate Solid phase epitaxy is performed between them. Metals and carbides act as transport media. There are many ways to form polycrystalline or amorphous films. One is the direct ion implantation method, which can inject a large dose of germanium ions onto a silicon single crystal substrate to form a GeSi amorphous thin layer, which is then annealed and regrown at 475 to 575°C to obtain a strained alloy layer. The other is to deposit thin films, such as evaporation or sputtering. Compared with general epitaxial methods, solid-phase epitaxial substrate temperature is low and impurity diffusion is small, which is conducive to the production of epitaxial layers with abrupt doping interfaces.

In the gas phase state, semiconductor material is deposited on a single crystal wafer so that it grows along the crystallographic axis of the single crystal wafer to form a single crystal layer with a required thickness and resistivity. This process is called vapor phase epitaxy. Its characteristics include: high epitaxial growth temperature and long growth time, so thicker epitaxial layers can be produced; the concentration and conductive type of impurities can be changed arbitrarily during the epitaxial growth process. Commonly used vapor phase epitaxy processes in industrial production include: silicon tetrachloride (germanium) epitaxy, silicon (germanium) alkane epitaxy, trichlorosilane and dichlorodihydrogen silicon, etc. (Dichlorodihydrogen silicon has the characteristics of low deposition temperature and high deposition speed. Fast, uniform deposition and film formation, etc.) epitaxy, etc. Common concepts and principles of silicon vapor phase epitaxy: gaseous silicon compounds (such as SiCl4, SiH4) chemically react with hydrogen on the surface of a heated silicon substrate or thermally decompose themselves, reduce to silicon, and deposit in the form of single crystals. accumulated on the surface of the silicon substrate. The growth methods of vapor phase epitaxy include chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), atomic layer outside (ALE), etc. Vapor phase epitaxy of semiconductors is a process in which the gaseous compound of silicon reacts with hydrogen on the surface of a heated substrate or thermally decomposes itself and is reduced to silicon, and is deposited on the surface of the substrate in the form of a single crystal. Specifically, it includes: the reactant molecules are transferred from the gas phase to the surface of the growth layer by diffusion; the reactant molecules are adsorbed by the growth layer; the adsorbed reactant molecules complete chemical reactions on the surface of the growth layer, producing semiconductors and other by-products; the by-product molecules are desorbed from the surface , discharged from the reaction chamber with the air flow; the atoms generated by the reaction form a crystal lattice, or are added to the crystal lattice to form a single crystal epitaxial layer.

Epitaxial system devices include: gas distribution and control systems, heating and temperature measurement devices, reaction chambers, and exhaust gas treatment devices. The process includes: Substrate and base treatment: Substrate treatment is mainly to remove the oxide layer and dust particles on the surface of the substrate wafer, rinse and dry it and then place it into the graphite base. The graphite base that has been used should be etched by HCI in advance to remove the silicon left on it from the previous epitaxy. Dopant preparation: Dopants include gaseous sources, such as phosphane PH3, borane B2H6, etc.; liquid sources such as POCI3, BBr3, etc. Different devices have different requirements for the resistivity and conductivity type of the epitaxial layer, which must be accurately controlled according to the resistivity. The amount of doping source. Epitaxial growth: The main procedures are: loading the furnace, venting, first venting nitrogen and then hydrogen, raising temperature, substrate heat treatment or HCl polishing - epitaxial growth - hydrogen flushing - cooling - nitrogen flushing. When the base temperature drops below 300°C, open the furnace and take out the slices. Vapor phase epitaxy quality requirements The quality of the epitaxial layer should meet: complete crystal structure, accurate and uniform resistivity, uniform epitaxial layer thickness and within the range, smooth surface, no oxidation and white haze, surface defects (pyramids, papillae, stars) Defects, etc.) and body defects (dislocations, stacking faults, slip lines, etc.) should be fewer. Epitaxial quality inspection includes: resistivity, impurity concentration distribution, epitaxial layer thickness, minority carrier lifetime and mobility, interlayer dislocation and stacking fault density, surface defects, etc. Commonly tested items in production are defect density, resistivity and epitaxial layer thickness. Epitaxial layer thickness measurement methods include stacking fault method, angle grinding or rolling groove dyeing method, direct reading method, infrared interference method, etc. The resistivity measurement methods include the four-probe method, the three-probe method, the capacitance-voltage method, and the extended resistance method. For epitaxial layers with higher resistivity or thinner epitaxial layers, the capacitance-voltage method, the extended resistance method, etc. are often used. .

S200, forming the body region and source region above the epitaxial layer;

The metal electrode deposition process is divided into chemical vapor deposition and physical vapor deposition. Chemical vapor deposition refers to the method of depositing coatings on the surface of wafers through chemical methods, usually by applying energy to a mixed gas. Assuming that substance (A) is deposited on the wafer surface, two gases (B and C) that can generate substance (A) are first input to the deposition equipment, and then energy is applied to the gas to promote a chemical reaction between gases B and C.

Physical vapor deposition coating technology is mainly divided into three categories: vacuum evaporation coating, vacuum sputtering coating and vacuum ion plating. The main methods of physical vapor deposition include: vacuum evaporation, sputtering coating, arc plasma coating, ion coating and molecular beam epitaxy, etc. Corresponding vacuum coating equipment includes vacuum evaporation coating machines, vacuum sputtering coating machines and vacuum ion coating machines.

S300, open a first through hole in the source region and the body region, open a trench in the upper layer of the epitaxial layer, and connect the first through hole to the trench;

S400, for TSV processing.

Preferably, performing TSV processing includes:

S401, open a second through hole in the source region, and the bottom of the second through hole is located inside the substrate;

Through-hole processing on silicon wafers is the core of TSV technology, including deep reactive ion etching and laser drilling. Deep reactive ion etching is an ion-enhanced chemical reaction. The etching system uses an RF powered plasma source to obtain ions and chemically reactive groups. In deep silicon etching, the main source gas used is sulfur hexafluoride, which provides a highly reactive free fluorine plasma for high-rate silicon etching. The ions in the plasma are accelerated by the electric field between the plasma and the wafer, and rush towards the wafer with strong directionality. While the etching speed is enhanced in the vertical direction, in order to obtain a highly anisotropic etching effect, additional gas must be used to protect the etched sidewalls. There are two methods to provide sidewall passivation protection for deep silicon etching. The first is the traditional method, which uses additional gases such as O2 and HBr mixed with SF6. This type of steady-state process generally requires the use of SiO2 hardeners. The second type is the Bosch process. In each etching cycle, the exposed silicon is isotropically etched by SF6, and then a polymer protective layer is deposited on the inner wall of the through hole through C4F8, and then the polymer It is decomposed and removed, and the exposed silicon is etched again, and the etching and passivation are rapidly cycled repeatedly until the through hole reaches the process requirements and ends. In each etching cycle, scallop-like undulations are left on the side walls of the through hole. . As a process that does not require a mask, laser drilling technology avoids the process steps of photoresist coating, photolithography exposure, development and glue removal.

S402, deposit an insulating layer on the sidewall of the second through hole;

Before completing the metal filling, an insulating layer must be deposited to block the electrical conduction between the filling metal and the silicon body material. Through-hole insulation layer materials include silicon oxide compounds, silicon nitride, polymers, etc. Different insulating layers require different deposition techniques. PECVD technology has high deposition rate, low process temperature, and strong film coverage ability. It is widely used in the deposition of SiO ₂ , Si ₃ N ₄ and other insulating materials. Vacuum vapor deposition technology is based on the principle of converting gaseous precursors into solid materials in a vacuum environment. The gaseous precursors are heated to the sublimation temperature to produce gaseous molecules, and then the gaseous molecules are transported to the surface of the base material to be coated. On the surface A chemical reaction occurs to form a solid film. During this process, because there are no gas molecules in the vacuum environment to diffuse or interfere with the reaction, a high-purity, high-quality film can be obtained, which is often used in Parylene materials.

S403, deposit a barrier layer on the sidewall of the second through hole;

Usually TSV uses electroplating copper process for through-hole filling. Using copper as a filling material has the following defects: copper diffuses very quickly in the silicon dioxide medium, which easily degrades its dielectric properties; copper has a strong trap effect on semiconductor carriers, and copper diffuses into the semiconductor body material It will seriously affect the electrical characteristics of semiconductor devices; the adhesion between copper and silicon dioxide is poor. Therefore, a diffusion barrier layer must be deposited between the copper and the insulating layer to prevent copper diffusion and improve copper adhesion. Commonly used deposition technologies include PVD, magnetron sputtering and PECVD. Commonly used barrier layer materials are Cu, Cr, Ta and its compounds, Ti and its compounds, etc. PVD coating technology is mainly divided into three categories: vacuum evaporation coating, vacuum sputtering coating and vacuum ion plating. The main methods of PVD are: vacuum evaporation, sputtering coating, arc plasma coating, ion plating and molecular beam epitaxy, etc. Corresponding vacuum coating equipment includes vacuum evaporation coating machines, vacuum sputtering coating machines and vacuum ion coating machines.

S404, filling the second through hole;

Through-hole copper filling technologies include magnetron sputtering, CVD, ALD, electroplating, etc. In industrial production, the cost of electroplating is lower and the deposition speed is faster, and the copper electroplating process has become the first choice for filling TSV through holes. Copper electroplating technology usually adopts a "bottom-up" electroplating process. "Bottom-up" electroplating technology suppresses the deposition rate on the outer surface of the through hole and accelerates the deposition inside the through hole during electroplating. This is achieved by developing special electroplating additives and special design of the electroplating equipment structure and electric field. Specifically, the strong adsorption inhibitor covers the atomic positions on the copper surface to inhibit surface copper deposition; the accelerator component is used to offset the effect of the inhibitor to accelerate the deposition rate of copper at the bottom of the through hole; the leveler inhibits the surface curvature distribution caused by Deposition in high electric field areas inhibits rapid nucleation at protruding surface locations; accelerator components accumulate at the bottom of the via to offset the effect of inhibitors to accelerate the deposition rate of copper at the bottom of the via; optimized structure and special electric field design reduce fluid boundary thickness , reduce the concentration of accelerator on the wafer surface and reduce the copper deposition rate; use periodic pulse reverse current for electroplating to inhibit the growth of sharp surfaces on the inner wall of the through hole.

After through-hole copper plating, a thicker uneven copper layer is also deposited on the wafer surface, and CMP technology needs to be used to remove excess copper and planarize it. Copper CMP technology mainly includes: the oxidant in the alkaline polishing solution chemically reacts with the copper surface to generate copper oxide and cuprous oxide, and the integrating agent converts copper ions or cuprous ions into stable soluble integrated compounds into the solution, which are then used on the grinding disc, Under the action of the polishing pad and abrasives, the products of the chemical reaction are ground down and taken away from the polishing surface by the polishing fluid, leaving the unreacted surface exposed again.

S405, the metal above the second through hole is connected to the substrate through the second through hole to form a drain electrode.

In some embodiments, the functions or modules provided by the device provided by the embodiments of the present disclosure can be used to execute the methods described in the above method embodiments. For specific implementation, refer to the description of the above method embodiments. For the sake of brevity, here No longer. In addition, each functional unit in each embodiment of the present application can be integrated into one processing unit, each unit can exist physically alone, or two or more units can be integrated into one unit.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in or transmitted over a computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server or data center to another through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) means. A website site, computer, server or data center for transmission. The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains one or more available media integrated. The available media may be magnetic media (eg, floppy disk, hard disk, tape), optical media (eg, digital versatile disc (DVD)), or semiconductor media (eg, solid state disk (SSD)) wait.

Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments are implemented. This process can be completed by instructing relevant hardware through a computer program. The program can be stored in a computer-readable storage medium. When the program is executed, , may include the processes of the above method embodiments. The aforementioned storage media include: read-only memory (ROM) or random access memory (RAM), magnetic disks, optical disks and other media that can store program codes.

The above descriptions are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be practiced in other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims (10)

1. A trench MOSFET device comprising a source, a gate, a drain, a source region, and a substrate, the drain being on the same side of the source region as the source and the gate; the drain contacts the substrate through the TSV.

2. The trench MOSFET device of claim 1, further comprising an epitaxial layer and a body region, said body region being located above said epitaxial layer;

the epitaxial layer is positioned above the substrate;

the body region is located below the source region;

the source region is in contact with a source.

3. The trench MOSFET device of claim 2, further comprising a trench passing through said source region and said body region, said trench bottom being located inside said epitaxial layer, said trench inner wall having a gate oxide layer, said gate oxide layer being in contact with said gate electrode.

4. A trench MOSFET device according to claim 3, wherein said substrate is an n+ type substrate;

the epitaxial layer is an N-type epitaxial layer;

the body region is a P-type body region;

the source region is an N+ source region.

5. A trench MOSFET device according to claim 3, wherein said substrate is a p+ type substrate;

the epitaxial layer is a P-type epitaxial layer;

the body region is an N-type body region;

the source region is a P+ type source region.

6. The trench MOSFET device of claim 1, wherein said TSV has a via diameter of 2-10um.

7. The trench MOSFET device of claim 1, wherein said TSV has an aspect ratio of 3:1-15:1.

8. the trench MOSFET device of claim 1, wherein said TSV filler material is copper.

9. A method of fabricating a trench MOSFET device, comprising:

depositing an epitaxial layer over a substrate;

forming a body region and a source region over the epitaxial layer;

a first through hole is formed in the source region and the body region, a groove is formed in the upper layer of the epitaxial layer, and the first through hole is connected with the groove;

and performing TSV processing.

10. The method of fabricating a trench MOSFET device of claim 9, wherein performing TSV processing comprises:

a second through hole is formed in the source electrode region, and the bottom of the second through hole is located in the substrate;

depositing an insulating layer on the side wall of the second through hole;

depositing a barrier layer on the side wall of the second through hole;

filling the second through hole;

and the metal above the second through hole is connected with the substrate through the second through hole to form a drain electrode.