CN116978954A - Groove type MOSFET device and manufacturing method - Google Patents
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/63—Vertical IGFETs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/025—Manufacture or treatment of FETs having insulated gates [IGFET] of vertical IGFETs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
- H10D64/251—Source or drain electrodes for field-effect devices
- H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
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Abstract
本发明公开了一种沟槽型MOSFET器件及制作方法,该沟槽型MOSFET器件包括源极、栅极、漏极、源极区和衬底,所述漏极与所述源极和所述栅极位于所述源极区的同一侧;所述漏极通过TSV与所述衬底接触。本发明将原位于沟槽型MOSFET器件底部的漏极通过TSV接到源极和栅极的一侧并与衬底接触,在封装时不需要额外的装置将漏极的引脚引出,减小了封装的面积和厚度。
The invention discloses a trench type MOSFET device and a manufacturing method. The trench type MOSFET device includes a source, a gate, a drain, a source region and a substrate. The drain, the source and the substrate The gate is located on the same side of the source region; the drain is in contact with the substrate through TSV. In the present invention, the drain originally located at the bottom of the trench MOSFET device is connected to one side of the source and gate through the TSV and in contact with the substrate. No additional device is required to lead out the drain pin during packaging, which reduces the The area and thickness of the package.
Description
技术领域Technical field
本发明涉及半导体技术领域,尤其涉及一种沟槽型MOSFET器件及制作方法。The present invention relates to the field of semiconductor technology, and in particular to a trench MOSFET device and a manufacturing method.
背景技术Background technique
半导体器件的一个实例是金属氧化物硅场效应晶体管器件,被称为MOSFET器件,其被用于许多电子设备中,包括电源、汽车用电子设备、计算机和磁盘驱动器。MOSFET器件可以用于许多应用中,例如,将电源连接至具有负载的特定电子器件的开关。可以在已经蚀刻在基板中或蚀刻在外延层上的沟槽中形成MOSFET器件。MOSFET器件通过向MOSFET器件的栅电极施加适当的电压来操作,栅电极使器件接通,并形成连接MOSFET器件的源极和漏极的通道,允许电流流过。An example of a semiconductor device is a metal oxide silicon field effect transistor device, known as a MOSFET device, which is used in many electronic devices, including power supplies, automotive electronics, computers, and disk drives. MOSFET devices can be used in many applications, such as switches that connect power to specific electronic devices with loads. MOSFET devices can be formed in trenches that have been etched into the substrate or etched into the epitaxial layer. MOSFET devices operate by applying an appropriate voltage to the MOSFET device's gate electrode, which turns the device on and forms a channel connecting the source and drain of the MOSFET device, allowing current to flow.
功率半导体器件作为电力控制的核心电力电子器件,应用于电能的变换和控制。近年来,新能源汽车、高速列车、光伏、风电、手机、电脑、电视机、空调等各个领域对于功率半导体器件的需求量大大增加,促进了该领域的飞速发展。MOSFET作为一种重要的功率半导体器件,其栅极通过电压控制既能完成器件导通,又可以实现关断,具有高输入阻抗和低导通损耗的优点,现阶段广泛的应用于开关电源、电机控制、移动通讯等领域。As the core power electronic device of power control, power semiconductor devices are used in the conversion and control of electric energy. In recent years, the demand for power semiconductor devices in various fields such as new energy vehicles, high-speed trains, photovoltaics, wind power, mobile phones, computers, televisions, and air conditioners has greatly increased, promoting the rapid development of this field. As an important power semiconductor device, MOSFET's gate can both turn on and turn off the device through voltage control. It has the advantages of high input impedance and low conduction loss. It is currently widely used in switching power supplies, Motor control, mobile communications and other fields.
随着电子制造业的发展,MOSFET朝着超薄,小型化的方向发展,沟槽型MOSFET是一种从传统平面MOSFET结构上优化发展而来的新型垂直结构的MOSFET器件。现有的沟槽MOSFET器件的源极和栅极位于器件的顶部,其漏极位于器件的底部并与衬底接触。源极金属和栅极金属与漏极金属位于不同侧的器件结构导致沟槽型MOSFET器件在封装过程中需要利用引线框架或铜夹将漏极接到器件的正面,再与PCB进行接合,这些加工封装方式增加了MOSFET的封装面积与封装厚度。With the development of electronic manufacturing, MOSFETs are developing in the direction of ultra-thin and miniaturization. Trench MOSFET is a new vertical structure MOSFET device optimized and developed from the traditional planar MOSFET structure. The source and gate of existing trench MOSFET devices are located at the top of the device, and their drain is located at the bottom of the device and in contact with the substrate. The device structure in which the source metal, gate metal and drain metal are located on different sides results in the trench MOSFET device needing to use a lead frame or copper clip to connect the drain to the front of the device during the packaging process, and then bond it to the PCB. The processing and packaging method increases the packaging area and packaging thickness of MOSFET.
发明内容Contents of the invention
为了解决上述提出的至少一个技术问题,本发明的目的在于提供一种沟槽型MOSFET器件及制作方法,将原位于沟槽型MOSFET器件底部的漏极通过TSV接到源极和栅极的一侧并与衬底接触,在封装时不需要额外的装置将漏极的引脚引出,减小了封装的面积和厚度。In order to solve at least one of the technical problems raised above, the purpose of the present invention is to provide a trench MOSFET device and a manufacturing method. The drain originally located at the bottom of the trench MOSFET device is connected to the source and gate through a TSV. Side and in contact with the substrate, no additional device is required to lead out the drain pin during packaging, which reduces the area and thickness of the package.
本发明的目的采用如下技术方案实现:The purpose of the present invention is achieved by adopting the following technical solutions:
第一方面,本发明提供了一种沟槽型MOSFET器件,包括源极、栅极、漏极、源极区和衬底,所述漏极与所述源极和所述栅极位于所述源极区的同一侧;所述漏极通过TSV与所述衬底接触。In a first aspect, the present invention provides a trench MOSFET device, including a source electrode, a gate electrode, a drain electrode, a source electrode region and a substrate, and the drain electrode, the source electrode and the gate electrode are located on the The same side of the source region; the drain is in contact with the substrate through the TSV.
优选地,还包括外延层和体区,所述体区位于所述外延层上方;Preferably, it also includes an epitaxial layer and a body region, and the body region is located above the epitaxial layer;
所述外延层位于所述衬底上方;The epitaxial layer is located above the substrate;
所述体区位于所述源极区下方;The body region is located below the source region;
所述源极区与源极接触。The source region is in contact with the source.
优选地,还包括沟槽,所述沟槽穿过所述源极区和所述体区,所述沟槽底部位于所述外延层内部,所述沟槽内壁有栅氧层,所述栅氧层与所述栅极接触。Preferably, it also includes a trench that passes through the source region and the body region, the bottom of the trench is located inside the epitaxial layer, the inner wall of the trench has a gate oxide layer, and the gate The oxygen layer is in contact with the gate.
优选地,所述衬底为N+型衬底;Preferably, the substrate is an N+ type substrate;
所述外延层为N-型外延层;The epitaxial layer is an N-type epitaxial layer;
所述体区为P-型体区;The body region is a P-type body region;
所述源极区为N+型源极区。The source region is an N+ type source region.
优选地,所述衬底为P+型衬底;Preferably, the substrate is a P+ type substrate;
所述外延层为P-型外延层;The epitaxial layer is a P-type epitaxial layer;
所述体区为N-型体区;The body region is an N-type body region;
所述源极区为P+型源极区。The source region is a P+ type source region.
优选地,所述TSV的通孔直径为2-10um。Preferably, the through hole diameter of the TSV is 2-10um.
优选地,所述TSV的深宽比为3:1-15:1。Preferably, the aspect ratio of the TSV is 3:1-15:1.
优选地,所述TSV的填充材料为铜。Preferably, the filling material of the TSV is copper.
第二方面,本发明提供了一种沟槽型MOSFET器件的制作方法,包括:In a second aspect, the present invention provides a method for manufacturing a trench MOSFET device, including:
在衬底上方沉积形成外延层;Deposit an epitaxial layer over the substrate;
在所述外延层上方形成体区和源极区;forming a body region and a source region above the epitaxial layer;
在所述源极区和所述体区上开设第一通孔,在所述外延层上层开设沟槽,所述第一通孔与所述沟槽连接;A first through hole is opened in the source region and the body region, a trench is opened in the upper layer of the epitaxial layer, and the first through hole is connected to the trench;
进行TSV加工。Perform TSV processing.
优选地,进行TSV加工包括:Preferably, performing TSV processing includes:
在所述源极区上开设第二通孔,所述第二通孔的底部位于所述衬底内部;A second through hole is opened in the source region, and the bottom of the second through hole is located inside the substrate;
在第二通孔侧壁沉积形成绝缘层;Deposit and form an insulating layer on the sidewall of the second through hole;
在第二通孔侧壁沉积形成阻挡层;Deposit and form a barrier layer on the sidewall of the second through hole;
填充所述第二通孔;Fill the second through hole;
所述第二通孔上方金属通过所述第二通孔与所述衬底连接形成漏极。The metal above the second through hole is connected to the substrate through the second through hole to form a drain electrode.
相比现有技术,本发明的有益效果在于:Compared with the existing technology, the beneficial effects of the present invention are:
本发明将原位于沟槽型MOSFET器件底部的漏极通过TSV接到源极和栅极的一侧并与衬底接触,在封装时不需要额外的装置将漏极的引脚引出,减小了封装的面积和厚度。In the present invention, the drain originally located at the bottom of the trench MOSFET device is connected to one side of the source and gate through TSV and in contact with the substrate. No additional device is required to lead out the drain pin during packaging, which reduces the cost The area and thickness of the package.
应当理解的是,以上的一般描述和后文的细节描述仅是示例性和解释性的,而非限制本公开。It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not restrictive of the disclosure.
附图说明Description of the drawings
为了更清楚地说明本申请实施例或背景技术中的技术方案,下面将对本申请实施例或背景技术中所需要使用的附图进行说明。In order to more clearly explain the technical solutions in the embodiments of the present application or the background technology, the drawings required to be used in the embodiments or the background technology of the present application will be described below.
此处的附图被并入说明书中并构成本说明书的一部分,这些附图示出了符合本公开的实施例,并与说明书一起用于说明本公开的技术方案。The accompanying drawings herein are incorporated into and constitute a part of this specification. They illustrate embodiments consistent with the disclosure and, together with the description, serve to explain the technical solutions of the disclosure.
图1为本发明实施例提供的一种沟槽型MOSFET器件的结构示意图;Figure 1 is a schematic structural diagram of a trench MOSFET device provided by an embodiment of the present invention;
图2为本发明实施例提供的一种沟槽型MOSFET器件的制作方法流程图。FIG. 2 is a flow chart of a manufacturing method of a trench MOSFET device provided by an embodiment of the present invention.
具体实施方式Detailed ways
为了使本技术领域的人员更好地理解本申请方案,下面将结合本申请实施例中的附图,对本申请实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本申请一部分实施例,而不是全部的实施例。基于本申请中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本申请保护的范围。In order to enable those in the technical field to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only These are part of the embodiments of this application, but not all of them. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.
本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别不同对象,而不是用于描述特定顺序。此外,术语“包括”和“具有”以及它们任何变形,意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元,而是可选地还包括没有列出的步骤或单元,或可选地还包括对于这些过程、方法、产品或设备固有的其他步骤或单元。The terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish different objects, rather than describing a specific sequence. Furthermore, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units that are not listed, or optionally also includes Other steps or units inherent to such processes, methods, products or devices.
本文中术语“和/或”,仅仅是一种描述关联对象的关联关系,表示可以存在三种关系,例如,A和/或B,可以表示:单独存在A,同时存在A和B,单独存在B这三种情况。另外,本文中术语“至少一种”表示多种中的任意一种或多种中的至少两种的任意组合,例如,包括A、B、C中的至少一种,可以表示包括从A、B和C构成的集合中选择的任意一个或多个元素。The term "and/or" in this article is just an association relationship that describes related objects, indicating that three relationships can exist. For example, A and/or B can mean: A exists alone, A and B exist simultaneously, and they exist alone. B these three situations. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, and C, which can mean including from A, Any one or more elements selected from the set composed of B and C.
在本文中提及“实施例”意味着,结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例,也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是,本文所描述的实施例可以与其它实施例相结合。Reference herein to "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The appearances of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those skilled in the art understand, both explicitly and implicitly, that the embodiments described herein may be combined with other embodiments.
另外,为了更好地说明本发明,在下文的具体实施方式中给出了众多的具体细节。本领域技术人员应当理解,没有某些具体细节,本发明同样能够实施。在一些实例中,对于本领域技术人员熟知的方法、手段、元件和电路未作详细描述,以便于凸显本发明的主旨。In addition, in order to better explain the present invention, numerous specific details are given in the following detailed description. It will be understood by those skilled in the art that the present invention may be practiced without certain specific details. In some instances, methods, means, components and circuits that are well known to those skilled in the art are not described in detail in order to emphasize the gist of the present invention.
功率半导体器件作为电力控制的核心电力电子器件,应用于电能的变换和控制。近年来,新能源汽车、高速列车、光伏、风电、手机、电脑、电视机、空调等各个领域对于功率半导体器件的需求量大大增加,促进了该领域的飞速发展。MOSFET作为一种重要的功率半导体器件,其栅极通过电压控制既能完成器件导通,又可以实现关断,具有高输入阻抗和低导通损耗的优点,现阶段广泛的应用于开关电源、电机控制、移动通讯等领域。As the core power electronic device of power control, power semiconductor devices are used in the conversion and control of electric energy. In recent years, the demand for power semiconductor devices in various fields such as new energy vehicles, high-speed trains, photovoltaics, wind power, mobile phones, computers, televisions, and air conditioners has greatly increased, promoting the rapid development of this field. As an important power semiconductor device, MOSFET's gate can both turn on and turn off the device through voltage control. It has the advantages of high input impedance and low conduction loss. It is currently widely used in switching power supplies, Motor control, mobile communications and other fields.
随着电子制造业的发展,MOSFET朝着超薄,小型化的方向发展,沟槽型MOSFET是一种从传统平面MOSFET结构上优化发展而来的新型垂直结构的MOSFET器件。现有的沟槽MOSFET器件的源极和栅极位于器件的顶部,其漏极位于器件的底部并与衬底接触。源极金属和栅极金属与漏极金属位于不同侧的器件结构导致沟槽型MOSFET器件在封装过程中需要利用引线框架或铜夹将漏极接到器件的正面,再与PCB进行接合,这些加工封装方式增加了MOSFET的封装面积与封装厚度。本发明将原位于沟槽型MOSFET器件底部的漏极通过TSV接到源极和栅极的一侧并与衬底接触,在封装时不需要额外的装置将漏极的引脚引出,减小了封装的面积和厚度。With the development of electronic manufacturing, MOSFETs are developing in the direction of ultra-thin and miniaturization. Trench MOSFET is a new vertical structure MOSFET device optimized and developed from the traditional planar MOSFET structure. The source and gate of existing trench MOSFET devices are located at the top of the device, and their drain is located at the bottom of the device and in contact with the substrate. The device structure in which the source metal, gate metal and drain metal are located on different sides results in the trench MOSFET device needing to use a lead frame or copper clip to connect the drain to the front of the device during the packaging process, and then bond it to the PCB. The processing and packaging method increases the packaging area and packaging thickness of MOSFET. In the present invention, the drain originally located at the bottom of the trench MOSFET device is connected to one side of the source and gate through TSV and in contact with the substrate. No additional device is required to lead out the drain pin during packaging, which reduces the cost The area and thickness of the package.
实施例1Example 1
本发明提供了一种沟槽型MOSFET器件,包括源极、栅极、漏极、源极区和衬底,漏极与源极和栅极位于源极区的同一侧;漏极通过TSV与衬底接触。The invention provides a trench type MOSFET device, which includes a source, a gate, a drain, a source region and a substrate. The drain, the source and the gate are located on the same side of the source region; the drain is connected to the source region through TSV. substrate contact.
沟槽型MOSFET是一种常见的场效应晶体管。沟槽型MOSFET的基本结构包括源极,漏极,栅极和沟道。其中,源极和漏极之间的沟道是电流流动的通道,栅极是控制沟道中电流的开关。沟槽型MOSFET的源极金属和栅极金属位于硅片的上方,硅片下部为衬底,漏极位于硅片的下方与衬底接触。沟槽型MOSFET也被称为表面效应晶体管,其将栅极埋入基体中形成垂直沟道,尽管其工艺复杂,单元一致性比平面结构差。但是,沟槽结构可以增加单元密度,没有JFET效应,寄生电容更小,开关速度快,开关损耗非常低;而且,通过选取合适沟道晶面以及优化设计的结构,可以实现最佳的沟道迁移率,明显降低导通电阻。本实施例提供的沟槽型MOSFET与传统沟槽型MOSFET不同,将原位于沟槽型MOSFET器件底部的漏极通过TSV接到源极和栅极的一侧并与衬底接触。Trench MOSFET is a common field effect transistor. The basic structure of trench MOSFET includes source, drain, gate and channel. Among them, the channel between the source and drain is the channel for current flow, and the gate is the switch that controls the current in the channel. The source metal and gate metal of the trench MOSFET are located above the silicon wafer, the lower part of the silicon wafer is the substrate, and the drain is located below the silicon wafer in contact with the substrate. Trench MOSFET, also known as surface effect transistor, buries the gate into the substrate to form a vertical channel. Although the process is complex, the unit consistency is worse than that of the planar structure. However, the trench structure can increase the cell density, has no JFET effect, smaller parasitic capacitance, fast switching speed, and very low switching loss; moreover, by selecting the appropriate channel crystal plane and optimizing the designed structure, the best channel can be achieved mobility, significantly reducing on-resistance. The trench MOSFET provided in this embodiment is different from the traditional trench MOSFET. The drain originally located at the bottom of the trench MOSFET device is connected to one side of the source and gate through the TSV and is in contact with the substrate.
优选地,还包括外延层和体区,体区位于外延层上方;Preferably, it also includes an epitaxial layer and a body region, and the body region is located above the epitaxial layer;
外延层位于衬底上方;The epitaxial layer is located above the substrate;
体区位于源极区下方;The body region is located below the source region;
源极区与源极接触。The source region is in contact with the source.
外延是指在经过切、磨、抛等仔细加工的单晶衬底上生长一层新单晶的过程,新单晶可以与衬底为同一材料,也可以是不同材料(同质外延或者是异质外延)。由于新生单晶层按衬底晶相延伸生长,从而被称之为外延层。外延层的厚度通常为几微米,以硅为例:硅外延生长其意义是在具有一定晶向的硅单晶衬底上生长一层具有和衬底相同晶向的电阻率与厚度不同的晶格结构完整性好的晶体,而长了外延层的衬底称为外延片,即外延片=外延层+衬底。MOSFET器件的制作在外延层上展开。Epitaxy refers to the process of growing a new layer of single crystal on a single crystal substrate that has been carefully processed by cutting, grinding, polishing, etc. The new single crystal can be the same material as the substrate, or it can be a different material (homoepitaxial or heteroepitaxy). Because the new single crystal layer extends and grows according to the crystal phase of the substrate, it is called an epitaxial layer. The thickness of the epitaxial layer is usually a few microns. Taking silicon as an example: The meaning of silicon epitaxial growth is to grow a layer of crystal with the same crystal orientation as the substrate and different resistivity and thickness on a silicon single crystal substrate with a certain crystal orientation. A crystal with good lattice structure integrity, and a substrate with an epitaxial layer is called an epitaxial wafer, that is, epitaxial wafer = epitaxial layer + substrate. The fabrication of MOSFET devices is carried out on the epitaxial layer.
对于传统的硅半导体产业链而言,在硅片上制作器件无法实现集电区高击穿电压,小串联电阻,小饱和压降要小的要求。而外延技术的发展则成功地解决了这一困难。外延技术在电阻极低的硅衬底上生长一层高电阻率外延层,器件制作在外延层上,这样高电阻率的外延层保证了管子有高的击穿电压,而低电阻的衬底又降低了基片的电阻,从而降低了饱和压降,从而解决了二者的矛盾。此外,GaAs等Ⅲ-Ⅴ族、Ⅱ-Ⅵ族以及其他分子化合物半导体材料的气相外延、液相外延等外延技术也都得到很大的发展,已成为绝大多数微波器件、光电器件、功率器件等制作不可缺少的工艺技术,特别是分子束、金属有机气相外延技术在薄层、超晶格、量子阱、应变超晶格、原子级薄层外延方面的成功应用,为半导体研究的新领域“能带工程”的开拓打下了夯实的基础。For the traditional silicon semiconductor industry chain, manufacturing devices on silicon wafers cannot meet the requirements of high breakdown voltage, small series resistance, and small saturation voltage drop in the collector area. The development of epitaxy technology has successfully solved this difficulty. Epitaxy technology grows a high-resistivity epitaxial layer on an extremely low-resistance silicon substrate, and the device is fabricated on the epitaxial layer. This high-resistivity epitaxial layer ensures that the tube has a high breakdown voltage, while the low-resistance substrate It also reduces the resistance of the substrate, thereby reducing the saturation voltage drop, thus resolving the contradiction between the two. In addition, epitaxy technologies such as vapor phase epitaxy and liquid phase epitaxy of GaAs and other III-V, II-VI and other molecular compound semiconductor materials have also been greatly developed and have become the basis for most microwave devices, optoelectronic devices and power devices. Indispensable process technologies for production, especially the successful application of molecular beam and metal-organic vapor phase epitaxy technology in thin layers, superlattices, quantum wells, strained superlattices, and atomic-level thin-layer epitaxy have become a new field of semiconductor research. The development of "Energy Belt Project" has laid a solid foundation.
优选地,还包括沟槽,沟槽穿过源极区和体区,沟槽底部位于外延层内部,沟槽内壁有栅氧层,栅氧层与栅极接触。Preferably, it also includes a trench, the trench passes through the source region and the body region, the bottom of the trench is located inside the epitaxial layer, the inner wall of the trench has a gate oxide layer, and the gate oxide layer is in contact with the gate electrode.
沟槽是指沟道区域,沟槽型MOSFET通过调整沟槽的尺寸,可以改变晶体管的性能和特性。为了形成垂直沟道结构,沟槽型MOSFET在外延层中开设沟槽,沟槽表面制作氧化层后,在沟槽内部填充多晶硅形成栅极。这种结构将栅极埋入基体中,形成垂直沟道,电流通路从下部衬底漏极,垂直流过外延层、沟道和源极区,沟道和电流方向平行。本实施例提供的沟槽型MOSFET与传统沟槽型MOSFET的差别在于设置了通过TSV与衬底接触的漏极金属,漏极金属与源极金属二号栅极金属位于同一平面,本实施例提供的沟槽型MOSFET的电流通路从漏极金属通过TSV填充金属到下部衬底,再垂直流过外延层、沟道和源极区。The trench refers to the channel area. Trench MOSFET can change the performance and characteristics of the transistor by adjusting the size of the trench. In order to form a vertical channel structure, a trench MOSFET is opened in the epitaxial layer. After an oxide layer is made on the surface of the trench, polysilicon is filled inside the trench to form a gate electrode. In this structure, the gate is buried in the matrix to form a vertical channel. The current path flows vertically from the drain electrode of the lower substrate through the epitaxial layer, channel and source area, and the channel is parallel to the current direction. The difference between the trench MOSFET provided in this embodiment and the traditional trench MOSFET is that the drain metal is provided in contact with the substrate through the TSV. The drain metal and the source metal and the second gate metal are located on the same plane. In this embodiment The current path of the trench MOSFET provided is from the drain metal through the TSV fill metal to the lower substrate, and then flows vertically through the epitaxial layer, channel and source region.
栅极氧化物是将MOSFET的栅极与源极和漏极分开以及晶体管导通时连接源极和漏极的导电通道分开的介电层。栅氧化层是通过热氧化沟道的硅形成薄的二氧化硅绝缘层。绝缘二氧化硅层是通过自限氧化过程形成的,该过程由Deal–Grove模型描述。随后在栅极氧化物上方沉积导电栅极材料以形成晶体管。栅极氧化物用作介电层,因此栅极可以承受高达1至5MV/cm的横向电场,以强烈调制沟道的电导。在栅极氧化物上方是一个薄电极层,由导体制成,导体可以是铝、高掺杂硅、钨等难熔金属、硅化物(TiSi、MoSi2、TaSi或WSi2)或这些层的夹层。该栅电极通常称为栅极金属或栅极导体。栅极导体电极的几何宽度(横向于电流流动的方向)称为物理栅极宽度。物理栅极宽度可能与用于模拟晶体管的电通道宽度略有不同,因为边缘电场会对不在栅极正下方的导体产生影响。Gate oxide is the dielectric layer that separates the MOSFET's gate from the source and drain and the conductive path that connects the source and drain when the transistor is on. The gate oxide layer is formed by thermally oxidizing the silicon in the channel to form a thin silicon dioxide insulating layer. The insulating silicon dioxide layer is formed through a self-limiting oxidation process, which is described by the Deal–Grove model. A conductive gate material is then deposited over the gate oxide to form the transistor. The gate oxide serves as a dielectric layer so the gate can withstand lateral electric fields of up to 1 to 5MV/cm to strongly modulate the conductance of the channel. Above the gate oxide is a thin electrode layer made of a conductor, which can be aluminum, highly doped silicon, a refractory metal such as tungsten, a suicide (TiSi, MoSi2, TaSi or WSi2) or a sandwich of these layers. This gate electrode is often called the gate metal or gate conductor. The geometric width of the gate conductor electrode (transverse to the direction of current flow) is called the physical gate width. The physical gate width may differ slightly from the electrical channel width used to simulate the transistor because fringing electric fields have an effect on conductors that are not directly beneath the gate.
栅极氧化物的电气特性对于栅极下方导电沟道区域的形成至关重要。在NMOS型器件中,栅极氧化物下方的区域是p型半导体衬底表面上的薄n型反型层。它是由施加的栅极电压VG的氧化物电场引起的。这被称为反转通道。它是允许电子从源极流向漏极的传导通道。The electrical properties of the gate oxide are critical to the formation of the conductive channel region beneath the gate. In NMOS-type devices, the area beneath the gate oxide is a thin n-type inversion layer on the surface of the p-type semiconductor substrate. It is caused by the oxide electric field of the applied gate voltage VG. This is called a reversal channel. It is the conductive channel that allows electrons to flow from source to drain.
优选地,衬底为N+型衬底;Preferably, the substrate is an N+ type substrate;
外延层为N-型外延层;The epitaxial layer is an N-type epitaxial layer;
体区为P-型体区;The body region is a P-type body region;
源极区为N+型源极区。The source region is an N+ type source region.
优选地,衬底为P+型衬底;Preferably, the substrate is a P+ type substrate;
外延层为P-型外延层;The epitaxial layer is a P-type epitaxial layer;
体区为N-型体区;The body region is an N-type body region;
源极区为P+型源极区。The source region is a P+ type source region.
+是重掺杂(掺杂浓度高),-是轻掺杂(掺杂浓度低),P型掺杂IIIA族元素,例如:硼、铝、镓、铟、铊。N型掺杂VA族元素,例如氮、磷、砷、锑、铋和镆。重掺杂半导体可以用于制造高性能的电子器件,重掺杂的掺杂浓度为1019cm-3以上,制备P+掺杂的方法包括扩散发和离子注入法。扩散法将杂质离子与半导体材料混合,然后将混合物加热到高温,使杂质离子扩散到半导体材料中,离子注入是将杂质离子加速到高速,然后注入到半导体材料中。轻掺杂半导体是指在制备半导体材料时添加了低浓度的杂质原子,使其成为半导体材料的一种。掺杂的杂质原子可以改变半导体材料的电学性质,从而提高其性能和功能。在轻掺杂半导体中,掺入的杂质原子浓度通常低于半导体材料的本征浓度(本征浓度是指在纯净半导体中杂质原子的浓度)。掺入的杂质原子也必须具有与半导体材料原子相似的晶格尺寸和电子结构,以确保其能够顺利地与半导体材料结合,并在半导体材料中运动。掺入杂质原子后,轻掺杂半导体的电学性质会发生相应变化。其中最重要的变化是电导率的提高。这是因为添加的杂质原子可以在半导体中形成额外的自由电子或空穴,使半导体材料的导电性能得到增强。除此之外,轻掺杂半导体还可以改变半导体材料的禁带宽度、载流子迁移率和光学吸收谱等性质,从而拓展其在电子学、光电子学、化学等领域的应用。轻掺杂半导体的制备通常采用离子注入和熔融扩散等技术。离子注入是将掺杂元素通过高压电场加速到高速,然后轰击半导体表面,将其注入到半导体晶格中。熔融扩散则是将半导体芯片放置在掺杂材料块上,然后加热至高温,掺杂原子被熔化后扩散到半导体材料中。在实际应用中,轻掺杂半导体广泛应用于电路、太阳能电池、纳米材料等领域。例如,硅掺杂铝元素后,可以形成n型硅,其导电性能显著提高,可以用于制造p-n结的太阳能电池。此外,轻掺杂半导体还可以制备金属氧化物半导体场效应晶体管(MOSFET)、低噪声功率放大器等微电子器件。在纳米技术领域,轻掺杂半导体可以用于制备各种光电子和生化传感器,具有广阔的应用前景。+ is heavily doped (high doping concentration), - is lightly doped (low doping concentration), P-type doped IIIA group elements, such as boron, aluminum, gallium, indium, and thallium. N-type doping with Group VA elements such as nitrogen, phosphorus, arsenic, antimony, bismuth and enrium. Heavily doped semiconductors can be used to manufacture high-performance electronic devices. The doping concentration of heavy doping is above 10 19 cm -3 . The methods for preparing P+ doping include diffusion and ion implantation. The diffusion method mixes impurity ions with the semiconductor material, and then heats the mixture to a high temperature to diffuse the impurity ions into the semiconductor material. Ion implantation accelerates the impurity ions to high speed and then injects them into the semiconductor material. Lightly doped semiconductor refers to a type of semiconductor material in which a low concentration of impurity atoms is added during the preparation of semiconductor materials. Doped impurity atoms can change the electrical properties of semiconductor materials, thereby improving their performance and functionality. In lightly doped semiconductors, the concentration of doped impurity atoms is usually lower than the intrinsic concentration of the semiconductor material (intrinsic concentration refers to the concentration of impurity atoms in a pure semiconductor). The doped impurity atoms must also have a similar lattice size and electronic structure to the semiconductor material atoms to ensure that they can successfully combine with the semiconductor material and move in the semiconductor material. After doping impurity atoms, the electrical properties of lightly doped semiconductors will change accordingly. The most important change is the increase in electrical conductivity. This is because the added impurity atoms can form additional free electrons or holes in the semiconductor, thereby enhancing the conductive properties of the semiconductor material. In addition, lightly doped semiconductors can also change the bandgap width, carrier mobility, optical absorption spectrum and other properties of semiconductor materials, thus expanding their applications in electronics, optoelectronics, chemistry and other fields. The preparation of lightly doped semiconductors usually uses techniques such as ion implantation and melt diffusion. Ion implantation is to accelerate doping elements to high speed through a high-voltage electric field, and then bombard the semiconductor surface to inject them into the semiconductor lattice. Melting diffusion places the semiconductor chip on a doped material block and then heats it to a high temperature. The doped atoms are melted and diffused into the semiconductor material. In practical applications, lightly doped semiconductors are widely used in circuits, solar cells, nanomaterials and other fields. For example, after silicon is doped with aluminum, n-type silicon can be formed, whose conductivity is significantly improved and can be used to manufacture pn junction solar cells. In addition, lightly doped semiconductors can also be used to prepare microelectronic devices such as metal oxide semiconductor field effect transistors (MOSFETs) and low-noise power amplifiers. In the field of nanotechnology, lightly doped semiconductors can be used to prepare various optoelectronic and biochemical sensors and have broad application prospects.
优选地,TSV的通孔直径为2-10um。Preferably, the through hole diameter of the TSV is 2-10um.
常用填充金属铜膨胀系数远大于硅、砷化家等材料而易导致可靠性问题。为提高可靠性,TSV通孔直径越小越好,应小于10um。当TSV的尺寸通孔降到5um以下时,也需要考虑加工成本和加工难度。本实施例的TSV的通孔直径为2-10um。The expansion coefficient of commonly used filler metal copper is much larger than that of materials such as silicon and arsenic, which can easily lead to reliability problems. In order to improve reliability, the smaller the diameter of the TSV through hole, the better, and it should be less than 10um. When the size of the TSV through hole drops below 5um, the processing cost and processing difficulty also need to be considered. The through hole diameter of the TSV in this embodiment is 2-10um.
优选地,TSV的深宽比为3:1-15:1。Preferably, the aspect ratio of the TSV is 3:1-15:1.
TSV深宽比过大,工艺释作困难,并且电阻值也随之增大,在深宽比为10:1时TSV的传输性能较好。本实施例的TSV的深宽比为3:1-15:1。The aspect ratio of TSV is too large, which makes process engineering difficult and the resistance value also increases. The transmission performance of TSV is better when the aspect ratio is 10:1. The aspect ratio of the TSV in this embodiment is 3:1-15:1.
优选地,TSV的填充材料为铜。Preferably, the filling material of the TSV is copper.
TSV的填充材料包括铜、钨、镍等金属或掺杂多晶硅等非金属。而铜作为具有良好的导电能力、低电迁移性及低成本的金属,通常用于TSV通孔填充材料。TSV filling materials include metals such as copper, tungsten, and nickel or non-metals such as doped polysilicon. As a metal with good electrical conductivity, low electromigration and low cost, copper is usually used as TSV via filling material.
实施例2Example 2
本发明提供了一种沟槽型MOSFET器件的制作方法,包括:The invention provides a method for manufacturing a trench MOSFET device, which includes:
S100,在衬底上方沉积形成外延层;S100, deposit an epitaxial layer on top of the substrate;
外延工艺是指在衬底上生长完全排列有序的单晶体层的工艺。一般来讲,外延工艺是在单晶衬底上生长一层与原衬底相同晶格取向的晶体层。外延工艺广泛用于半导体制造,如集成电路工业的外延硅片。MOS晶体管的嵌入式源漏外延生长,LED衬底上的外延生长等。根据生长源物相狀态的不同,外延生长方式分为固相外延、液相外延、气相外延。在集成电路制造中,常用的外延方式是固相外延和气相外延。The epitaxial process refers to the process of growing a fully ordered single crystal layer on a substrate. Generally speaking, the epitaxial process is to grow a crystal layer with the same lattice orientation as the original substrate on a single crystal substrate. Epitaxial processes are widely used in semiconductor manufacturing, such as epitaxial silicon wafers in the integrated circuit industry. Embedded source-drain epitaxial growth of MOS transistors, epitaxial growth on LED substrates, etc. According to the different phase states of the growth source, epitaxial growth methods are divided into solid phase epitaxy, liquid phase epitaxy, and vapor phase epitaxy. In integrated circuit manufacturing, the commonly used epitaxy methods are solid-phase epitaxy and vapor-phase epitaxy.
固相外延,是指半导体单晶上的非晶层在低于该材料的熔点或共晶点温度下外延再结晶的过程。没有外延的再结晶过程不属于固相外延。固相外延主要有两种生长方式:一种是非晶层直接与单晶衬底相接触,进行外延生长;另一种是将一层金属或碳化物夹在非晶层和单晶硅衬底之间进行固相外延。金属和碳化物起到输运介质的作用。有多种方法形成多晶或无定形薄膜。一种是直接离子注入的方法,可在硅单晶衬底上大剂量注入锗离子,形成GeSi非晶薄层,475~575℃退火再生长,得到应变合金层。另一种是淀积薄膜,如蒸发或溅射。与一般外延方法相比,固相外延衬底温度低,杂质扩散小,有利于制造突变掺杂界面的外延层。Solid-phase epitaxy refers to the process of epitaxial recrystallization of the amorphous layer on a semiconductor single crystal at a temperature lower than the melting point or eutectic point of the material. The recrystallization process without epitaxy does not belong to solid phase epitaxy. There are two main growth methods in solid-phase epitaxy: one is that the amorphous layer is directly in contact with the single crystal substrate for epitaxial growth; the other is that a layer of metal or carbide is sandwiched between the amorphous layer and the single crystal silicon substrate Solid phase epitaxy is performed between them. Metals and carbides act as transport media. There are many ways to form polycrystalline or amorphous films. One is the direct ion implantation method, which can inject a large dose of germanium ions onto a silicon single crystal substrate to form a GeSi amorphous thin layer, which is then annealed and regrown at 475 to 575°C to obtain a strained alloy layer. The other is to deposit thin films, such as evaporation or sputtering. Compared with general epitaxial methods, solid-phase epitaxial substrate temperature is low and impurity diffusion is small, which is conducive to the production of epitaxial layers with abrupt doping interfaces.
在气相状态下,将半导体材料淀积在单晶片上,使它沿着单晶片的结晶轴方向生长出一层厚度和电阻率合乎要求的单晶层,这一工艺称为气相外延。其特点有:外延生长温度高,生长时间长,因而可以制造较厚的外延层;在外延过程中可以任意改变杂质的浓度和导电类型。工业生产常用的气相外延工艺有:四氯化硅(锗)外延,硅(锗)烷外延、三氯氢硅及二氯二氢硅等(二氯二氢硅具有淀积温度低,沉积速度快,淀积成膜均匀等优点)外延等。常见的硅气相外延的概念、原理:用硅的气态化合物(如:SiCl4、SiH4)在加热的硅衬底表面与氢气发生化学反应或自身发生热分解,还原成硅,并以单晶形式淀积在硅衬底表面。气相外延的生长方法包括化学气相外延生长(CVE)、分子束外延(MBD)、原子层外(ALE)等。半导体的气相外延是硅的气态化合物在加热的衬底表面与氢发生反应或自身热分解还原成硅,并以单晶的形式淀积在衬底表面的过程。具体包括:反应剂分子以扩散方式从气相转移到生长层表面;反应剂分子被生长层吸附;被吸附的反应剂分子在生长层表面完成化学反应,产生半导体及其它副产品;副产品分子从表面解析,随着气流排出反应腔;反应生成的原子形成晶格,或加接到晶格点阵上,形成单晶外延层。In the gas phase state, semiconductor material is deposited on a single crystal wafer so that it grows along the crystallographic axis of the single crystal wafer to form a single crystal layer with a required thickness and resistivity. This process is called vapor phase epitaxy. Its characteristics include: high epitaxial growth temperature and long growth time, so thicker epitaxial layers can be produced; the concentration and conductive type of impurities can be changed arbitrarily during the epitaxial growth process. Commonly used vapor phase epitaxy processes in industrial production include: silicon tetrachloride (germanium) epitaxy, silicon (germanium) alkane epitaxy, trichlorosilane and dichlorodihydrogen silicon, etc. (Dichlorodihydrogen silicon has the characteristics of low deposition temperature and high deposition speed. Fast, uniform deposition and film formation, etc.) epitaxy, etc. Common concepts and principles of silicon vapor phase epitaxy: gaseous silicon compounds (such as SiCl4, SiH4) chemically react with hydrogen on the surface of a heated silicon substrate or thermally decompose themselves, reduce to silicon, and deposit in the form of single crystals. accumulated on the surface of the silicon substrate. The growth methods of vapor phase epitaxy include chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), atomic layer outside (ALE), etc. Vapor phase epitaxy of semiconductors is a process in which the gaseous compound of silicon reacts with hydrogen on the surface of a heated substrate or thermally decomposes itself and is reduced to silicon, and is deposited on the surface of the substrate in the form of a single crystal. Specifically, it includes: the reactant molecules are transferred from the gas phase to the surface of the growth layer by diffusion; the reactant molecules are adsorbed by the growth layer; the adsorbed reactant molecules complete chemical reactions on the surface of the growth layer, producing semiconductors and other by-products; the by-product molecules are desorbed from the surface , discharged from the reaction chamber with the air flow; the atoms generated by the reaction form a crystal lattice, or are added to the crystal lattice to form a single crystal epitaxial layer.
外延系统装置包括:气体分配及控制系统、加热和测温装置、反应室、废气处理装置。工艺过程包括:衬底和基座处理:衬底处理主要是为了去除衬底圆片表面氧化层及尘粒,冲洗干燥后放入石墨基座内。对于已经用过的石墨基座应预先经过HCI腐蚀,去除前次外延留在上面的硅。掺杂剂配制:掺杂剂有气态源,如磷烷PH3,硼烷B2H6等;液态源如POCI3、BBr3等,不同的器件对外延层电阻率及导电类型要求不同,必须根据电阻率精确控制掺杂源的用量。外延生长:主要程序为:装炉一通气,先通氮气再通氢气一升温一衬底热处理或HCl抛光-外延生长-氢气冲洗-降温-氮气冲洗。当基座温度降到300℃以下时开炉取片。气相外延质量要求外延层质量应满足:晶体结构完整、电阻率精确而均匀、外延层厚度均匀且在范围内、表面光洁,无氧化和白雾、表面缺陷(角锥体、乳突、星形缺陷等)和体内缺陷(位错、层错、滑移线等)要少。外延质量检验内容包括:电阻率、杂质浓度分布、外延层厚度、少子寿命及迁移率、夹层位错与层错密度、表面缺陷等。生产中通常检测项目是缺陷密度、电阻率和外延层厚度。外延层厚度测量方法有层错法、磨角或滚槽染色法、直读法、红外干涉法等。电阻率测量的方法有四探针法、三探针法、电容一电压法、扩展电阻法,对于外延层电阻率较高或者厚度较薄的外延层往往采用电容-电压法、扩展电阻法等。Epitaxial system devices include: gas distribution and control systems, heating and temperature measurement devices, reaction chambers, and exhaust gas treatment devices. The process includes: Substrate and base treatment: Substrate treatment is mainly to remove the oxide layer and dust particles on the surface of the substrate wafer, rinse and dry it and then place it into the graphite base. The graphite base that has been used should be etched by HCI in advance to remove the silicon left on it from the previous epitaxy. Dopant preparation: Dopants include gaseous sources, such as phosphane PH3, borane B2H6, etc.; liquid sources such as POCI3, BBr3, etc. Different devices have different requirements for the resistivity and conductivity type of the epitaxial layer, which must be accurately controlled according to the resistivity. The amount of doping source. Epitaxial growth: The main procedures are: loading the furnace, venting, first venting nitrogen and then hydrogen, raising temperature, substrate heat treatment or HCl polishing - epitaxial growth - hydrogen flushing - cooling - nitrogen flushing. When the base temperature drops below 300°C, open the furnace and take out the slices. Vapor phase epitaxy quality requirements The quality of the epitaxial layer should meet: complete crystal structure, accurate and uniform resistivity, uniform epitaxial layer thickness and within the range, smooth surface, no oxidation and white haze, surface defects (pyramids, papillae, stars) Defects, etc.) and body defects (dislocations, stacking faults, slip lines, etc.) should be fewer. Epitaxial quality inspection includes: resistivity, impurity concentration distribution, epitaxial layer thickness, minority carrier lifetime and mobility, interlayer dislocation and stacking fault density, surface defects, etc. Commonly tested items in production are defect density, resistivity and epitaxial layer thickness. Epitaxial layer thickness measurement methods include stacking fault method, angle grinding or rolling groove dyeing method, direct reading method, infrared interference method, etc. The resistivity measurement methods include the four-probe method, the three-probe method, the capacitance-voltage method, and the extended resistance method. For epitaxial layers with higher resistivity or thinner epitaxial layers, the capacitance-voltage method, the extended resistance method, etc. are often used. .
S200,在外延层上方形成体区和源极区;S200, forming the body region and source region above the epitaxial layer;
金属电极沉积工艺分为化学气相沉积和物理气相沉积。化学气相沉积是指通过化学方法在晶圆表面沉积涂层的方法,一般是通过给混合气体施加能量来进行。假设在晶圆表面沉积物质(A),则先向沉积设备输入可生成物质(A)的两种气体(B和C),然后给气体施加能量,促使气体B和C发生化学反应。The metal electrode deposition process is divided into chemical vapor deposition and physical vapor deposition. Chemical vapor deposition refers to the method of depositing coatings on the surface of wafers through chemical methods, usually by applying energy to a mixed gas. Assuming that substance (A) is deposited on the wafer surface, two gases (B and C) that can generate substance (A) are first input to the deposition equipment, and then energy is applied to the gas to promote a chemical reaction between gases B and C.
物理气相沉积镀膜技术主要分为三类:真空蒸发镀膜、真空溅射镀膜和真空离子镀膜。物理气相沉积的主要方法有:真空蒸镀、溅射镀膜、电弧等离子体镀膜、离子镀膜和分子束外延等。相应的真空镀膜设备包括真空蒸发镀膜机、真空溅射镀膜机和真空离子镀膜机。Physical vapor deposition coating technology is mainly divided into three categories: vacuum evaporation coating, vacuum sputtering coating and vacuum ion plating. The main methods of physical vapor deposition include: vacuum evaporation, sputtering coating, arc plasma coating, ion coating and molecular beam epitaxy, etc. Corresponding vacuum coating equipment includes vacuum evaporation coating machines, vacuum sputtering coating machines and vacuum ion coating machines.
S300,在源极区和体区上开设第一通孔,在外延层上层开设沟槽,第一通孔与沟槽连接;S300, open a first through hole in the source region and the body region, open a trench in the upper layer of the epitaxial layer, and connect the first through hole to the trench;
S400,进行TSV加工。S400, for TSV processing.
优选地,进行TSV加工包括:Preferably, performing TSV processing includes:
S401,在源极区上开设第二通孔,第二通孔的底部位于衬底内部;S401, open a second through hole in the source region, and the bottom of the second through hole is located inside the substrate;
硅片上的通孔加工是TSV技术的核心,包括深反应离子刻蚀和激光钻孔。深反应离子刻蚀是一种离子增强型化学反应。刻蚀系统使用RF供电的等离子源获得离子及化学上可反应的基团。在深硅刻蚀时,使用的主要源气体是六氟化硫,为硅的高速率刻蚀提供具有高度反应性质的自由氟等离子体。等离子中的离子经等离子与晶圆间的电场加速,以很强的方向性冲向晶圆。在垂直方向上获得刻蚀速度增强的同时,为了获得高度各向异性的刻蚀效果,还需要使用附加气体来钟化保护刻蚀出的侧壁。有两种方法可以为深硅刻蚀提供侧壁钝化保护,第一种是传统的方法,将如O2和HBr等附加气体与SF6混在一起使用,这类稳态工艺一般需要使用SiO2的硬质掩膜,第二种是Bosch工艺,在每个刻蚀循环周期中,暴露的硅被SF6各向同性刻蚀,再通过C4F8在通孔内壁淀积一层聚合物保护层,然后聚合物被分解去除,暴露的硅再被蚀刻,周而复始快速循环切换刻蚀和钝化,直至通孔达到工艺要求而结束,在每个刻蚀周期中都会在通孔侧壁上留下扇贝状的起伏。激光钻孔技术作为一种不需要掩膜的工艺,避免了光刻胶涂布、光刻曝光、显影和去胶等工艺步骤。Through-hole processing on silicon wafers is the core of TSV technology, including deep reactive ion etching and laser drilling. Deep reactive ion etching is an ion-enhanced chemical reaction. The etching system uses an RF powered plasma source to obtain ions and chemically reactive groups. In deep silicon etching, the main source gas used is sulfur hexafluoride, which provides a highly reactive free fluorine plasma for high-rate silicon etching. The ions in the plasma are accelerated by the electric field between the plasma and the wafer, and rush towards the wafer with strong directionality. While the etching speed is enhanced in the vertical direction, in order to obtain a highly anisotropic etching effect, additional gas must be used to protect the etched sidewalls. There are two methods to provide sidewall passivation protection for deep silicon etching. The first is the traditional method, which uses additional gases such as O2 and HBr mixed with SF6. This type of steady-state process generally requires the use of SiO2 hardeners. The second type is the Bosch process. In each etching cycle, the exposed silicon is isotropically etched by SF6, and then a polymer protective layer is deposited on the inner wall of the through hole through C4F8, and then the polymer It is decomposed and removed, and the exposed silicon is etched again, and the etching and passivation are rapidly cycled repeatedly until the through hole reaches the process requirements and ends. In each etching cycle, scallop-like undulations are left on the side walls of the through hole. . As a process that does not require a mask, laser drilling technology avoids the process steps of photoresist coating, photolithography exposure, development and glue removal.
S402,在第二通孔侧壁沉积形成绝缘层;S402, deposit an insulating layer on the sidewall of the second through hole;
在完成金属填充之前必须淀积绝缘层,隔断填充金属和硅本体材料的电导通。通孔绝缘层材料有硅氧化合物、硅氮化物、聚合物等。不同的绝缘层需要不同的淀积技术。PECVD技术的淀积速率高,工艺温度低,膜层覆盖能力强,广泛应用在淀积SiO2、Si3N4等绝缘材料。真空气相沉积技术是基于真空环境中将气态前驱物转化为固态材料的原理,将气态前驱物加热至升华温度,生产气态分子,然后将气态分子输送到待涂层的基底材料表面,在表面上发生化学反应生成固态薄膜。在此过程中,因为真空环境中没有气体分子来扩散或干扰反应,可以得到高纯度,高质量的薄膜,常应用于Parylene材料。Before completing the metal filling, an insulating layer must be deposited to block the electrical conduction between the filling metal and the silicon body material. Through-hole insulation layer materials include silicon oxide compounds, silicon nitride, polymers, etc. Different insulating layers require different deposition techniques. PECVD technology has high deposition rate, low process temperature, and strong film coverage ability. It is widely used in the deposition of SiO 2 , Si 3 N 4 and other insulating materials. Vacuum vapor deposition technology is based on the principle of converting gaseous precursors into solid materials in a vacuum environment. The gaseous precursors are heated to the sublimation temperature to produce gaseous molecules, and then the gaseous molecules are transported to the surface of the base material to be coated. On the surface A chemical reaction occurs to form a solid film. During this process, because there are no gas molecules in the vacuum environment to diffuse or interfere with the reaction, a high-purity, high-quality film can be obtained, which is often used in Parylene materials.
S403,在第二通孔侧壁沉积形成阻挡层;S403, deposit a barrier layer on the sidewall of the second through hole;
通常TSV采用电镀铜工艺进行通孔填充。使用铜作为填充材料存在以下缺陷:铜在二氧化硅介质中扩散速度很快,容易使其介电性能退化;铜对半导体的载流子具有很强的陷阱效应,铜扩散到半导体本体材料中会严重影响半导体器件电性特征;铜和二氧化硅的粘附程度较差。因此,必须在铜和绝缘层之间淀积一层扩散阻挡层,防止铜扩散并提高铜的粘附程度。常用的淀积技术包括PVD,磁控溅射和PECVD,常用的阻挡层材料为Cu、Cr、Ta及其化合物、Ti及其化合物等。PVD镀膜技术主要分为三类:真空蒸发镀膜、真空溅射镀膜和真空离子镀膜。PVD的主要方法有:真空蒸镀、溅射镀膜、电弧等离子体镀膜、离子镀膜和分子束外延等。相应的真空镀膜设备包括真空蒸发镀膜机、真空溅射镀膜机和真空离子镀膜机。Usually TSV uses electroplating copper process for through-hole filling. Using copper as a filling material has the following defects: copper diffuses very quickly in the silicon dioxide medium, which easily degrades its dielectric properties; copper has a strong trap effect on semiconductor carriers, and copper diffuses into the semiconductor body material It will seriously affect the electrical characteristics of semiconductor devices; the adhesion between copper and silicon dioxide is poor. Therefore, a diffusion barrier layer must be deposited between the copper and the insulating layer to prevent copper diffusion and improve copper adhesion. Commonly used deposition technologies include PVD, magnetron sputtering and PECVD. Commonly used barrier layer materials are Cu, Cr, Ta and its compounds, Ti and its compounds, etc. PVD coating technology is mainly divided into three categories: vacuum evaporation coating, vacuum sputtering coating and vacuum ion plating. The main methods of PVD are: vacuum evaporation, sputtering coating, arc plasma coating, ion plating and molecular beam epitaxy, etc. Corresponding vacuum coating equipment includes vacuum evaporation coating machines, vacuum sputtering coating machines and vacuum ion coating machines.
S404,填充第二通孔;S404, filling the second through hole;
通孔铜填充技术有磁控溅射、CVD、ALD、电镀等。在工业生产中,电镀成本更低且淀积速度更快,铜电镀工艺成为TSV通孔填充首选。铜电镀技术通常采用“自底向上”的电镀工艺。“自底向上”电镀技术在电镀时抑制通孔外表面的沉积速率而加速通孔内部的沉积,通过开发特殊电镀添加剂和电镀设备结构、电场的特殊设计等技术手段来实现。具体地,强吸附力抑制剂覆盖在铜表面的原子位置来抑制表面铜沉积;加速剂成份用来抵消抑制剂的作用来加速通孔底部铜的沉积速率;整平剂抑制表面曲率分布引起的高电场区域的沉积,抑制凸出表面位置的快速成核;加速剂成份在通孔底部聚集以抵消抑制剂的作用来加速通孔底部铜的沉积速率;优化结构、电场特殊设计减少流体边界厚度,减小加速剂在晶圆表面的浓度,降低铜淀积速率;采用周期脉冲反向电流进行电镀,抑制通孔内壁尖锐表面生长。Through-hole copper filling technologies include magnetron sputtering, CVD, ALD, electroplating, etc. In industrial production, the cost of electroplating is lower and the deposition speed is faster, and the copper electroplating process has become the first choice for filling TSV through holes. Copper electroplating technology usually adopts a "bottom-up" electroplating process. "Bottom-up" electroplating technology suppresses the deposition rate on the outer surface of the through hole and accelerates the deposition inside the through hole during electroplating. This is achieved by developing special electroplating additives and special design of the electroplating equipment structure and electric field. Specifically, the strong adsorption inhibitor covers the atomic positions on the copper surface to inhibit surface copper deposition; the accelerator component is used to offset the effect of the inhibitor to accelerate the deposition rate of copper at the bottom of the through hole; the leveler inhibits the surface curvature distribution caused by Deposition in high electric field areas inhibits rapid nucleation at protruding surface locations; accelerator components accumulate at the bottom of the via to offset the effect of inhibitors to accelerate the deposition rate of copper at the bottom of the via; optimized structure and special electric field design reduce fluid boundary thickness , reduce the concentration of accelerator on the wafer surface and reduce the copper deposition rate; use periodic pulse reverse current for electroplating to inhibit the growth of sharp surfaces on the inner wall of the through hole.
在通孔铜电镀之后,晶圆表面也淀积了一层较厚的不均匀铜层,需要采用CMP技术去除多余铜并平坦化。铜CMP技术主要包括:碱性抛光液中的氧化剂与铜表面进行化学反应生成氧化铜和氧化亚铜,整合剂使铜离子或亚铜离子转化为稳定的可溶整合物进入溶液,在磨盘、抛光垫及研磨料的作用下,化学反应的产物被研磨下来并被抛光液带离抛光表面,使未反应的表面重新裸露出来。After through-hole copper plating, a thicker uneven copper layer is also deposited on the wafer surface, and CMP technology needs to be used to remove excess copper and planarize it. Copper CMP technology mainly includes: the oxidant in the alkaline polishing solution chemically reacts with the copper surface to generate copper oxide and cuprous oxide, and the integrating agent converts copper ions or cuprous ions into stable soluble integrated compounds into the solution, which are then used on the grinding disc, Under the action of the polishing pad and abrasives, the products of the chemical reaction are ground down and taken away from the polishing surface by the polishing fluid, leaving the unreacted surface exposed again.
S405,第二通孔上方金属通过第二通孔与衬底连接形成漏极。S405, the metal above the second through hole is connected to the substrate through the second through hole to form a drain electrode.
在一些实施例中,本公开实施例提供的装置具有的功能或包含的模块可以用于执行上文方法实施例描述的方法,其具体实现可以参照上文方法实施例的描述,为了简洁,这里不再赘述。另外,在本申请各个实施例中的各功能单元可以集成在一个处理单元中,也可以是各个单元单独物理存在,也可以两个或两个以上单元集成在一个单元中。In some embodiments, the functions or modules provided by the device provided by the embodiments of the present disclosure can be used to execute the methods described in the above method embodiments. For specific implementation, refer to the description of the above method embodiments. For the sake of brevity, here No longer. In addition, each functional unit in each embodiment of the present application can be integrated into one processing unit, each unit can exist physically alone, or two or more units can be integrated into one unit.
在上述实施例中,可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时,可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时,全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中,或者通过所述计算机可读存储介质进行传输。所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(digital subscriberline,DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质,(例如,软盘、硬盘、磁带)、光介质(例如,数字通用光盘(digital versatiledisc,DVD))、或者半导体介质(例如固态硬盘(solid state disk ,SSD))等。In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in or transmitted over a computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server or data center to another through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) means. A website site, computer, server or data center for transmission. The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains one or more available media integrated. The available media may be magnetic media (eg, floppy disk, hard disk, tape), optical media (eg, digital versatile disc (DVD)), or semiconductor media (eg, solid state disk (SSD)) wait.
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程,该流程可以由计算机程序来指令相关的硬件完成,该程序可存储于计算机可读取存储介质中,该程序在执行时,可包括如上述各方法实施例的流程。而前述的存储介质包括:只读存储器(read-only memory,ROM)或随机存储存储器(random access memory,RAM)、磁碟或者光盘等各种可存储程序代码的介质。Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments are implemented. This process can be completed by instructing relevant hardware through a computer program. The program can be stored in a computer-readable storage medium. When the program is executed, , may include the processes of the above method embodiments. The aforementioned storage media include: read-only memory (ROM) or random access memory (RAM), magnetic disks, optical disks and other media that can store program codes.
以上所述仅是本发明的具体实施方式,使本领域技术人员能够理解或实现本发明。对这些实施例的多种修改对本领域的技术人员来说将是显而易见的,本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下,在其它实施例中实现。因此,本发明将不会被限制于本文所示的这些实施例,而是要符合与本文所申请的原理和新颖特点相一致的最宽的范围。The above descriptions are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be practiced in other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features claimed herein.
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070132017A1 (en) * | 2005-12-06 | 2007-06-14 | Sanyo Electric Co., Ltd. | Semiconductor device and manufacturing method of same |
CN101095218A (en) * | 2004-08-03 | 2007-12-26 | 飞兆半导体公司 | Semiconductor power device having a top-side drain using a sinker trench |
CN102610636A (en) * | 2011-02-07 | 2012-07-25 | 成都芯源系统有限公司 | Vertical semiconductor device and manufacturing method thereof |
-
2023
- 2023-09-25 CN CN202311235601.6A patent/CN116978954A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101095218A (en) * | 2004-08-03 | 2007-12-26 | 飞兆半导体公司 | Semiconductor power device having a top-side drain using a sinker trench |
US20070132017A1 (en) * | 2005-12-06 | 2007-06-14 | Sanyo Electric Co., Ltd. | Semiconductor device and manufacturing method of same |
CN102610636A (en) * | 2011-02-07 | 2012-07-25 | 成都芯源系统有限公司 | Vertical semiconductor device and manufacturing method thereof |
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