JP2019145716A - Semiconductor device - Google Patents

Abstract

To provide a lateral semiconductor device capable of reducing on-resistance without decreasing breakdown voltage.SOLUTION: A semiconductor device 100 is lateral. A semiconductor layer is separated into a first semiconductor region 10 and a second semiconductor region 50 by an insulation film 4. The semiconductor layer comprises a drain electrode 2 in contact with both the first semiconductor region 10 and the second semiconductor region 50, a source electrode 22 in contact with the first semiconductor region 10, and a gate electrode 64 in contact with the second semiconductor region 50. The first semiconductor region 10 comprises an n-type drain region 14 connected to the drain electrode 2, an n-type drift region 16, a p-type base region 18, and an n-type source region 20 provided in a surface layer of the base region 18. The second semiconductor region 50 comprises a p-type first region 52 connected to the drain electrode 2, an n-type second region 54 adjacent to the first region 52, and a p-type third region 62 adjacent to the second region 54 and connected to the gate electrode 64.SELECTED DRAWING: Figure 1

Description

  The present specification discloses a technique related to a horizontal semiconductor device.

Patent Document 1 discloses a horizontal semiconductor device. The semiconductor device of Patent Document 1 includes a source electrode and a drain electrode that are provided on the surface of a semiconductor layer at a distance from each other. The semiconductor layer is provided with an n-type drain region connected to the drain electrode, an n ⁻ -type drift region provided adjacent to the drain region, and adjacent to the drift region on the opposite side of the drain region. A p-type base region, and an n-type source region provided on the surface of the base region and connected to the source electrode and separated from the drift region by the base region. In the semiconductor device of Patent Document 1, a gate electrode is provided on the surface of a semiconductor layer with a gate insulating film interposed therebetween. The gate electrode faces a portion (base region) that separates the drift region and the source region.

JP-A-6-318714

In the semiconductor device of Patent Document 1, when a positive voltage is applied to the gate electrode, an electron channel is formed in a portion (base region) that separates the drift region and the source region, and the drift region and the source region become conductive. The device turns on. Electrons introduced from the source region pass through the drift region and move to the drain region. Thereby, a current flows between the drain electrode and the source electrode. When the application of the positive voltage to the gate electrode is stopped, the electron channel disappears and the semiconductor device is turned off. When the semiconductor device is in the off state, the electric field spreads from the p-type base region to the n ⁻ -type drift region (depletion layer extends), and the breakdown voltage of the semiconductor device is maintained. In Patent Document 1, the n-type impurity contained in the drift region is thinned in order to maintain the breakdown voltage. That is, an n ⁻ type drift region is employed. Therefore, when the semiconductor device is in an on state, electrons need to pass through an n ⁻ type drift region having a high resistance. As a result, the on-resistance of the semiconductor device is increased. Thus, in the conventional semiconductor device, there is a trade-off relationship between increasing the breakdown voltage and reducing the on-resistance. The present specification provides a technique for reducing on-resistance in a lateral semiconductor device without lowering breakdown voltage.

  The semiconductor device disclosed in this specification is a lateral semiconductor device, and a semiconductor layer is separated into a first semiconductor region and a second semiconductor region by an insulating film extending from the front surface to the back surface. The semiconductor device includes a drain electrode in contact with both the first semiconductor region and the second semiconductor region, a source electrode in contact with the first semiconductor region at a position away from the drain electrode, and a position at a distance from the drain electrode. A gate electrode is provided in contact with the second semiconductor region. The first semiconductor region is provided adjacent to the n-type drain region connected to the drain electrode, the n-type drift region having an impurity concentration lower than that of the drain region, and opposite to the drain region. The p-type base region provided adjacent to the drift region on the side, the n-type base region provided on the surface layer of the base region and connected to the source electrode and separated from the drift region by the base region It has a source region. The second semiconductor region includes a p-type first region connected to the drain electrode, an n-type second region provided adjacent to the first region, and an adjacent second region. And has a p-type third region connected to the gate electrode.

  In the semiconductor device, when a positive voltage is applied to the gate electrode (turning on the semiconductor device), holes are injected from the third region to the second region. While positive voltage is applied to the gate electrode, holes injected into the second region have a pn junction (p-type first region and n-type second region) on the drain electrode side. Therefore, it cannot move to the drain electrode through the first region. Therefore, holes are accumulated in the second region, and the potential of the second semiconductor region increases. As a result, in the first semiconductor region, an inversion layer is formed at the interface between the base region and the insulating film, and the interface between the drift region and the insulating film is in an accumulation state. That is, in the semiconductor device, when a positive voltage is applied to the gate electrode, a low resistance accumulation layer is formed in the drift region. When the semiconductor device is in an on state, electrons can move through a low-resistance channel (accumulation layer). When the application of the positive voltage to the gate electrode is stopped (semiconductor device is turned off), holes accumulated in the second region are discharged from the third region, and the potential of the second semiconductor region is lowered. As a result, in the first semiconductor region, the accumulation layer formed in the drift region disappears, and a desired breakdown voltage can be maintained in the high resistance drift region. The semiconductor device can reduce the on-resistance without increasing the impurity concentration of the drift region (without reducing the breakdown voltage of the semiconductor device).

  In the semiconductor device, the interface between the drift region and the base region may be opposed to the interface between the second region and the third region via the insulating film. When the semiconductor device is turned off, an electric field spreads from the p-type base region to the n-type drift region in the first semiconductor region, and an electric field spreads from the p-type third region to the n-type second region in the second semiconductor region. If the two interfaces face each other through the insulating film, the potentials of the first semiconductor region and the second semiconductor region are substantially the same through the insulating film when the semiconductor device is turned off. A load (voltage stress) applied to the insulating film can be reduced, and deterioration of the insulating film can be suppressed.

  In the semiconductor device, the third region may be connected to the gate electrode through a fourth region having a higher p-type impurity concentration than the third region. The gate electrode and the second semiconductor region (third region) can be electrically connected well (contact property is improved).

In the semiconductor device, a fifth region having an n-type impurity concentration higher than that of the second region may be provided at a position away from the first region and the third region in the second region. In the second semiconductor region, a p-type layer (first region) / n ⁻ -type layer (second region) / n-type layer (fifth region) structure is formed from the drain electrode side to the gate electrode side. The It is possible to more reliably prevent holes injected from the third region into the second region from moving to the drain electrode.

  In the semiconductor device, the second semiconductor region may be provided on both sides of the first semiconductor region via an insulating film when the semiconductor layer is viewed in plan. Channels are formed on both side surfaces of the first semiconductor region, and the on-resistance can be further reduced.

  In the semiconductor device, the semiconductor layer may include an active layer of an SOI substrate. By using the SOI substrate, an insulating film from the front surface to the back surface of the semiconductor layer can be formed, and the first semiconductor region and the second semiconductor region can be easily separated.

The top view of the semiconductor device of an Example is shown. Sectional drawing along the II-II line | wire of FIG. 1 is shown. Sectional drawing along the III-III line | wire of FIG. 1 is shown. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 1.

  The semiconductor device 100 will be described with reference to FIGS. The semiconductor device 100 is a horizontal semiconductor device. Therefore, in the semiconductor device 100, the drain electrode 2, the source electrode 22, and the gate electrode 64 appear on the surface side of the device. The drain electrode 2 and the source electrode 22 are provided at intervals (in a non-contact manner). The drain electrode 2 and the gate electrode 64 are also provided at an interval. The drain electrode 2 and the source electrode 22 and the drain electrode 2 and the gate electrode 64 are insulated by the passivation film 6 (see FIGS. 2 to 4). The source electrode 22 and the gate electrode 64 are insulated by an insulating film 4 described later.

  The semiconductor device 100 is manufactured using an SOI (Silicon on Insulator) substrate 9 including a semiconductor substrate 3, a buried insulating layer 5, and a semiconductor layer 7 (see FIGS. 2 to 4). In FIG. 1, illustration of the passivation film 6 is omitted. The semiconductor layer 7 includes a part of the active layer of the SOI substrate 9. The material of the semiconductor substrate 3 is single crystal silicon, and the material of the buried insulating layer 5 is silicon oxide. The semiconductor substrate 3 contains impurities (n-type impurities or p-type impurities) at a high concentration and has a low resistance. Although details will be described later, the semiconductor layer 7 in which the first semiconductor region 10 is provided is formed using the active layer itself of the SOI substrate 9, and the material thereof is single crystal silicon. The semiconductor layer 7 in which the second semiconductor region 50 is provided is formed by removing a part of the active layer of the SOI substrate 9 and using polycrystalline silicon (polysilicon) filled in the removed portion. In the following description, the surface of the semiconductor layer 7 on the side where the passivation film 6 is provided is referred to as the surface of the semiconductor layer 7, and the surface of the semiconductor layer 7 on the side where the embedded insulating layer 5 is provided is the semiconductor layer. 7 may be referred to as the back surface. In the semiconductor device 100, phosphorus (P) is used as an n-type impurity, and boron (B) is used as a p-type impurity.

  As shown in FIG. 1, in the semiconductor device 100, the first semiconductor regions 10 and the second semiconductor regions 50 are alternately provided via the insulating film 4. As shown in FIG. 4, the insulating film 4 extends from the front surface to the back surface of the semiconductor layer 7 (from the passivation film 6 to the buried insulating layer 5). That is, the semiconductor layer 7 is separated into the first semiconductor region 10 and the second semiconductor region 50 by the insulating film 4. The drain electrode 2 is in contact with the side surface of the semiconductor layer 7 (both the first semiconductor region 10 and the second semiconductor region 50). The source electrode 22 is in contact with the surface of the semiconductor layer 7 (first semiconductor region 10) at a position away from the drain electrode 2. The gate electrode 64 is in contact with the side surface of the semiconductor layer 7 (second semiconductor region 50) at a position away from the drain electrode 2. As the material for the drain electrode 2, the source electrode 22, and the gate electrode 64, a metal such as aluminum (Al), an alloy of aluminum and silicon (Al—Si alloy), tungsten (W), copper (Cu), or the like is used. it can. Further, between the drain electrode 2 and the high concentration region 12 and / or the first region 52, between the source electrode 22 and the source region 20 and / or the base contact region 24, and between the gate electrode 64 and the fourth region 62. In addition, a barrier metal layer in which titanium (Ti) and titanium nitride (TiN) are stacked may be disposed.

The first semiconductor region 10 will be described with reference to FIGS. 1 and 2. The first semiconductor region 10 includes an n-type drain region 14, an n-type drift region 16, a p-type base region 18, an n-type source region 20, and a p-type base contact region 24. . The drain region 14 is connected to the drain electrode 2 through a high concentration region 12 containing n-type impurities at a high concentration. The high concentration region 12 can be regarded as a contact region for connecting the drain region 14 and the drain electrode 2 to a low resistance. Therefore, the high concentration region 12 can also be called a part of the drain region 14. That is, it can be said that the drain region 14 is connected to the drain 2 directly or via the high concentration region 12. The impurity concentration of the drain region 14 is adjusted to 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ . The impurity concentration of the high concentration region 12 is adjusted to 5 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ . The high concentration region 12 constitutes one side surface (side surface on the drain electrode 2 side) of the first semiconductor region 10. That is, the high concentration region 12 is provided in a range from the front surface to the back surface of the semiconductor layer 7. Similarly, the drain region 14 is also provided in a range from the front surface to the back surface of the semiconductor layer 7. The high concentration region 12 and the drain region 14 are in contact with the passivation film 6 and the buried insulating layer 5. The drain electrode 2 is in contact with the entire surface of one side surface (high concentration region 12) of the first semiconductor region 10.

The drift region 16 is provided adjacent to the drain region 14. The drift region 16 is provided on the opposite side of the drain electrode 2 with respect to the drain region 14. That is, the drain region 14 and the high concentration region 12 are provided between the drift region 16 and the drain electrode 2. The impurity concentration of the drift region 16 is adjusted to 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ . The impurity concentration of the drift region 16 is lower than the impurity concentration of the drain region 14 (and the high concentration region 12). The drift region 16 is provided in a range from the front surface to the back surface of the semiconductor layer 7 and is in contact with the passivation film 6 and the buried insulating layer 5.

The base region 18 is provided adjacent to the drift region 16. The base region 18 is provided on the opposite side of the drain region 14 with respect to the drift region 16. That is, the drift region 16 is provided between the base region 18 and the drain region 14. The impurity concentration of the base region 18 is adjusted to 5 × 10 ¹⁶ cm ^{−3 to} 5 × 10 ¹⁷ cm ⁻³ . The base region 18 is provided in a range from the front surface to the back surface of the semiconductor layer 7 and is in contact with the passivation film 6 and the buried insulating layer 5.

The source region 20 is provided on the surface layer of the base region 18. The source region 20 is separated from the drift region 16 by the base region 18. That is, a part of the p-type base region 18 exists between the n-type source region 20 and the n-type drift region 16. The impurity concentration of the source region 20 is adjusted to 1 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ . In the thickness direction (Z-axis direction) of the semiconductor layer 7, the thickness of the source region 20 (distance in the Z-axis direction) is adjusted to be half or less of the thickness of the base region 18. Therefore, the source region 20 is not in contact with the buried insulating layer 5.

The base contact region 24 is provided on the surface layer of the base region 18. The base contact region 24 can also be regarded as a high concentration region for connecting the base region 18 and the source electrode 22 to a low resistance. That is, the base contact region 24 can be evaluated as a part of the base region 18. The base contact region 24 is provided on the opposite side of the drift region 16 with respect to the source region 20. That is, the base contact region 24 is not provided in the portion that separates the source region 20 and the drift region 16 in the base region 18. The impurity concentration of the base contact region 24 is adjusted to 5 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ . In the Z-axis direction, the thickness of the base contact region 24 is adjusted to be less than half the thickness of the base region 18. The base contact region 24 is not in contact with the buried insulating layer 5.

Next, the second semiconductor region 50 will be described with reference to FIGS. 1 and 3. In the second semiconductor region 50, from the drain electrode 2 side toward the gate electrode 64, a p ⁺ -type first region 52, an n ⁻ -type second region 54 (54 a), an n-type fifth region 56, n ^{A −} type second region 54 (54 b), a p type third region 60, and a p ⁺ type fourth region 62 are provided. The first to fifth regions 52 to 62 extend from the front surface to the back surface of the semiconductor layer 7 and are in contact with the passivation film 6 and the buried insulating layer 5. The first region 52 is connected to the drain electrode 2, and the fourth region 62 is connected to the gate electrode 64. The impurity concentration of the first region 52 is adjusted to 5 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ , and the impurity concentration of the second region 54 (54a, 54b) is 1 × 10 ¹⁴ cm ^{−. 3} to 1 × 10 ¹⁶ cm ⁻³ , and the impurity concentration of the third region 60 is adjusted to 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ . The impurity concentration is adjusted to 5 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ , and the impurity concentration of the fifth region 56 is 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ . It has been adjusted.

  The fifth region 56 is a region formed by introducing an n-type impurity in a position away from the first region 52 and the third region 60 in the second region 54. The fifth region 56 is formed closer to the first region 52 than the middle point of the second region 54 in the direction connecting the drain electrode 2 and the gate electrode 64 (X-axis direction). In the following description, the second region 54 closer to the drain electrode 2 than the fifth region 54 is referred to as a second region 54a, and the second region 54 closer to the gate electrode 64 than the fifth region 54 is referred to as a second region 54b. May be distinguished. The fourth region 62 can be regarded as a contact region for connecting the third region 60 and the gate electrode 64 to a low resistance. Therefore, it can be said that the third region 60 is connected to the gate electrode 64 through the fourth region 62.

  Next, the relationship between the first semiconductor region 10 and the second semiconductor region 50 will be described. The insulating film 4 extends from the passivation film 6 to the buried insulating layer 5 and separates the first semiconductor region 10 and the second semiconductor region 50. In other words, the insulating film 4 extends from the front surface to the back surface of the semiconductor layer 7, and the first semiconductor region 10 and the second semiconductor region 50 face each other with the insulating film 4 interposed therebetween. The interface between the drift region 16 and the base region 18 of the first semiconductor region 10 is opposed to the interface between the second region 54 b and the third region 60 with the insulating film 4 interposed therebetween. The first semiconductor region 10 and the second semiconductor region 50 are connected to the common drain electrode 2.

  As described above, the first semiconductor regions 10 and the second semiconductor regions 50 are alternately provided via the insulating films 4. That is, the second semiconductor region 50 is provided on both sides of the first semiconductor region 10 in a direction (Y-axis direction) orthogonal to the direction connecting the drain electrode 2 and the source electrode 22 (X-axis direction). In other words, the first semiconductor region 10 is provided on both sides of the second semiconductor region 50 in the Y-axis direction. However, at the end of the semiconductor device 100, the first semiconductor region 10 or the second semiconductor region 50 is provided only on one side of the first semiconductor region 10 and / or the second semiconductor region 50.

  As described above, the second semiconductor region 50 is formed using polycrystalline silicon in which a part of the active layer of the SOI substrate 9 is removed and the removed portion is filled. In the semiconductor device 100, after removing a part of the active layer of the SOI substrate 9, the insulating film 4 is formed by a known method on the side surface (side surface in the Y-axis direction) of the remaining active layer, and then the active layer is removed. Fill the part with polycrystalline silicon. Thereby, a semiconductor layer 7 is manufactured in which the remaining portion of the active layer and the polycrystalline silicon layer face each other with the insulating film 4 interposed therebetween. Thereafter, using a known ion implantation technique, the first semiconductor region 10 is formed in the remaining portion of the active layer, and the second semiconductor region 50 is formed in the polycrystalline silicon layer. Examples of the method for forming the insulating film 4 include thermal oxidation, CVD method, and combined technology of thermal oxidation and CVD method.

Advantages of the semiconductor device 100 will be described. In the semiconductor device 100, the drain electrode 2 is connected to the high potential side of the power supply, the source electrode 22 is connected to the low potential side (for example, ground potential) of the power supply, and the gate electrode 64 is connected to a gate drive circuit (not shown). Connected. The source electrode 22 is also connected to the semiconductor substrate 3. When an on-voltage (positive voltage) is applied to the drift region 16, holes are injected from the third region 60 into the second region 54 b in the second semiconductor region 50. In addition, a p ⁺ / n ⁻ / n structure including a first region 52, a second region 54 a, and a fifth region 56 is provided on the drain electrode 2 side. Since the p ⁺ -type first region 52 is connected to the drain electrode 2, holes injected from the third region 60 into the second region 54 b do not move to the drain electrode 2. Therefore, the potential of the second semiconductor region 50 rises due to the holes injected from the third region 60 into the second region 54b.

When the potential of the second semiconductor region 50 rises, an inversion layer (electron channel) is formed at the interface between the insulating film 4 and the base region 18, and the source region 20 and the drift region 16 become conductive. Electrons injected from the source region 20 move to the drain region 14, and a current flows between the drain electrode 2 and the source electrode 22. Further, when the potential of the second semiconductor region 50 increases, the interface between the insulating film 4 and the drift region 16 is in an accumulation state, and a low resistance (substantially n ⁺ state between the insulating film 4 and the drift region 16 is obtained. ) An accumulation layer is formed. The electrons injected from the source region 20 can move to the drain region 14 through the low resistance accumulation layer when passing through the drift region 16. The semiconductor device 100 can reduce the on-resistance as compared with the conventional semiconductor device in which electrons move in the high-resistance n ⁻ -type drift region, and can pass a larger current than the conventional one. The second semiconductor region 50 functions as a gate portion of the semiconductor device 100.

  When the application of the on-voltage to the gate electrode 64 is stopped, the holes injected into the second region 54b are discharged, and the potential of the second semiconductor region 50 is lowered. As a result, in the first semiconductor region 10, the inversion layer formed in the base region 18 disappears, and the source region 20 and the drift region 16 become nonconductive. No current flows between the drain electrode 2 and the source electrode 22, and the semiconductor device 100 is turned off. When the application of the on-voltage to the gate electrode 64 is stopped, the electric field spreads from the base region 18 toward the drift region 16 in the first semiconductor region 10. Similarly, when the application of the on-voltage to the gate electrode 64 is stopped, the electric field spreads from the third region 60 toward the second region 54b. As a result, the breakdown voltage of the semiconductor device 100 is maintained.

Note that when the potential of the second semiconductor region 50 decreases, the accumulation layer formed in the drift region 16 also disappears in the first semiconductor region 10. That is, when the application of the on-voltage to the gate electrode 64 is stopped, the electric field spreads from the p-type base region 18 to the n ⁻ -type (high resistance) drift region 16. Therefore, the breakdown voltage of the semiconductor device 100 does not decrease as compared with the conventional semiconductor device. The semiconductor device 100 can reduce the on-resistance without lowering the breakdown voltage as compared with the conventional semiconductor device.

  Other advantages of the semiconductor device 100 will be described. As described above, the second semiconductor region 50 (corresponding to the gate portion of the semiconductor device 100) is provided on both sides of the first semiconductor region 10 in the Y-axis direction. Therefore, in semiconductor device 100, inversion layers are formed on both sides of base region 18 and accumulation layers are formed on both sides of drift region 16 in the Y-axis direction when semiconductor device 100 is on. . That is, a channel is formed on both side surfaces in the Y-axis direction of the first semiconductor region 10. Therefore, since the semiconductor device 100 can secure a wide channel, the on-resistance can be further reduced (a large current flows).

  The first semiconductor region 10 and the second semiconductor region 50 are connected to the common drain electrode 2, and the interface between the drift region 16 and the base region 18 is connected to the second region 54 b and the third region via the insulating film 4. Opposite the interface of the region 60. Therefore, when the semiconductor device 100 is in the OFF state, the potential on the first semiconductor region 10 side (potential of the drift region 16) and the potential on the second semiconductor region 50 side (potential of the second region 54b) are interposed via the insulating film 4. ) Are almost the same potential. That is, when the semiconductor device 100 is in the OFF state, the potential difference between the first semiconductor region 10 side of the insulating film 4 and the second semiconductor region 50 side of the insulating film 4 becomes substantially zero. Therefore, when the semiconductor device 100 is in the OFF state, the voltage load applied to the insulating film 4 is suppressed, and deterioration of the insulating film 4 can be suppressed. As a result, it is possible to prevent the durability (life) of the semiconductor device 100 from decreasing.

Further, in the second semiconductor region 50, a fifth region 56 is provided in the second region 54 and divides the second region 54. As a result, a p ⁺ / n ⁻ / n structure is provided from the drain electrode 2 toward the gate electrode 64. By providing the p ⁺ / n ⁻ / n structure, when a positive voltage is applied to the gate electrode 64, the holes introduced into the second region 54 b are suppressed from moving to the first region 52, and the second The potential of the semiconductor region 50 can be easily increased. Further, the fifth region 56 is provided in the second region 54 on the drain electrode 2 side (on the drain electrode 2 side from the midpoint of the second region 54 in the X-axis direction). Therefore, the distance of the second region 54 (second region 54b) closer to the gate electrode 64 than the fifth region 56 can be ensured. When the semiconductor device 100 is in the off state, the electric field tends to spread from the third region 60 toward the second region 54. The breakdown voltage of the semiconductor device 100 (second semiconductor region 50) can be maintained high.

  Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

2: drain electrode 4: insulating film 6: first region 7: semiconductor layer 10: first semiconductor region 14: drain region 16: drift region 18: base region 20: source region 22: source electrode 50: second semiconductor region 52 : First region 54: second region 60: third region 64: gate electrode 100: semiconductor device

Claims (6)

A horizontal semiconductor device,
The semiconductor layer is separated into a first semiconductor region and a second semiconductor region by an insulating film extending from the front surface to the back surface;
A drain electrode in contact with both the first semiconductor region and the second semiconductor region;
A source electrode in contact with the first semiconductor region at a position away from the drain electrode;
A gate electrode in contact with the second semiconductor region at a position away from the drain electrode;
With
The first semiconductor region is
An n-type drain region connected to the drain electrode;
An n-type drift region provided adjacent to the drain region and having an impurity concentration lower than that of the drain region;
A p-type base region provided adjacent to the drift region on the opposite side of the drain region;
An n-type source region provided on a surface layer of the base region and connected to the source electrode and separated from the drift region by the base region;
The second semiconductor region is
A p-type first region connected to the drain electrode;
An n-type second region provided adjacent to the first region;
And a p-type third region provided adjacent to the second region and connected to the gate electrode.   The semiconductor device according to claim 1, wherein an interface between the drift region and the base region is opposed to an interface between the second region and the third region with the insulating film interposed therebetween.   The semiconductor device according to claim 1, wherein the third region is connected to the gate electrode through a fourth region having a p-type impurity concentration higher than that of the third region.   4. The fifth region according to claim 1, wherein a fifth region having an n-type impurity concentration higher than that of the second region is provided at a position apart from the first region and the third region in the second region. The semiconductor device according to one item.   5. The semiconductor device according to claim 1, wherein the second semiconductor region is provided on both sides of the first semiconductor region via the insulating film when the semiconductor layer is viewed in plan.   The semiconductor device according to claim 1, wherein the semiconductor layer includes an active layer of an SOI substrate.

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