CN108461545B - Silicon carbide semiconductor component - Google Patents
Silicon carbide semiconductor component Download PDFInfo
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- CN108461545B CN108461545B CN201710235256.4A CN201710235256A CN108461545B CN 108461545 B CN108461545 B CN 108461545B CN 201710235256 A CN201710235256 A CN 201710235256A CN 108461545 B CN108461545 B CN 108461545B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 39
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 38
- 230000005669 field effect Effects 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000010410 layer Substances 0.000 claims description 84
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 20
- 239000011229 interlayer Substances 0.000 claims description 16
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
- 229910021332 silicide Inorganic materials 0.000 claims description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 7
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 2
- LKTZODAHLMBGLG-UHFFFAOYSA-N alumanylidynesilicon;$l^{2}-alumanylidenesilylidenealuminum Chemical compound [Si]#[Al].[Si]#[Al].[Al]=[Si]=[Al] LKTZODAHLMBGLG-UHFFFAOYSA-N 0.000 claims description 2
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 claims description 2
- -1 aluminum-silicon-copper Chemical compound 0.000 claims description 2
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 claims description 2
- 239000011733 molybdenum Substances 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 229910021344 molybdenum silicide Inorganic materials 0.000 claims description 2
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 claims description 2
- 229910021334 nickel silicide Inorganic materials 0.000 claims description 2
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 abstract description 9
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 5
- 150000004706 metal oxides Chemical class 0.000 abstract description 5
- 230000000694 effects Effects 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- 238000000926 separation method Methods 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- KPSZQYZCNSCYGG-UHFFFAOYSA-N [B].[B] Chemical compound [B].[B] KPSZQYZCNSCYGG-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- VRAIHTAYLFXSJJ-UHFFFAOYSA-N alumane Chemical compound [AlH3].[AlH3] VRAIHTAYLFXSJJ-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
- H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/1608—Silicon carbide
Abstract
A silicon carbide semiconductor component utilizes a silicon carbide substrate to form an integrated structure, and the integrated structure is provided with a metal oxide semiconductor field effect transistor and a junction barrier Schottky diode which is connected with the metal oxide semiconductor field effect transistor in a reverse parallel mode.
Description
[ technical field ] A method for producing a semiconductor device
The present invention relates to a silicon carbide semiconductor device, and more particularly, to a silicon carbide semiconductor device with a low on-resistance ratio.
[ background of the invention ]
In terms of characteristics of the semiconductor power device, it is required that a designed Breakdown voltage should have as small as possible on-resistance, low reverse leakage current, and fast Switching speed so as to reduce on-loss (Conduction loss) and Switching loss (Switching loss) during operation. Silicon carbide (SiC) is considered to be an excellent material for power switch elements because of its characteristics such as a wide energy gap (3.26 eV), a high critical breakdown field strength (2.2MV/cm), and a high thermal conductivity (4.9W/cm-K). Under the condition of the same breakdown voltage, the thickness of a voltage-resistant layer (Drift layer with low doping concentration) of the power component made by taking the silicon carbide as the base material is only one tenth of that of the silicon (Si) power component; and theoretically the on-resistance can be one hundred times of silicon.
However, due to the wide energy gap of SiC, the Body diode (Body diode) of SiC MOSFET has a threshold voltage of about 3V, which causes large power loss when reverse current flows back during switching and limits the switching speed. In addition, the epitaxial Basal plane dislocation (Basal plane dislocation) generated during the deposition of the drift layer of silicon carbide will expand into stacking faults (stacking faults) due to Recombination of carriers when the body diode is turned on, and in severe cases, the SiC MOSFET will fail. Therefore, when a SiC MOSFET is manufactured by a semiconductor manufacturer, a Schottky diode (Schottky diode) is often designed in parallel to increase the operation speed, reduce the switching loss, and avoid the reliability problem caused by the expansion of stacking defects.
For example, taiwan patent publication No. I521718 proposes an integrated device with a Junction Barrier Schottky (JBS) diode embedded in a Metal Oxide Semiconductor (MOS) field effect transistor cell array, comprising a plurality of regions, each region comprising: a plurality of MOS transistor units, wherein the adjacent MOS transistors are separated by a plurality of separation tracks, a first MOS transistor unit is separated from a second MOS transistor unit adjacent in the first direction by a first separation track, and the first MOS transistor unit is separated from a third MOS transistor unit adjacent in the second direction by a second separation track, wherein the MOS transistor units of each region comprise a plurality of well regions with a second conductive type, and the adjacent two well regions are separated by the separation tracks; a drift layer of a first conductivity type on a substrate, the well regions being in the drift layer; at least one JBS diode located in the drift layer at a junction of the first street and the second street, the JBS diode being connected in reverse parallel with the first, second and third MOS transistor units, wherein at least the JBS diode comprises a plurality of first junction barrier regions of the second conductivity type located in the drift layer at the junction, and the first junction barrier regions extending into corners of the wells; a plurality of source regions of the first conductivity type in the wells; a plurality of base layers of the second conductivity type in the source regions of the well regions; and a plurality of source contact windows located on the base layers and part of the source regions and electrically connected with the base layers and part of the source regions; a first anode contact window covering part of the first junction barrier regions and part of the drift layer, and electrically connected with the source contact windows and the first junction barrier regions; and a cathode in the substrate under the drift layer.
For example, in taiwan patent publication No. I352421, an additional area is provided outside the mosfet cell to form an antiparallel junction barrier schottky diode.
In the prior art, the JBS diode of patent I521718 is disposed at the intersection between the MOS transistor cells, i.e., the JBS diode occupies a portion of the area of the well and the separation Channel, respectively, in such a way that the Channel width (Channel width,
unit μm) decrease; in the patent I352421, since the chip area needs to be additionally allocated to the JBS, there is no channel required for the transistor to be turned on in the chip area; both approaches reduce the total channel width per unit area (μm/cm) of the chip2) The current density flowing through the integrated component is reduced, and the on-resistance ratio (i.e. the product RA of the on-resistance and the chip area) of the whole component is improved2) Thus, there is an improvement.
[ summary of the invention ]
The main purpose of the present invention is to solve the problem of high on-resistance caused by the need of sacrificing part of the channel width in the silicon carbide semiconductor device integrated with the JBS diode in the prior art.
In order to achieve the above object, the present invention provides a silicon carbide semiconductor device, which comprises a substrate, an n-type drift layer, a plurality of doped regions, a gate dielectric layer, a gate electrode, an interlayer dielectric layer, a plurality of source openings, a plurality of junction openings, a plurality of gate openings, a first metal layer and a second metal layer, wherein the substrate has an n-type heavy doping, the n-type drift layer is disposed on the substrate and has a first doping concentration, the doped regions are disposed on the n-type drift layer at intervals, a first junction field effect region is formed between the doped regions, the doped regions comprise a p-type well, a plurality of n-type heavy doping regions disposed in the p-type well, a plurality of p-type heavy doping regions adjacent to the n-type heavy doping regions and overlapping with part of the p-type well, and a plurality of second junction field effect regions surrounded by the p-type well, the gate dielectric layer is disposed on the n-type drift layer, the gate electrode is disposed on the gate dielectric layer, the interlayer dielectric layer is disposed on the gate dielectric layer and the gate electrode, the source opening penetrates through the interlayer dielectric layer and the gate dielectric layer until contacting a portion of the n-type heavily doped region and a portion of the p-type heavily doped region, the junction opening penetrates through the interlayer dielectric layer and the gate dielectric layer until contacting the second junction field effect region, a portion of the p-type well and a portion of the p-type heavily doped region, the gate opening penetrates through the interlayer dielectric layer to the gate electrode, the first metal layer is disposed on a bottom side of the source opening and forms an ohmic contact with a portion of the n-type heavily doped region and a portion of the p-type heavily doped region, the second metal layer comprises a first portion and a second portion, and the first portion covers the source opening and is electrically connected with the first metal layer, the first portion covers the junction opening to form a Schottky contact with the second junction field effect region, and the second portion covers the gate opening and is electrically insulated from the first portion.
The silicon carbide semiconductor module according to the present invention may further have the following features: the first junction field effect region has a second doping concentration, the second junction field effect region has a third doping concentration, and the second doping concentration and the third doping concentration are greater than or equal to the first doping concentration.
The silicon carbide semiconductor module according to the present invention may further have the following features: wherein the second doping concentration and the third doping concentration are less than 1 × 1018cm-3。
The silicon carbide semiconductor module according to the present invention may further have the following features: wherein the first doping concentration is less than 5 × 1017cm-3。
The silicon carbide semiconductor module according to the present invention may further have the following features: wherein the p-well has a first depth, the first junction field effect region has a second depth, and the second junction field effect region has a third depth; the second depth and the third depth are greater than or equal to the first depth.
The silicon carbide semiconductor module according to the present invention may further have the following features: wherein the first metal layer comprises a silicide containing nickel.
The silicon carbide semiconductor module according to the present invention may further have the following features: the second metal layer may be selected from the group consisting of titanium, molybdenum, nickel, aluminum, titanium silicide, molybdenum silicide, nickel silicide, aluminum silicide, titanium nitride, aluminum copper alloy, and aluminum silicon copper alloy.
The silicon carbide semiconductor module according to the present invention may further have the following features: wherein the substrate has a resistivity of less than 0.3 Ω · cm.
The silicon carbide semiconductor module according to the present invention may further have the following features: the n-type heavily doped region comprises a plurality of surrounding parts which are adjacent to each other to form a continuous structure, the second junction field effect region is formed in the surrounding parts, and the p-type heavily doped region is formed between the surrounding parts.
The silicon carbide semiconductor module according to the present invention may further have the following features: the n-type heavily doped region comprises a plurality of surrounding parts which are arranged at intervals to form a discontinuous structure, the second junction field effect region is formed in the surrounding parts, and the p-type heavily doped region is formed between the surrounding parts and separates the surrounding parts.
[ Effect and Effect of the invention ]
As can be seen from the above, the present invention has an effect that the n-type heavily doped region, the p-type heavily doped region, the source opening and the junction opening are respectively and correspondingly disposed in the same p-type well, and do not occupy part of the area of the p-type well and the first junction field effect region, nor additionally configure the chip area to form a schottky diode, so that the total channel width of the sic semiconductor device is not affected compared to the conventional integrated device under the condition of the same area, and relatively, the current flowing through the sic semiconductor device is not affected to achieve the effect of reducing the on-resistance ratio.
[ description of the drawings ]
FIG. 1 is a schematic top view of a silicon carbide semiconductor assembly of the present invention;
FIG. 2A is an enlarged schematic view of the area X in FIG. 1 according to a first embodiment of the present invention;
FIG. 2B is an enlarged schematic view of the region X' in FIG. 2A according to a first embodiment of the present invention;
FIG. 2C is a schematic sectional view taken along line A-A in FIG. 2B;
FIG. 2D is a schematic cross-sectional view taken along line B-B of FIG. 2B;
FIG. 2E is a schematic cross-sectional view of C-C of FIG. 2B;
fig. 3A is an enlarged schematic view of the Y region in fig. 1 according to a first embodiment of the present invention.
FIG. 3B is a schematic cross-sectional view taken along line D-D of FIG. 3A;
FIG. 4 is a schematic view of a second embodiment of the present invention; and
fig. 5 is a schematic diagram of a third embodiment of the present invention.
[ embodiment ] A method for producing a semiconductor device
The present invention will be described in detail and with reference to the accompanying drawings, wherein: fig. 1 to 3B are a schematic top view, an enlarged schematic X region in fig. 1 in the first embodiment of the present invention, an enlarged schematic X' region in fig. 2A, a-a cross-sectional view in fig. 2B, a B-B cross-sectional view in fig. 2B, a C-C cross-sectional view in fig. 2B, an enlarged schematic Y region in fig. 1 in the first embodiment of the present invention, and a D-D cross-sectional view in fig. 3A, respectively. As shown in fig. 1 to 3B, a silicon carbide semiconductor device of the present invention includes a substrate 10, an n-type drift layer 20, a plurality of doped regions 30, a gate dielectric layer 40, a gate electrode 50, an interlayer dielectric layer 60, a plurality of source openings 70, a plurality of junction openings 80, a plurality of gate openings 90, a first metal layer 100, and a second metal layer 110. The substrate 10 is a 4H-silicon carbide (4H-SiC) substrate, and in the first embodiment, the substrate 10 is heavily n-doped and has a Resistivity (Resistivity) less than 0.3 Ω · cm. The n-type drift layer 20 is disposed on the substrate 10, and in the first embodiment, the n-type drift layer 20 is lightly doped n-type and has a first doping concentration less than 5 × 1017cm-3In this implementationPreferred embodiments in the examples: for example, when the rated voltage is 650V, the first doping concentration is 1X 1016cm-3The thickness of the n-type drift layer 20 is 5 μm; or when the rated voltage is 1200V, the first doping concentration is 6 multiplied by 1015cm-3The thickness of the n-type drift layer 20 was 11 μm.
The doped regions 30 are disposed on the n-type drift layer 20 at intervals, and a first Junction field effect (Junction field effect) region 31 is formed between the doped regions 30, in the first embodiment, the first Junction field effect region 31 has a second doping concentration, and the second doping concentration is less than 1 × 1018cm-3(ii) a In the preferred embodiment of this embodiment: the second doping concentration is between 1 × 1016cm-3To 2X 1017cm-3In the meantime. The doped region 30 includes a p-well 32, a plurality of n-type heavily doped regions 33, a plurality of p-type heavily doped regions 34, and a plurality of second junction field effect regions 35. As shown in fig. 2A, an outer contour of the top view shape of the p-well 32, the heavily n-doped region 33, the heavily p-doped region 34, and the second jfet region 35 may be square, rectangular, hexagonal, or a combination thereof, in this embodiment, the outer contours are rectangles, for example, the minor axis of the rectangle is parallel to the x-axis, and the major axis is parallel to the y-axis.
As shown in fig. 2B to 2E, the p-type well 32 forms a rectangular ring shape in a top view, and the n-type heavily doped region 33 is disposed in the p-type well 32; the p-type heavily doped region 34 is adjacent to the n-type heavily doped region 33 and overlaps with part of the p-type well 32, the second junction field effect region 35 is surrounded by the p-type well 32, and in the first embodiment, the second junction field effect region 35 has a third doping concentration, and the third doping concentration is less than 1 × 1018cm-3(ii) a The preferred implementation ranges in this embodiment: the third doping concentration is between 1 × 1016cm-3To 2X 1017cm-3In the meantime. In the present embodiment, a portion of the second jfet region 35 is surrounded by the p-well 32, and another portion is adjacent to the p-type heavily doped region 34; in addition, the second junction field region 35 can also be completely surrounded by the p-well 32(ii) a Or completely surrounded by the p-type heavily doped region 34, all of which can achieve the efficacy of the present invention.
In the present invention, the second doping concentration and the third doping concentration are respectively greater than or equal to the first doping concentration. In the first embodiment, the first jfet region 31 has a first depth D1 between 0.5 μm and 1 μm, the p-well 32 has a second depth D2 between 0.5 μm and 1 μm, and the second jfet region 35 has a third depth D3 between 0.5 μm and 1 μm, wherein in the present embodiment, the first depth D1 and the third depth D3 are equal to or greater than the second depth D2, as shown in fig. 2D, the first depth D1 is equal to the third depth D3, and both are greater than the second depth D2. The p-well 32, the n-type heavily doped region 33, and the p-type heavily doped region 34 each have a thickness of 5 × 1017cm-3To 3X 1018cm-3Fourth doping concentration in between, a doping concentration in the range of 5 × 1018cm-3To 1X 1020cm-3A fifth doping concentration in between and a doping concentration in the range of 5 x 1018cm-3To 5X 1019cm-3Sixth doping concentration in between; the heavily n-doped region 33 is doped with phosphorus (Phosphorous) or Nitrogen (Nitrogen), and the p-well 32 and the heavily p-doped region 34 are doped with Aluminum (Aluminum) or Boron (Boron) at an energy of 10keV to 1400 keV.
As shown in fig. 2C, the gate dielectric layer 40 is disposed on the n-type drift layer 20, and the gate dielectric layer 40 may be made of silicon oxide, silicon oxide containing nitrogen, or aluminum oxide, and is formed by thermal oxidation, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or the like. The gate electrode 50 is disposed on the gate dielectric layer 40 and correspondingly on the first junction field effect region 31, and the gate electrode 50 may be made of, for example, p-type heavily doped polysilicon (poly-Si) doped with phosphorus or n-type heavily doped polysilicon doped with boron. The interlayer dielectric layer 60 is disposed on the gate dielectric layer 40 and the gate electrode 50, and may be made of Tetraethoxysilane (TEOS), borophosphosilicate glass (BPSG), Oxynitride (Oxynitride), Undoped Silicate Glass (USG), Silicon nitride (SRN), or a combination thereof.
The source opening 70 is formed by an etching process, the source opening 70 penetrates through the interlayer dielectric layer 60 and the gate dielectric layer 40 until contacting a portion of the heavily n-doped region 33 and a portion of the heavily p-doped region 34, and is correspondingly located above the doped region 30, and the source opening 70 and another source opening 70a are spaced apart from the interlayer dielectric layer 60 by the gate electrode 50.
As shown in fig. 2D and 2B, the junction opening 80 is also formed by the etching, the junction opening 80 penetrates through the interlayer dielectric layer 60 and the gate dielectric layer 40 until contacting the second jfet region 35, a portion of the p-well 32 and a portion of the p-type heavily doped region 34, the junction opening 80 also corresponds to the doped region 30, and the junction opening 80 and another junction opening 80a are separated by the gate electrode 50 and the interlayer dielectric layer 60.
In the present invention, the junction opening 80 and the source opening 70 are spaced apart from each other in the area of one p-type well 32 region and form one unit Cell (Cell), and the area of the silicon carbide semiconductor device is effectively utilized, as shown in fig. 2E.
In the present embodiment, the doped regions 30 are illustrated as rectangles with dimensions similar to those of fig. 2B, and one p-well 32, one n-type heavily doped region 33, one p-type heavily doped region 34, one second junction field effect region 35, one source opening 70 and one junction opening 80 are respectively disposed in a unit cell. In addition, the doped regions 30 may also be strip-shaped with a larger ratio of long side to short side, and one p-type well 32, one continuous n-type heavily doped region 33 or a plurality of n-type heavily doped regions 33 arranged at intervals, a plurality of p-type heavily doped regions 34 arranged at intervals, a plurality of second junction field effect regions 35 arranged at intervals, a plurality of source openings 70 arranged at intervals, and a plurality of junction openings 80 arranged at intervals are respectively arranged in a unit cell.
As shown in fig. 2C and 2E, the first metal layer 100 is disposed on a bottom side of the source opening 70, the material of the first metal layer 100 may be Silicides (Silicides) formed of nickel, titanium, aluminum or a combination thereof, and the preferred embodiment is silicide including nickel, which is deposited by Physical Vapor Deposition (PVD) or chemical vapor deposition (cvd) and then annealed (Annealing), etc., and the first metal layer 100 contacts with a portion of the heavily n-doped region 33 and a portion of the heavily p-doped region 34 and forms an ohmic contact.
As shown in fig. 2C, fig. 2E and fig. 1, the second metal layer 110 may be made of ti, mo, ni, al, ti silicide, mo silicide, ni silicide, al silicide, tin, al-cu (AlCu) alloy, al-si-cu alloy, etc. and is formed by pvd or cvd. In the present invention, the second metal layer 110 includes a first portion 1101 and a second portion 1102, the first portion 1101 covers the source opening 70 and is electrically connected to the first metal layer 100, the first portion 1101 covers the junction opening 80 and forms a Schottky contact (Schottky contact) with the second jfet region 35, the Schottky contact can form a junction barrier Schottky, and the second portion 1102, as shown in fig. 3B, covers the gate opening 90 and is non-contact and electrically insulated from the first portion 1101.
As shown in fig. 3A and 3B, the gate opening 90 passes through the interlayer dielectric layer 60 to the gate electrode 50, in this embodiment, the gate opening 90 can also be formed by etching and is correspondingly located on the gate electrode 50, and a Field oxide layer 51(Field oxide) is further disposed between the gate electrode 50 and the n-type drift layer 20.
In addition, fig. 4 is a schematic diagram of a second embodiment of the invention, and the viewing angle of fig. 4 is the same as that of fig. 2B. As shown in fig. 4, in the present embodiment, the n-type heavily doped region 33 includes a plurality of surrounding portions 331 adjacent to each other, the surrounding portions 331 form a continuous structure, the second jfet region 35 is formed in the surrounding portions 331, and the p-type heavily doped region 34 is formed between the surrounding portions 331.
Fig. 5 is a schematic view of a third embodiment of the present invention, and the viewing angle of fig. 5 is the same as that of fig. 2B. As shown in fig. 5, wherein the n-type heavily doped region 33 forms a discontinuous structure and includes a plurality of surrounding portions 331 spaced apart from each other, the second jfet region 35 is formed in the surrounding portions 331, and the p-type heavily doped region 34 is formed between the surrounding portions 331 and spaced apart from the surrounding portions 331. In the present invention, the sic semiconductor device further includes a drain 120, and the drain 120 is disposed on a side of the substrate 10 away from the n-type drift layer 20, as shown in fig. 2C. Accordingly, the silicon carbide semiconductor component can form an integrated structure which is provided with a metal oxide semiconductor field effect transistor and a junction barrier Schottky diode which is connected with the metal oxide semiconductor field effect transistor in a reverse parallel mode.
[ Effect and Effect of example ]
In summary, since the n-type heavily doped region, the p-type heavily doped region, the source opening, and the junction opening are respectively and correspondingly disposed in the same p-type well in the sic semiconductor device of the present embodiment, and do not occupy a portion of the area of the p-type well and the first junction field effect region, nor do they additionally configure an area to form a schottky diode, the total channel width of the sic semiconductor device in the present embodiment is not affected when compared with the conventional integrated device under the condition of the same area, and relatively, the current flowing through the sic semiconductor device is not affected to achieve the effect of reducing the on-resistance ratio.
The present invention has been described in detail, but the above description is only a preferred embodiment of the present invention, and should not be construed as limiting the scope of the present invention. All equivalent changes and modifications made according to the scope of the present invention should also be covered by the scope of the present invention.
Claims (10)
1. A silicon carbide semiconductor component, comprising:
a substrate with a heavily n-doped region;
an n-type drift layer disposed on the substrate and having a first doping concentration;
the n-type drift layer is arranged on the substrate, a plurality of doped regions are arranged at intervals on the n-type drift layer, a first junction field effect region is formed among the doped regions, and each doped region comprises a p-type well, an n-type heavily doped region arranged in the p-type well, a plurality of p-type heavily doped regions which are adjacent to the n-type heavily doped regions and are overlapped with part of the p-type well, and at least one second junction field effect region which is completely surrounded by the p-type well;
a gate dielectric layer disposed on the n-type drift layer;
a gate electrode disposed on the gate dielectric layer;
an interlayer dielectric layer disposed on the gate dielectric layer and the gate electrode;
a plurality of source openings through the interlayer dielectric layer and the gate dielectric layer to contact portions of the n-type heavily doped region and the p-type heavily doped region;
a plurality of junction openings through the interlayer dielectric layer and the gate dielectric layer to contact the second junction field effect region, a portion of the p-type well, and a portion of the p-type heavily doped region;
a plurality of gate openings through the interlayer dielectric layer to the gate electrodes;
a first metal layer disposed on a bottom side of the source opening and forming an ohmic contact region contacting a portion of the n-type heavily doped region and a portion of the p-type heavily doped region; and
a second metal layer including a first portion and a second portion, the first portion covering the source opening and electrically connected to the first metal layer, the first portion covering the junction opening to form a schottky contact region in contact with the second junction field effect region, the second portion covering the gate opening and electrically insulated from the first portion;
wherein the Schottky contact region is completely surrounded by the n-type heavily doped region and the junction opening and is separated by the source opening.
2. The silicon carbide semiconductor component of claim 1, wherein:
the first junction field effect region has a second doping concentration, the second junction field effect region has a third doping concentration, and the second doping concentration and the third doping concentration are greater than or equal to the first doping concentration.
3. The silicon carbide semiconductor component of claim 2, wherein:
the second doping concentration and the third doping concentration are less than 1 x 1018cm-3。
4. The silicon carbide semiconductor component of claim 1, wherein:
the first doping concentration is less than 5 x 1017cm-3。
5. The silicon carbide semiconductor component of claim 1, wherein:
the p-type well has a first depth, the first junction field effect region has a second depth, and the second junction field effect region has a third depth; the second depth and the third depth are greater than or equal to the first depth.
6. The silicon carbide semiconductor component of claim 1, wherein:
the first metal layer comprises a silicide comprising nickel.
7. The silicon carbide semiconductor component of claim 1, wherein:
the second metal layer is any one of titanium, molybdenum, nickel, aluminum, titanium silicide, molybdenum silicide, nickel silicide, aluminum silicide, titanium nitride, aluminum-copper alloy and aluminum-silicon-copper alloy.
8. The silicon carbide semiconductor component of claim 1, wherein:
the substrate has a resistivity of less than 0.3 Ω · cm.
9. The silicon carbide semiconductor component of claim 1, wherein:
the n-type heavily doped region comprises a plurality of surrounding parts which are adjacent to each other to form a continuous structure, the second junction field effect region is formed in the surrounding parts, and the p-type heavily doped region is formed between the surrounding parts.
10. The silicon carbide semiconductor component of claim 1, wherein:
the n-type heavily doped region comprises a plurality of surrounding parts which are arranged at intervals to form a discontinuous structure, the second junction field effect region is formed in the surrounding parts, and the p-type heavily doped region is formed between the surrounding parts and separates the surrounding parts.
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| JP2005108926A (en) * | 2003-09-29 | 2005-04-21 | Nissan Motor Co Ltd | Semiconductor device |
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| US9583482B2 (en) * | 2015-02-11 | 2017-02-28 | Monolith Semiconductor Inc. | High voltage semiconductor devices and methods of making the devices |
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