JP2005108926A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2005108926A
JP2005108926A JP2003336892A JP2003336892A JP2005108926A JP 2005108926 A JP2005108926 A JP 2005108926A JP 2003336892 A JP2003336892 A JP 2003336892A JP 2003336892 A JP2003336892 A JP 2003336892A JP 2005108926 A JP2005108926 A JP 2005108926A
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schottky
electrode
semiconductor device
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JP4013874B2 (en
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Saichiro Kaneko
佐一郎 金子
Masakatsu Hoshi
正勝 星
Tetsuya Hayashi
哲也 林
Hideaki Tanaka
秀明 田中
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Nissan Motor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can reduce an element area, can improve the degree of integration, and is advantageous to miniaturization. <P>SOLUTION: The semiconductor device is constituted of an N<SP>+</SP>-type SiC substrate 10, an N<SP>-</SP>-type SiC epitaxial region 20 connected and formed with the N<SP>+</SP>-type SiC substrate 10, a P-type well region 30 formed in the predetermined region of a surface layer of N<SP>-</SP>-type SiC epitaxial region 20, an N<SP>+</SP>-type source region 40 formed in the predetermined region of a surface layer of the well region 30, an N-type Schottky connection region 120 formed in a predetermined region different from the source region 40 in the same well region 30 in such a manner that it is separated from the source region 40 and connected with the N<SP>-</SP>-type SiC epitaxial region 20, a Schottky electrode 90 connected with the Schottky connection region 120 and the source region 40, a gate electrode 70 formed on the well region 30 through a gate insulated film 60, and of a drain electrode 100 connected with the N<SP>+</SP>-type SiC substrate 10. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、半導体装置に関するものである。   The present invention relates to a semiconductor device.

下記特許文献に記載された従来のショットキーダイオードを内蔵したSiCパワーMOSFET構造について説明する。
このパワーMOSFETでは、高濃度N＋型SiC基板上にN−型SiCエピタキシャル領域が形成されている。そして、エピタキシャル領域の表層部における所定領域にはP型ウエル領域が形成され、P型ウエル領域内にはN＋型ソース領域が形成されている。P型ウエル領域上にはゲート絶縁膜を介してゲート電極が配置され、ゲート電極は層間絶縁膜にて覆われている。また、隣接するP型ウエル領域間から半導体表面に露出しているエピタキシャル領域上に、このエピタキシャル領域とショットキー接続するショットキー電極が配置されている。このショットキー電極はソース電極と電気的に接続されるか、またはソース電極と同一で構わない。ソース電極はP型ウエル領域及びN＋型ソース領域に接するように形成されるとともに、N＋型SiC基板の裏面にはドレイン電極が形成されている。
その動作は、ドレイン電極とソース電極との間に電圧が印加された状態で、ゲート電極に正の電圧が印加されると、ゲート電極に対向したP型ウエル領域の表層に反転型のチャネルが形成され、ドレイン電極からソース電極へと電流を流すことが可能となる（オン状態）。また、ゲート電極に印加された電圧を取り去ることによってドレイン電極とソース電極との間は電気的に絶縁され（オフ状態）、スイッチング機能を示すことになる。
このパワーMOSFETでは、上記のように隣接するP型ウエル領域間にショットキー電極が配置されるため、オン状態からオフ状態にスイッチングされたときに、P型ウエル領域とエピタキシャル領域からなる内蔵PNダイオードの、遅いリカバリー特性を反映することなく、逆回復時間を決定できるから、スイッチング損失が少ないという特長がある。 A conventional SiC power MOSFET structure incorporating a Schottky diode described in the following patent document will be described.
In this power MOSFET, an N − type SiC epitaxial region is formed on a high concentration N + type SiC substrate. A P-type well region is formed in a predetermined region in the surface layer portion of the epitaxial region, and an N + -type source region is formed in the P-type well region. A gate electrode is disposed on the P-type well region via a gate insulating film, and the gate electrode is covered with an interlayer insulating film. A Schottky electrode that is Schottky connected to the epitaxial region is disposed on the epitaxial region exposed to the semiconductor surface from between adjacent P-type well regions. The Schottky electrode may be electrically connected to the source electrode or the same as the source electrode. The source electrode is formed in contact with the P-type well region and the N + -type source region, and a drain electrode is formed on the back surface of the N + -type SiC substrate.
In the operation, when a positive voltage is applied to the gate electrode while a voltage is applied between the drain electrode and the source electrode, an inverted channel is formed on the surface layer of the P-type well region facing the gate electrode. Thus, current can flow from the drain electrode to the source electrode (ON state). Further, by removing the voltage applied to the gate electrode, the drain electrode and the source electrode are electrically insulated (off state) and exhibit a switching function.
In this power MOSFET, the Schottky electrode is arranged between adjacent P-type well regions as described above, and therefore, when switched from the on-state to the off-state, the built-in PN diode composed of the P-type well region and the epitaxial region Since the reverse recovery time can be determined without reflecting the slow recovery characteristics, the switching loss is small.

特開２００２−２０３９６７号公報JP 2002-203967 A

しかしながら、上記パワーMOSFETでは、隣接するP型ウエル領域間にショットキー電極を設ければ素子面積が拡大する。ショットキー電極はゲート電極と層間絶縁膜によって電気的に絶縁されなければならない。このような構造では層間絶縁膜にコンタクトホールを形成しなければならず、このため、P型ウエル領域相互間の距離は、少なくとも8μｍ程度は必要である。これはP型ウエル領域間にショットキー電極を形成しない構造におけるP型ウエル領域相互間の距離、例えば3μｍに対して2倍以上である。
このような素子面積の拡大は、半導体装置の集積化、小型化にとって大きな支障となる。
本発明の目的は、素子面積を低減し、集積度が向上でき、小型化に有利な半導体装置を提供することにある。 However, in the power MOSFET, the element area is increased if a Schottky electrode is provided between adjacent P-type well regions. The Schottky electrode must be electrically insulated by the gate electrode and the interlayer insulating film. In such a structure, a contact hole must be formed in the interlayer insulating film. For this reason, the distance between the P-type well regions must be at least about 8 μm. This is more than twice the distance between the P-type well regions in a structure in which no Schottky electrode is formed between the P-type well regions, for example, 3 μm.
Such an increase in element area is a major obstacle to the integration and miniaturization of semiconductor devices.
An object of the present invention is to provide a semiconductor device that can reduce the element area, improve the degree of integration, and is advantageous for downsizing.

上記課題を解決するために、本発明は、半導体基体に形成される第1導電型のドレイン領域と、ドレイン領域と接続された第1導電型のドリフト領域と、ドリフト領域の表層部に形成される第2導電型のウエル領域と、ウエル領域の表層部に形成される第1導電型のソース領域と、ウエル領域内のソース領域とは異なる領域に、ソース領域とは分離され、ドリフト領域と接続された第1導電型のショットキー接続領域と、ショットキー接続領域及びソース領域に接続されるショットキー電極と、ウエル領域上にゲート絶縁膜を介して形成されるゲート電極と、ドレイン領域に接続されるドレイン電極とを有する構成になっている。   In order to solve the above problems, the present invention is formed in a first conductivity type drain region formed in a semiconductor substrate, a first conductivity type drift region connected to the drain region, and a surface layer portion of the drift region. The second conductivity type well region, the first conductivity type source region formed in the surface layer of the well region, and the source region are separated from the source region in the well region, and the drift region and A first conductivity type Schottky connection region connected, a Schottky electrode connected to the Schottky connection region and the source region, a gate electrode formed on the well region via a gate insulating film, and a drain region And a drain electrode to be connected.

本発明によれば、素子面積を低減し、集積度が向上でき、小型化に有利な半導体装置を提供することができる。   According to the present invention, an element area can be reduced, an integration degree can be improved, and a semiconductor device advantageous for miniaturization can be provided.

以下、本発明の実施の形態を図面に従って詳細に説明する。以下で説明する図面で、同一機能を有するものは同一符号を付け、その繰り返しの説明は省略する。
なお、本実施の形態で用いられる炭化珪素（SiC）のポリタイプは4Hが代表的であるが、6H、3C等その他のポリタイプでも構わない。また、本実施の形態では、すべてドレイン電極を半導体基板の裏面に形成し、ソース電極を半導体基板の表面に配置して電流を素子内部に縦方向に流す構造の半導体装置で説明した。しかし、例えばドレイン電極をソース電極と同じく半導体基板の表面に配置して、電流を横方向に流す構造の半導体装置でも本発明が適用可能である。
さらに、本実施の形態においては、例えばドレイン領域10がN型、ウエル領域30がP型となるような構成で説明したが、N型、P型の組み合わせはこの限りではなく、例えばドレイン領域10がP型、ウエル領域30がN型となるような構成にしてもよい。
また、本発明の主旨を逸脱しない範囲での変形を含むことは言うまでもない。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings described below, components having the same function are denoted by the same reference numerals, and repeated description thereof is omitted.
The polytype of silicon carbide (SiC) used in this embodiment is typically 4H, but other polytypes such as 6H and 3C may be used. Further, in this embodiment, the semiconductor device has been described in which the drain electrode is formed on the back surface of the semiconductor substrate, the source electrode is disposed on the surface of the semiconductor substrate, and current flows vertically in the element. However, for example, the present invention can also be applied to a semiconductor device having a structure in which a drain electrode is disposed on the surface of a semiconductor substrate in the same manner as the source electrode and current flows in the lateral direction.
Further, in the present embodiment, the drain region 10 is described as being N-type and the well region 30 is defined as P-type, for example, but the combination of N-type and P-type is not limited thereto. May be configured to be P-type and the well region 30 to be N-type.
Moreover, it cannot be overemphasized that the deformation | transformation in the range which does not deviate from the main point of this invention is included.

（実施の形態1）
以下、本発明の半導体装置の実施の形態1を、図1(a)から(c)を参照しながら説明する。図1(b)は半導体装置の平面図である。図1(c)は図1(b)のA-A´断面図、図1(a)は図1(b)のB-B´断面図である。図1(b)の平面図において本来図示されるべきゲート絶縁膜60、ゲート電極70、層間絶縁膜80及びショットキー電極90は、わかりやすさのため、省略した(ゲート電極70の形状については図4(g)、ゲート絶縁膜60、層間絶縁膜80、ショットキー電極90の形状については図4(h)参照)。
図1(b)の平面図及び図1(a)、(c)の断面図に示すように、高濃度N＋型SiC基板(ドレイン領域)10上にN−型SiCエピタキシャル領域(ドリフト領域)20が形成されている。なお、N＋型SiC基板10とN−型SiCエピタキシャル領域20により半導体基体が構成される。そして、エピタキシャル領域20の表層部における所定領域には、P型ウエル領域30が形成されている。このP型ウエル領域30の表層部にはN＋型ソース領域40が形成されている。また、同じくP型ウエル領域30内には、N型ショットキー接続領域120が、エピタキシャル領域20と接続されて形成されている。このショットキー接続領域120上にはコンタクトホール110によりショットキー電極90が形成されている。ショットキー電極90は、N＋型ソース領域40とオーミック接続している。
また、P型ウエル領域30上にはゲート絶縁膜60を介してゲート電極70が配置され、ゲート電極70は層間絶縁膜80にて覆われている。N＋型SiC基板10の裏面にはドレイン電極100が形成されている。 (Embodiment 1)
Hereinafter, a semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS. 1 (a) to 1 (c). FIG. 1B is a plan view of the semiconductor device. 1C is a cross-sectional view taken along the line AA ′ in FIG. 1B, and FIG. 1A is a cross-sectional view taken along the line BB ′ in FIG. The gate insulating film 60, the gate electrode 70, the interlayer insulating film 80, and the Schottky electrode 90 that should be originally illustrated in the plan view of FIG.1 (b) are omitted for the sake of clarity (see FIG. 4 for the shape of the gate electrode 70). (g) For the shapes of the gate insulating film 60, the interlayer insulating film 80, and the Schottky electrode 90, see FIG. 4 (h)).
As shown in the plan view of FIG. 1 (b) and the cross-sectional views of FIGS. 1 (a) and 1 (c), an N − type SiC epitaxial region (drift region) on a high concentration N + type SiC substrate (drain region) 10 20 is formed. The N + -type SiC substrate 10 and the N − -type SiC epitaxial region 20 constitute a semiconductor substrate. A P-type well region 30 is formed in a predetermined region in the surface layer portion of the epitaxial region 20. An N + type source region 40 is formed in the surface layer portion of the P type well region 30. Similarly, an N-type Schottky connection region 120 is formed in the P-type well region 30 so as to be connected to the epitaxial region 20. A Schottky electrode 90 is formed on the Schottky connection region 120 by a contact hole 110. Schottky electrode 90 is in ohmic contact with N + type source region 40.
A gate electrode 70 is disposed on the P-type well region 30 via a gate insulating film 60, and the gate electrode 70 is covered with an interlayer insulating film 80. A drain electrode 100 is formed on the back surface of the N + type SiC substrate 10.

この実施の形態の半導体装置の動作について説明する。
ドレイン電極100とソース電極90との間に電圧が印加された状態で、ゲート電極70に正の電圧が印加されると、ゲート電極70に対向するP型ウエル領域30の表層部に、反転型チャネルが形成される。その結果、ドレイン電極100からP型ウエル領域30、N＋型ソース領域40を経て、ソース電極90へと電流が流れる（オン状態）。
また、ゲート電極70に印加された電圧を取り去ると、P型ウエル領域30の表層部に形成されたチャネルは消失する。その結果、ドレイン電極100とソース電極90との間は電気的に絶縁され（オフ状態）、スイッチング機能を示すことになる。 The operation of the semiconductor device of this embodiment will be described.
When a positive voltage is applied to the gate electrode 70 in a state where a voltage is applied between the drain electrode 100 and the source electrode 90, an inversion type is formed on the surface layer portion of the P-type well region 30 facing the gate electrode 70. A channel is formed. As a result, current flows from the drain electrode 100 to the source electrode 90 through the P-type well region 30 and the N + -type source region 40 (ON state).
Further, when the voltage applied to the gate electrode 70 is removed, the channel formed in the surface layer portion of the P-type well region 30 disappears. As a result, the drain electrode 100 and the source electrode 90 are electrically insulated (off state) and exhibit a switching function.

この半導体装置においては、上記のようにショットキー接続領域120を介してショットキー電極90が配置されているため、オン状態からオフ状態にスイッチングされたときに、P型ウエル領域30とエピタキシャル領域20からなる内蔵PNダイオードの遅いリカバリー特性を反映することなく、逆回復時間を決定できるからスイッチング損失が少ない。もちろん、半導体装置がオン状態の際にはショットキー接続領域120に電流は流れないから、ショットキーダイオードが素子動作に影響を及ぼすことはない。
また、ショットキー電極90はP型ウエル領域30上に形成できるから、上記の従来例のように半導体素子以外の基板表面にショットキー接続領域を設ける必要が無く、より素子面積を小さくできる特長がある。さらに、ショットキー電極90がP型ウエル領域30上に形成できるため、逆導通時に流れる電流密度によって、ショットキー接続領域120とソース領域40の面積比率や間隔を自由に設計できるため、デバイス設計が容易となる。
なお、図1(a)ではショットキー接続領域120はP型ウエル領域30の表層部に形成する例で説明したが、エピタキシャル領域20と接続されさえすれば、ショットキー接続領域120は例えば深さ方向にP型ウエル領域30を貫通して形成されても構わない。 In this semiconductor device, since the Schottky electrode 90 is disposed via the Schottky connection region 120 as described above, the P-type well region 30 and the epitaxial region 20 are switched when switched from the on state to the off state. Since the reverse recovery time can be determined without reflecting the slow recovery characteristics of the built-in PN diode, switching loss is low. Of course, since no current flows through the Schottky connection region 120 when the semiconductor device is in the on state, the Schottky diode does not affect the element operation.
Further, since the Schottky electrode 90 can be formed on the P-type well region 30, there is no need to provide a Schottky connection region on the substrate surface other than the semiconductor element as in the conventional example, and the element area can be further reduced. is there. In addition, since the Schottky electrode 90 can be formed on the P-type well region 30, the area ratio and interval between the Schottky connection region 120 and the source region 40 can be freely designed depending on the current density that flows during reverse conduction, so device design It becomes easy.
In FIG. 1 (a), the Schottky connection region 120 is described as being formed in the surface layer portion of the P-type well region 30, but as long as it is connected to the epitaxial region 20, the Schottky connection region 120 has a depth of, for example, It may be formed through the P-type well region 30 in the direction.

次に、本実施の形態で示した半導体装置の製造方法の一例を、図2(a)から図4(h)の断面図を用いて説明する。
図2（a）の工程においては、N＋型SiC基板10の上に例えば不純物濃度が1×10１４〜1×10１８ｃｍ−３、厚さが１〜100μｍのN−型SiCエピタキシャル領域20が形成されている。
図2（b）の工程においては、エピタキシャル領域20に対して犠牲酸化を行い、その犠牲酸化膜を除去した後（犠牲酸化は行わなくても構わない）にマスク材150を用いて、例えば100〜1000℃の高温でアルミニウムイオンを10k〜3MeVの加速電圧で多段注入し、P型ウエル領域30を形成する。総ドーズ量は例えば1×10１２〜1×10１６cm−２である。もちろんP型不純物としてはアルミニウムの他にほう素、ガリウムなどを用いてもよい。
図2（c）の工程においては、マスク材151を用いて例えば100〜1000℃の高温でアルミニウムイオンを10k〜1MeVの加速電圧で多段注入し、P＋型コンタクト領域50を形成する。総ドーズ量は例えば1×10１４〜1×10１６cm−２である。
図3（d）の工程においては、マスク材152を用いて例えば100〜1000℃の高温で燐イオンを10k〜1MeVの加速電圧で多段注入し、N＋型ソース領域40を形成する。総ドーズ量は例えば1×10１４〜1×10１６cm−２である。もちろんN型不純物としては燐の他に窒素、ヒ素などを用いてもよい。
図3（e）の工程においては、マスク材153を用いて例えば100〜1000℃の高温で窒素イオンを10k〜1MeVの加速電圧で多段注入し、N型ショットキー接続領域120を形成する。総ドーズ量は例えば1×10１２〜1×10１６cm−２である。もちろんN型不純物としては窒素の他に燐、ヒ素などを用いてもよい。
なお、各領域を形成するイオン注入を行う順番については、本例で示す限りではない。
図3（f）の工程においては、例えば1000〜1800℃での熱処理を行い。注入した不純物を活性化させる。
図4（g）の工程においては、ゲート絶縁膜60を1200℃程度での熱酸化により形成し、次に例えば多結晶シリコンによりゲート電極70を形成する。
図4（h）の工程においては、層間絶縁膜80としてCVD酸化膜を堆積し、N＋型ソース領域40、P＋型コンタクト領域50及びN型ショットキー接続領域120上にコンタクトホール110を開孔し、ショットキー（ソース）電極90を形成する。また、N＋基板10裏面にドレイン電極100として金属膜を蒸着し、例えば600〜1400℃程度で熱処理してオーミック電極として、本実施の形態の半導体装置が完成する。 Next, an example of a method for manufacturing the semiconductor device described in this embodiment will be described with reference to cross-sectional views in FIGS. 2 (a) to 4 (h).
In the step of FIG. 2A, an N − type SiC epitaxial region 20 having, for example, an impurity concentration of 1 × 10 14 to 1 × 10 18 cm −3 and a thickness of 1 to 100 μm is formed on the N + type SiC substrate 10. Is formed.
In the step of FIG. 2B, sacrificial oxidation is performed on the epitaxial region 20, and after the sacrificial oxide film is removed (sacrificial oxidation may not be performed), the mask material 150 is used, for example, 100 Multi-stage implantation of aluminum ions at an acceleration voltage of 10 k to 3 MeV at a high temperature of ˜1000 ° C. forms the P-type well region 30. The total dose is, for example, 1 × 10 12 to 1 × 10 16 cm −2 . Of course, boron or gallium may be used as the P-type impurity in addition to aluminum.
In the step of FIG. 2C, aluminum ions are implanted in a multistage manner at an acceleration voltage of 10 k to 1 MeV at a high temperature of, for example, 100 to 1000 ° C. using the mask material 151 to form the P + -type contact region 50. The total dose is, for example, 1 × 10 14 to 1 × 10 16 cm −2 .
In the step of FIG. 3D, phosphorus ions are implanted in multiple stages at a high temperature of, for example, 100 to 1000 ° C. with an acceleration voltage of 10 k to 1 MeV using the mask material 152 to form the N + type source region 40. The total dose is, for example, 1 × 10 14 to 1 × 10 16 cm −2 . Of course, as the N-type impurity, nitrogen, arsenic, or the like may be used in addition to phosphorus.
In the step of FIG. 3 (e), the N-type Schottky connection region 120 is formed by multi-stage implantation of nitrogen ions at a high temperature of, for example, 100 to 1000 ° C. with an acceleration voltage of 10 k to 1 MeV using the mask material 153. The total dose is, for example, 1 × 10 12 to 1 × 10 16 cm −2 . Of course, as the N-type impurity, phosphorus, arsenic, or the like may be used in addition to nitrogen.
Note that the order of ion implantation for forming each region is not limited to that shown in this example.
In the step of FIG. 3 (f), for example, heat treatment is performed at 1000 to 1800 ° C. The implanted impurity is activated.
In the step of FIG. 4G, the gate insulating film 60 is formed by thermal oxidation at about 1200 ° C., and then the gate electrode 70 is formed from, for example, polycrystalline silicon.
In the process of FIG. 4 (h), a CVD oxide film is deposited as the interlayer insulating film 80, and contact holes 110 are opened on the N + type source region 40, the P + type contact region 50, and the N type Schottky connection region 120. A Schottky (source) electrode 90 is formed. In addition, a metal film is deposited as the drain electrode 100 on the back surface of the N + substrate 10 and heat-treated at, for example, about 600 to 1400 ° C. to complete the semiconductor device of this embodiment as an ohmic electrode.

上記ではP型ウエル領域30を図1に示したように縞（ストライプ）状に配置する例で説明したが、P型ウエル領域30は必ずしも縞状に配置する必要は無く、格子状、セル状などとなるように形成してもよい。   In the above description, the P-type well region 30 is arranged in a striped pattern as shown in FIG. 1, but the P-type well region 30 is not necessarily arranged in a striped pattern. You may form so that it may become.

例えば、図5、図6にP型ウエル領域30をセル状に配置した例を示す。図5(a)、図6(a)は半導体装置の平面図である（図6(a)は図5(a)を90°左回転させた図）。ここでは数個の単位MOSFETセルを配置した例を示しているが、単位MOSFETセルの個数に制限は無く、所望の電流容量などに基づいて集積化するセルの数を適宜定めればよい。また、ここでは同形（正六角形）のMOSFETセルを規則的に配列しているが、その形状や配列方法にも特に制限はない。例えばP型ウエル領域30の角部を丸みを帯びた形状とすると、耐圧を確保する上で有利となる。さらに、絶縁耐圧を上げるためにMOSFET領域全体の外側にガードリングなど耐圧が向上する構造を配置してもよい。
図5(a)（図6(a)）において本来図示されるべきゲート絶縁膜60、ゲート電極70、層間絶縁膜80及びショットキー電極90は、わかりやすさのため省略した。
図5(b)は図5(a)のJ-J´の断面図、図6(b)は図6(a)のK-K´の断面図である。
図6(a)の平面図及び図6(b)の断面図に示されるように、P型ウエル領域30内にはN型ショットキー接続領域124が、エピタキシャル領域20と接続されて形成される。ショットキー接続領域124上にはコンタクトホール110によりショットキー電極90が形成され、このショットキー電極90は、同じくP型ウエル領域30の表層部に形成されるN＋型ソース領域40とオーミック接続している。
このようにP型ウエル領域30をセル状に配置した半導体装置においても、縞（ストライプ）状に形成した図1(a)から(c)の半導体装置と同様の効果が得られる。 For example, FIGS. 5 and 6 show examples in which the P-type well regions 30 are arranged in a cell shape. FIGS. 5 (a) and 6 (a) are plan views of the semiconductor device (FIG. 6 (a) is a diagram obtained by rotating FIG. 5 (a) 90 ° counterclockwise). Although an example in which several unit MOSFET cells are arranged is shown here, the number of unit MOSFET cells is not limited, and the number of cells to be integrated may be appropriately determined based on a desired current capacity or the like. In addition, here, the same-shaped (regular hexagonal) MOSFET cells are regularly arranged, but the shape and arrangement method are not particularly limited. For example, if the corner of the P-type well region 30 has a rounded shape, it is advantageous in securing a breakdown voltage. Furthermore, in order to increase the withstand voltage, a structure such as a guard ring that improves the withstand voltage may be arranged outside the entire MOSFET region.
In FIG. 5 (a) (FIG. 6 (a)), the gate insulating film 60, the gate electrode 70, the interlayer insulating film 80, and the Schottky electrode 90 that should be originally illustrated are omitted for the sake of clarity.
5B is a cross-sectional view of JJ ′ in FIG. 5A, and FIG. 6B is a cross-sectional view of KK ′ in FIG. 6A.
As shown in the plan view of FIG. 6 (a) and the cross-sectional view of FIG. 6 (b), an N-type Schottky connection region 124 is formed in the P-type well region 30 so as to be connected to the epitaxial region 20. . A Schottky electrode 90 is formed on the Schottky connection region 124 by a contact hole 110, and this Schottky electrode 90 is ohmically connected to an N + type source region 40 that is also formed in the surface layer portion of the P-type well region 30. ing.
Thus, even in the semiconductor device in which the P-type well region 30 is arranged in a cell shape, the same effects as those of the semiconductor device in FIGS. 1A to 1C formed in a stripe shape can be obtained.

上記のように本実施の形態の半導体装置は、半導体基体に形成される第1導電型のドレイン領域であるN＋型SiC基板10と、該N＋型SiC基板10と接続されて形成される第1導電型のドリフト領域であるN−型SiCエピタキシャル領域20と、該N−型SiCエピタキシャル領域20の表層部の所定領域に形成される第2導電型のP型ウエル領域30と、該ウエル領域30の表層部の所定領域に形成される第1導電型のN＋型ソース領域40と、同じくウエル領域30内のソース領域40とは異なる所定領域に、ソース領域40とは分離され、N−型SiCエピタキシャル領域20と接続されるように形成される第1導電型のN型ショットキー接続領域120と、該ショットキー接続領域120及びソース領域40に接続されるショットキー電極90と、ウエル領域30上にゲート絶縁膜60を介して形成されるゲート電極70と、N＋型SiC基板10接続されるドレイン電極100とを有する構成になっている。本実施の形態は、SiC半導体で形成したMOSFETと並列接続されるショットキーダイオードをMOSFETと同一の半導体基板に形成する半導体装置であって、ショットキーダイオードとMOSFETの配置を工夫することで集積度を向上させるもので、その特徴は、図1(b)に示したように、トランジスタのチャネル領域を構成するP型ウエル領域30の中に所定の間隔でトランジスタのドレイン領域を構成するN−型SiCエピタキシャル領域20と接合するN型ショットキー接続領域120を形成することと、MOSFETとショットキーダイオードの配置、特にN−型SiCエピタキシャル領域20の形成位置にある。このような構成によれば、ショットキー電極90を第2導電型のウエル領域30上に配置できるので、半導体素子以外の基板表面にショットキー接続領域を設ける必要がなく、従来の半導体素子に比べてより素子面積を小さくできる。また、ショットキー電極90を第2導電型のウエル領域30上に配置できるので、ショットキー接続領域120とソース領域40との面積比率や間隔の設計が容易である。
また、ショットキー電極90が、ショットキー接続領域120とはショットキー接続し、ソース領域40とはオーミック接続しているので、ソース電極40とショットキー電極90を同一材料で形成できるため、素子の作製が容易となる。
また、半導体基体として炭化珪素(SiC)を用いたので、半導体基板として最大絶縁破壊電界がシリコンと比較して一桁も大きいSiCを用いることができるため、電気的な耐圧特性に優れ、高耐圧化が容易となる。 As described above, the semiconductor device of the present embodiment is formed by connecting to the N + type SiC substrate 10 which is the drain region of the first conductivity type formed on the semiconductor substrate, and the N + type SiC substrate 10. An N − type SiC epitaxial region 20 which is a drift region of the first conductivity type, a P type well region 30 of a second conductivity type formed in a predetermined region of the surface layer portion of the N − type SiC epitaxial region 20, and the well The first conductivity type N + type source region 40 formed in a predetermined region of the surface layer portion of the region 30 is separated from the source region 40 into a predetermined region which is also different from the source region 40 in the well region 30, and N A first conductivity type N-type Schottky connection region 120 formed so as to be connected to the − type SiC epitaxial region 20, a Schottky electrode 90 connected to the Schottky connection region 120 and the source region 40, and a well Gate electricity formed on the region 30 through the gate insulating film 60 The electrode 70 and the drain electrode 100 connected to the N + type SiC substrate 10 are configured. This embodiment is a semiconductor device in which a Schottky diode connected in parallel with a MOSFET formed of a SiC semiconductor is formed on the same semiconductor substrate as the MOSFET, and the degree of integration is devised by devising the arrangement of the Schottky diode and the MOSFET. As shown in FIG. 1 (b), the feature is that the N − type that forms the drain region of the transistor at a predetermined interval in the P type well region 30 that forms the channel region of the transistor. The N-type Schottky connection region 120 to be joined to the SiC epitaxial region 20 is formed, and the arrangement of the MOSFET and the Schottky diode, particularly the N − -type SiC epitaxial region 20 is formed. According to such a configuration, since the Schottky electrode 90 can be disposed on the second conductivity type well region 30, it is not necessary to provide a Schottky connection region on the surface of the substrate other than the semiconductor element, compared to a conventional semiconductor element. Thus, the element area can be further reduced. In addition, since the Schottky electrode 90 can be disposed on the second conductivity type well region 30, it is easy to design the area ratio and interval between the Schottky connection region 120 and the source region 40.
Since the Schottky electrode 90 is Schottky connected to the Schottky connection region 120 and ohmic connected to the source region 40, the source electrode 40 and the Schottky electrode 90 can be formed of the same material. Manufacture is easy.
In addition, since silicon carbide (SiC) is used as the semiconductor substrate, it is possible to use SiC with a maximum dielectric breakdown electric field that is an order of magnitude larger than that of silicon as the semiconductor substrate. It becomes easy.

（実施の形態2）
以下、本発明の半導体装置の実施の形態2を、図7、図8を参照しながら説明する。図7(b)及び図8(b)は半導体装置の平面図である。
図7(a)は図7(b)のC-C´断面図、図8(a)は図8(b)のD-D´の断面図となっている。
図7(b)及び図8(b)におけるA-A´断面図は図1(c)参照。
図7(b)及び図8(b)において本来図示されるべきゲート絶縁膜60、ゲート電極70、層間絶縁膜80及びショットキー電極90は、わかりやすさのため省略した。
図7(a)、(b)で表される半導体装置と実施の形態1との相違は、N型ショットキー接続領域の配置方法にある。実施の形態1では図1(a)に示すようにN型ショットキー接続領域120の真上にゲート絶縁膜60を介してゲート電極70が形成された。一方、本半導体装置では、ショットキー接続領域121の真上にゲート絶縁膜60を介してゲート電極70が形成されないように、ショットキー接続領域121がウエル領域30の内部に配置されている（図7(a)）。
図8(a)、(b)で表される半導体装置と実施の形態1との相違も同様で、ショットキー接続領域122の真上にゲート絶縁膜60を介してゲート電極70が形成されないように、ショットキー接続領域122がウエル領域30の内部に配置されている（図8(a)）。
このような構造では、ショットキー電極90からショットキー接続領域121（122）を経てドレイン電極100へ流れる逆電流がゲート電極70の直下を流れないため、ゲート絶縁膜60の信頼性が向上し、実施の形態1に比べて半導体素子の寿命をより長くできるという特長がある。 (Embodiment 2)
Hereinafter, a second embodiment of the semiconductor device of the present invention will be described with reference to FIGS. 7 (b) and 8 (b) are plan views of the semiconductor device.
FIG. 7 (a) is a cross-sectional view taken along the line CC ′ of FIG. 7 (b), and FIG. 8 (a) is a cross-sectional view taken along the line DD ′ of FIG. 8 (b).
Refer to FIG. 1C for the AA ′ cross-sectional views in FIG. 7B and FIG. 8B.
The gate insulating film 60, the gate electrode 70, the interlayer insulating film 80, and the Schottky electrode 90 that should be originally illustrated in FIGS. 7B and 8B are omitted for the sake of clarity.
The difference between the semiconductor device shown in FIGS. 7 (a) and 7 (b) and the first embodiment is the arrangement method of the N-type Schottky connection region. In the first embodiment, as shown in FIG. 1A, the gate electrode 70 is formed directly above the N-type Schottky connection region 120 with the gate insulating film 60 interposed therebetween. On the other hand, in this semiconductor device, the Schottky connection region 121 is disposed inside the well region 30 so that the gate electrode 70 is not formed directly above the Schottky connection region 121 via the gate insulating film 60 (FIG. 7 (a)).
The difference between the semiconductor device shown in FIGS. 8 (a) and 8 (b) and the first embodiment is also the same, and the gate electrode 70 is not formed via the gate insulating film 60 directly above the Schottky connection region 122. In addition, a Schottky connection region 122 is disposed inside the well region 30 (FIG. 8 (a)).
In such a structure, since the reverse current flowing from the Schottky electrode 90 to the drain electrode 100 via the Schottky connection region 121 (122) does not flow directly under the gate electrode 70, the reliability of the gate insulating film 60 is improved. Compared to the first embodiment, there is a feature that the lifetime of the semiconductor element can be extended.

（実施の形態3）
以下、本発明の半導体装置の実施の形態3を、図9(a)から(c)を参照しながら説明する。図9(b)は半導体装置の平面図である。図9(c)は図9(b)のE-E´断面図、図9(a)は図9(b)のF-F´の断面図となっている。
図9(b)において本来図示されるべきゲート絶縁膜60、ゲート電極70、層間絶縁膜80及びショットキー電極90は、わかりやすさのため省略した。
図9(a)から(c)に表される半導体装置と実施の形態1との相違は、ゲート絶縁膜60直下のP型ウエル領域30の表層部、すなわち、P型ウエル領域30の表層部及び基板表面に露出されたエピタキシャル領域20の表層部に蓄積型チャネル130が配置されていることである。
この実施の形態の半導体装置の動作について説明する。
ドレイン電極100とソース電極90との間に電圧が印加された状態で、ゲート電極70に正の電圧が印加されると、ゲート電極70に対向する蓄積型チャネル130の表層部にキャリアが誘起される。その結果、ドレイン電極100から蓄積型チャネル130、N＋型ソース領域40を経て、ソース電極90へと電流が流れる（オン状態）。
また、ゲート電極70に印加された電圧を取り去ると、蓄積型チャネル130はP型ウエル領域30とのビルトインポテンシャルにより空乏化されるため、チャネルは消失する。その結果、ドレイン電極100とソース電極90との間は電気的に絶縁され（オフ状態）、スイッチング機能を示すことになる。
本実施の形態で形成した蓄積型チャネル130を流れるキャリアは、実施の形態1で形成された反転型チャネルを流れるそれに比べて、ゲート絶縁膜60とP型ウエル領域30との界面準位の影響を受けにくく、その結果、チャネル抵抗を小さくできる特長がある。即ち、本実施の形態では素子のオン抵抗をより小さくできる。 (Embodiment 3)
The third embodiment of the semiconductor device of the present invention will be described below with reference to FIGS. 9 (a) to (c). FIG. 9B is a plan view of the semiconductor device. 9C is a cross-sectional view taken along the line EE ′ of FIG. 9B, and FIG. 9A is a cross-sectional view taken along the line FF ′ of FIG. 9B.
In FIG. 9B, the gate insulating film 60, the gate electrode 70, the interlayer insulating film 80, and the Schottky electrode 90 that should be originally illustrated are omitted for the sake of clarity.
The difference between the semiconductor device shown in FIGS. 9A to 9C and the first embodiment is that the surface layer portion of the P-type well region 30 immediately below the gate insulating film 60, that is, the surface layer portion of the P-type well region 30 In addition, the storage channel 130 is disposed in the surface layer portion of the epitaxial region 20 exposed on the substrate surface.
The operation of the semiconductor device of this embodiment will be described.
When a positive voltage is applied to the gate electrode 70 with a voltage applied between the drain electrode 100 and the source electrode 90, carriers are induced in the surface layer portion of the storage channel 130 facing the gate electrode 70. The As a result, a current flows from the drain electrode 100 to the source electrode 90 through the storage channel 130 and the N + -type source region 40 (ON state).
When the voltage applied to the gate electrode 70 is removed, the storage channel 130 is depleted by the built-in potential with the P-type well region 30, and the channel disappears. As a result, the drain electrode 100 and the source electrode 90 are electrically insulated (off state) and exhibit a switching function.
The carrier flowing through the storage channel 130 formed in the present embodiment is more influenced by the interface state between the gate insulating film 60 and the P-type well region 30 than that flowing through the inverted channel formed in the first embodiment. As a result, the channel resistance can be reduced. That is, in this embodiment, the on-resistance of the element can be further reduced.

なお、本実施の形態では基板表面に露出されたエピタキシャル領域20の表層部にも蓄積型チャネル130を形成した例で説明したが、エピタキシャル領域20の表層部には蓄積型チャネル130は形成されなくて構わない。図9(a)では蓄積型チャネル130はショットキー接続領域120と接続された例で説明したが、両者は接続されなくても構わない。   In this embodiment, the storage channel 130 is formed in the surface layer portion of the epitaxial region 20 exposed on the substrate surface. However, the storage channel 130 is not formed in the surface layer portion of the epitaxial region 20. It doesn't matter. In FIG. 9 (a), the storage channel 130 has been described as being connected to the Schottky connection region 120, but the two may not be connected.

（実施の形態4）
以下、本発明の半導体装置の実施の形態4を、図10(a)から(c)を参照しながら説明する。図10(b)は半導体装置の平面図である。図10(c)は図10(b)のG-G´断面図、図10(a)は図10(b)のH-H´断面図である。図10(b)において本来図示されるべきゲート絶縁膜61、ゲート電極71、層間絶縁膜80及びショットキー電極90は、わかりやすさのため省略した。
図10(b)の平面図及び図10(a)、(c)の断面図に示すように、高濃度N＋型SiC基板10上にN−型SiCエピタキシャル領域20が形成されている。そして、エピタキシャル領域20の表層部における所定領域にはP型ウエル領域31が形成されている。さらにP型ウエル領域31の表層部にはN＋型ソース領域40が形成されている。エピタキシャル領域20は、N＋型ソース領域40からウエル領域31を貫通してエピタキシャル領域20にまで達する凹部（溝、トレンチ）140を有している。また、P型ウエル領域31の表層部にはN型ショットキー接続領域123が、エピタキシャル領域20と接続されて形成されている。ショットキー接続領域123上にはコンタクトホール110を介してショットキー電極90が形成され、このショットキー電極90は、同じくP型ウエル領域31の表層部に形成されるN＋型ソース領域40とオーミック接続している。
また、ゲート電極71が凹部140内にゲート絶縁膜61を介して配置され、ゲート電極71は層間絶縁膜80にて覆われている。N＋型SiC基板10の裏面にはドレイン電極100が形成されている。
この実施の形態の半導体装置が実施の形態1と異なる点は、N＋型ソース領域40からウエル領域31を貫通してエピタキシャル領域20にまで達する凹部140を有し、ゲート電極71が凹部140内にゲート絶縁膜61を介して配置されている溝（トレンチ）ゲート型構造を採用している点である。
その結果、実施の形態1の半導体装置と比べて、より素子面積を小さくすることができる。
なお、ここでも図5(a)（図6(a)）を参照して説明したように、単位MOSFETセルの個数、形状、配置方法などに特に制限はないことはもちろんである。 (Embodiment 4)
Hereinafter, a semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIGS. 10 (a) to 10 (c). FIG. 10B is a plan view of the semiconductor device. 10C is a cross-sectional view taken along the line GG ′ in FIG. 10B, and FIG. 10A is a cross-sectional view taken along the line HH ′ in FIG. The gate insulating film 61, the gate electrode 71, the interlayer insulating film 80, and the Schottky electrode 90 that should be originally illustrated in FIG. 10B are omitted for the sake of clarity.
As shown in the plan view of FIG. 10B and the cross-sectional views of FIGS. 10A and 10C, the N − type SiC epitaxial region 20 is formed on the high concentration N + type SiC substrate 10. A P-type well region 31 is formed in a predetermined region in the surface layer portion of the epitaxial region 20. Further, an N + type source region 40 is formed in the surface layer portion of the P type well region 31. The epitaxial region 20 has a recess (groove, trench) 140 that extends from the N + type source region 40 to the epitaxial region 20 through the well region 31. Further, an N-type Schottky connection region 123 is formed in the surface layer portion of the P-type well region 31 so as to be connected to the epitaxial region 20. A Schottky electrode 90 is formed on the Schottky connection region 123 through a contact hole 110. The Schottky electrode 90 is in ohmic contact with the N + type source region 40 which is also formed in the surface layer portion of the P-type well region 31. Connected.
Further, the gate electrode 71 is disposed in the recess 140 via the gate insulating film 61, and the gate electrode 71 is covered with the interlayer insulating film 80. A drain electrode 100 is formed on the back surface of the N + type SiC substrate 10.
The semiconductor device of this embodiment is different from that of the first embodiment in that it has a recess 140 that extends from the N + type source region 40 to the epitaxial region 20 through the well region 31, and the gate electrode 71 is in the recess 140. In other words, a trench (trench) gate type structure is employed, which is disposed with a gate insulating film 61 interposed therebetween.
As a result, the element area can be further reduced as compared with the semiconductor device of the first embodiment.
Here, as described with reference to FIG. 5 (a) (FIG. 6 (a)), there are of course no particular restrictions on the number, shape, arrangement method, etc. of the unit MOSFET cells.

(a)は(b)のB-B´の断面図、(b)は本発明の半導体装置の実施の形態1を表す平面図、(c)は(b)のA-A´の断面図である。(a) is a sectional view taken along the line BB ′ of (b), (b) is a plan view showing the first embodiment of the semiconductor device of the present invention, and (c) is a sectional view taken along the line AA ′ of (b). （a）〜（c）は本発明の実施の形態1の製造工程を示す断面図である。(A)-(c) is sectional drawing which shows the manufacturing process of Embodiment 1 of this invention. （d）〜（f）は本発明の実施の形態1の製造工程を示す断面図である。(D)-(f) is sectional drawing which shows the manufacturing process of Embodiment 1 of this invention. （g）、（h）は本発明の実施の形態1の製造工程を示す断面図である。(G), (h) is sectional drawing which shows the manufacturing process of Embodiment 1 of this invention. (a)は本発明の半導体装置の実施の形態1の、別の配置例を示す平面図、(b)は(a)のJ-J´の断面図である。(a) is a plan view showing another arrangement example of the semiconductor device according to the first embodiment of the present invention, and (b) is a sectional view taken along line J-J ′ of (a). (a)は図5(a)を90°左回転させた図、(b)は図6(a)（または図5(a)）のK-K´の断面図である。FIG. 5A is a diagram in which FIG. 5A is rotated 90 ° counterclockwise, and FIG. 5B is a cross-sectional view taken along the line K-K ′ in FIG. 6A (or FIG. 5A). (a)は(b)のC-C´の断面図、(b)は本発明の半導体装置の実施の形態2を表す平面図である。(a) is a cross-sectional view taken along the line CC ′ of (b), and (b) is a plan view showing the second embodiment of the semiconductor device of the present invention. (a)は(b)のD-D´の断面図、(b)は本発明の半導体装置の実施の形態2の、ショットキー接続領域の別の配置例を示す平面図である。(a) is a cross-sectional view taken along the line DD ′ of (b), and (b) is a plan view showing another arrangement example of the Schottky connection region in the second embodiment of the semiconductor device of the present invention. (a)は(b)のF-F´の断面図、(b)は本発明の半導体装置の実施の形態3を表す平面図、(c)は(b)のE-E´の断面図である。(a) is a sectional view taken along line FF ′ in (b), (b) is a plan view showing the third embodiment of the semiconductor device of the present invention, and (c) is a sectional view taken along line E-E ′ in (b). (a)は(b)のH-H´の断面図、(b)は本発明の半導体装置の実施の形態4を表す平面図、(c)は(b)のG-G´の断面図である。(a) is a cross-sectional view taken along the line H-H 'in (b), (b) is a plan view showing the fourth embodiment of the semiconductor device of the present invention, and (c) is a cross-sectional view taken along the line GG' in (b).

符号の説明Explanation of symbols

10…N＋型SiC基板(ドレイン領域)
20…N−型SiCエピタキシャル領域(ドリフト領域)
30、31…P型ウエル領域
40…N＋型ソース領域
50…P＋型コンタクト領域
60、61…ゲート絶縁膜
70、71…ゲート電極
80…層間絶縁膜
90…ショットキー電極（ソース電極）
100…ドレイン電極
110…ソースコンタクトホール
120、121、122、123、124…N型ショットキー接続領域
130…蓄積型チャネル
140…溝
150、151、152、153…マスク材 10… N + SiC substrate (drain region)
20 ... N - type SiC epitaxial region (drift region)
30, 31 ... P-type well region
40 ... N + type source region
50… P + contact area
60, 61 ... Gate insulation film
70, 71 ... gate electrode
80… Interlayer insulation film
90 ... Schottky electrode (source electrode)
100 ... Drain electrode
110 ... Source contact hole
120, 121, 122, 123, 124 ... N-type Schottky connection area
130 ... Storage channel
140 ... groove
150, 151, 152, 153 ... Mask material

Claims (6)

半導体基体に形成される第1導電型のドレイン領域と、該ドレイン領域と接続されて形成される第1導電型のドリフト領域と、該ドリフト領域の表層部の所定領域に形成される第2導電型のウエル領域と、該ウエル領域の表層部の所定領域に形成される第1導電型のソース領域と、同じく前記ウエル領域内の前記ソース領域とは異なる所定領域に、前記ソース領域とは分離され、前記ドリフト領域と接続されるように形成される第1導電型のショットキー接続領域と、該ショットキー接続領域及び前記ソース領域に接続されるショットキー電極と、前記ウエル領域上にゲート絶縁膜を介して形成されるゲート電極と、前記ドレイン領域に接続されるドレイン電極と、を有することを特徴とする半導体装置。   A drain region of the first conductivity type formed in the semiconductor substrate, a drift region of the first conductivity type formed by being connected to the drain region, and a second conductivity formed in a predetermined region of the surface layer portion of the drift region The well region of the mold, the source region of the first conductivity type formed in the predetermined region of the surface layer portion of the well region, and the source region separated from the source region in the well region, A first conductivity type Schottky connection region formed so as to be connected to the drift region, a Schottky electrode connected to the Schottky connection region and the source region, and gate insulation on the well region A semiconductor device comprising: a gate electrode formed through a film; and a drain electrode connected to the drain region. 前記ソース領域から前記ウエル領域を貫通して前記ドリフト領域にまで達する凹部を有し、前記ゲート電極が、前記凹部内にゲート絶縁膜を介して配置されていることを特徴とする請求項1記載の半導体装置。   2. The concave portion that reaches the drift region from the source region to the well region, and the gate electrode is disposed in the concave portion via a gate insulating film. Semiconductor device. 前記ショットキー電極が、前記ショットキー接続領域とはショットキー接続し、前記ソース領域とはオーミック接続していることを特徴とする請求項1または2記載の半導体装置。   3. The semiconductor device according to claim 1, wherein the Schottky electrode is Schottky connected to the Schottky connection region and ohmic connected to the source region. 前記ショットキー接続領域の真上に前記ゲート絶縁膜を介して前記ゲート電極が形成されないように、前記ショットキー接続領域が前記ウエル領域の内部に配置されていることを特徴とする請求項1ないし3のいずれかに記載の半導体装置。   2. The Schottky connection region is disposed inside the well region so that the gate electrode is not formed directly over the Schottky connection region via the gate insulating film. 4. The semiconductor device according to any one of 3. 前記ゲート絶縁膜直下の前記ウエル領域の表層部に、第1導電型の蓄積チャネルが配置されていることを特徴とする請求項1ないし4のいずれかに記載の半導体装置。   5. The semiconductor device according to claim 1, wherein a storage channel of a first conductivity type is disposed in a surface layer portion of the well region immediately below the gate insulating film. 上記半導体基体として、炭化珪素を用いたことを特徴とする請求項1ないし5のいずれかに記載の半導体装置。   6. The semiconductor device according to claim 1, wherein silicon carbide is used as the semiconductor substrate.
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