US9024330B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
US9024330B2
US9024330B2 US14/141,174 US201314141174A US9024330B2 US 9024330 B2 US9024330 B2 US 9024330B2 US 201314141174 A US201314141174 A US 201314141174A US 9024330 B2 US9024330 B2 US 9024330B2
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silicon carbide
semiconductor device
carbide layer
electrode
region
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US20140231827A1 (en
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Yukihiko Watanabe
Sachiko Aoi
Masahiro Sugimoto
Akitaka SOENO
Shinichiro Miyahara
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Denso Corp
Toyota Motor Corp
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Denso Corp
Toyota Motor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/048—Making electrodes
    • H01L21/0485—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

Definitions

  • the present application relates to a semiconductor device of which semiconductor material is silicon carbide, and a manufacturing method thereof.
  • Silicon carbide is known as a semiconductor material allowing implementation of a semiconductor device with a low loss and which can operate stably at high temperature.
  • a structure has been proposed in which a field effect transistor includes a built-in Schottky barrier diode in order to reduce the number of components of the semiconductor device.
  • An example of such a structure is disclosed in Japanese Patent Application Publication No. H8-204179.
  • a trench penetrating a p-type base region needs to be formed. This increases the number of masks needed to manufacture the semiconductor device, thus increasing manufacturing costs.
  • a semiconductor device has been desired which is formed using silicon carbide as a semiconductor material and includes a built-in Schottky barrier diode and which can be manufactured by simplified manufacturing steps.
  • a method of manufacturing a semiconductor device disclosed herein includes forming an ohmic electrode in a first area on one of main surfaces of a silicon carbide layer, siliciding the ohmic electrode, and forming a Schottky electrode in a second area on the one of the main surfaces of the silicon carbide layer with self alignment. The second area is exposed where the ohmic electrode is not formed.
  • the ohmic electrode is preformed to allow the Schottky electrode to be formed by self alignment.
  • the manufacturing method allows the manufacture, by simplified manufacturing steps, of the semiconductor device formed using silicon carbide as a semiconductor material and including a built-in Schottky barrier diode.
  • a semiconductor device disclosed herein includes a silicon carbide layer, an ohmic electrode being in an ohmic contact with a first area on one of main surfaces of the silicon carbide layer, and a Schottky electrode being in an ohmic contact with a second area on the one of the main surfaces of the silicon carbide layer and covering the ohmic electrode.
  • the silicon carbide layer includes a drift region of a first conductivity type, a base region of a second conductivity type, and a source region of the first conductivity type.
  • the drift region includes an exposure portion exposed in the second area on the one of the main surfaces of the silicon carbide layer.
  • the base region is disposed above the drift region, exposed in the first area on the one of the main surfaces of the silicon carbide layer, and includes portions that are spaced apart by the exposure region in between.
  • the source region is surrounded by the base region and exposed in the first area on the one of the main surfaces of the silicon carbide layer.
  • the exposure portion of the drift region is exposed in the second area on the one of the main surfaces of the silicon carbide layer.
  • the Schottky electrode is in Schottky contact with the exposure portion of the drift region.
  • the base region and the source region are exposed in the first area on the one of the main surfaces of the silicon carbide layer.
  • the ohmic electrode is in ohmic contact with the base region and the source region.
  • the Schottky electrode covers the ohmic electrode. That is, the Schottky electrode has a structure that can be produced by self alignment using the ohmic electrode.
  • the semiconductor device has a structure that can be manufactured by simplified manufacturing steps.
  • FIG. 1 schematically shows a cross-sectional view of a main part of a semiconductor device
  • FIG. 2 schematically shows a cross-sectional view of a characteristic part of the semiconductor device during a step of manufacturing the semiconductor device
  • FIG. 3 schematically shows a cross-sectional view of the characteristic part of the semiconductor device during a step of manufacturing the semiconductor device
  • FIG. 4 schematically shows a cross-sectional view of the characteristic part of the semiconductor device during a step of manufacturing the semiconductor device
  • FIG. 5 schematically shows a cross-sectional view of the characteristic part of the semiconductor device during a step of manufacturing the semiconductor device
  • FIG. 6 schematically shows a cross-sectional view of the characteristic part of the semiconductor device during a step of manufacturing the semiconductor device
  • FIG. 7 schematically shows a cross-sectional view of the characteristic part of the semiconductor device during a step of manufacturing the semiconductor device
  • FIG. 8 schematically shows a cross-sectional view of the characteristic part of the semiconductor device during a step of manufacturing the semiconductor device
  • FIG. 9 schematically shows a cross-sectional view of the characteristic part of the semiconductor device during a step of manufacturing the semiconductor device.
  • FIG. 10 schematically shows a cross-sectional view of a characteristic part of the semiconductor device during a step of manufacturing the semiconductor device.
  • a manufacturing method disclosed herein is used to manufacture a semiconductor device formed using silicon carbide as a semiconductor material and including a built-in Schottky barrier diode.
  • the semiconductor device may be, for example, a metal oxide semiconductor field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT).
  • the manufacturing method includes forming an ohmic electrode in a first area on one of main surfaces of a silicon carbide layer, siliciding the ohmic electrode, and forming a Schottky electrode in a second area on the one of the main surfaces of the silicon carbide layer with self alignment, wherein the second area is exposed where the ohmic electrode is not formed.
  • a material for the ohmic electrode may be, for example, nickel, titanium, or aluminum.
  • a material for the Schottky electrode may be, for example, molybdenum, nickel, gold, titanium, or aluminum.
  • An embodiment of a semiconductor device disclosed herein includes a silicon carbide layer, an ohmic electrode being in an ohmic contact with a first area on one of main surfaces of the silicon carbide layer, and a Schottky electrode being in an ohmic contact with a second area on the one of the main surfaces of the silicon carbide layer and covering the ohmic electrode.
  • the silicon carbide layer includes a drift region of a first conductivity type, a base region of a second conductivity type, and a source region of the first conductivity type.
  • the drift region includes an exposure portion exposed in the second area on the one of the main surfaces of the silicon carbide layer.
  • the base region is disposed above the drift region, exposed in the first area on the one of the main surfaces of the silicon carbide layer, and includes portions that are spaced apart by the exposure region in between.
  • the source region is surrounded by the base region and exposed in the first area on the one of the main surfaces of the silicon carbide layer.
  • the semiconductor device has a built-in Schottky barrier diode formed by the Schottky contact between the exposure portion of the drift region and the Schottky electrode.
  • the semiconductor device may further include a gate portion facing the base region separating the drift region and the source region.
  • the semiconductor device has a structure in which a field effect transistor includes a built-in Schottky barrier diode.
  • the gate portion may include a trench gate electrode filled within a trench penetrating the base region from the one of the main surfaces of the silicon carbide layer.
  • the semiconductor device has a field effect transistor with a trench type insulating gate portion.
  • the semiconductor device may further include a barrier layer of an insulating material, the barrier layer covering the trench gate electrode.
  • the Schottky electrode may cover the barrier layer.
  • a semiconductor device 1 includes a drain electrode 12 , a silicon carbide layer 20 , an ohmic electrode 14 , a Schottky electrode 16 , a source electrode 18 , an insulating gate portion 32 , and a barrier layer 34 .
  • the drain electrode 12 is formed to cover an entire back surface 20 a of the silicon carbide layer 20 and is in ohmic contact with the back surface 20 a of the silicon carbide layer 20 .
  • a material for the drain electrode 12 may be, for example, nickel, titanium, gold, or a layered electrode thereof.
  • the silicon carbide layer 20 has an n-type substrate 22 , an n-type drift region 24 , a p-type base region 26 , and an n-type source region 28 .
  • the n-type substrate 22 is a silicon carbide substrate with a [0001] plane orientation.
  • the drift region 24 is formed by crystal growth from the substrate 22 utilizing an epitaxial growth technique.
  • the drift region 24 has a protruding exposure portion 24 a in an upper portion of the drift region 24 .
  • An upper surface of the exposure portion 24 a is exposed in a second area 2 A on a surface 20 b of the silicon carbide layer 20 .
  • the base region 26 is formed by introducing p-type impurities (by way of example, aluminum) through the surface 20 b of the silicon carbide layer 20 by performing an ion implantation operation a plurality of times with an ion range changed for each operation. Opposite portions of the base region 26 are arranged with the exposure portion 24 a of the drift region 24 located between the portions. In other words, the exposure portion 24 a of the drift region 24 is formed between the opposite portions of the base region 26 .
  • the base region 26 has a contact portion 26 a in an upper portion thereof. The contact portion 26 a is exposed in a part of a first area 1 A on the surface 20 b of the silicon carbide layer 20 and contains a relatively high concentration of impurities.
  • the source region 28 is formed by introducing n-type impurities (by way of example, phosphor) through the surface 20 b of the silicon carbide layer 20 utilizing the ion implantation technique.
  • the source region 28 is surrounded by the base region 26 and spaced apart from the drift region 24 by the base region 26 .
  • the source region 28 is exposed in a part of the first area 1 A on the surface 20 b of the silicon carbide layer 20 .
  • the exposure portion 24 a of the drift region 24 , the contact portion 26 a of the base region 26 , and the source region 28 appear to have a striped layout.
  • the ohmic electrode 14 is formed on a part of the surface 20 b of the silicon carbide layer 20 by patterning and is in ohmic contact with the contact portion 26 a of the base region 26 and the source region 28 both exposed in the first area 1 A on the surface 20 b of the silicon carbide layer 20 .
  • a material for the ohmic electrode 14 maybe, for example, silicided nickel.
  • the Schottky electrode 16 is formed to cover the entire surface side 20 b of the silicon carbide layer 20 and covers a part of the surface 20 b of the silicon carbide layer 20 , the ohmic electrode 14 , and a barrier layer 34 .
  • the Schottky electrode 16 is in Schottky contact with the exposure portion 24 a of the drift region 24 exposed in the second area 2 A on the surface 20 b of the silicon carbide layer 20 .
  • Molybdenum is used as a material for the Schottky electrode 16 .
  • the source electrode 18 covers the entire surface of the Schottky electrode 16 .
  • a material for the source electrode 18 may be, for example, titanium, aluminum, or a layered electrode thereof.
  • the insulating gate portion 32 faces the base region 26 separating the drift region 24 and the source region 28 , and forms a channel in the base region 26 between the drift region 24 and the source region 28 .
  • the insulating gate portion 32 includes a gate insulating film 32 a and a trench gate electrode 32 b both provided in a trench penetrating the base region 26 from the surface of the silicon carbide layer 20 .
  • the gate insulating film 32 a is formed by being coated on an inner wall of the trench utilizing a thermal oxidation technique or a CVD technique.
  • the trench gate electrode 32 b is formed by being filled into the trench coated with the gate insulating film 32 a utilizing the CVD technique.
  • the barrier layer 34 covers and insulates the trench gate electrode 32 b from the ohmic electrode 14 , the Schottky electrode 16 , and the source electrode 18 .
  • the semiconductor device 1 is, for example, used for an inverter device that supplies an alternating current to an AC motor.
  • the semiconductor device 1 has a structure in which a metal oxide semiconductor field effect transistor (MOSFET) with the trench type insulating gate portion 32 includes a built-in Schottky barrier diode.
  • MOSFET metal oxide semiconductor field effect transistor
  • the Schottky barrier diode is built into the MOSFET by bringing the Schottky electrode 16 into Schottky contact with the exposure portion 24 a of the drift region 24 .
  • the Schottky barrier diode operates as a freewheel diode. That is, the Schottky barrier diode serves to pass a current to the AC motor while the MOSFET is off.
  • the drift region 24 , the base region 26 , and the source region 28 are formed on the substrate 22 utilizing the epitaxial growth technique and the ion implantation technique.
  • the gate insulating film 32 a and trench gate electrode 32 b of the insulating gate portion 32 are formed utilizing an etching technique or the CVD technique.
  • a known manufacturing method may be applied.
  • the barrier layer 34 is patterned on the insulating gate portion 32 utilizing the CVD technique and the etching technique.
  • a material for the barrier layer 34 may be a material with hydrofluoric acid resistance.
  • the barrier layer 34 is a silicon nitride film.
  • a mask layer 42 is patterned on the barrier layer 34 and the exposure portion 24 a of the drift region 24 utilizing the CVD technique and the etching technique.
  • a material for the mask layer 42 has the property of being dissolved in hydrofluoric acid.
  • the mask layer 42 is a silicon oxide film.
  • the ohmic electrode 14 is formed utilizing a PVD technique (sputtering method or vapor deposition method). Subsequently, an anneal process is carried out on the silicon carbide layer 20 at about 1,000° C. for about 10 minutes. This allows an interface portion of the ohmic electrode 14 which is in contact with the silicon carbide layer 20 to be silicided to have ohmic characteristics.
  • PVD technique sputtering method or vapor deposition method
  • a portion of the ohmic electrode 14 which is not silicided is selectively removed utilizing a solution having the property of dissolving metal.
  • the ohmic electrode 14 is patterned in association with the first area 1 A on the surface 20 b of the silicon carbide layer 20 .
  • the mask layer 42 is selectively removed utilizing hydrofluoric acid.
  • the Schottky electrode 16 is formed utilizing the PVD technique (sputtering method or vapor deposition technique).
  • the Schottky electrode 16 is formed all over the surface side 20 b of the silicon carbide layer 20 .
  • the Schottky electrode 16 is formed by self alignment in contact with the exposure portion 24 a of the drift region 24 present between opposite portions of the ohmic electrode 14 .
  • the source electrode 18 is formed utilizing the CVD technique on the Schottky electrode 16 to complete the semiconductor device 1 shown in FIG. 1 .
  • the ohmic electrode 14 covering the contact portion 26 a of the base region 26 and the source region 28 is preformed, and a window portion is formed between opposite portions of the ohmic electrode 14 .
  • the semiconductor device 1 adopts a structure in which the exposure portion 24 a of the drift region 24 is exposed in the surface 20 b of the silicon carbide layer 20 in association with the window portion.
  • the Schottky electrode 16 can be produced by self alignment.
  • the semiconductor device 1 can be manufactured by simplified manufacturing steps.

Abstract

A method of manufacturing a semiconductor device includes forming an ohmic electrode in a first area on one of main surfaces of a silicon carbide layer, siliciding the ohmic electrode, and forming a Schottky electrode in a second area on the one of the main surfaces of the silicon carbide layer with self alignment. The second area is exposed where the ohmic electrode is not formed.

Description

CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority to Japanese Patent Application No. 2013-027352 filed on Feb. 15, 2013, the contents of which are hereby incorporated by reference into the present application.
TECHNICAL FIELD
The present application relates to a semiconductor device of which semiconductor material is silicon carbide, and a manufacturing method thereof.
DESCRIPTION OF RELATED ART
Silicon carbide is known as a semiconductor material allowing implementation of a semiconductor device with a low loss and which can operate stably at high temperature. For semiconductor devices using silicon carbide as the semiconductor material, a structure has been proposed in which a field effect transistor includes a built-in Schottky barrier diode in order to reduce the number of components of the semiconductor device. An example of such a structure is disclosed in Japanese Patent Application Publication No. H8-204179.
BRIEF SUMMARY OF INVENTION
To manufacture the semiconductor device proposed in Japanese Patent Application Publication No. H8-204179, a trench penetrating a p-type base region needs to be formed. This increases the number of masks needed to manufacture the semiconductor device, thus increasing manufacturing costs. A semiconductor device has been desired which is formed using silicon carbide as a semiconductor material and includes a built-in Schottky barrier diode and which can be manufactured by simplified manufacturing steps.
A method of manufacturing a semiconductor device disclosed herein includes forming an ohmic electrode in a first area on one of main surfaces of a silicon carbide layer, siliciding the ohmic electrode, and forming a Schottky electrode in a second area on the one of the main surfaces of the silicon carbide layer with self alignment. The second area is exposed where the ohmic electrode is not formed.
According to this manufacturing method, the ohmic electrode is preformed to allow the Schottky electrode to be formed by self alignment. Thus, the manufacturing method allows the manufacture, by simplified manufacturing steps, of the semiconductor device formed using silicon carbide as a semiconductor material and including a built-in Schottky barrier diode.
A semiconductor device disclosed herein includes a silicon carbide layer, an ohmic electrode being in an ohmic contact with a first area on one of main surfaces of the silicon carbide layer, and a Schottky electrode being in an ohmic contact with a second area on the one of the main surfaces of the silicon carbide layer and covering the ohmic electrode. The silicon carbide layer includes a drift region of a first conductivity type, a base region of a second conductivity type, and a source region of the first conductivity type. The drift region includes an exposure portion exposed in the second area on the one of the main surfaces of the silicon carbide layer. The base region is disposed above the drift region, exposed in the first area on the one of the main surfaces of the silicon carbide layer, and includes portions that are spaced apart by the exposure region in between. The source region is surrounded by the base region and exposed in the first area on the one of the main surfaces of the silicon carbide layer.
In the semiconductor device, the exposure portion of the drift region is exposed in the second area on the one of the main surfaces of the silicon carbide layer. The Schottky electrode is in Schottky contact with the exposure portion of the drift region. Moreover, in the semiconductor device, the base region and the source region are exposed in the first area on the one of the main surfaces of the silicon carbide layer. The ohmic electrode is in ohmic contact with the base region and the source region. In this case, the Schottky electrode covers the ohmic electrode. That is, the Schottky electrode has a structure that can be produced by self alignment using the ohmic electrode. The semiconductor device has a structure that can be manufactured by simplified manufacturing steps.
BRIEF DESCRIPTION OF DRAWINGS
FIG. 1 schematically shows a cross-sectional view of a main part of a semiconductor device;
FIG. 2 schematically shows a cross-sectional view of a characteristic part of the semiconductor device during a step of manufacturing the semiconductor device;
FIG. 3 schematically shows a cross-sectional view of the characteristic part of the semiconductor device during a step of manufacturing the semiconductor device;
FIG. 4 schematically shows a cross-sectional view of the characteristic part of the semiconductor device during a step of manufacturing the semiconductor device;
FIG. 5 schematically shows a cross-sectional view of the characteristic part of the semiconductor device during a step of manufacturing the semiconductor device;
FIG. 6 schematically shows a cross-sectional view of the characteristic part of the semiconductor device during a step of manufacturing the semiconductor device;
FIG. 7 schematically shows a cross-sectional view of the characteristic part of the semiconductor device during a step of manufacturing the semiconductor device;
FIG. 8 schematically shows a cross-sectional view of the characteristic part of the semiconductor device during a step of manufacturing the semiconductor device;
FIG. 9 schematically shows a cross-sectional view of the characteristic part of the semiconductor device during a step of manufacturing the semiconductor device; and
FIG. 10 schematically shows a cross-sectional view of a characteristic part of the semiconductor device during a step of manufacturing the semiconductor device.
 DETAILED DESCRIPTION OF INVENTION
A manufacturing method disclosed herein is used to manufacture a semiconductor device formed using silicon carbide as a semiconductor material and including a built-in Schottky barrier diode. Here, the semiconductor device may be, for example, a metal oxide semiconductor field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT). The manufacturing method includes forming an ohmic electrode in a first area on one of main surfaces of a silicon carbide layer, siliciding the ohmic electrode, and forming a Schottky electrode in a second area on the one of the main surfaces of the silicon carbide layer with self alignment, wherein the second area is exposed where the ohmic electrode is not formed. In this case, a material for the ohmic electrode may be, for example, nickel, titanium, or aluminum. A material for the Schottky electrode may be, for example, molybdenum, nickel, gold, titanium, or aluminum.
An embodiment of a semiconductor device disclosed herein includes a silicon carbide layer, an ohmic electrode being in an ohmic contact with a first area on one of main surfaces of the silicon carbide layer, and a Schottky electrode being in an ohmic contact with a second area on the one of the main surfaces of the silicon carbide layer and covering the ohmic electrode. The silicon carbide layer includes a drift region of a first conductivity type, a base region of a second conductivity type, and a source region of the first conductivity type. The drift region includes an exposure portion exposed in the second area on the one of the main surfaces of the silicon carbide layer. The base region is disposed above the drift region, exposed in the first area on the one of the main surfaces of the silicon carbide layer, and includes portions that are spaced apart by the exposure region in between. The source region is surrounded by the base region and exposed in the first area on the one of the main surfaces of the silicon carbide layer. The semiconductor device has a built-in Schottky barrier diode formed by the Schottky contact between the exposure portion of the drift region and the Schottky electrode.
The semiconductor device may further include a gate portion facing the base region separating the drift region and the source region. The semiconductor device has a structure in which a field effect transistor includes a built-in Schottky barrier diode.
The gate portion may include a trench gate electrode filled within a trench penetrating the base region from the one of the main surfaces of the silicon carbide layer. The semiconductor device has a field effect transistor with a trench type insulating gate portion.
When the gate portion includes the trench gate electrode, the semiconductor device may further include a barrier layer of an insulating material, the barrier layer covering the trench gate electrode. In this case, the Schottky electrode may cover the barrier layer.
Representative, non-limiting examples of the present invention will now be described in further detail with reference to the attached drawings. This detailed description is merely intended to teach a person of skill in the art further details for practicing preferred aspects of the present teachings and is not intended to limit the scope of the invention. Furthermore, each of the additional features and teachings disclosed below may be utilized separately or in conjunction with other features and teachings to provide improved semiconductor devices, as well as manufacturing methods for the same.
Moreover, combinations of features and steps disclosed in the following detailed description may not be necessary to practice the invention in the broadest sense, and are instead taught merely to particularly describe representative examples of the invention. Furthermore, various features of the above-described and below-described representative examples, as well as the various independent and dependent claims, may be combined in ways that are not specifically and explicitly enumerated in order to provide additional useful embodiments of the present teachings.
All features disclosed in the description and/or the claims are intended to be disclosed separately and independently from each other for the purpose of original written disclosure, as well as for the purpose of restricting the claimed subject matter, independent of the compositions of the features in the embodiments and/or the claims. In addition, all value ranges or indications of groups of entities are intended to disclose every possible intermediate value or intermediate entity for the purpose of original written disclosure, as well as for the purpose of restricting the claimed subject matter.
Example
As shown in FIG. 1, a semiconductor device 1 includes a drain electrode 12, a silicon carbide layer 20, an ohmic electrode 14, a Schottky electrode 16, a source electrode 18, an insulating gate portion 32, and a barrier layer 34.
The drain electrode 12 is formed to cover an entire back surface 20 a of the silicon carbide layer 20 and is in ohmic contact with the back surface 20 a of the silicon carbide layer 20. A material for the drain electrode 12 may be, for example, nickel, titanium, gold, or a layered electrode thereof.
The silicon carbide layer 20 has an n-type substrate 22, an n-type drift region 24, a p-type base region 26, and an n-type source region 28. The n-type substrate 22 is a silicon carbide substrate with a [0001] plane orientation. The drift region 24 is formed by crystal growth from the substrate 22 utilizing an epitaxial growth technique. The drift region 24 has a protruding exposure portion 24 a in an upper portion of the drift region 24. An upper surface of the exposure portion 24 a is exposed in a second area 2A on a surface 20 b of the silicon carbide layer 20.
The base region 26 is formed by introducing p-type impurities (by way of example, aluminum) through the surface 20 b of the silicon carbide layer 20 by performing an ion implantation operation a plurality of times with an ion range changed for each operation. Opposite portions of the base region 26 are arranged with the exposure portion 24 a of the drift region 24 located between the portions. In other words, the exposure portion 24 a of the drift region 24 is formed between the opposite portions of the base region 26. The base region 26 has a contact portion 26 a in an upper portion thereof. The contact portion 26 a is exposed in a part of a first area 1A on the surface 20 b of the silicon carbide layer 20 and contains a relatively high concentration of impurities.
The source region 28 is formed by introducing n-type impurities (by way of example, phosphor) through the surface 20 b of the silicon carbide layer 20 utilizing the ion implantation technique. The source region 28 is surrounded by the base region 26 and spaced apart from the drift region 24 by the base region 26. The source region 28 is exposed in a part of the first area 1A on the surface 20 b of the silicon carbide layer 20. By way of example, when the surface 20 b of the silicon carbide layer 20 is observed, the exposure portion 24 a of the drift region 24, the contact portion 26 a of the base region 26, and the source region 28 appear to have a striped layout.
The ohmic electrode 14 is formed on a part of the surface 20 b of the silicon carbide layer 20 by patterning and is in ohmic contact with the contact portion 26 a of the base region 26 and the source region 28 both exposed in the first area 1A on the surface 20 b of the silicon carbide layer 20. A material for the ohmic electrode 14 maybe, for example, silicided nickel.
The Schottky electrode 16 is formed to cover the entire surface side 20 b of the silicon carbide layer 20 and covers a part of the surface 20 b of the silicon carbide layer 20, the ohmic electrode 14, and a barrier layer 34. The Schottky electrode 16 is in Schottky contact with the exposure portion 24 a of the drift region 24 exposed in the second area 2A on the surface 20 b of the silicon carbide layer 20. Molybdenum is used as a material for the Schottky electrode 16.
The source electrode 18 covers the entire surface of the Schottky electrode 16. A material for the source electrode 18 may be, for example, titanium, aluminum, or a layered electrode thereof.
The insulating gate portion 32 faces the base region 26 separating the drift region 24 and the source region 28, and forms a channel in the base region 26 between the drift region 24 and the source region 28. The insulating gate portion 32 includes a gate insulating film 32 a and a trench gate electrode 32 b both provided in a trench penetrating the base region 26 from the surface of the silicon carbide layer 20. The gate insulating film 32 a is formed by being coated on an inner wall of the trench utilizing a thermal oxidation technique or a CVD technique. The trench gate electrode 32 b is formed by being filled into the trench coated with the gate insulating film 32 a utilizing the CVD technique. The barrier layer 34 covers and insulates the trench gate electrode 32 b from the ohmic electrode 14, the Schottky electrode 16, and the source electrode 18.
The semiconductor device 1 is, for example, used for an inverter device that supplies an alternating current to an AC motor. The semiconductor device 1 has a structure in which a metal oxide semiconductor field effect transistor (MOSFET) with the trench type insulating gate portion 32 includes a built-in Schottky barrier diode. The Schottky barrier diode is built into the MOSFET by bringing the Schottky electrode 16 into Schottky contact with the exposure portion 24 a of the drift region 24. The Schottky barrier diode operates as a freewheel diode. That is, the Schottky barrier diode serves to pass a current to the AC motor while the MOSFET is off.
Now, a method of manufacturing the semiconductor device 1 will be described. First, as shown in FIG. 2, the drift region 24, the base region 26, and the source region 28 are formed on the substrate 22 utilizing the epitaxial growth technique and the ion implantation technique. Then, the gate insulating film 32 a and trench gate electrode 32 b of the insulating gate portion 32 are formed utilizing an etching technique or the CVD technique. For the above-described portion of the manufacturing method, a known manufacturing method may be applied.
Now, as shown in FIG. 3 and FIG. 4, the barrier layer 34 is patterned on the insulating gate portion 32 utilizing the CVD technique and the etching technique. A material for the barrier layer 34 may be a material with hydrofluoric acid resistance. By way of example, the barrier layer 34 is a silicon nitride film.
Then, as shown in FIG. 5 and FIG. 6, a mask layer 42 is patterned on the barrier layer 34 and the exposure portion 24 a of the drift region 24 utilizing the CVD technique and the etching technique. A material for the mask layer 42 has the property of being dissolved in hydrofluoric acid. By way of example, the mask layer 42 is a silicon oxide film.
Then, as shown in FIG. 7, the ohmic electrode 14 is formed utilizing a PVD technique (sputtering method or vapor deposition method). Subsequently, an anneal process is carried out on the silicon carbide layer 20 at about 1,000° C. for about 10 minutes. This allows an interface portion of the ohmic electrode 14 which is in contact with the silicon carbide layer 20 to be silicided to have ohmic characteristics.
Then, as shown in FIG. 8, a portion of the ohmic electrode 14 which is not silicided is selectively removed utilizing a solution having the property of dissolving metal. Thus, the ohmic electrode 14 is patterned in association with the first area 1A on the surface 20 b of the silicon carbide layer 20.
Then, as shown in FIG. 9, the mask layer 42 is selectively removed utilizing hydrofluoric acid.
Then, as shown in FIG. 10, the Schottky electrode 16 is formed utilizing the PVD technique (sputtering method or vapor deposition technique). The Schottky electrode 16 is formed all over the surface side 20 b of the silicon carbide layer 20. At this time, the Schottky electrode 16 is formed by self alignment in contact with the exposure portion 24 a of the drift region 24 present between opposite portions of the ohmic electrode 14. Subsequently, the source electrode 18 is formed utilizing the CVD technique on the Schottky electrode 16 to complete the semiconductor device 1 shown in FIG. 1.
Thus, in the method of manufacturing the semiconductor device 1, the ohmic electrode 14 covering the contact portion 26 a of the base region 26 and the source region 28 is preformed, and a window portion is formed between opposite portions of the ohmic electrode 14. Moreover, the semiconductor device 1 adopts a structure in which the exposure portion 24 a of the drift region 24 is exposed in the surface 20 b of the silicon carbide layer 20 in association with the window portion. Thus, the Schottky electrode 16 can be produced by self alignment. The semiconductor device 1 can be manufactured by simplified manufacturing steps.

Claims (4)

What is claimed is:
1. A semiconductor device comprising:
a silicon carbide layer;
an ohmic electrode being in an ohmic contact with a first area on one of main surfaces of the silicon carbide layer; and
a Schottky electrode being in an ohmic contact with a second area on the one of the main surfaces of the silicon carbide layer,
wherein the silicon carbide layer comprises:
a drift region of a first conductivity type, the drift region including an exposure portion exposed in the second area on the one of the main surfaces of the silicon carbide layer;
a base region of a second conductivity type, the base region disposed above the drift region, exposed in the first area on the one of the main surfaces of the silicon carbide layer, and including portions that are spaced apart by the exposure region in between; and
a source region of the first conductivity type, the source region surrounded by the base region and exposed in the first area on the one of the main surfaces of the silicon carbide layer.
2. The semiconductor device according to claim 1, further comprising:
a gate portion facing the base region separating the drift region and the source region.
3. The semiconductor device according to claim 2, wherein
the gate portion includes a trench gate electrode filled within a trench penetrating the base region from the one of the main surfaces of the silicon carbide layer.
4. The semiconductor device according to claim 3, further comprising:
a barrier layer of an insulating material, the barrier layer covering the trench gate electrode,
wherein the Schottky electrode covers the barrier layer.
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