CN112349783B - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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CN112349783B
CN112349783B CN202011223737.1A CN202011223737A CN112349783B CN 112349783 B CN112349783 B CN 112349783B CN 202011223737 A CN202011223737 A CN 202011223737A CN 112349783 B CN112349783 B CN 112349783B
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body contact
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CN112349783A (en
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程亚杰
施森华
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Wuhan Xinxin Integrated Circuit Co.,Ltd.
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

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Abstract

The present invention provides a semiconductor device and a method of manufacturing the same, the semiconductor device including: the substrate comprises a lower substrate, an insulating buried layer and an upper substrate which are sequentially formed from bottom to top, wherein the upper substrate comprises a body contact region and a device active region; a gate layer formed on the upper substrate, the gate layer extending at least from the device active region to the body contact region, a low dielectric constant layer formed between the gate layer and the body contact region, and a gate oxide layer formed between the gate layer and the device active region; the side wall is formed on the side wall of the grid layer and seals the low dielectric constant layer; wherein the low-k layer has a relative dielectric constant lower than that of the gate oxide layer. The technical scheme of the invention reduces the parasitic capacitance formed by the upper substrate of the body contact parasitic region and the low dielectric constant layer and the grid layer above the upper substrate, thereby improving the cut-off frequency.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly, to a semiconductor device and a method for fabricating the same.
Background
A silicon-on-insulator (SOI) structure comprising a lower silicon substrate, a buried insulating layer and an upper silicon substrate has a number of advantages over conventional silicon substrates, such as: the latch-up effect is eliminated, the short channel effect of the device is reduced, the radiation resistance is improved, and the like, so that the device is widely applied to the fields of radio frequency, high voltage, radiation resistance and the like.
For example, silicon-on-insulator technology is currently being applied in the radio frequency field (e.g., radio frequency switching devices), and cutoff frequency is one of the most important parameters for radio frequency silicon-on-insulator (RF-SOI) devices. Wherein the condition for achieving the maximum cut-off frequency is the input current IinIs equal to the output current IoutI.e. the gate current IGTEqual to the drain current Idrain。
For radio frequency silicon-on-insulator devices, how to suppress the floating body effect has been one of the hot spots in the research of SOI devices. One of the solutions to the floating body effect is to release holes accumulated in the body region by using a body contact method, wherein the body contact is above the buried insulating layer and at the bottom of the upper silicon layerThe body region in a floating state is in contact with the outside so that holes do not accumulate in the region. However, this causes the portion of the body contact region under the gate to become a body contact parasitic region, which forms a parasitic capacitance with the gate oxide layer and the gate thereon, and the gate oxide layer is often made of a material with a relatively high dielectric constant, such as silicon oxide, or even a material with a high dielectric constant (HiK), which causes the parasitic capacitance to increase, thereby causing the gate current I to flow into the gateGTIncrease, but for drain current IdrainThere is little boost resulting in a reduction in the cutoff frequency of the rf soi device.
Therefore, how to reduce the parasitic capacitance to increase the cutoff frequency of the radio frequency soi device is a problem that needs to be solved.
Disclosure of Invention
An object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which enable parasitic capacitance to be reduced and thus enable cutoff frequency to be improved.
To achieve the above object, the present invention provides a semiconductor device comprising:
the substrate comprises a lower substrate, an insulating buried layer and an upper substrate which are sequentially formed from bottom to top, wherein the upper substrate comprises a body contact region and a device active region;
a gate layer formed on the upper substrate, the gate layer extending at least from the device active region to the body contact region, a low dielectric constant layer formed between the gate layer and the body contact region, and a gate oxide layer formed between the gate layer and the device active region; and the number of the first and second groups,
the side wall is formed on the side wall of the grid layer and seals the low dielectric constant layer;
wherein the low-k layer has a relative dielectric constant lower than that of the gate oxide layer.
Optionally, the material of the low dielectric constant layer is SiOC, inorganic or organic glass; or, the low dielectric constant layer is an air gap.
Optionally, a top surface of the low-k layer is not lower than a top surface of the gate oxide layer.
Optionally, a shallow trench isolation structure is formed on the insulating buried layer, and the shallow trench isolation structure surrounds the body contact region and the device active region.
Optionally, the gate layer extends from the body contact region to the shallow trench isolation structures on both sides of the body contact region.
Optionally, the gate layer is shaped like a T, the body contact region is located on one side of the device active region, and the low-k layer is located at least between a portion-of the gate layer of the T and the body contact region; or the shape of the gate layer is H-shaped, the body contact region is positioned on two sides of the device active region, and the low-dielectric-constant layer is at least positioned between the "|" part of the H-shaped gate layer and the body contact region; or, the shape of the gate layer is comb-shaped, the body contact region is positioned at one side of the device active region, and the low dielectric constant layer is at least positioned between the comb back part of the comb-shaped gate layer and the body contact region.
Optionally, the semiconductor device further includes a source region, a drain region, and a conductive contact plug, the source region and the drain region are respectively located in the device active region on both sides of the gate layer, and the conductive contact plug is located on the source region, the drain region, the body contact region, and the gate layer.
The present invention also provides a method for manufacturing a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises a lower substrate, an insulating buried layer and an upper substrate which are sequentially formed from bottom to top, and the upper substrate comprises a body contact region and a device active region;
forming an insulating dielectric layer on the body contact region close to the device active region and forming a gate oxide layer on the device active region;
forming a gate layer at least on the insulating dielectric layer and the gate oxide layer; and the number of the first and second groups,
forming a side wall on the side wall of the grid layer;
the insulating medium layer is a low dielectric constant layer with a relative dielectric constant lower than that of the gate oxide layer; or after the gate layer is formed and before the side wall is formed, removing the insulating dielectric layer, and forming an air gap between the gate layer and the body contact region to serve as a low dielectric constant layer; the side wall seals the low dielectric constant layer.
Optionally, when the insulating dielectric layer is removed, the insulating dielectric layer and the gate oxide layer have a high etching selectivity ratio.
Optionally, a top surface of the low-k layer is not lower than a top surface of the gate oxide layer.
Optionally, a shallow trench isolation structure is formed on the insulating buried layer, and the shallow trench isolation structure surrounds the body contact region and the device active region.
Optionally, the gate layer extends from the body contact region to the shallow trench isolation structures on both sides of the body contact region.
Optionally, the gate layer is T-shaped, the body contact region is located on one side of the device active region, and the insulating dielectric layer is located at least between a "-" portion of the T-shaped gate layer and the body contact region; or the shape of the gate layer is H-shaped, the body contact region is positioned on two sides of the active region of the device, and the insulating dielectric layer is at least positioned between the '|' part of the H-shaped gate layer and the body contact region; or, the shape of the gate layer is comb-shaped, the body contact region is positioned on one side of the device active region, and the insulating medium layer is at least positioned between the comb back part of the comb-shaped gate layer and the body contact region.
Optionally, the method for manufacturing a semiconductor device further includes:
forming a source region and a drain region in the device active region on both sides of the gate layer; and the number of the first and second groups,
forming a conductive contact plug on the source region, the drain region, the body contact region, and the gate layer.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. according to the semiconductor device, the grid layer at least extends from the active region of the device to the body contact region, and the low dielectric constant layer is formed between the grid layer and the body contact region, so that parasitic capacitance formed by the upper substrate of the body contact parasitic region and the low dielectric constant layer and the grid layer above the upper substrate is reduced, and cut-off frequency is improved.
2. According to the manufacturing method of the semiconductor device, the low dielectric constant layer is formed between the grid layer and the body contact region, so that parasitic capacitance formed by the upper substrate of the body contact parasitic region and the low dielectric constant layer and the grid layer above the upper substrate is reduced, and the cut-off frequency is improved.
Drawings
FIG. 1 is a schematic top view of a prior art silicon-on-insulator device;
FIG. 2 is a schematic cross-sectional view of the silicon-on-insulator device shown in FIG. 1 taken along the direction A-A';
FIG. 3 is a schematic cross-sectional view of the silicon-on-insulator device shown in FIG. 1 taken along the direction B-B';
FIG. 4 is a schematic top view of another prior art silicon-on-insulator device;
FIG. 5 is a schematic cross-sectional view of the silicon-on-insulator device shown in FIG. 4, taken along the direction C-C';
fig. 6a to 6c are schematic views of a semiconductor device according to a first embodiment of the present invention;
fig. 7a to 7c are schematic views of a semiconductor device according to a second embodiment of the present invention;
fig. 8a to 8b are schematic views of a semiconductor device according to a third embodiment of the present invention;
fig. 9 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 10a to 10i are device schematic views in the method of manufacturing the semiconductor device shown in fig. 9;
wherein the reference numerals of figures 1 to 10i are as follows:
10-a lower substrate; 11-an insulating buried layer; 12-upper substrate; 121-a body contact region; 1211-body contact parasitic region; 1212-a body contact doped region; 122-device active area; 1221-source region; 1222-a drain region; 13-shallow trench isolation structures; 14-a gate oxide layer; 15-T type grid; 151-main gate; 152-an extension gate; 16-side walls; 20-a lower substrate; 21-insulating buried layer; 22-upper substrate; 221-body contact region; 2211-body contact parasitic region; 2212-body contact doped regions; 222-device active area; 2221-source region; 2222-drain region; 23-shallow trench isolation structures; 24-a gate oxide layer; 25-a gate layer; 251-a main gate; 252-an extension gate; 26-an air gap; 261-an insulating dielectric layer; 27-side walls; 28-a metal silicide layer; 29-conductive contact plug.
Detailed Description
Taking the structure of the conventional soi device shown in fig. 1 to 5 as an example, the soi device includes a lower substrate 10, a buried insulating layer 11 and an upper substrate 12 from bottom to top, an active region is enclosed in the upper substrate 12 by a shallow trench isolation structure 13, the active region includes a body contact region 121 and a device active region 122, a T-type gate 15 is formed on the upper substrate 12 of the active region, a sidewall 16 is formed on a sidewall of the T-type gate 15, a gate oxide layer 14 is formed between the T-type gate 15 and the upper substrate 12, the T-type gate 15 includes a main gate 151 (a "|" portion of the T-type) and an extension gate 152 (a "-" portion of the T-type), an active region 1221 and a drain region 1222 are formed in the upper substrate 12 on both sides of the main gate 151, respectively, a channel region (not shown in the figure) is formed between the source region 1221 and the drain region 1222, and a region 1222 of the body contact region 121 on a side opposite to the main gate 151 is formed by ion implantation (for inserting a body contact plug 1212 and a conductive plug for electrical plug contact) and a conductive plug for electrical plug Connected), the region of the body contact region 121 under the T-shaped gate 15 becomes a body contact parasitic region 1211, the body contact parasitic region 1211 shown in fig. 1 is under the main gate 151, the body contact parasitic region 1211 shown in fig. 4 is under both the main gate 151 and the extension gate 152, and the area of the body contact parasitic region 1211 under the main gate 151 is reduced compared to fig. 1 in fig. 4.
The body contact parasitic region 1211 is not an effective channel region, but belongs to a parasitic capacitance region specific to the body contact device, and the body contact parasitic region 1211 forms a parasitic capacitance with the gate oxide layer 14 and the T-shaped gate 15 above the body contact parasitic region. Input electricityStream Iin(i.e., gate current I)GT) And an output current Iout(i.e. drain current I)drain) The following formula exists:
Iin＝2πf(Vgs*CGS+Vgs*CGD+Vgs*CGOX)；
Iout＝gm*Vgs；
wherein, VgsIs the gate-source voltage, f is the turn-on frequency, CGSIs a gate-source capacitance, CGDIs a gate-drain capacitance, CGOXIs the parasitic capacitance formed by the body contact parasitic 1211 and the gate oxide layer 14 and the gate electrode 15 above it. gmIs transconductance, gmIs the drain current IoutThe variation value of (C) and the gate-source voltage VgsThe ratio between the change values reflects the ability of the gate to control the channel region of the MOS transistor.
The gate capacitor is charged once every time the MOS transistor is turned on, the charging magnitude Q is equal to C, and the gate current I is equal to VinQ ═ f. Wherein C ═ CGS+CGD+CGOX，CGS+CGDEqual to the capacitance of the channel region, the capacitive charging is then equivalent to providing the channel with inversion carriers, the parasitic capacitance CGOXThe charged charges do not provide carriers to the channel, thereby reducing the parasitic capacitance CGOXWill reduce the gate current IinWithout reducing the drain current Iout。
When the gate current IinEqual to the drain current IoutWhen the frequency f is the maximum cut-off frequency, the above formula calculates that f is gm/[2π(CGS+CGD+CGOX)]According to the formula, when the parasitic capacitance C is reducedGOXDue to drain current IoutUnchanged, transconductance gmWithout change, then the cutoff frequency will increase.
Then, as can be seen from the above, if the parasitic capacitance C is reduced or removedGOXTherefore, the present invention provides a semiconductor device and a method for manufacturing the same, which can reduce or remove the body parasitic capacitance CGOXFromAnd the cut-off frequency is increased.
To make the objects, advantages and features of the present invention more apparent, a semiconductor device and a method for manufacturing the same according to the present invention will be described in further detail with reference to the accompanying drawings. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
An embodiment of the invention provides a semiconductor device, which comprises a substrate, a gate electrode layer and a side wall, wherein the substrate comprises a lower substrate, an insulating buried layer and an upper substrate which are sequentially formed from bottom to top, and the upper substrate comprises a body contact region and a device active region; the gate layer is formed on the upper substrate, the gate layer at least extends from the device active region to the body contact region, a low dielectric constant layer is formed between the gate layer and the body contact region, and a gate oxide layer is formed between the gate layer and the device active region; the side wall is formed on the side wall of the grid layer and seals the low dielectric constant layer; wherein the low-k layer has a relative dielectric constant lower than that of the gate oxide layer.
The semiconductor device provided in this embodiment will be described in detail with reference to fig. 6a to 8b, in which fig. 6a, 7a and 8a are schematic top views of the semiconductor device, fig. 6b is a schematic cross-sectional view of the semiconductor device shown in fig. 6a taken along the direction DD ', fig. 6c is a schematic cross-sectional view of the semiconductor device shown in fig. 6a taken along the direction EE', fig. 7b is a schematic cross-sectional view of the semiconductor device shown in fig. 7a taken along the direction FF ', fig. 7c is a schematic cross-sectional view of the semiconductor device shown in fig. 7a taken along the direction GG', fig. 8b is a schematic cross-sectional view of the semiconductor device shown in fig. 8a taken along the direction II ', and fig. 7b is referred to for a schematic cross-sectional view of the semiconductor device shown in fig. 8a taken along the direction HH'.
The substrate comprises a lower substrate 20, an insulating buried layer 21 and an upper substrate 22 which are sequentially formed from bottom to top, wherein the upper substrate 22 comprises a body contact region 221 and a device active region 222. The body contact regions 221 are immediately adjacent to the device active region 222.
The material of the lower substrate 20 and the upper substrate 22 may be any suitable substrate known to those skilled in the art; the buried insulating layer 21 is made of insulating materials such as silicon oxide and silicon oxynitride. The lower substrate 20, the buried insulating layer 21 and the upper substrate 22 form an SOI substrate.
A shallow trench isolation structure 23 is formed on the insulating buried layer 21; according to the design of the layout of the body contact area 221 and the device active area 222, the shallow trench isolation structure 23 is formed in the upper substrate 22, the shallow trench isolation structure 23 surrounds the body contact area 221 and the device active area 222, the bottom surface of the shallow trench isolation structure 23 is in contact with the insulating buried layer 21, and the top surface of the shallow trench isolation structure 23 is flush with the top surface of the upper substrate 22 or slightly higher than the top surface of the upper substrate 22. The shallow trench isolation structure 23 may be made of silicon oxide or silicon oxynitride.
The gate layer 25 is formed on the upper substrate 22, the gate layer 25 at least extends from the device active region 222 to the body contact region 221, and a low-k layer is formed between the gate layer 25 and the body contact region 221. Then, an area of the body contact region 221 covered by the gate layer 25 becomes a body contact parasitic region 2211, the low dielectric constant layer is located between the body contact parasitic region 2211 and the gate layer 25, and the upper substrate 22 of the body contact parasitic region 2211 and the low dielectric constant layer and the gate layer 25 above it constitute a structure of a parasitic capacitance.
A gate oxide layer 24 is formed between the gate layer 25 and the upper substrate 22 of the device active region 222, the sidewall of the low-k dielectric layer is in contact with the sidewall of the gate oxide layer 24 facing the body contact region 221, and the top surface of the low-k dielectric layer is not lower than the top surface of the gate oxide layer 24.
Wherein the relative dielectric constant of the low dielectric constant layer is lower than the relative dielectric constant of the gate oxide layer 24. The gate oxide layer 24 may be made of silicon oxide (with a relative dielectric constant of 4.1) or a high-K dielectric with a relative dielectric constant greater than 7, and may include, but is not limited to, silicon oxynitride, titanium dioxide, tantalum pentoxide, and the like. The low-k layer may be made of silicon oxycarbide (SiOC, relative dielectric constant of 2.5), inorganic or organic spin-on glass (SOG, relative dielectric constant of 3 or less), or the like; alternatively, the low-k layer is an air gap 26, as shown in fig. 6b to 6c, 7b to 7c, and 8b, and the air gap 26 may be a vacuum (relative dielectric constant is 1.0) or air (relative dielectric constant is 1.001).
If the low dielectric constant layer is the air gap 26, the air gap 26 may expose a sidewall of the gate oxide layer 24 facing the body contact region 221, and a top wall of the air gap 26 is not lower than a top surface of the gate oxide layer 24. The height of the air gap 26 may be
Figure BDA0002762944470000081
When the height of the air gap 26 is low, the top surface of the gate oxide layer 24 may be flush with the top wall of the air gap 26; when the height of the air gap 26 is high, the top surface of the gate oxide layer 24 may be lower than the top wall of the air gap 26.
The body contact region 221 may be located on one side or two sides of the device active region 222, a direction in which the body contact region 221 is located on one side or two sides of the device active region 222 is defined as a length direction, and a direction perpendicular to the length direction is defined as a width direction, so that the gate layer 25 extends from the body contact region 221 to the shallow trench isolation structures 23 on two sides of the body contact region 221 in the width direction, that is, the gate layer 25 wraps the body contact parasitic region 2211 on two sides of the body contact parasitic region 2211 in the width direction.
Also, when the body contact region 221 is located at a side of the device active region 222, the gate layer 25 may further extend from the device active region 222 to the shallow trench isolation structure 23 at a side of the device active region 222 opposite to the body contact region 221.
The gate layer 25 includes a main gate 251 and an extension gate 252, if the body contact region 221 is located on one side of the device active region 222, the main gate 251 extends at least from the device active region 222 to the shallow trench isolation structure 23 on the side of the device active region 222 opposite to the body contact region 221, the extension gate 252 connected to one end of the main gate 251 extends from the body contact region 221 to the shallow trench isolation structures 23 on both sides of the body contact region 221 in the width direction, and the extension gate 252 wraps the body contact parasitic region 2211 on both sides of the body contact parasitic region 2211 in the width direction; if the body contact area 221 is located on both sides of the device active area 222, the main gate 251 is located at least on the device active area 222, the extension gates 252 at both ends of the main gate 251 extend from the body contact area 221 to the shallow trench isolation structures 23 on both sides of the body contact area 221 in the width direction, and the extension gates 252 wrap the body contact parasitic area 2211 on both sides of the body contact parasitic area 2211 in the width direction.
Taking the body contact region 221 located at one side of the device active region 222 and the low dielectric constant layer as the air gap 26, as shown in fig. 6a to 6c, the main gate 251 extends from the device active region 222 to the shallow trench isolation structure 23 at one side of the device active region 222 facing away from the body contact region 221, the extension gate 252 extends from the body contact region 221 to the shallow trench isolation structure 23 at two sides of the body contact region 221 in the width direction, the boundary between the main gate 251 and the extension gate 252 is aligned with the boundary between the body contact region 221 and the device active region 222, and the air gap 26 is located between the extension gate 252 and the upper substrate 22 of the body contact region 221; as shown in fig. 7a to 7c and fig. 8a to 8b, the main gate 251 extends from the body contact region 221 through the device active region 222 to the shallow trench isolation structure 23 on the side of the device active region 222 away from the body contact region 221, the extension gate 252 extends from the body contact region 221 to the shallow trench isolation structures 23 on both sides of the body contact region 221 in the width direction, the boundary between the main gate 251 and the extension gate 252 is located on the body contact region 221, and the air gap 26 extends from between the extension gate 252 and the upper substrate 22 of the body contact region 221 to between the main gate 251 and the upper substrate 22 of the body contact region 221. In the semiconductor device shown in fig. 6a to 6c, the semiconductor device shown in fig. 8a to 8b, and the semiconductor device shown in fig. 7a to 7c, the area of the body contact region 221 is sequentially reduced, and the area of the body contact parasitic region 2211 is also sequentially reduced.
The gate layer 25 may be T-shaped, and then the main gate 251 is a "|" portion of the T-shape, and the extension gate 252 is a "-" portion of the T-shape, in which case the body contact region 221 is located at one side of the device active region 222, and the low dielectric constant layer is located between the "-" portion of the gate layer 25 of the T-shape and the body contact region 221 (as in fig. 6a to 6c), or the low dielectric constant layer extends from between the "-" portion of the gate layer 25 of the T-shape and the body contact region 221 to between the "|" portion of the gate layer 25 of the T-shape and the body contact region 221 (as in fig. 7a to 8 b). Alternatively, the gate layer 25 is shaped like an H (not shown), the main gate 251 is a "-" part of the H, and the extension gate 252 is two "|" parts of the H, in which case the body contact region 221 is located at both sides of the device active region 222, and the low dielectric constant layer is located between the "|" part of the H-type gate layer 25 and the body contact region 221, or the low dielectric constant layer extends from between the "|" part of the H-type gate layer 25 and the body contact region 221 to between the "-" part of the H-type gate layer 25 and the body contact region 221. Alternatively, the gate layer 25 is shaped like a comb (not shown), the body contact region 221 is located on one side of the device active region 222, the gate layer 25 includes a comb back and a plurality of comb teeth, the comb teeth of the comb structure are the main gates 251, the comb back of the comb structure is the extension gates 252, and the low dielectric constant layer is located between the comb back of the gate layer 25 and the body contact region 221, or the low dielectric constant layer extends from between the comb back of the gate layer 25 and the body contact region 221 to between the comb teeth of the gate layer 25 and the body contact region 221.
The sidewall spacers 27 are formed on the sidewalls of the gate layer 25, the sidewall spacers 27 seal the low dielectric constant layer, and the bottom surfaces of the sidewall spacers 27 on the body contact regions 221 contact the upper substrate 22 of the body contact regions 221. If the low-k layer is the air gap 26, the spacer 27 seals the air gap 26, that is, the upper substrate 22 of the body contact region 221, the gate layer 25, the gate oxide layer 24 and the spacer 26 surround the air gap 26.
For an N-type MOS transistor, P-type heavily doping is performed on the gate layer 25 in the region a1 and the region of the body contact region 221 not covered by the gate layer 25 in the region a1, and N-type heavily doping is performed on the gate layer 25 in the region a2 and the upper substrate 22 not covered by the gate layer 25 in the region a 2; for a P-type MOS transistor, the gate layer 25 in the region a1 and the region of the body contact region 221 not covered by the gate layer 25 in the region a1 are heavily N-doped, and the gate layer 25 in the region a2 and the upper substrate 22 not covered by the gate layer 25 in the region a2 are heavily P-doped. The boundary between the region a1 and the region a2 may be located in the region where the expansion gate 252 is located, and the region a1 and the region a2 may be in contact or not in contact, for example, the boundary between the region a1 and the region a2 in fig. 6a is EE ', the boundary between the region a1 and the region a2 in fig. 7a is GG ', and the boundary between the region a1 and the region a2 in fig. 8a is II '.
Wherein heavily doping a region of the body contact region 221 not covered by the gate layer 25 in the region a1, a body contact doped region 2212 may be formed, and the body contact doped region 2212 may be located on the top of the upper substrate 22 of the body contact region 221 or may extend from the top to the bottom of the upper substrate 22 of the body contact region 221; heavily doping the upper substrate 22 not covered by the gate layer 25 in the region a2, forming a source region 2221 and a drain region 2222 on the top of the upper substrate 22 on both sides of the gate layer 25, respectively, wherein the source region 2221 and the drain region 2222 may be located in the device active region 222 on both sides of the main gate 251, respectively, a channel region is located between the source region 2221 and the drain region 2222, and the body contact doped region 2212 is used for leading out the upper substrate 22 (i.e., a body region) located below the channel region.
The semiconductor device further comprises a conductive contact plug 29, the conductive contact plug 29 is located on the source region 2221, the drain region 2222, the body contact region 221 and the extension gate 252, the conductive contact plug 29 on the body contact region 221 is located on the upper substrate 22 of the region of the body contact region 221 not covered by the gate layer 25, and the conductive contact plug 29 on the extension gate 252 is located above the shallow trench isolation structure 23.
Since the gate layer 25 wraps the body contact parasitic region 2211 at two sides of the width direction of the body contact parasitic region 2211, the body contact doped region 2212 is isolated from the source region 2221/the drain region 2222, and since the body contact doped region 2212 is used for leading out the body region, the body region and the source region 2221/the drain region 2222 can be respectively led out separately through the corresponding conductive contact plugs 29, so that effective isolation between the body region and the source/drain regions is realized.
In addition, a metal silicide layer 28 may be further formed on the upper substrate 22, the source region 2221, the drain region 2222, and the gate layer 25 in a region of the body contact region 221 not covered by the gate layer 25, and the conductive contact plug 29 is located on the metal silicide layer 28.
As can be seen from the above, compared to the structure of the conventional semiconductor device (as shown in fig. 1 to 5), in the structure of the semiconductor device of the present invention, the gate oxide layer 14 located between the body contact region 121 and the gate electrode layer 15 is replaced with the low-k layer, that is, the gate oxide layer 14 located above the body contact parasitic region 1211 is replaced with the low-k layer, since the relative dielectric constant of the material of the low-k layer is lower than the relative dielectric constant of the material of the gate oxide layer 14, for example, when the low-k layer is the air gap 26, the relative dielectric constant of the air or vacuum in the air gap 26 is only 1/4 to 1/20 of the relative dielectric constant of the material of the gate oxide layer 14 (when the material of the gate oxide layer 14 is silicon oxide, the relative dielectric constant of the air gap 26 is 1/4 of the relative dielectric constant of the material of the gate oxide layer 14; when the material of the gate oxide layer 14 is a high-k material, the relative permittivity of the air gap 26 may reach 1/20, which is only the relative permittivity of the material of the gate oxide layer 14), so that the parasitic capacitance formed by the upper substrate 22 of the body contact parasitic region 2211 and the low-permittivity layer and the gate layer 25 above the upper substrate is reduced, and the cut-off frequency of the semiconductor device is improved.
In summary, the semiconductor device provided by the present invention includes: the substrate comprises a lower substrate, an insulating buried layer and an upper substrate which are sequentially formed from bottom to top, wherein the upper substrate comprises a body contact region and a device active region; a gate layer formed on the upper substrate, the gate layer extending at least from the device active region to the body contact region, a low dielectric constant layer formed between the gate layer and the body contact region; and the side wall is formed on the side walls of the grid layer and the low dielectric constant layer. The semiconductor device of the invention enables the parasitic capacitance to be reduced, thereby enabling the cut-off frequency to be improved.
An embodiment of the present invention provides a method for manufacturing a semiconductor device, and referring to fig. 9, fig. 9 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, the method for manufacturing a semiconductor device including:
step S1, providing a substrate, wherein the substrate comprises a lower substrate, an insulating buried layer and an upper substrate which are sequentially formed from bottom to top, and the upper substrate comprises a body contact region and a device active region;
step S2, forming an insulating medium layer on the body contact region close to the device active region and forming a gate oxide layer on the device active region;
step S3, forming a gate electrode layer on the insulating dielectric layer and the gate oxide layer;
step S4, forming a side wall on the side wall of the gate layer;
the insulating medium layer is a low dielectric constant layer with a relative dielectric constant lower than that of the gate oxide layer; or after the gate layer is formed and before the side wall is formed, removing the insulating dielectric layer, and forming an air gap between the gate layer and the body contact region to serve as a low dielectric constant layer; the side wall seals the low dielectric constant layer.
The method for manufacturing the semiconductor device according to the present embodiment will be described in more detail with reference to fig. 6a to 8b and fig. 10a to 10i, and fig. 10a to 10i are also the method for manufacturing the semiconductor device shown in fig. 6 b.
According to step S1, a substrate is provided, the substrate includes a lower substrate 20, a buried insulating layer 21 and an upper substrate 22 formed in sequence from bottom to top, and the upper substrate 22 includes a body contact region 221 and a device active region 222. The body contact regions 221 are immediately adjacent to the device active region 222.
The material of the lower substrate 20 and the upper substrate 22 may be any suitable substrate known to those skilled in the art; the buried insulating layer 21 is made of an insulating material such as silicon oxide or silicon oxynitride. The lower substrate 20, the buried insulating layer 21 and the upper substrate 22 form an SOI substrate.
According to step S2, referring to fig. 10a to 10c, an insulating dielectric layer 261 is formed on the body contact region 221 adjacent to the device active region 222 and a gate oxide layer 24 is formed on the device active region 222. The side wall of the insulating dielectric layer 261 is in contact with the side wall of the gate oxide layer 24 facing to the body contact region 221, and the top surface of the insulating dielectric layer 261 is not lower than the top surface of the gate oxide layer 24.
The insulating dielectric layer 261 may be formed on the body contact region 221 adjacent to the device active region 222, and then the gate oxide layer 24 may be formed on the device active region 222; alternatively, the gate oxide layer 24 is formed on the device active region 222, and then the insulating dielectric layer 261 is formed on the body contact region 221 close to the device active region 222.
If the insulating dielectric layer 261 is formed first and then the gate oxide layer 24 is formed, the specific steps may include: firstly, covering the upper substrate 22 with the material of the insulating medium layer 261, as shown in fig. 10 a; then, according to the design of the layout of the body contact region 221 and the device active region 222, etching the material of the insulating medium layer 261 and the upper substrate 22 to form a shallow trench isolation structure 23 in the upper substrate 22, as shown in fig. 10b, the shallow trench isolation structure 23 surrounds the body contact region 221 and the device active region 222, the bottom surface of the shallow trench isolation structure 23 is in contact with the buried insulating layer 21, the top surface of the shallow trench isolation structure 23 is flush with the top surface of the upper substrate 22 or slightly higher than the top surface of the upper substrate 22, and at this time, the insulating medium layer 261 only covers the body contact region 221 and the device active region 222; then, further reducing the thickness of the insulating dielectric layer 261 to a desired thickness, and etching to remove a portion of the insulating dielectric layer 261, as shown in fig. 10c, so that the remaining insulating dielectric layer 261 is only located on the body contact region 221 close to the device active region 222; next, a thermal oxidation process is performed on the region of the upper substrate 22 not covered by the remaining insulating dielectric layer 261 to form a film layer of the gate oxide layer 24, and the film layer of the gate oxide layer 24 is etched to form the gate oxide layer 24 on the device active region 222, as shown in fig. 10 d. In addition, after the insulating dielectric layer 261 is thinned to a desired thickness, well region ion implantation and threshold voltage adjustment ion implantation may be performed on the body contact regions 221 and the upper substrate 22 of the device active region 222.
If the gate oxide layer 24 is formed on the device active region 222 first and then the insulating dielectric layer 261 is formed on the body contact region 221 close to the device active region 222, the shallow trench isolation structure 23 may be formed first before the gate oxide layer 24 is formed on the device active region 222. Then, the gate oxide layer 24 is formed by performing thermal oxidation and etching processes on the upper substrate 22 surrounded by the shallow trench isolation structure 23, and then the insulating dielectric layer 261 is formed by deposition and etching processes. The shallow trench isolation structure 23 may be made of silicon oxide or silicon oxynitride. The material of the insulating dielectric layer 261 may have a high etching selectivity ratio with the material of the shallow trench isolation structure 23, so that the shallow trench isolation structure 23 is not etched or only slightly etched when the insulating dielectric layer 261 is removed by etching to form an air gap 26 at the insulating dielectric layer 261. According to step S3, a gate layer 25 is formed at least on the insulating dielectric layer 261 and the gate oxide layer 24.
The method comprises the following steps: firstly, depositing a gate layer 25 material to cover the upper substrate 22 and the shallow trench isolation structure 23, and burying the gate oxide layer 24 and the insulating dielectric layer 261 with the gate layer 25 material; then, the material of the gate layer 25 is etched to form the gate layer 25, as shown in fig. 10 e. In addition, the surface of the gate layer 25 may be oxidized later to protect the gate layer 25; also, a lightly doped drain implant (LDD) may be performed on a region of the device active region 222 not covered by the gate layer 25. The body contact region 221 may be located on one side or two sides of the device active region 222, a direction in which the body contact region 221 is located on one side or two sides of the device active region 222 is defined as a length direction, and a direction perpendicular to the length direction is defined as a width direction, so that the gate layer 25 extends from the insulating dielectric layer 261 on the body contact region 221 to the shallow trench isolation structures 23 on two sides of the body contact region 221 in the width direction, and the gate layer 25 wraps the body contact parasitic region 2211 on two sides of the body contact parasitic region 2211 in the width direction.
Also, when the body contact region 221 is located at a side of the device active region 222, the gate layer 25 may further extend from the device active region 222 to the shallow trench isolation structure 23 at a side of the device active region 222 opposite to the body contact region 221.
If the body contact region 221 is located on one side of the device active region 222, the main gate 251 extends at least from the device active region 222 to the shallow trench isolation structure 23 on the side of the device active region 222 opposite to the body contact region 221, the extension gate 252 connected to one end of the main gate 251 extends from the insulating dielectric layer 261 on the body contact region 221 to the shallow trench isolation structures 23 on both sides of the body contact region 221 in the width direction, and the extension gate 252 surrounds the body contact parasitic region 2211 on both sides of the body contact parasitic region 2211 in the width direction; if the body contact area 221 is located on both sides of the device active area 222, the main gate 251 is located at least on the device active area 222, the extension gates 252 at both ends of the main gate 251 extend from the insulating dielectric layer 261 on the body contact area 221 to the shallow trench isolation structures 23 on both sides of the body contact area 221 in the width direction, and the extension gates 252 wrap the body contact parasitic area 2211 on both sides of the body contact parasitic area 2211 in the width direction.
Taking the body contact region 221 located at one side of the device active region 222 as an example, as shown in fig. 6a to 6c, the main gate 251 extends from the device active region 222 to the shallow trench isolation structure 23 at one side of the device active region 222 facing away from the body contact region 221, the extension gate 252 extends from the insulating dielectric layer 261 on the body contact region 221 to the shallow trench isolation structure 23 at two sides of the body contact region 221 in the width direction, and the boundary between the main gate 251 and the extension gate 252 is aligned with the boundary between the body contact region 221 and the device active region 222; as shown in fig. 7a to 7c and fig. 8a to 8b, the main gate 251 extends from the insulating dielectric layer 261 on the body contact region 221 through the device active region 222 to the shallow trench isolation structure 23 on the side of the device active region 222 facing away from the body contact region 221, the extension gate 252 extends from the insulating dielectric layer 261 on the body contact region 221 to the shallow trench isolation structures 23 on both sides of the body contact region 221 in the width direction, and the boundary between the main gate 251 and the extension gate 252 is located on the body contact region 221.
The gate layer 25 may be T-shaped, and then the main gate 251 is a "|" portion of the T-shape, the extension gate 252 is a "-" portion of the T-shape, in this case, the body contact region 221 is located at one side of the device active region 222, and the insulating dielectric layer 261 is located between the "-" portion of the T-shaped gate layer 25 and the body contact region 221 (as shown in fig. 6a to 6c), or the insulating dielectric layer 261 extends from between the "-" portion of the T-shaped gate layer 25 and the body contact region 221 to between the "|" portion of the T-shaped gate layer 25 and the body contact region 221 (as shown in fig. 7a to 8 b). Alternatively, the gate layer 25 is shaped like an H (not shown), the main gate 251 is a "-" part of the H, and the extension gate 252 is two "|" parts of the H, in which case, the body contact region 221 is located at two sides of the device active region 222, and the insulating dielectric layer 261 is located between the "|" part of the H-shaped gate layer 25 and the body contact region 221, or the insulating dielectric layer 261 extends from between the "|" part of the H-shaped gate layer 25 and the body contact region 221 to between the "-" part of the H-shaped gate layer 25 and the body contact region 221. Alternatively, the gate layer 25 is comb-shaped (not shown), the body contact region 221 is located on one side of the device active region 222, the gate layer 25 includes a comb back and a plurality of comb teeth, the comb teeth of the comb-shaped structure are the main gates 251, the comb back of the comb-shaped structure is the expansion gates 252, and the insulating dielectric layer 261 is located between the comb back of the comb-shaped gate layer 25 and the body contact region 221, or the insulating dielectric layer 261 extends from between the comb back of the comb-shaped gate layer 25 and the body contact region 221 to between the comb teeth of the comb-shaped gate layer 25 and the body contact region 221.
The gate oxide layer 24 may be made of silicon oxide (having a relative dielectric constant of 4.1) or a high-K dielectric having a relative dielectric constant greater than 7, and may include, but is not limited to, silicon oxynitride, titanium dioxide, tantalum pentoxide, and the like.
The insulating dielectric layer 261 may be a low-k layer having a relative dielectric constant lower than that of the gate oxide layer 24, and in this case, the material of the insulating dielectric layer 261 and the low-k layer may be silicon oxycarbide (SiOC, having a relative dielectric constant of 2.5), inorganic or organic spin-on glass (SOG, having a relative dielectric constant of 3 or less), or the like. The side wall of the low dielectric constant layer is in contact with the side wall of the gate oxide layer 24 facing to the side of the body contact region 221, and the top surface of the low dielectric constant layer is not lower than the top surface of the gate oxide layer 24.
Or, the relative permittivity of the material of the insulating dielectric layer 261 may be not lower than the relative permittivity of the material of the gate oxide layer 24, for example, the material of the insulating dielectric layer 261 is silicon nitride or silicon carbide, and the like, then, after the gate layer 25 is formed and before the sidewall 27 is formed subsequently, the insulating dielectric layer 261 is removed to form an air gap 26 between the gate layer 25 and the body contact region 221, where the air gap 26 serves as a low permittivity layer, as shown in fig. 10f, the air gap 26 may expose a sidewall of the gate oxide layer 24 facing the body contact region 221, and at this time, the insulating dielectric layer 261 is a sacrificial layer. When the insulating medium layer 261 is removed, the material of the insulating medium layer 261 and the material of the gate oxide layer 24 have a high etching selection ratio, so that when the insulating medium layer 261 is removed by etching, the gate oxide layer 24 is not etched or only slightly etched, and the structure of the gate oxide layer 24 is prevented from being damaged. For example, when the insulating dielectric layer 261 is made of silicon nitride, and the gate oxide layer 24 may be made of silicon oxide, the gate oxide layer 24 is hardly etched when the insulating dielectric layer 261 is removed by etching with a phosphoric acid solution.
The top wall of the air gap 26 is not lower than the top surface of the gate oxide layer 24. The height of the air gap 26 may be
Figure BDA0002762944470000171
When the height of the air gap 26 is low, the top surface of the gate oxide layer 24 may be flush with the top wall of the air gap 26; when the height of the air gap 26 is high, the top surface of the gate oxide layer 24 may be lower than the top wall of the air gap 26. As shown in fig. 6a to 6c and 10f, the air gap 26 is located between the extension gate 252 and the upper substrate 22 of the body contact region 221; as shown in fig. 7a to 7c and 8a to 8b, the air gap 26 extends from between the expansion gate 252 and the upper substrate 22 of the body contact region 221 to between the main gate 251 and the upper substrate 22 of the body contact region 221.
In the semiconductor device shown in fig. 6a to 6c, the semiconductor device shown in fig. 8a to 8b, and the semiconductor device shown in fig. 7a to 7c, the area of the body contact region 221 is sequentially reduced, and the area of the body contact parasitic region 2211 is also sequentially reduced.
Since the region of the body contact region 221 covered by the gate layer 25 becomes the body contact parasitic region 2211, and the insulating dielectric layer 261 between the body contact parasitic region 2211 and the gate layer 25 is replaced by the low dielectric constant layer, then the upper substrate 22 of the body contact parasitic region 2211 and the low dielectric constant layer and the gate layer 25 above it constitute a structure of a parasitic capacitor. The low-k layer may be a material having a relative dielectric constant lower than that of the gate oxide layer 24, such as silicon oxycarbide (SiOC, having a relative dielectric constant of 2.5), inorganic or organic spin-on glass (SOG, having a relative dielectric constant of 3 or less), or the air gap 26.
According to step S4, a sidewall spacer 27 is formed on the sidewall of the gate layer 25, and the sidewall spacer 27 seals the low dielectric constant layer.
The bottom surfaces of the side walls 27 on the body contact regions 221 contact the upper substrate 22 of the body contact regions 221. If the low-k layer is the air gap 26, the sidewall 27 seals the air gap 26, as shown in fig. 10g, that is, the upper substrate 22 of the body contact region 221, the gate layer 25, the gate oxide layer 24 and the sidewall 26 surround the air gap 26.
When the sidewall 27 is formed, if the low dielectric constant layer is the air gap 26, the sidewall 27 can only grow in a direction perpendicular to the upper substrate 22 and hardly grow in a direction parallel to the upper substrate 22 by controlling a deposition method and process parameters, so as to prevent the sidewall 27 from filling into the air gap 26.
In addition, the method of manufacturing a semiconductor device further includes:
first, a source region 2221 and a drain region 2222 are formed in the device active region 222 on both sides of the main gate 251, and the gate layer 25 in the region a1, the region of the body contact region 221 in the region a1 not covered by the gate layer 25, and the gate layer 25 in the region a2 are heavily doped while the source region 2221 and the drain region 2222 are formed by ion implantation into the device active region 222.
Wherein, for an N-type MOS transistor, a region of the gate layer 25 in the region a1 and the body contact region 221 in the region a1, which is not covered by the gate layer 25, is heavily P-doped, and an upper substrate 22 of the gate layer 25 in the region a2 and the region a2, which is not covered by the gate layer 25, is heavily N-doped; for a P-type MOS transistor, the gate layer 25 in the region a1 and the region of the body contact region 221 not covered by the gate layer 25 in the region a1 are heavily N-doped, and the gate layer 25 in the region a2 and the upper substrate 22 not covered by the gate layer 25 in the region a2 are heavily P-doped. The boundary between the region a1 and the region a2 may be located in the region where the expansion gate 252 is located, and the region a1 and the region a2 may be in contact or not in contact, for example, the boundary between the region a1 and the region a2 in fig. 6a is EE ', the boundary between the region a1 and the region a2 in fig. 7a is GG ', and the boundary between the region a1 and the region a2 in fig. 8a is II '.
Heavily doping a region of the body contact region 221 not covered by the gate layer 25 in the region a1, a body contact doped region 2212 may be formed, the body contact doped region 2212 may be located on the top of the upper substrate 22 of the body contact region 221 (as shown in fig. 10 h) or may extend from the top to the bottom of the upper substrate 22 of the body contact region 221; heavily doping the upper substrate 22 not covered by the gate layer 25 in the region a2, forming a source region 2221 and a drain region 2222 on the top of the upper substrate 22 on both sides of the gate layer 25, respectively, wherein the source region 2221 and the drain region 2222 may be located in the device active region 222 on both sides of the main gate 251, respectively, a channel region is located between the source region 2221 and the drain region 2222, and the body contact doped region 2212 is used for leading out the upper substrate 22 (i.e., a body region) located below the channel region. Then, as shown in fig. 10i, a conductive contact plug 29 is formed on the source region 2221, the drain region 2222, the body contact region 221 and the extension gate 252, the conductive contact plug 29 on the body contact region 221 is located on the upper substrate 22 of the region of the body contact region 221 not covered by the gate layer 25, and the conductive contact plug 29 on the extension gate 252 is located above the shallow trench isolation structure 23.
Since the gate layer 25 wraps the body contact parasitic region 2211 at two sides of the width direction of the body contact parasitic region 2211, the body contact doped region 2212 is isolated from the source region 2221/the drain region 2222, and since the body contact doped region 2212 is used for leading out the body region, the body region and the source region 2221/the drain region 2222 can be respectively led out separately through the corresponding conductive contact plugs 29, so that effective isolation between the body region and the source/drain regions is realized.
In addition, a metal silicide layer 28 may be further formed on the upper substrate 22, the source region 2221, the drain region 2222, and the gate layer 25 in a region of the body contact region 221 not covered by the gate layer 25, and the conductive contact plug 29 is located on the metal silicide layer 28.
As can be seen from the above, compared to the structure of the conventional semiconductor device (as shown in fig. 1 to 5), in the manufacturing method of the semiconductor device of the present invention, the gate oxide layer 14 located between the body contact region 121 and the gate layer 15 is replaced with the low-k layer, that is, the gate oxide layer 14 located above the body contact parasitic region 1211 is replaced with the low-k layer, since the relative dielectric constant of the material of the low-k layer is lower than the relative dielectric constant of the material of the gate oxide layer 14, for example, when the low-k layer is the air gap 26, the relative dielectric constant of the air or vacuum in the air gap 26 is only 1/4 to 1/20 of the relative dielectric constant of the material of the gate oxide layer 14 (when the material of the gate oxide layer 14 is silicon oxide, the relative dielectric constant of the air gap 26 is 1/4 of the relative dielectric constant of the material of the gate oxide layer 14; when the material of the gate oxide layer 14 is a high-k material, the relative permittivity of the air gap 26 may reach 1/20, which is only the relative permittivity of the material of the gate oxide layer 14), so that the parasitic capacitance formed by the upper substrate 22 of the body contact parasitic region 2211 and the low-permittivity layer and the gate layer 25 above the upper substrate is reduced, and the cut-off frequency of the semiconductor device is improved.
In addition, the steps in the method for manufacturing a semiconductor device are not limited to the above formation order, and the order of the steps can be adaptively adjusted.
In summary, the method for manufacturing a semiconductor device provided by the present invention includes: providing a substrate, wherein the substrate comprises a lower substrate, an insulating buried layer and an upper substrate which are sequentially formed from bottom to top, and the upper substrate comprises a body contact region and a device active region; forming an insulating dielectric layer on the body contact region close to the device active region and forming a gate oxide layer on the device active region; forming a gate layer at least on the insulating dielectric layer and the gate oxide layer; forming a side wall on the side wall of the grid layer; the insulating medium layer is a low dielectric constant layer with a relative dielectric constant lower than that of the gate oxide layer; or after the gate layer is formed and before the side wall is formed, removing the insulating dielectric layer, and forming an air gap between the gate layer and the body contact region to serve as a low dielectric constant layer; the side wall seals the low dielectric constant layer. The manufacturing method of the semiconductor device of the invention enables the parasitic capacitance to be reduced, thereby enabling the cut-off frequency to be improved.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (13)

1. A semiconductor device, comprising:
the substrate comprises a lower substrate, an insulating buried layer and an upper substrate which are sequentially formed from bottom to top, wherein the upper substrate comprises a body contact region and a device active region;
a gate layer formed on the upper substrate, the gate layer extending at least from the device active region to the body contact region, a low dielectric constant layer formed between the gate layer and the body contact region, and a gate oxide layer formed between the gate layer and the device active region; and the number of the first and second groups,
the side wall is formed on the side wall of the grid layer and seals the low dielectric constant layer;
the relative dielectric constant of the low-dielectric-constant layer is lower than that of the gate oxide layer, the low-dielectric-constant layer is an air gap, so that parasitic capacitance formed by the upper substrate of the body contact region, the low-dielectric-constant layer above the body contact region and the gate layer is reduced, and the cut-off frequency of the radio-frequency silicon-on-insulator device is further improved.
2. The semiconductor device according to claim 1, wherein a top surface of the low dielectric constant layer is not lower than a top surface of the gate oxide layer.
3. The semiconductor device of claim 1, wherein a shallow trench isolation structure is formed on the buried insulating layer, the shallow trench isolation structure surrounding the body contact region and the device active region.
4. The semiconductor device of claim 3, wherein the gate layer extends from over the body contact region to over the shallow trench isolation structures on both sides of the body contact region.
5. The semiconductor device of claim 1, wherein the gate layer is shaped as a T, the body contact region is located on a side of the device active region, and the low-k layer is located at least between a "-" portion of the gate layer of the T and the body contact region; or the shape of the gate layer is H-shaped, the body contact region is positioned on two sides of the device active region, and the low-dielectric-constant layer is at least positioned between the "|" part of the H-shaped gate layer and the body contact region; or, the shape of the gate layer is comb-shaped, the body contact region is positioned at one side of the device active region, and the low dielectric constant layer is at least positioned between the comb back part of the comb-shaped gate layer and the body contact region.
6. The semiconductor device of claim 1, further comprising a source region, a drain region, and a conductive contact plug, the source region and the drain region respectively located in the device active region on both sides of the gate layer, the conductive contact plug located on the source region, the drain region, the body contact region, and the gate layer.
7. A method of manufacturing a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises a lower substrate, an insulating buried layer and an upper substrate which are sequentially formed from bottom to top, and the upper substrate comprises a body contact region and a device active region;
forming an insulating dielectric layer on the body contact region close to the device active region and forming a gate oxide layer on the device active region;
forming a gate layer at least on the insulating dielectric layer and the gate oxide layer; and the number of the first and second groups,
forming a side wall on the side wall of the grid layer;
after the gate layer is formed and before the side wall is formed, removing the insulating dielectric layer, and forming an air gap between the gate layer and the body contact region to serve as a low dielectric constant layer, so as to reduce parasitic capacitance formed by an upper substrate of the body contact region, the low dielectric constant layer above the upper substrate of the body contact region and the gate layer, and further improve cut-off frequency of the radio frequency silicon-on-insulator device; the side wall seals the low dielectric constant layer.
8. The method for manufacturing a semiconductor device according to claim 7, wherein the insulating dielectric layer and the gate oxide layer have a high etching selectivity when the insulating dielectric layer is removed.
9. The method for manufacturing a semiconductor device according to claim 7, wherein a top surface of the low dielectric constant layer is not lower than a top surface of the gate oxide layer.
10. The method for manufacturing a semiconductor device according to claim 7, wherein a shallow trench isolation structure is formed on the buried insulating layer, the shallow trench isolation structure surrounding the body contact region and the device active region.
11. The method of manufacturing the semiconductor device of claim 10, wherein the gate layer extends from over the body contact region to over the shallow trench isolation structures on both sides of the body contact region.
12. A method of manufacturing a semiconductor device according to claim 7, wherein said gate layer is shaped like a T, said body contact region is located on one side of said device active region, and said insulating dielectric layer is located at least between a "-" portion of said gate layer of the T and said body contact region; or the shape of the gate layer is H-shaped, the body contact region is positioned on two sides of the active region of the device, and the insulating dielectric layer is at least positioned between the '|' part of the H-shaped gate layer and the body contact region; or, the shape of the gate layer is comb-shaped, the body contact region is positioned on one side of the device active region, and the insulating medium layer is at least positioned between the comb back part of the comb-shaped gate layer and the body contact region.
13. The method for manufacturing a semiconductor device according to claim 7, further comprising:
forming a source region and a drain region in the device active region on both sides of the gate layer; and the number of the first and second groups,
forming a conductive contact plug on the source region, the drain region, the body contact region, and the gate layer.
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