JP4228416B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a MOS field effect transistor and a manufacturing method thereof.
[0002]
[Prior art]
Transistors used in semiconductor devices are roughly classified into bipolar transistors and metal-oxide-semiconductor field effect transistors (MOSFETs). MOSFETs are further classified into n-channel and p-channel types depending on the channel conductivity type of the transistor. MOSFETs are widely used as typical semiconductor devices today, and large-scale integration has been promoted.
[0003]
Today, there is a demand for higher performance, higher performance, and larger capacity for the performance required for semiconductor devices, and along with this, the above-mentioned MOSFETs are also being miniaturized and reduced in size. In the process, fine processing technology has been developed and studied. In particular, in the formation of MOSFETs of the 0.35 μm generation and beyond, development of microfabrication techniques for gate electrodes has been active. When the gate length is 1 μm or less, a polycide structure formed by stacking polysilicon and silicide such as tungsten silicide is used, and when the gate length is 0.5 μm or less, the short channel effect is suppressed and transistor characteristics are deteriorated due to hot carriers. In order to suppress this, an LDD (Lightly Doped Drain) structure in which an impurity-containing region having a lower concentration than the source / drain diffusion layer is formed on the channel formation region side of the source / drain diffusion layer has been used.
[0004]
FIG. 11A is a cross-sectional view of a semiconductor device having a MOSFET using the LDD structure. For example, a gate insulating film 21a made of, for example, silicon oxide is formed on the active region (channel forming region) of the p-type semiconductor substrate 10 separated by an element isolation insulating film 20 formed by STI (Shallow Trench Isolation). Yes. A gate electrode 30a made of, for example, polysilicon is formed on the upper layer. Side wall insulating films 22 made of, for example, silicon oxide are formed on both sides of the gate electrode 30a. A source / drain diffusion layer 13 containing, for example, an n-type impurity is formed in the semiconductor substrate 10 on both sides of the gate electrode. Further, for example, an n-type impurity is added to the source / drain diffusion layer on the channel formation region side. An LDD (Lightly Doped Drain) diffusion layer 12 containing a lower concentration than 13 is formed. Further, in the channel formation region (the lower region of the gate electrode 30a) in the semiconductor substrate 10, a punch-through prevention layer for containing a high concentration of p-type impurities to prevent punch-through which is one of the short channel effects. 11 is formed. In the punch-through prevention layer 11, as shown in FIG. 11 (b) which is a p-type impurity concentration profile at a position along XX ′ in FIG. The impurity concentration is increased, and for example, a profile having a maximum value in the depth between the junction surface of the LDD diffusion layer 12 and the junction surface of the source / drain diffusion layer 13 is taken.
[0005]
The above MOSFET induces an n-type inversion layer in the channel formation region of the p-type semiconductor substrate 10 by applying a voltage to the gate electrode 30a, the induced inversion layer becomes a channel, and current flows from the source diffusion layer to the drain. It is possible to flow to the diffusion layer.
[0006]
[Problems to be solved by the invention]
However, when the gate length and the gate insulating film are reduced in accordance with the scaling law in order to increase the integration density and miniaturization of the semiconductor device in the above-mentioned LDD structure MOSFET, the channel resistance of the transistor is reduced, but on the other hand, it is short. There arises a problem that the channel effect becomes prominent. In order to suppress punch-through current, which is one of the short channel effects, in particular, the source / drain junction depth should be reduced to reduce the amount of source / drain depletion layer protruding to the channel side, or It is known that it is effective to form a punch-through prevention layer by increasing the channel impurity concentration.
[0007]
However, when the junction depth is reduced for the above reasons, the surface resistance of the junction region increases, and the channel resistance is reduced by reducing the gate length in accordance with the scaling law. The parasitic resistance due to the surface resistance increases, and the current driving capability of the transistor is reduced.
[0008]
Further, unlike the semiconductor device of FIG. 11A, the channel impurity concentration in the channel formation region is not so high, and the substrate impurity concentration maximum is at a predetermined depth from the substrate surface below the channel formation region. When a punch-through prevention layer having a concentration profile is formed, it is effective in suppressing punch-through current. However, the channel impurity is usually formed by ion implantation before the gate electrode forming step, and the above-mentioned surface is formed on the entire surface of the substrate. Therefore, the channel impurity is also introduced at a high concentration in the vicinity of the junction surface of the source / drain diffusion layer. In this case, the junction capacitance of the source / drain diffusion layer increases, and the current driving capability of the transistor decreases.
[0009]
As a method for solving the above problem, Japanese Patent Publication No. 3-43787 discloses a method of masking a source / drain region using a photolithography process and introducing a high-concentration channel impurity only in a channel formation region. It is disclosed. According to this method, a high concentration of channel impurities is introduced only into the channel formation region to suppress the punch-through current, while the channel impurity is not introduced into the region near the junction surface of the source / drain diffusion layer, thereby increasing the junction capacitance. Can be prevented. However, since the photolithography process is used, the manufacturing cost increases, and the misalignment becomes unacceptable as the semiconductor device is miniaturized.
[0010]
Japanese Patent Laid-Open No. 62-141778 discloses an interlayer insulating film that covers a transistor formed by forming a gate electrode and a source / drain diffusion layer after implanting a high concentration of channel impurities over the entire surface of the substrate. A contact hole reaching the source / drain diffusion layer is formed, an impurity having a conductivity type opposite to that of the channel impurity is implanted into the opening, and the source / drain region and the semiconductor substrate are formed below the source / drain region. A method of forming a semiconductor layer having an intermediate impurity concentration is disclosed. However, the formation of a semiconductor layer having an intermediate impurity concentration is limited to the opening of the contact hole, and the contact hole must be smaller than the source / drain region in order to compensate for misalignment with the source / drain region. Therefore, the junction capacitance of the source / drain regions other than the contact hole opening cannot be reduced.
[0011]
Japanese Patent Laid-Open No. 8-213600 discloses that a gate electrode is formed after implanting a high concentration of channel impurities over the entire surface of the substrate, and further, channel impurities perpendicular to the substrate surface are formed using the gate electrode as a mask. A method of forming source / drain diffusion layers so as to have a junction surface deeper than the channel impurity region by implanting impurity ions of the opposite conductivity type and causing channeling is disclosed. According to this method, since the source / drain diffusion layers are formed deeply by utilizing channeling that does not spread from the implantation direction of the impurity ions to the lateral direction, effective channel impurities in the channel formation region below the gate electrode are formed. The concentration can be kept high to suppress the punch-through current, while the junction capacitance of the source / drain diffusion layer can be reduced. Since the same mask as that for forming the source / drain diffusion layer can be used, impurities can be implanted into the entire surface under the source / drain diffusion layer, and the effect of reducing the junction capacitance of the source / drain diffusion layer is disclosed in It is larger than the method described in JP-A No. 62-141778.
[0012]
However, since the method described in Japanese Patent Laid-Open No. 8-213600 uses channeling during ion implantation for forming the source / drain diffusion layer, the process margin with respect to the ion implantation angle is small, and impurity ions It is difficult to control the injection amount. For example, when a semiconductor substrate having a plane orientation (100) plane is used, the implantation angle with respect to the normal of the substrate surface that causes channeling is limited to about −2 ° to 2 °, and channeling is also performed in this angular range. The ratio of ions greatly varies with the implantation angle. Since the effect of reducing the junction capacitance of the source / drain diffusion layer greatly depends on the amount of impurity ions to be implanted, it is difficult to stably reduce the junction capacitance of the source / drain diffusion layer by this method.
[0013]
  The present invention has been made in view of the above circumstances, and an object of the present invention is to form a shallow source / drain diffusion layer and to increase a channel impurity to suppress a punch-through current, thereby increasing a punch impurity. Semiconductor device having a MOS field effect transistor that does not increase the source-drain junction capacitancePlaceIt is to provide a production method that can be produced stably.
[0014]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor device of the present invention includes a first conductivity type semiconductor substrate having a channel formation region, a gate insulating film formed in an upper layer of the channel formation region, and an upper layer of the gate insulating film. A gate electrode formed in the semiconductor substrate, a source / drain region of a second conductivity type formed in the semiconductor substrate on both sides of the gate electrode in connection with the channel formation region, and the semiconductor substrate in the channel formation region A first conductivity type punch-through prevention layer formed therein, and a first conductivity type effective carrier concentration lower than the punch-through prevention layer formed below the junction surface of the source / drain region. And a conductive type region.
[0015]
The semiconductor device of the present invention is a semiconductor device having a MOS field effect transistor (MOSFET) formed on a semiconductor substrate, and a first conductivity type punch-through prevention layer formed in the semiconductor substrate in a channel formation region. And the punch-through current is suppressed, and the lower part of the junction surface of the source / drain region is the first conductivity type region having an effective carrier concentration of the first conductivity type lower than that of the punch-through prevention layer. Therefore, even if the channel impurity is increased and the punch-through prevention layer is formed, the source-drain junction capacitance is not increased.
[0016]
In the semiconductor device of the present invention, preferably, the first conductivity type region having an effective carrier concentration of the first conductivity type lower than that of the punch through prevention layer is the first conductivity type impurity in the punch through prevention layer. The second conductivity type impurity is contained in the same order as the concentration and at a low concentration. Thereby, the lower part of the junction surface of the source / drain region can be a first conductivity type region having an effective carrier concentration of the first conductivity type lower than that of the punch-through prevention layer.
[0017]
In the semiconductor device of the present invention, preferably, the semiconductor substrate on the channel formation region side of the source / drain region contains a second conductivity type impurity at a lower concentration than the source / drain region. A two-conductivity type low-concentration impurity-containing region is formed. As a result, a MOSFET having an LDD (Lightly Doped Drain) structure can be obtained.
[0018]
In the semiconductor device of the present invention, preferably, a sidewall insulating film is formed on the side wall portion of the gate electrode. Since the sidewall insulating film on the side wall portion of the gate electrode can be used as an ion implantation mask (LDD spacer) when forming the diffusion layer having the LDD structure, an MOSFET having the LDD structure can be formed.
[0019]
  In the semiconductor device of the present invention, preferably, the first conductivity type impurity is higher than the punch-through prevention layer in the semiconductor substrate on the channel formation region side of the second conductivity type low concentration impurity containing region. A pocket layer containing the concentration is formed. ThisThe secondThe punch-through current can be further suppressed by relaxing the drain electric field in the vicinity of the two-conductivity-type low-concentration impurity-containing region (LDD diffusion layer).
[0020]
In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device having a first transistor and a second transistor having a threshold voltage higher than that of the first transistor on a semiconductor substrate. The transistor and the second transistor are formed on a first conductivity type semiconductor substrate, a channel formation region in the semiconductor substrate, a gate insulating film formed in an upper layer of the channel formation region, and an upper layer of the gate insulating film A gate electrode formed in the semiconductor substrate, a source / drain region of a second conductivity type formed in the semiconductor substrate on both sides of the gate electrode in connection with the channel formation region, and the semiconductor substrate in the channel formation region A punch-through prevention layer of a first conductivity type formed therein and a lower portion of a joint surface of the source / drain region, A first conductivity type region having an effective carrier concentration of the first conductivity type lower than that of the anti-routing layer, the gate electrode of the second transistor being higher than the gate electrode of the first transistor, The effective carrier concentration in the channel formation region is higher than the effective carrier concentration in the channel formation region of the first transistor.
[0021]
The semiconductor device according to the present invention is a semiconductor device having a first transistor and a second transistor having a threshold voltage higher than that of the first transistor. In the first transistor and the second transistor, respectively, in the channel formation region in the semiconductor substrate. The punch-through prevention layer of the first conductivity type formed in the first layer is formed to suppress the punch-through current, and the lower part of the junction surface of the source / drain region is more effective of the first conductivity type than the punch-through prevention layer. Since the first conductivity type region has a low target carrier concentration, even if the channel impurity is increased to form the punch-through prevention layer, the junction capacitance between the source and the drain is not increased. In addition, since the effective carrier concentration in the channel formation region of the second transistor is higher than the effective carrier concentration in the channel formation region of the first transistor, the threshold voltage of the second transistor is made higher than that of the first transistor. It is possible. This is because the height of the gate electrode is different between the first transistor and the second transistor, so that the effective carrier concentration of the first conductivity type is lower than the punch-through prevention layer at the lower part of the junction surface of the source / drain region in the manufacturing process. When the first conductivity type region is low, the effective carrier concentration in the channel formation region of each transistor can be changed.
[0022]
In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step of introducing a first conductivity type impurity serving as a punch-through prevention layer into a first conductivity type semiconductor substrate having a channel formation region. Forming a gate insulating film on the channel formation region; forming a gate electrode on the gate insulating film; and introducing the second conductivity type impurity into the semiconductor substrate to form the channel. Forming a source / drain region connected to the region, and ion-implanting a second conductivity type impurity at an angle to the surface of the semiconductor substrate, thereby forming a second under the source / drain region. And introducing a conductivity type impurity.
[0023]
In the method of manufacturing a semiconductor device according to the present invention, a first conductivity type impurity serving as a punch-through prevention layer is introduced into a first conductivity type semiconductor substrate having a channel formation region, and a gate insulating film is formed on the channel formation region. And a gate electrode is formed on the gate insulating film. Next, a second conductivity type impurity is introduced into the semiconductor substrate to form source / drain regions connected to the channel formation region, and the second conductivity type impurity is formed at an angle with respect to the surface of the semiconductor substrate. By ion implantation, a second conductivity type impurity is introduced below the source / drain regions.
[0024]
According to the method for manufacturing a semiconductor device of the present invention, a MOS field effect transistor (MOSFET) can be formed on a semiconductor substrate, and a first conductivity type impurity is introduced to form a punch-through prevention layer. Therefore, the punch-through current is suppressed, and the second conductivity type impurity is ion-implanted at an oblique angle with respect to the surface of the semiconductor substrate so that channeling does not occur, and the second conductivity is formed below the source / drain regions. Since the impurity of the type is introduced, the MOSFET can be formed stably without increasing the amount of the introduced impurity and without increasing the source-drain junction capacitance.
[0025]
In the method of manufacturing a semiconductor device according to the present invention, preferably, in the step of introducing a second conductivity type impurity below the source / drain regions, a 3 to 3 normal to the surface of the semiconductor substrate is used. The second conductivity type impurity is ion-implanted at an angle of 10 °. Thereby, impurities of the second conductivity type can be introduced so as not to cause channeling.
[0026]
In the method of manufacturing a semiconductor device according to the present invention, preferably, in the step of introducing a second conductivity type impurity below the source / drain region, the punch-through prevention is provided below the source / drain region. In the step of introducing the first conductivity type region having a lower effective carrier concentration of the first conductivity type than that of the layer, and more preferably, in the step of introducing the second conductivity type impurity below the source / drain region, A second conductivity type impurity is introduced below the drain region so as to have the same order and low concentration as the first conductivity type impurity concentration in the punch-through prevention layer. Thereby, even if the punch-through prevention layer is formed, it can be formed without increasing the source-drain junction capacitance.
[0027]
In the method of manufacturing a semiconductor device according to the present invention, preferably, in the step of forming the source / drain region and the step of introducing a second conductivity type impurity below the source / drain region, A second conductivity type impurity is introduced using the gate electrode as a mask. As a result, the source / drain regions can be formed in a self-aligned manner with respect to the gate electrode, and the second conductivity type may be formed so as not to increase the source / drain junction capacitance below the source / drain regions. Impurities can be introduced.
[0028]
In the method of manufacturing a semiconductor device according to the present invention, preferably, after the step of forming the gate electrode and before the step of forming the source / drain region, the gate electrode is used as a mask in the semiconductor substrate. Introducing a second conductivity type impurity to form a second conductivity type low concentration impurity-containing region containing a second conductivity type impurity having a lower concentration than the source / drain region; A step of forming a wall insulating film, and in the step of forming the source / drain regions and the step of introducing impurities of the second conductivity type into the lower portions of the source / drain regions, the sidewall insulation is performed. Impurities of the second conductivity type are introduced using the film as a mask. Thereby, a MOSFET having an LDD structure can be formed.
[0029]
In the method of manufacturing a semiconductor device according to the present invention, preferably, after the step of forming the gate electrode and before the step of forming the sidewall insulating film, the surface of the semiconductor substrate using the gate electrode as a mask. The method further includes the step of ion-implanting the first conductivity type impurity at an angle to the first. As a result, a pocket layer containing the first conductivity type impurity at a higher concentration than the punch-through prevention layer can be formed on the channel formation region side of the second conductivity type low concentration impurity containing region (LDD diffusion layer). The through current can be further suppressed.
[0030]
In the method of manufacturing a semiconductor device according to the present invention, preferably, in the step of introducing the second conductivity type impurity below the source / drain region, the projected range distance Rp of impurity ions to be implanted, impurity ions The second conductivity type impurities are ionized so that Xj ≦ Rp ≦ Xj + ΔRp is satisfied with respect to the fluctuation ΔRp of the projected range distance of the substrate and the depth Xj of the junction surface of the source / drain region from the surface of the semiconductor substrate. inject. Here, the fluctuation ΔRp of the projected range distance of impurity ions is (1 / e) of the impurity concentration at the depth Rp from the substrate.^1/2It is the distance from the depth Rp of the depth which becomes the density | concentration of. By setting Xj ≦ Rp ≦ Xj + ΔRp, it becomes possible to selectively introduce the second conductivity type impurity into the lower portion of the source / drain region, and this impurity of the second conductivity type is introduced into the channel forming region side. Since it can be formed while suppressing the spread, it is possible to effectively suppress the punch-through current.
[0031]
In the method of manufacturing a semiconductor device according to the present invention, preferably, in the step of introducing a second conductivity type impurity below the source / drain region, the height H of the gate electrode, the impurity ions to be implanted, The second conductivity type impurity is ion-implanted so that H <Rp + 2ΔRp is satisfied with respect to the projected range distance Rp and the fluctuation ΔRp of the projected range distance of impurity ions. Thus, when the second conductivity type impurity is introduced into the lower portion of the source / drain region, the threshold voltage can be adjusted by simultaneously introducing the second conductivity type impurity into the channel formation region.
[0032]
In the method of manufacturing a semiconductor device according to the present invention, preferably, in the step of introducing a second conductivity type impurity below the source / drain region, the height H of the gate electrode, the impurity ions to be implanted, The second conductivity type impurity is ion-implanted so as to satisfy H ≧ Rp + 2ΔRp with respect to the projected range distance Rp and the fluctuation ΔRp of the projected range of impurity ions. Thus, when the second conductivity type impurity is introduced into the lower portion of the source / drain region, it is possible to prevent the second conductivity type impurity from being introduced into the channel formation region at the same time.
[0033]
In the semiconductor device manufacturing method according to the present invention, preferably, after the step of forming the gate electrode, before the step of forming the source / drain region, an offset insulating film is formed on the upper layer of the gate electrode. In the step of introducing a second conductivity type impurity below the source / drain region, the sum H ′ of the height of the gate electrode and the offset insulating film, and the projection of impurity ions to be implanted The second conductivity type impurities are ion-implanted so as to satisfy H ′ <Rp + 2ΔRp with respect to the range Rp and the fluctuation ΔRp of the projected range of impurity ions. Thus, when the second conductivity type impurity is introduced into the lower portion of the source / drain region, the threshold voltage can be adjusted by simultaneously introducing the second conductivity type impurity into the channel formation region.
[0034]
In the semiconductor device manufacturing method according to the present invention, preferably, after the step of forming the gate electrode, before the step of forming the source / drain region, an offset insulating film is formed on the upper layer of the gate electrode. In the step of introducing a second conductivity type impurity below the source / drain region, the sum H ′ of the height of the gate electrode and the offset insulating film, and the projection of impurity ions to be implanted The second conductivity type impurities are ion-implanted so as to satisfy H ′ ≧ Rp + 2ΔRp with respect to the range Rp and the fluctuation ΔRp of the projected range of impurity ions. Thus, when the second conductivity type impurity is introduced into the lower portion of the source / drain region, it is possible to prevent the second conductivity type impurity from being introduced into the channel formation region at the same time.
[0035]
  In order to achieve the above object, a method for manufacturing a semiconductor device of the present invention includes:A first transistor formed on a semiconductor substrate and a second transistor having a threshold voltage different from that of the first transistor, wherein the first transistor and the second transistor are respectively formed on a first conductivity type semiconductor substrate; A channel forming region in the semiconductor substrate, a gate insulating film formed in an upper layer of the channel forming region, a gate electrode formed in an upper layer of the gate insulating film, and in the semiconductor substrate on both sides of the gate electrode A second conductivity type source / drain region formed in connection with the channel formation region; a first conductivity type punch-through prevention layer formed in the semiconductor substrate in the channel formation region; A first conductor formed below the junction surface of the drain region and having a lower effective carrier concentration of the first conductivity type than the punch-through prevention layer. And the height of the gate electrode of the second transistor is different from the height of the gate electrode of the first transistor so that the threshold value is different. To manufacture a semiconductor device having a carrier concentration higher than the effective carrier concentration in the channel formation region of the first transistor, First transistor formation region and second transistor formation regionEach ofInAboveIn a first conductivity type semiconductor substrate having a channel formation region,To have a maximum value of concentration at a predetermined depth from the surface of the semiconductor substrateAnd introducing a first conductivity type impurity to be a punch-through prevention layerFirstProcess, first transistor formation region and second transistor formation regionEach ofIn the semiconductor substrateOn the channel formation region,Form a gate insulating filmSecondForming a first gate electrode on the gate insulating film in the first transistor forming region; and forming the first gate electrode on the gate insulating film in the second transistor forming region.Different height fromForming a second gate electrodeThirdProcess, first transistor formation region and second transistor formation regionEach ofIn the method, a source / drain region connected to the channel formation region is formed by introducing a second conductivity type impurity into the semiconductor substrate.the fourthProcess, first transistor formation region and second transistor formation regionEach ofInUsing the first gate electrode and the second gate electrode having different heights as masks,The projected range distance Rp of the impurity ions to be implanted, the fluctuation ΔRp of the projected range distance of the impurity ions, the height H1 of the first gate electrode, and the height H2 of the second gate electrode H1 <Rp + 2ΔRp ≦ H2 SatisfyUnder the same conditions, the semiconductor substrate andOf the source / drain regionJoint surfaceAt the bottomIn contact with the punch-through prevention layer,Impurities of the second conductivity typeBy ion implantationIntroducedAnd a fifth step of making the threshold value of the second transistor different from the threshold value of the first transistor.
[0036]
  The method of manufacturing a semiconductor device according to the present invention includes a first transistor formation region and a second transistor formation region.Each ofIn the first conductivity type semiconductor substrate having a channel formation region,In order to have a maximum value of concentration at a predetermined depth from the surface of the semiconductor substrate,A first transistor type region and a second transistor region are formed by introducing a first conductivity type impurity to be a punch-through prevention layerEach ofIn the semiconductor substrateOn the channel formation region,A gate insulating film is formed. Next, in the first transistor formation region, a first gate electrode is formed above the gate insulating film, and in the second transistor formation region, a second gate electrode higher than the second gate electrode is formed above the gate insulating film. Form. Next, a first transistor formation region and a second transistor formation regionEach ofAnd introducing a second conductivity type impurity into the semiconductor substrate to form a source / drain region connected to the channel formation region,Further, using the first gate electrode and the second gate electrode as a mask,The projected range distance Rp of the impurity ions to be implanted, the fluctuation ΔRp of the projected range distance of the impurity ions, the height H1 of the first gate electrode, and the height H2 of the second gate electrode H1 <Rp + 2ΔRp ≦ H2 SatisfyUnder the same conditions, the semiconductor substrate andOf the source / drain regionJoint surfaceAt the bottomIn contact with the punch-through prevention layer,Impurities of the second conductivity typeBy ion implantationIntroduce.
[0037]
According to the method for manufacturing a semiconductor device of the present invention, when the first transistor and the second transistor are formed, the second conductive layer is formed below the source / drain region by changing the height of the gate electrode of each transistor. When the impurity of the type is introduced, the second conductivity type impurity is ion-implanted so as to satisfy H1 <Rp + 2ΔRp ≦ H2, so that in the first transistor, the second conductivity type impurity is simultaneously introduced into the channel formation region. Then, the threshold voltage is adjusted to prevent the second conductivity type impurity from being introduced into the channel formation region at the same time in the second transistor. Thereby, a semiconductor device having a first transistor and a second transistor having different threshold voltages can be manufactured.
[0038]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of a semiconductor device according to the present invention will be described below with reference to the drawings by way of examples.
[0039]
First embodiment
FIG. 1A is a cross-sectional view of a semiconductor device having an n-channel MOSFET using the LDD structure according to the present embodiment. For example, a gate insulating film 21a made of, for example, silicon oxide is formed on the active region (channel forming region) of the p-type semiconductor substrate 10 separated by an element isolation insulating film 20 formed by STI (Shallow Trench Isolation). Yes. A gate electrode 30a made of, for example, polysilicon is formed on the upper layer. Side wall insulating films 22 made of, for example, silicon oxide are formed on both sides of the gate electrode 30a. A source / drain diffusion layer 13 containing, for example, an n-type impurity is formed in the semiconductor substrate 10 on both sides of the gate electrode. Further, for example, an n-type impurity is added to the source / drain diffusion layer on the channel formation region side. An LDD (Lightly Doped Drain) diffusion layer 12 containing a lower concentration than 13 is formed. Further, in the channel formation region (the lower region of the gate electrode 30a) in the semiconductor substrate 10, a punch-through prevention layer for containing a high concentration of p-type impurities to prevent punch-through which is one of the short channel effects. 11 is formed. In the punch-through prevention layer 11, as the depth from the surface of the semiconductor substrate 10 increases, as shown in FIG. 1B, which is a p-type impurity concentration profile at a position along XX ′ in FIG. The impurity concentration is increased, and for example, a profile having a maximum value in the depth between the junction surface of the LDD diffusion layer 12 and the junction surface of the source / drain diffusion layer 13 is taken. A p-type region 14 having a lower p-type effective carrier concentration than the punch-through prevention layer 11 is formed below the junction surface of the source / drain diffusion layer 13.
[0040]
The above MOSFET induces an n-type inversion layer in the channel formation region of the p-type semiconductor substrate 10 by applying a voltage to the gate electrode 30a, the induced inversion layer becomes a channel, and current flows from the source diffusion layer to the drain. It is possible to flow to the diffusion layer. Here, since the p-type punch-through prevention layer 11 is formed in the semiconductor substrate in the channel formation region, the punch-through current can be suppressed, and the lower part of the junction surface of the source / drain diffusion layer 13 is Since the p-type region 14 has a lower p-type effective carrier concentration than the punch-through prevention layer 11, even if the channel impurity is increased to form the punch-through prevention layer 11, the source-drain junction capacitance is increased. Do not increase. The p-type region 14 having a lower p-type effective carrier concentration than the punch-through prevention layer 11 contains a p-type impurity having the same concentration as the punch-through prevention layer 11, and is in the same order and low as the p-type impurity. By containing an n-type impurity in the concentration, the p-type effective carrier concentration can be made lower than that of the punch-through prevention layer 11.
[0041]
Next, a method for manufacturing the semiconductor device will be described. First, as shown in FIG. 2A, for example, an element isolation insulating film 20 having a thickness of 300 nm is formed on a p-type silicon semiconductor substrate 10 by an STI method or the like.
[0042]
Next, as shown in FIG. 2B, on the active region of the p-type semiconductor substrate 10 separated by the element isolation insulating film 20, well formation, channel stop layer formation, punch through prevention layer formation, In order to adjust the threshold value, p-type impurity D1 is ion-implanted. In the drawing, only the punch-through prevention layer 11 is shown. For example, boron is ion-implanted with an energy of 50 keV, and the concentration profile of the p-type impurity is, for example, at a predetermined depth from the substrate surface as shown in FIG. 1B. It is introduced so as to have a maximum value of concentration.
[0043]
Next, as shown in FIG. 3C, a silicon oxide gate insulating film 21 having a thickness of 4 nm is formed by, eg, thermal oxidation.
[0044]
Next, as shown in FIG. 3D, a gate electrode layer 30 is formed by depositing polysilicon with a thickness of 200 nm on the gate insulating film 21 by, for example, a CVD (Chemical Vapor Deposition) method.
[0045]
Next, as shown in FIG. 4E, a resist film having a gate electrode pattern is formed by a photolithography process, and etching such as RIE (reactive ion etching) is performed to form the gate electrode 30a.
[0046]
  Next, as shown in FIG.aAs an n-type impurity D2, for example, arsenic is ion-implanted with an energy of 10 keV to form the LDD diffusion layer 12. Next, for example, RTA (Rapid Thermal Annealing) processing is performed by lamp annealing at 1000 ° C. for 10 seconds in a nitrogen atmosphere, thereby recovering crystal defects in the semiconductor substrate and activating the introduced impurity D2.
[0047]
Next, as shown in FIG. 5G, for example, a silicon oxide layer is deposited to a thickness of 100 nm by a CVD method, and the entire surface is etched back by etching such as RIE. Silicon oxide or silicon nitride is removed leaving the side wall portion of the electrode 30a, and a side wall insulating film 22 having a width of about 100 nm is formed on the side wall portion of the gate electrode 30a.
[0048]
Next, as shown in FIG. 5H, for example, arsenic is ion-implanted as an n-type impurity D3 with an energy of 50 keV using the sidewall insulating film 22 as a mask to form the source / drain diffusion layer 13.
[0049]
Next, as shown in FIG. 6I, the sidewall insulating film 22 is used as a mask and an angle of 3 to 10 ° is formed with respect to the normal of the surface of the semiconductor substrate 10 to form, for example, phosphorus as the n-type impurity D4. Is implanted at an energy of 100 keV, and an n-type impurity is introduced below the source / drain diffusion layer 12 in the same order as the p-type impurity concentration in the punch-through prevention layer 11 and at a low concentration. The lower part of the source / drain diffusion layer 13 is a p-type region 14 having a lower p-type effective carrier concentration than the punch-through prevention layer 11.
[0050]
Next, for example, by performing RTA treatment by lamp annealing at 1000 ° C. for 10 seconds in a nitrogen atmosphere, recovery of crystal defects in the semiconductor substrate, activation of the introduced impurities D3 and D4, and the like are performed. Thus, the semiconductor device having the MOSFET shown in FIG. As the subsequent steps, for example, an interlayer insulating film of silicon oxide is formed so as to cover the MOSFET, a contact hole reaching the source / drain diffusion layer 12 is opened in the interlayer insulating film, and a buried electrode is formed in the contact hole. Further, an upper layer wiring or the like is formed to form a desired semiconductor device. As the MOSFET, a refractory metal silicide region can be formed above the gate electrode and the source / drain diffusion layer by a SALICIDE (Self Aligned Silicide) process.
[0051]
Here, n-type impurities for forming a p-type region 14 having a lower p-type effective carrier concentration than the punch-through prevention layer 11 below the source / drain diffusion layer 13 shown in FIG. Ion implantation will be described with reference to FIG. The total impurity implantation amount at the time of ion implantation is Q, the projected range distance of impurity ions to be implanted is Rp, and the projected range distance of impurity ions fluctuates (impurity concentration (1 / e) at the depth Rp from the substrate).^1/2Is a range of Rp−ΔRp to Rp + ΔRp (in the figure), where ΔRp is the depth of the depth at which the concentration of the source / drain region is from Rp and Xj is the depth of the junction surface of the source / drain region from the surface of the semiconductor substrate. About 70% (0.7Q) of impurities are implanted into the hatched portion), and only about 1.5% (0.15Q) of impurities are implanted into a region deeper than Rp + ΔRp. . Here, by setting Rp to be Xj + ΔRp, approximately 70% (0.7Q) of impurities are injected into the range of Xj to Xj + 2ΔRp, which is the region immediately below the source / drain region, thereby effectively It is possible to reduce the source / drain junction capacitance. Since the ion implantation is performed with an angle with respect to the substrate so that channeling does not occur, it is possible to stably perform the impurity implantation by controlling the amount of impurity implantation. Further, since there is a relationship similar to the above in the manner in which the impurity to be implanted spreads toward the channel formation region side, the impurity is not implanted into a region farther than Xj + 2ΔRp, and the punch-through current is effectively suppressed. be able to. Rp is preferably set to satisfy Xj ≦ Rp ≦ Xj + ΔRp.
[0052]
In the above ion implantation, only about 2.3% (0.023Q) or less is implanted into a region deeper than Rp + 2ΔRp. Therefore, by adjusting the height of the gate electrode (the sum of the height of the gate electrode and the offset insulating film when the offset insulating film is formed on the upper layer of the gate electrode), the punch-through preventing layer 11 In the ion implantation of the n-type impurity for forming the p-type region 14 having a low p-type effective carrier concentration, an n-type impurity is simultaneously introduced into the channel formation region to adjust the threshold voltage, or the channel It is possible to prevent the n-type impurity from being introduced into the formation region. That is, as shown in FIG. 7B, by reducing the gate electrode so that the height H of the gate electrode satisfies H <Rp + 2ΔRp, a part of the impurity ions penetrates through the gate electrode to form a channel. As a result, the effective carrier concentration is lowered and the threshold voltage can be lowered. On the contrary, by raising the gate electrode so as to satisfy H ≧ Rp + 2ΔRp, a part of the impurity ions does not penetrate the gate electrode and are implanted into the channel formation region, thereby reducing the effective carrier concentration. It can be formed without lowering. When the offset insulating film is formed on the upper layer of the gate electrode, the sum H ′ of the heights of the gate electrode and the offset insulating film is set so as to satisfy H ′ <Rp + 2ΔRp. The portion penetrates the gate electrode and is implanted into the channel formation region. By setting H ′ ≧ Rp + 2ΔRp, a part of the impurity ions penetrates the gate electrode and is implanted into the channel formation region. Will never be done.
[0053]
In the above ion implantation, since the threshold value of the transistor can be adjusted according to the height of the gate electrode, transistors with different gate electrode heights are formed, for example, with respect to the height H of the gate electrode. , H <Rp + 2ΔRp, and H ≧ Rp + 2ΔRp are formed (for example, a gate electrode having a height of 200 nm and a gate electrode having a height of 250 nm are formed). Part of the ions are implanted into the channel formation region, and the latter does not cause impurity ions to be implanted into the channel formation region in the above-described ion implantation, and transistors with different threshold values can be formed by a simple method. It is. In order to form gate electrodes having different heights as described above, for example, a resist mask is formed by a photolithography process, and only a gate electrode to be formed with a low height is removed by dry etching by a necessary amount. It is possible. At this time, when the impurity is introduced into the gate electrode, it is preferable to implant the impurity in advance.
[0054]
According to the semiconductor device manufacturing method of the present embodiment, an n-channel MOS field effect transistor (MOSFET) can be formed on a semiconductor substrate. The punch-through prevention layer is formed by introducing p-type impurities, so that the punch-through current is suppressed, and the n-type impurities are ionized at an angle to the surface of the semiconductor substrate so as not to cause channeling. Since n-type impurities are introduced into the lower portion of the source / drain region by implantation, MOSFETs can be formed stably without increasing the amount of impurities introduced and without increasing the junction capacitance of the source / drain. It is.
[0055]
  In the present embodiment, an n-channel transistor has been described. However, an n-type impurity is a p-type impurity.WhenA p-channel transistor can be obtained by replacement. In the manufacturing process, for example, an n-type semiconductor substrate is used, phosphorus is ion-implanted at 100 keV in the punch-through prevention layer forming process, and BF in the LDD diffusion layer forming process.₂ Is implanted at 10 keV, and BF is formed in the source / drain diffusion layer forming process.₂ Is implanted at 20 keV, and in the ion implantation step of the p-type impurity for making the lower part of the source / drain diffusion layer an n-type region having an n-type effective carrier concentration lower than that of the punch-through prevention layer, boron is implanted. It can be formed by ion implantation at 40 keV.
[0056]
(Example)
An n-channel MOSFET was formed on a p-type silicon semiconductor substrate as follows. First, as shown in FIG. 2A, an element isolation insulating film 20 having a thickness of 300 nm is formed on a p-type silicon semiconductor substrate 10 by STI or the like. As shown in FIG. Boron ions were implanted as D1 at an energy of 50 keV to form the punch-through prevention layer 11. Next, as shown in FIG. 3C, a silicon oxide gate insulating film 21 having a thickness of 4 nm was formed by thermal oxidation. Next, as shown in FIG. 3D, polysilicon is deposited to a thickness of 200 nm on the gate insulating film 21 by, for example, a CVD method to form a gate electrode layer 30, and FIG. As shown, a resist film having a gate electrode pattern was formed by a photolithography process and processed into a gate electrode 30a pattern by RIE (reactive ion etching).
[0057]
Next, as shown in FIG. 4F, arsenic is ion-implanted as an n-type impurity D2 with an energy of 10 keV using the gate electrode 30 as a mask to form an LDD diffusion layer 12, and the temperature is 1000 ° C., 10 ° C. in a nitrogen atmosphere. After performing the RTA process by the second lamp annealing, as shown in FIG. 5G, a sidewall insulating film 22 having a width of about 100 nm was formed on the sidewall of the gate electrode 30a. Next, as shown in FIG. 5 (h), arsenic is ion-implanted as an n-type impurity D3 with an energy of 50 keV using the sidewall insulating film 22 as a mask to form a source / drain diffusion layer 13, and FIG. As shown in i), phosphorus is ion-implanted with an energy of 100 keV as an n-type impurity D4 at an angle of 3 to 10 ° with respect to the normal of the surface of the semiconductor substrate 10 using the sidewall insulating film 22 as a mask. Then, an n-type impurity is introduced below the source / drain diffusion layer 12 so as to be in the same order as the p-type impurity concentration in the punch-through prevention layer 11 and to have a low concentration so that the lower part of the source / drain diffusion layer 13 is formed. The p-type region 14 has a lower p-type effective carrier concentration than the punch-through prevention layer 11. Next, for example, RTA treatment was performed by lamp annealing at 1000 ° C. for 10 seconds in a nitrogen atmosphere.
[0058]
In the ion implantation of phosphorus for forming the p-type region 14 having a lower p-type effective carrier concentration than the punch-through prevention layer 11 below the source / drain diffusion layer 13, the dose is set to 0 (conditions for not implanting). ) 5 × 10¹²atoms / cm²1 × 10¹³atoms / cm² The conditions were as follows. Further, the projected range distance of the impurity ions to be implanted is set to Rp, and the depth of the junction surface of the source / drain region from the surface of the semiconductor substrate is set to about Xj, and the height H of the gate electrode is H <Rp + 2ΔRp As a condition, a part of phosphorus to be implanted penetrates the gate electrode and is implanted into the channel formation region.
[0059]
FIG. 8A is a diagram in which the junction capacitance C of the source / drain diffusion layer of the n-channel transistor formed as described above is plotted for each dose with respect to the cumulative probability. Thus, it was confirmed that the junction capacitance of the source / drain diffusion layer was effectively reduced by phosphorus ion implantation.
[0060]
FIG. 8B is a diagram showing roll-off characteristics in which the threshold value Vth of the transistor is plotted against the gate length L for the n-channel transistor formed as described above. Thus, the increase in roll-off can be suppressed by phosphorus ion implantation, that is, the increase in punch-through current can be suppressed, and the threshold voltage of the transistor can be lowered as the phosphorus dose is increased. It was confirmed.
[0061]
Second embodiment
FIG. 9A is a cross-sectional view of a semiconductor device having a p-channel MOSFET using the LDD structure according to the present embodiment. Although substantially the same as the semiconductor device according to the first embodiment, a pocket layer 15 containing a p-type impurity at a higher concentration than the punch-through prevention layer 11 is further provided on the channel formation region side of the LDD diffusion layer 12. It differs in that it is formed. As in the first embodiment, in the punch-through prevention layer 11, as shown in FIG. 9B, which is a p-type impurity concentration profile at a position along XX ′ in FIG. As the depth from the surface of the semiconductor substrate 10 increases, the impurity concentration increases. For example, the profile has a maximum value in the depth between the junction surface of the LDD diffusion layer 12 and the junction surface of the source / drain diffusion layer 13. In addition, a p-type region 14 having a lower p-type effective carrier concentration than the punch-through prevention layer 11 is formed below the junction surface of the source / drain diffusion layer 13.
[0062]
Next, a method for manufacturing the semiconductor device will be described. In the same manner as in the first embodiment, after forming the LDD diffusion layer 12, as shown in FIG. 10A, boron is ion-implanted as a p-type impurity obliquely (for example, about 45 °) with respect to the semiconductor substrate. Then, a pocket layer 15 containing a p-type impurity at a higher concentration than the punch-through prevention layer 11 is formed. The subsequent steps are the same as in the first embodiment, and n-type impurities such as arsenic are ion-implanted to form the source / drain diffusion layer 13, and further n-type impurities D4 such as phosphorus are ion-implanted to form the source / drain. The lower part of the diffusion layer 13 is the p-type region 14 having a lower p-type effective carrier concentration than the punch-through prevention layer 11, leading to the semiconductor device shown in FIG.
[0063]
In the semiconductor device of the present embodiment, the pocket layer 15 containing the p-type impurity having a higher concentration than the punch-through prevention layer 11 is formed on the channel formation region side of the LDD diffusion layer 12. Can be further suppressed.
[0064]
The semiconductor device and the manufacturing method thereof according to the present invention are not limited to the above embodiments. For example, the gate electrode may have two or more layers such as polycide as well as a single layer configuration as in the present embodiment. The height of the gate electrode is not particularly limited, and can be various heights as necessary. In addition, various modifications can be made without departing from the scope of the present invention.
[0065]
【The invention's effect】
According to the semiconductor device of the present invention, the punch-through prevention layer of the first conductivity type formed in the semiconductor substrate is formed in the channel formation region, the punch-through current is suppressed, and the junction surface of the source / drain region Is a first conductivity type region having an effective carrier concentration of the first conductivity type lower than that of the punch-through prevention layer. Therefore, even if the channel impurity is increased to form the punch-through prevention layer, the source Does not increase the drain junction capacitance.
[0066]
Further, according to the method for manufacturing a semiconductor device of the present invention, the semiconductor device of the present invention can be easily manufactured. Since the punch-through prevention layer is formed by introducing the first conductivity type impurity, the punch-through current is suppressed, and the second conductivity is formed at an angle with respect to the surface of the semiconductor substrate so as not to cause channeling. Since the second conductivity type impurity is introduced into the lower portion of the source / drain region by ion implantation of the type impurity, the MOSFET can be stably supplied without variation in the amount of the introduced impurity without increasing the junction capacitance of the source / drain. Can be formed.
[Brief description of the drawings]
FIG. 1A is a sectional view of a semiconductor device according to a first embodiment, and FIG. 1B is an impurity profile at X-X ′ in FIG.
2A and 2B are cross-sectional views showing the manufacturing process of the semiconductor device manufacturing method according to the first embodiment, wherein FIG. 2A shows the element isolation insulating film forming process, and FIG. 2B shows the punch-through prevention layer. The formation process is shown.
FIGS. 3A and 3B show a continuation process of FIG. 2, in which FIG. 3C shows the process up to the formation process of the gate insulating film, and FIG.
4 shows a process continued from FIG. 3, in which (e) shows up to the gate electrode patterning process and (f) shows up to the LDD diffusion layer forming process.
5 shows a process continued from FIG. 4, in which (g) shows the process up to the side wall insulating film formation process and (h) shows the process up to the process of forming the source / drain diffusion layer.
6 shows a step subsequent to FIG. 5, and (i) shows a step up to a step of ion-implanting a first conductivity type impurity under the source / drain diffusion layer. FIG.
FIG. 7A is a schematic diagram for explaining an implantation position in the step of ion-implanting the first conductivity type impurity below the source / drain diffusion layer, and FIG. 7B is a diagram illustrating the height of the gate electrode. FIG. 6 is a schematic diagram for explaining a method for controlling the implantation of impurities into a channel formation region.
FIG. 8A is a diagram in which the junction capacitance C of the source / drain diffusion layer of the transistor is plotted against the cumulative probability in the example, and FIG. It is a figure which shows the roll-off characteristic which plotted the threshold value Vth.
9A is a cross-sectional view of the semiconductor device according to the second embodiment, and FIG. 9B is an impurity profile at X-X ′ in FIG. 9A.
FIGS. 10A and 10B are cross-sectional views showing a manufacturing process of the semiconductor device manufacturing method according to the second embodiment, wherein FIG. 10A is a pocket layer forming process and FIG. 10B is a lower part of a source / drain diffusion layer; 1 to the step of ion-implanting the first conductivity type impurity.
11A is a cross-sectional view of a conventional semiconductor device, and FIG. 11B is an impurity profile at X-X ′ in FIG. 11A.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... p-type semiconductor substrate, 11 ... p-type punch through prevention layer, 12 ... n-type LDD diffusion layer, 13 ... n-type source / drain diffusion layer, 14 ... p-type region, 15 ... p-type pocket layer, 20 ... element Isolation insulating films, 21, 21a ... gate insulating films, 22 sidewall insulating films, 30 ... gate electrode layers, 30a ... gate electrodes, D1, D2, D3, D4, D5 ... impurity ions.

Claims (1)

A first transistor formed on a semiconductor substrate and a second transistor having a threshold voltage different from that of the first transistor;
The first transistor and the second transistor are each formed on a first conductivity type semiconductor substrate, a channel formation region in the semiconductor substrate, a gate insulating film formed in an upper layer of the channel formation region, and the gate insulation A gate electrode formed in an upper layer of the film; a source / drain region of a second conductivity type formed in the semiconductor substrate on both sides of the gate electrode in connection with the channel formation region; and the channel formation region. A first conductivity type punch-through prevention layer formed in the semiconductor substrate and an effective carrier concentration of the first conductivity type formed below the junction surface of the source / drain region. A low first conductivity type region;
The height of the gate electrode of the second transistor is different from the height of the gate electrode of the first transistor so that the threshold values are different.
In order to manufacture a semiconductor device in which the effective carrier concentration in the channel formation region of the second transistor is higher than the effective carrier concentration in the channel formation region of the first transistor ,
In each of the first transistor forming region and a second transistor forming region, a first conductivity type semiconductor substrate having the channel formation region, so as to have a maximum value of the density from the semiconductor substrate surface at a given depth, A first step of introducing a first conductivity type impurity to be a punch-through prevention layer;
A second step of forming a gate insulating film on the channel formation region of the semiconductor substrate in each of the first transistor formation region and the second transistor formation region;
In the first transistor formation region, a first gate electrode is formed above the gate insulating film, and in the second transistor formation region, a height different from the height of the first gate electrode is formed on the gate insulating film. A third step of forming the second gate electrode;
A fourth step of forming a source / drain region connected to the channel formation region by introducing a second conductivity type impurity into the semiconductor substrate in each of the first transistor formation region and the second transistor formation region; ,
In each of the first transistor formation region and the second transistor formation region , the projection range distance Rp of the impurity ions to be implanted and the projection of the impurity ions with the first gate electrode and the second gate electrode having different heights as masks The semiconductor substrate and the source / drain are subjected to the same conditions that satisfy H1 <Rp + 2ΔRp ≦ H2 with respect to the range distance fluctuation ΔRp, the height H1 of the first gate electrode, and the height H2 of the second gate electrode. in contact with Oite the punch-through prevention layer in the lower portion of the joint surface region, a second conductivity type impurity is introduced by ion implantation, and the threshold of the second transistor, the first transistor threshold DOO possess a fifth step of varying the performs processing in the order of the fifth step from the first step, a method of manufacturing a semiconductor device.

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