CN104681608B - The n-type LDMOS device and its manufacture method of a kind of high isolation - Google Patents
The n-type LDMOS device and its manufacture method of a kind of high isolation Download PDFInfo
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- 239000000758 substrate Substances 0.000 claims abstract description 69
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 28
- 239000010703 silicon Substances 0.000 claims abstract description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 25
- 229920005591 polysilicon Polymers 0.000 claims abstract description 25
- 239000002210 silicon-based material Substances 0.000 claims abstract description 12
- 238000002347 injection Methods 0.000 claims description 10
- 239000007924 injection Substances 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 2
- 238000000605 extraction Methods 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 description 12
- 238000001259 photo etching Methods 0.000 description 11
- 238000000137 annealing Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 4
- 238000005260 corrosion Methods 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
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- H—ELECTRICITY
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0642—Isolation within the component, i.e. internal isolation
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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Abstract
This application discloses a kind of n-type LDMOS device of high isolation.There is deep n traps in p-type silicon substrate, n traps are lightly doped and p traps one are lightly doped.Have in deep n traps and p traps two are lightly doped；There is heavy doping p traps two and heavy doping n traps one in p traps two are lightly doped；The source electrode with n-type heavy doping and body area draw-out area in heavy doping p traps two；There is drain electrode in heavy doping n traps one；There is gate oxide on the heavy doping p traps two and partial heavy doping n traps one of part；Gate oxide and close to portions of isolation structure four on there is polysilicon gate.There is heavy doping p traps one in p traps one are lightly doped；There is substrate draw-out area in heavy doping p traps one.There is heavy doping n traps two in n traps are lightly doped；There is protection ring draw-out area in heavy doping n traps two.There are multiple isolation structures on the surface of silicon materials.The application can realize that body area isolates with substrate, substrate with protection ring, drain electrode with the good electrical of protection ring.
Description
Technical field
The application is related to a kind of semiconductor devices, more particularly to a kind of LDMOS（Laterally diffused MOS transistor）Device.
Background technology
Referring to Fig. 1, this is a kind of cross-sectional view of existing n-type LDMOS device.In p-type silicon substrate（It is or outer
Prolong layer）There is the drift region 101 and heavy doping p traps 2 192 that n-type is lightly doped, the latter is as body area in 100.In silicon substrate 100
The also annular p traps 1 that are lightly doped are enclosed in drift region 101 and the outside of body area 192.Also have in p traps 1 are lightly doped
The heavy doping p traps 1 of annular.There is the substrate draw-out area 221 of the p-type heavy doping of annular in heavy doping p traps 1.
The source electrode 223 of body area draw-out area 225 and n-type heavy doping in body area 192 with p-type heavy doping.There is n in drift region 101
The drain electrode 224 of type heavy doping.There is the isolation structure of multiple dielectric materials on the surface of silicon substrate 100.Wherein, annular isolation
Structure 1 is enclosed in the outside of substrate draw-out area 221.Annular isolation structure 170 in the inner side of substrate draw-out area 221, and
In the outside of drain electrode 224 and body area draw-out area 225.Isolation structure 4 174 is between grid 210 and drain electrode 224.In part body area
192nd, there is gate oxide 200 on part drift region 101.Have on gate oxide 200 and portions of isolation structure 4 174
Polysilicon gate 210.
Above-mentioned n-type LDMOS device has as a drawback that：
First, because p-type body area 192 is located in p-type silicon substrate 100, thus can not realize the electricity of body area and substrate every
From.
Second, it may not apply to high side circuitry.Referring to Fig. 2, this is the high-end of n-type MOS transistor（high side）Electricity
Road schematic diagram, its connection power supply that drains, source electrode connect load with body area draw-out area and then are grounded.If above-mentioned n-type LDMOS device
Applied to high side circuitry, then because body area can not isolate with substrate, and source electrode is caused to be connected with body area draw-out area with substrate three
Load and then ground connection.When above-mentioned n-type LDMOS device turns on, loaded level is raised, while makes source electrode and body area draw-out area and lining
Bottom three's current potential is also raised, and have impact on normal electric isolation between device and substrate.
Third, it may not apply to drain electrode plus negative pressure, the situation of Substrate ground.If silicon substrate 100 is grounded, drain simultaneously
224 plus negative voltage, then the PN junction formed between p-type silicon substrate 100 and n-type drift region 101 will forward bias and turn on,
The electric isolation of the n-type drain 224 and substrate in n-type drift region 101 can not be realized.
Referring to Fig. 3, this is the cross-sectional view of another existing n-type LDMOS device.Compared to Figure 1, it is used
The deep n traps 120 being lightly doped instead of drift region 101.In Fig. 1, drift region 101 substantially has identical junction depth with body area 192, and
Do not include mutually, both do not contact either or only contacts side surfaces.In figure 3, deep n traps 120 surround body area 192.Due to depth
The presence of n traps 120, the electric isolation between body area 192 and silicon substrate 100 is realized, thus can apply to high side circuitry.But
It is that device shown in Fig. 3 still may not apply to drain electrode plus negative pressure, the situation of Substrate ground.
Referring to Fig. 4, this is the cross-sectional view of another existing n-type LDMOS device.It is lightly doped in p-type
Silicon substrate（Or epitaxial layer）There is the deep n traps 120 being lightly doped in 100 and p traps 1 are lightly doped.P traps one are lightly doped in annular
131 are enclosed in the outside of deep n traps 120.Have in deep n traps 120 and p traps 2 132 and heavy doping n traps 2 180 is lightly doped, it is annular
Heavy doping n traps 2 180 are enclosed in the outside that p traps 2 132 are lightly doped.There is heavy doping p traps 2 192 in p traps 2 132 are lightly doped
With heavy doping n traps 1, annular heavy doping p traps 2 192 are enclosed in the outside of heavy doping n traps 1.In the heavily doped of part
There is gate oxide 200 on miscellaneous p traps 2 192 and partial heavy doping n traps 1.Gate oxide 200 and close to part
There is polysilicon gate 210 on isolation structure 4 174.There is the heavy doping p traps one of annular in p traps 1 are lightly doped
191.There is the p-type heavy doping substrate draw-out area 221 of annular in heavy doping p traps 1.Have in heavy doping n traps 2 180
The protection ring draw-out area 222 of the n-type heavy doping of annular.There is the source electrode 223 and ring of n-type heavy doping in heavy doping p traps 2 192
The body area draw-out area 225 of the p-type heavy doping of shape.There is the drain electrode 224 of n-type heavy doping in heavy doping n traps 1.In silicon material
The surface of material has multiple isolation structures 171~175.The isolation structure 1 of annular is enclosed in the outer of substrate draw-out area 221
Side.The isolation structure 2 172 of annular is between substrate draw-out area 221 and protection ring draw-out area 222.The isolation structure of annular
173 between protection ring draw-out area 222 and body area draw-out area 225.Isolation structure 4 174 is located in heavy doping n traps 1,
And between polysilicon gate 210 and drain electrode 224.Isolation structure 5 175 is between drain electrode 224 and body area draw-out area 225.
Compared with Fig. 3, Fig. 4 has increased protection ring draw-out area 222 newly, and also serves as protection ring by deep n traps 120.Due in deep n traps
Increased newly again in 120 and p traps 2 132 are lightly doped, thus can apply to drain electrode plus negative pressure, the situation of Substrate ground.But if
Reverse bias is presented between substrate draw-out area 221 and protection ring draw-out area 222, then because the junction depth of deep n traps 120 is very big, it is difficult to
It is completely depleted, thus pressure-resistant be restricted.
The content of the invention
Technical problems to be solved in this application are to provide a kind of n-type LDMOS device with high isolation, its high isolation
Property is embodied in：
First, the electric isolation between body area and substrate is realized, to meet the application demand of high side circuitry.
Second, the electric isolation of the High Pressure Difference between substrate and protection ring is realized, it is pressure-resistant to reach more than 100V, such as reach
100~200V.
Third, the electric isolation between drain electrode and protection ring is realized, to meet the application demand of drain electrode plus negative pressure.
In order to solve the above technical problems, silicon substrate that the n-type LDMOS device of the application high isolation is lightly doped in p-type or
There is the deep n traps being lightly doped in epitaxial layer, n traps are lightly doped and p traps one are lightly doped；The n traps that are lightly doped of annular are enclosed in deep n traps
Outside；The p traps one that are lightly doped of annular are enclosed in the outside that n traps are lightly doped；
Have in deep n traps and p traps two are lightly doped；There is the heavy doping of heavy doping n traps one and annular in p traps two are lightly doped
P traps two；The body area draw-out area of the p-type heavy doping of source electrode and annular in heavy doping p traps two with n-type heavy doping；Heavily doped
There is the drain electrode of n-type heavy doping in miscellaneous n traps one；There are grid on the heavy doping p traps two and partial heavy doping n traps one of part
Oxide layer；Gate oxide and close to portions of isolation structure four on there is polysilicon gate；
There is the heavy doping p traps one of annular in p traps one are lightly doped；Have the p-type of annular heavily doped in heavy doping p traps one
Miscellaneous substrate draw-out area；
There is the heavy doping n traps two of annular in n traps are lightly doped；There is the n-type heavy doping of annular in heavy doping n traps two
Protection ring draw-out area；
There are multiple isolation structures on the surface of silicon materials；The isolation structure one of annular is enclosed in the outer of substrate draw-out area
Side；The isolation structure two of annular is between substrate draw-out area and protection ring draw-out area；The isolation structure three of annular is positioned at protection
Between ring draw-out area and body area draw-out area；Isolation structure four is located in heavy doping n traps one, and positioned at polysilicon gate and drain electrode
Between；Isolation structure five is between drain electrode and body area draw-out area.
The manufacture method of the n-type LDMOS device of the high isolation of the application comprises the following steps：
1st step, go out one layer of screen oxide in the Film by Thermal Oxidation of p-type silicon substrate or epitaxial layer, then served as a contrast in silicon
The deep n traps that ion implanting is lightly doped to be formed are carried out in bottom；
2nd step, carry out ion implanting in a silicon substrate to form annular is lightly doped p traps one, is enclosed in the outer of deep n traps
Side；Formed simultaneously in deep n traps and p traps two are lightly doped；
3rd step, carry out ion implanting in a silicon substrate to form annular is lightly doped n traps, and it is positioned at being lightly doped p traps one
Inner side, and it is enclosed in the outside of deep n traps；
4th step, ion implanting is carried out in p traps two are lightly doped to form heavy doping n traps one；
5th step, one layer of silicon nitride is first deposited on screen oxide, then existed using selective oxidation or shallow grooved-isolation technique
Silicon materials surface forms each isolation structure, then removes remaining silicon nitride；
6th step, ion implanting is carried out in n traps are lightly doped to form the heavy doping n traps two of annular；P traps one are being lightly doped
The middle ion implanting that carries out also forms annular heavy doping p to form the heavy doping p traps one of annular in p traps two are lightly doped
Trap two；
7th step, all screen oxides, then one layer of gate oxide of Film by Thermal Oxidation in silicon materials are first removed, is connect
One layer of polysilicon of deposit on gate oxide and each isolation structure, finally etching is polysilicon gate；
8th step, first remove except polysilicon gate lower section is with the gate oxide of exterior domain, then enter in heavy doping p traps one
Row ion implanting forms the substrate draw-out area of the p-type heavy doping of annular, while the p-type of annular is also formed in heavy doping p traps two
The body area draw-out area of heavy doping；Ion implanting is carried out in heavy doping n traps two to form the protection ring of the n-type heavy doping of annular to draw
Go out area, while the source electrode of n-type heavy doping is also formed in heavy doping p traps two, while n-type weight is also formed in heavy doping n traps one
The drain electrode of doping.
The n-type LDMOS device of the application high isolation can realize electric isolation, substrate and the guarantor between body area and substrate
The electric isolation between electric isolation, drain electrode and protection ring between retaining ring.
Brief description of the drawings
Fig. 1 is the structural representation one of existing n-type LDMOS device；
Fig. 2 is the connection relationship diagram of the high side circuitry of n-type MOS device；
Fig. 3 is the structural representation two of existing n-type LDMOS device；
Fig. 4 is the structural representation three of existing n-type LDMOS device；
Fig. 5 is the structural representation of the n-type LDMOS device of the application high isolation；
Fig. 6 a~Fig. 6 g are each step schematic diagrams of the manufacture method of the n-type LDMOS device of the application high isolation.
Description of reference numerals in figure：
100 be the silicon substrate that p-type is lightly doped（Or epitaxial layer）；101 be the drift region that n-type is lightly doped；110 be shielding oxidation
Layer；The 120 deep n traps to be lightly doped；131 be that p traps one are lightly doped；132 be that p traps two are lightly doped；140 be that n traps are lightly doped；150 are
Heavy doping n traps one；160 be silicon nitride；170~175 be isolation structure；180 be heavy doping n traps two；191 be heavy doping p traps one；
192 be heavy doping p traps two；200 be gate oxide；210 be polysilicon gate；221 be the substrate draw-out area of p-type heavy doping；222
For the protection ring draw-out area of n-type heavy doping；223 be the source electrode of n-type heavy doping；224 be the drain electrode of n-type heavy doping；225 be p-type
The body area draw-out area of heavy doping.
Embodiment
Referring to Fig. 5, this is the cross-sectional view of the n-type LDMOS device of the high isolation of the application.It is light in p-type
The silicon substrate of doping（Or epitaxial layer）There is the deep n traps 120 being lightly doped in 100, n traps 140 are lightly doped and p traps 1 are lightly doped.
Deep n traps 120 have maximum junction depth.If from depression angle, it is loop configuration that n traps 140, which are lightly doped, is enclosed in deep n traps 120
Outside, both contact with each other side.It is also loop configuration that p traps 1, which are lightly doped, is enclosed in the outside that n traps 140 are lightly doped,
Both also contact with each other side.Have in deep n traps 120 and p traps 2 132 are lightly doped.Have in p traps 2 132 are lightly doped heavily doped
Miscellaneous p traps 2 192 and heavy doping n trap 1.Heavy doping p traps 2 192 are also loop configuration, are enclosed in heavy doping n traps 1
Outside.The side for the part that heavy doping n traps 1 are located at the lower section of polysilicon gate 210 with heavy doping p traps 2 192 is in contact,
And do not contact with the side of the remainder of heavy doping p traps 2 192 and isolated by p traps 2 132 are lightly doped.Weight can so be improved
Adulterate the breakdown voltage of the PN junction between p traps 2 192 and heavy doping n traps 1.In the heavy doping p traps 2 192 of part and part
Heavy doping n traps 1 on there is gate oxide 200.Gate oxide 200 and close to portions of isolation structure 4 174 it
It is upper that there is polysilicon gate 210.The part that polysilicon gate 210 is located on isolation structure 4 174, which is higher than, is located at gate oxide
Part on 200.A part for polysilicon gate 210 be separated by gate oxide 200 part heavy doping p traps 2 192 just on
Side, another part are separated by gate oxide 200 or isolation structure 4 174 in the surface of part heavy doping n traps 1.Gently mixing
There is the heavy doping p traps 1 of annular in miscellaneous p traps 1.There is the p-type heavy doping lining of annular in heavy doping p traps 1
Bottom draw-out area 221.There is the heavy doping n traps 2 180 of annular in n traps 140 are lightly doped.There is ring in heavy doping n traps 2 180
The protection ring draw-out area 222 of the n-type heavy doping of shape.There is the source electrode 223 and annular of n-type heavy doping in heavy doping p traps 2 192
P-type heavy doping body area draw-out area 225.There is the drain electrode 224 of n-type heavy doping in heavy doping n traps 1.In silicon materials
Surface there are multiple isolation structures 171~175.The isolation structure 1 of annular is enclosed in the outside of substrate draw-out area 221.
The isolation structure 2 172 of annular is between substrate draw-out area 221 and protection ring draw-out area 222, for isolating both.Annular
Isolation structure 3 173 is located between protection ring draw-out area 222 and body area draw-out area 225, for isolating both.Isolation structure four
174 are located in heavy doping n traps 1, and between polysilicon gate 210 and drain electrode 224, for isolating both.Isolation junction
Structure 5 175 is between drain electrode 224 and body area draw-out area 225, for isolating both.
Wherein, heavy doping n traps 2 180, heavy doping p traps 1, the junction depth of heavy doping p traps 2 192 are roughly the same.And weigh
The junction depth of doping n traps 1 is more than former three.The doping concentration substantially phase of heavy doping p traps 1 and heavy doping p traps 2 192
Together.And the doping concentration of heavy doping n traps 1 is less than heavy doping n traps 2 180.Why there is the feature, be due to heavy doping
N traps 1 are to be formed before the formation of isolation structure 171~175 by ion implantation technology, and heavy doping n traps 2 180,
Heavy doping p traps 1, heavy doping p traps 2 192 are by ion implantation technology shape after the formation of isolation structure 171~175
Into.The manufacture of isolation structure 171~175 needs to pass through the long period in high temperature furnace, and this can make heavy doping n traps 1
Depth becomes big, doping concentration diminishes, while also the doping of heavy doping n traps 1 is more uniformly distributed, when LDMOS device works
Vicinity electric field can be optimized in off state, improve breakdown voltage.
The n-type LDMOS device of the high isolation of the application has the following advantages that：
First, the electric isolation between body area and substrate is realized, so as to applied to high side circuitry.Deep n traps 120 will be light
Doping p traps 2 132 are enclosed in the inside, it is achieved thereby that the heavy doping p traps 2 192 being lightly doped in p traps 2 132（Ji Ti areas）With lining
Electric isolation between bottom.
Second, realize the electric isolation between drain electrode and protection ring.P traps 2 132 are lightly doped by heavy doping n traps 1
The inside is enclosed in, it is achieved thereby that the electric isolation between the drain electrode 224 and deep n traps 120 in heavy doping n traps 1, also just real
Drain electrode 224 is showed and n traps 140 is lightly doped（That is protection ring）Between electric isolation.
Third, meet the application demand of drain electrode plus negative pressure.Heavy doping n traps 1 are the drift region of drain electrode 224.Due to
P traps 2 132 are lightly doped to keep apart itself and deep n traps 120, so drain electrode 224 can add negative pressure.The application can be in drain electrode 224
Add negative pressure, body area draw-out area 225 plus identical or smaller negative pressure, protection ring draw-out area 222 plus malleation, substrate draw-out area 221
Ground connection, LDMOS device also can in specific operating voltage range normal work.
Further, in the application, the junction depth of the deep n traps 120 is 8~10 μm, and its bulk concentration is 1 × 1015~2.5 ×
1015Atoms per cubic centimeter.The junction depth that p traps 2 132 are lightly doped is 4~4.5 μm, and its bulk concentration is 1 × 1016~2 × 1016It is former
Son is per cubic centimeter.The junction depth of heavy doping n traps 1 is 1.2~1.4 μm, and its bulk concentration is 6 × 1016~8 × 1016Atom is every
Cubic centimetre.As protection ring（Guard Ring）The junction depth that n traps 140 are lightly doped be 2.5~3 μm, its bulk concentration be 5 ×
1014~7 × 1014Atoms per cubic centimeter.
Each trap parameter can bring following bonus effect above：
Fourth, deep n traps 120 and the pressure-resistant 50V by Fig. 4 that the PN junction that p traps 2 132 are formed is lightly doped are brought up to
More than 100V；Simultaneously body area 192 can be avoided and when deep n traps 120 are added high pressure, substrate 100 is grounded, parasitic PNP tri- in device
Pole pipe（It is made up of p-type body area 192, deep n traps 120, p-substrate 100）Horizontal and vertical punchthrough issues occur.
Fifth, the pressure-resistant 50V by Fig. 4 for the PN junction that substrate 100 and deep n traps 120 are formed brings up to more than 100V；
It is based on RESURF simultaneously（Reduce surface field, Reduced SURfsce Field）Principle, p traps 1 are lightly doped by transverse direction
The interaction of p-type silicon substrate 100 with longitudinal direction makes n traps 140 are lightly doped before lateral junction reaches critical avalanche breakdown electric field all
Exhaust.Compared with deep n traps 120, the junction depth for being lightly doped n traps 140 is more shallow, bulk concentration is lighter, thus can thus apply
Higher voltage, the pressure-resistant of the PN junction formed by protection ring 140 and silicon substrate 100 can reach 100~200V.
In Fig. 4, because deep n traps 120 also serve as protection ring, if the bulk concentration of deep n traps 120 it is light to make enough deep n traps 120 with
The pressure-resistant junction depth that reaches more than 100V and keep deep n traps 120 of the PN junction formed between p-substrate 100 is constant, then device
The parasitic PNP triode of part（It is made up of p-type body area 192, deep n traps 120, p-substrate 100）Can be because of the deep n traps as base
120 too it is light be unable to ensure punch through voltage it is constant.Therefore, Fig. 4 can not meet simultaneously：Improve deep n traps 120 and p-substrate 100
Between formed PN junction it is pressure-resistant, improve parasitic PNP triode（By p-type body area 192, deep n traps 120, the structure of p-substrate 100
Into）Punch through voltage the two conflicting demands, limit the application of device operation voltage, and the structure of the application
Then solve this pair of demands simultaneously.
Sixth, the pressure-resistant 50V by Fig. 4 that the PN junction that p traps 2 132 and heavy doping n traps 1 are formed is lightly doped is carried
It is high to more than 100V；Body area 192 can be avoided simultaneously and when heavy doping n traps 1 connect negative pressure, deep n traps 120 connect high pressure, device
Middle parasitic NPN triode（By heavy doping n traps 1, n traps 2 132 are lightly doped, deep n traps 120 are formed）Generation is horizontal and vertical
Punchthrough issues.
Seventh, being based on RESURF principles, weight is made by the interaction of p traps 2 132 that is lightly doped in the body area 192 and longitudinal direction of transverse direction
Doping n traps 1 all exhaust before lateral junction reaches critical avalanche breakdown electric field, so as to by the breakdown of whole LDMOS device
Voltage brings up to more than 100V by the 50V in Fig. 4.
The manufacture method of the n-type LDMOS device of the high isolation of the application comprises the following steps：
1st step, Fig. 6 a are referred to, using thermal oxide growth technique in p-type silicon substrate（Or epitaxial layer）100 superficial growth
Go out one layer of screen oxide 110, then form the deep n traps being lightly doped in silicon substrate 100 using photoetching and ion implantation technology
120, finally carry out annealing process.
2nd step, Fig. 6 b are referred to, annular is formed in silicon substrate 100 using photoetching and ion implantation technology is lightly doped p
Trap 1, it is enclosed in the outside of deep n traps 120.Same step n-type impurity injection is also formed in deep n traps 120 is lightly doped p traps two
132, then carry out annealing process.
3rd step, Fig. 6 c are referred to, annular is formed in silicon substrate 100 using photoetching and ion implantation technology is lightly doped n
Trap 140, it is located at the inner side that p traps 1 are lightly doped, and is enclosed in the outside of deep n traps 120.Then annealing process is carried out.
4th step, Fig. 6 d are referred to, heavy doping n is formed in p traps 2 132 are lightly doped using photoetching and ion implantation technology
Trap 1, then carry out annealing process.
5th step, Fig. 6 e are referred to, first using chemical vapor deposition（CVD）Technique deposits one on screen oxide 110
Layer silicon nitride 160, then removed the silicon nitride 160 of subregion and screen oxide 110 and sudden and violent using photoetching and etching technics
Expose silicon materials.Then selective oxidation is used（LOCOS）Or shallow-trench isolation（STI）Technique is formed in the region for exposing silicon materials
Isolation structure 171~175.The isolation structure 1 of annular crosses over silicon substrate 100 and the line of demarcation of p traps 1 is lightly doped.Ring
The isolation structure 2 172 of shape, which is crossed over, to be lightly doped p traps 1 and the line of demarcation of n traps 140 is lightly doped.The isolation structure 3 173 of annular
Across n traps 140, deep n traps 120 and the line of demarcation that the three of p traps 2 132 is lightly doped is lightly doped.Isolation structure 4 174 is located at heavy doping
The surface of n traps 1.Isolation structure 5 175 crosses over heavy doping n traps 1 and the line of demarcation of p traps 2 132 is lightly doped.Then go
Except remaining silicon nitride 160, for example with wet corrosion technique.
6th step, Fig. 6 f are referred to, the heavily doped of annular is formed in n traps 140 are lightly doped using photoetching and ion implantation technology
Miscellaneous n traps 2 180.Form the heavy doping p traps one of annular in p traps 1 are lightly doped using photoetching and ion implantation technology again
191, same step n-type impurity injection also forms the heavy doping p traps 2 192 of annular in p traps 2 132 are lightly doped.In the step
Twi-lithography and ion implantation technology（It is n-type injection, p-type injection respectively）Order can be exchanged.Finally carry out annealing process.
7th step, Fig. 6 g are referred to, first anti-carved using dry method or wet corrosion technique removes all screen oxides 110, so
Thermal oxide growth technique is used afterwards in one layer of gate oxide 200 of superficial growth of silicon materials.Then chemical vapor deposition work is used
Skill deposits one layer of polysilicon 210 on gate oxide 200 and each isolation structure 171~175.Finally use photoetching and etching
Technique etches this layer of polysilicon 210 for polysilicon gate 210.A part for polysilicon gate 210 after etching is separated by grid oxygen
Change layer 200 in the surface of the heavy doping p traps 2 192 of part, another part is separated by gate oxide 200 or isolation structure 4 174
In the surface of the heavy doping n traps 1 of part.
8th step, referring to Fig. 5, first being anti-carved using dry method or wet corrosion technique is removed except the lower section of polysilicon gate 210
With the gate oxide 200 of exterior domain.Form the p-type of annular in heavy doping p traps 1 using photoetching and ion implantation technology again
The substrate draw-out area 221 of heavy doping, the p-type that same step n-type impurity injection also forms annular in heavy doping p traps 2 192 are heavily doped
Za Ti areas draw-out area 225.The n-type for forming annular in heavy doping n traps 2 180 using photoetching and ion implantation technology again is heavily doped
Miscellaneous protection ring draw-out area 222, same step p-type impurity injection also form the source electrode of n-type heavy doping in heavy doping p traps 2 192
223, same step p-type impurity injection also forms the drain electrode 224 of n-type heavy doping in heavy doping n traps 1.Two in the step
Secondary photoetching and ion implantation technology（It is p-type injection, n-type injection respectively）Order can be exchanged.Finally carry out annealing process.
The preferred embodiment of the application is these are only, is not used to limit the application.Come for those skilled in the art
Say, the application there can be various modifications and variations.All any modifications within spirit herein and principle, made, it is equal
Replace, improve etc., it should be included within the protection domain of the application.
Claims (5)
1. a kind of n-type LDMOS device, it is characterized in that, have in the silicon substrate or epitaxial layer that p-type is lightly doped be lightly doped deep n traps,
N traps are lightly doped and p traps one are lightly doped；The n traps that are lightly doped of annular are enclosed in the outside that deep n traps are lightly doped；P traps are lightly doped in annular
One is enclosed in the outside that n traps are lightly doped；
Have in deep n traps are lightly doped and p traps two are lightly doped；In p traps two are lightly doped have heavy doping n traps one and annular it is heavily doped
Miscellaneous p traps two；The body area draw-out area of the p-type heavy doping of source electrode and annular in heavy doping p traps two with n-type heavy doping；In weight
Adulterating has the drain electrode of n-type heavy doping in n traps one；Have on the heavy doping p traps two and partial heavy doping n traps one of part
Gate oxide；Gate oxide and close to portions of isolation structure four on there is polysilicon gate；
There is the heavy doping p traps one of annular in p traps one are lightly doped；There is the p-type heavy doping lining of annular in heavy doping p traps one
Bottom draw-out area；
There is the heavy doping n traps two of annular in n traps are lightly doped；There is the guarantor of the n-type heavy doping of annular in heavy doping n traps two
Retaining ring draw-out area；
There are multiple isolation structures on the surface of silicon materials；The isolation structure one of annular is enclosed in the outside of substrate draw-out area；Ring
The isolation structure two of shape is between substrate draw-out area and protection ring draw-out area；The isolation structure three of annular is located at protection ring extraction
Between area and body area draw-out area；Isolation structure four is located in heavy doping n traps one, and between polysilicon gate and drain electrode；Every
From structure five between drain electrode and body area draw-out area.
2. n-type LDMOS device according to claim 1, it is characterized in that, the depth of heavy doping n traps one is more than heavy doping n traps
2nd, heavy doping p traps one and heavy doping p traps two；The doping concentration of heavy doping n traps two is more than heavy doping n traps one.
3. n-type LDMOS device according to claim 1, it is characterized in that, the junction depth that deep n traps are lightly doped is 8~10 μm, body
Concentration is 1 × 1015~2.5 × 1015Atoms per cubic centimeter；Be lightly doped p traps two junction depth be 4~4.5 μm, bulk concentration be 1 ×
1016~2 × 1016Atoms per cubic centimeter；The junction depth of heavy doping n traps one is 1.2~1.4 μm, and bulk concentration is 6 × 1016~8 ×
1016Atoms per cubic centimeter；The junction depth that n traps are lightly doped is 2.5~3 μm, and bulk concentration is 5 × 1014~7 × 1014Every cube of atom
Centimetre.
4. n-type LDMOS device according to claim 1, it is characterized in that, deep n traps are lightly doped in the junction depth ratio that n traps are lightly doped
Shallow, the doping concentration ratios of n traps is lightly doped, and that deep n traps are lightly doped is small.
5. a kind of manufacture method of n-type LDMOS device, it is characterized in that, comprise the following steps：
1st step, go out one layer of screen oxide in the Film by Thermal Oxidation of p-type silicon substrate or epitaxial layer, then in a silicon substrate
Carry out ion implanting and deep n traps are lightly doped to be formed；
2nd step, carry out ion implanting in a silicon substrate to form annular is lightly doped p traps one, is enclosed in and the outer of deep n traps is lightly doped
Side；Formed simultaneously in deep n traps are lightly doped and p traps two are lightly doped；
3rd step, carry out ion implanting in a silicon substrate to form annular is lightly doped n traps, and it is positioned at being lightly doped the interior of p traps one
Side, and it is enclosed in the outside that deep n traps are lightly doped；
4th step, ion implanting is carried out in p traps two are lightly doped to form heavy doping n traps one；
5th step, one layer of silicon nitride is first deposited on screen oxide, then using selective oxidation or shallow grooved-isolation technique in silicon material
Material surface forms each isolation structure, then removes remaining silicon nitride；
6th step, ion implanting is carried out in n traps are lightly doped to form the heavy doping n traps two of annular；Enter in p traps one are lightly doped
Row ion implanting also forms annular heavy doping p traps two to form the heavy doping p traps one of annular in p traps two are lightly doped；
7th step, all screen oxides, then one layer of gate oxide of Film by Thermal Oxidation in silicon materials are first removed, is then existed
One layer of polysilicon is deposited on gate oxide and each isolation structure, finally etching is polysilicon gate；
8th step, first remove except below polysilicon gate with the gate oxide of exterior domain, then carry out in heavy doping p traps one from
Son injection forms the substrate draw-out area of the p-type heavy doping of annular, while the p-type for also forming in heavy doping p traps two annular is heavily doped
Za Ti areas draw-out area；Ion implanting is carried out in heavy doping n traps two to draw to form the protection ring of the n-type heavy doping of annular
Area, while also form in heavy doping p traps two source electrode of n-type heavy doping, while it is heavily doped in heavy doping n traps one also to form n-type
Miscellaneous drain electrode.
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