JP3721159B2 - Nonvolatile semiconductor memory device - Google Patents

Description

【００６７】
隣り合う２つのメモリセルで９つの記憶状態ができる。このうち８状態を用いて３ビット分のデータを記憶している。データ入出力線ＩＯＡ，ＩＯＢに出力された信号は、隣り合う偶数、奇数２カラム分の３値情報をもとに３ビットのデータにデータ入出力バッファ９で変換されて出力される。例えば、次の（表２）のように対応させる。
【００６８】
【表２】

【００６９】
図１４は、書き込み動作を示している。書き込み動作前に、入力された３ビット分のデータは、（表２）のようにデータ入出力バッファ９で２つの３値データに変換されて、隣り合う偶数、奇数カラムのデータ回路に入力される。３値データとデータ入出力線ＩＯＡ，ＩＯＢ、ノードＮ１，Ｎ２，Ｎ３の関係は、次の（表３）の通りである。
【００７０】
【表３】

【００７１】
変換された３値データは、カラム活性化信号ＣＥＮＢが“Ｈ”で、アドレス信号で指定されたカラム番地のデータ回路に転送される。
【００７２】
書き込み動作は、まず信号ＰＲＥが“Ｌ”となってビット線がフローティングにされる。
【００７３】
次に、信号ＢＬＣ２が“Ｈ”、電圧ＶＬＨが２．５Ｖ、ＶＬＬが０Ｖとされる。これによって、データ“０”が保持されているデータ回路からはＶcc、データ“１”が保持されているデータ回路からはＶＬＨ、データ“２”が保持されているデータ回路からはＶＬＬがビット線に出力される。ｎチャネルＭＯＳトランジスタＱn8，Ｑn9、高耐圧ｎチャネルＭＯＳトランジスタＨn33 のしきい値分の電圧降下分が問題になるときは、信号ＢＬＣ１，ＢＬＣ２，ＥＲＳＢを昇圧すればよい。
【００７４】
ワード線選択・駆動回路１１によって、選択されたブロックの選択ゲートＳＧ１、制御ゲートＣＧ１〜ＣＧ４がＶccとなる。選択ゲートＳＧ２は０Ｖである。次に、選択された制御ゲートＣＧ２が高電圧Ｖpp（例えば２０Ｖ）、非選択制御ゲートＣＧ１，ＣＧ３，ＣＧ４と選択ゲートＳＧ１がＶＭ（例えば１０Ｖ）となる。
【００７５】
データ“２”が保持されているデータ回路に対応するメモリセルでは、０Ｖのチャネル電位と制御ゲートのＶppの電位差によって、浮遊ゲートに電子が注入されしきい値が上昇する。データ“１”が保持されているデータ回路に対応するメモリセルでは、２．５Ｖのチャネル電位と制御ゲートのＶppの電位差によって、浮遊ゲートに電子が注入されしきい値が上昇する。チャネル電位を２．５Ｖにしているのは、“２”データ書き込みより電子の注入量が少なくてよいからである。データ“０”が保持されているデータ回路に対応するメモリセルでは、チャネル電位と制御ゲートのＶppの電位差が小さいため、実効的には浮遊ゲートに電子は注入されない。よって、メモリセルのしきい値は変動しない。
【００７６】
書き込み動作後、メモリセルのしきい値を検出する（書き込みベリファイ）。もし、所望のしきい値に達していれば、データ回路のデータを“０”に変更する。もし、所望のしきい値に達していなければ、データ回路のデータを保持して再度書き込み動作を行う。書き込み動作と書き込みベリファイは、全ての選択されたメモリセルが所望のしきい値に達するまで繰り返される。
【００７７】
図１５を用いて、この書き込みベリファイ動作を説明する。まず、電圧ＶＢＬＰが電源電圧Ｖcc（例えば５Ｖ）となって、ビット線は“Ｈ”レベルになる。信号ＰＲＥが“Ｌ”となって、ビット線はフローティング状態になる。続いて、電圧ＶＬＨがＶcc、電圧ＶＬＬが０Ｖとされ信号ＢＬＣ２が“Ｈ”となると、データ回路に“２”データが保持されされているデータ回路に対応するビット線ＢＬのみ０Ｖとされる。
【００７８】
次に、ワード線選択・駆動回路１１によって選択されたブロックの選択された制御ゲートＣＧ２は０．５Ｖ、非選択制御ゲートＣＧ１，ＣＧ３，ＣＧ４と選択ゲートＳＧ１，ＳＧ２はＶccにされる。選択されたメモリセルのしきい値が０．５Ｖ以下なら、ビット線電圧は“Ｌ”となる。選択されたメモリセルのしきい値が０．５Ｖ以上なら、ビット線電圧は“Ｈ”のままとなる。この後、信号ＳＥＮ１が“Ｈ”となる。もし、ビット線が“Ｌ”ならｎチャネルＭＯＳトランジスタＱn1は“ＯＦＦ”で、ノードＮ１は変わらない。もし、ビット線が“Ｈ”ならｎチャネルＭＯＳトランジスタＱn1は“ＯＮ”で、ノードＮ１は０Ｖの電圧ＶSRによって“Ｌ”とされる。つまり、ここまでの“１”データベリファイ動作で、“１”書き込みに成功したメモリセルに対応するデータ回路のデータが“１”である場合、“０”に変更される。その他のデータは変更されない。
【００７９】
続いて、電圧ＶＢＬＰが電源電圧Ｖcc（例えば５Ｖ）となって、ビット線は“Ｈ”レベルになる。次に、ワード線選択・駆動回路１１によって選択されたブロックの選択された制御ゲートＣＧ２は３Ｖ、非選択制御ゲートＣＧ１，ＣＧ３，ＣＧ４と選択ゲートＳＧ１，ＳＧ２はＶccにされる。選択されたメモリセルのしきい値が３Ｖ以下なら、ビット線電圧は“Ｌ”となる。選択されたメモリセルのしきい値が３Ｖ以上なら、ビット線電圧は“Ｈ”のままとなる。この後、信号ＳＥＮ１が“Ｈ”となる。もし、ビット線が“Ｌ”ならｎチャネルＭＯＳトランジスタＱn1は“ＯＦＦ”で、ノードＮ１は変わらない。もし、ビット線が“Ｈ”ならｎチャネルＭＯＳトランジスタＱn1は“ＯＮ”で、ノードＮ１は０Ｖの電圧ＶSRによって“Ｌ”とされる。つまり、ここまでの“２”データベリファイ動作で、“２”書き込みに成功したメモリセルに対応するデータ回路のデータが“２”である場合、“０”に変更される。その他のデータは変更されない。
【００８０】
全てのメモリセルが所望のしきい値に達すると、全てのデータ回路のノードＮ１は“Ｌ”となるので、全てのデータ回路のノードＮ１のレベルが“Ｌ”になるとデータのメモリセルへの書き込みは終了させられる。書き込みベリファイ時の、データ回路のデータ変換則は次の（表４）の通りである。
【００８１】
【表４】

【００８２】
図１４、１５で説明したように、ベリファイしながら書き込みを行うことで、“１”データに対応するメモリセルのしきい値はベリファイ参照電圧の０．５Ｖ以上で２Ｖ以下、“２”データに対応するメモリセルのしきい値はベリファイ参照電圧の３Ｖ以上でＶcc以下に制御される。図１３で説明したように、読み出し時の参照電圧は、０Ｖと２Ｖであるから、“１”データのしきい値マージンは０．５Ｖ、“２”データのしきい値マージンは１．０Ｖとされる。“０”データに対応するしきい値は０Ｖ以下であり、これは消去状態と同じである。消去は、セルウェルを高電圧Ｖpp（例えば２０Ｖ）にして、制御ゲートＣＧを０Ｖとして行われる。電子が浮遊ゲートから放出されしきい値は０Ｖ以下となる。
【００８３】
図２０は、図９中のセルウェル制御回路１２の具体的な構成を示している。高耐圧ｎチャネルＭＯＳトランジスタＨｎ17〜Ｈｎ28は昇圧回路を構成している。ポンプ活性化信号ＰＭＰが“Ｈ”で、振動する信号Φが入力されると、出力ＶqqはＶcc以上の高電圧となる。電圧Ｖqqは電圧リミッタ１６によってリミットされる。昇圧回路リセット信号ＲＳＴＢが“Ｌ”となると、ＶqqはＶccにリセットされる。デバイス待機信号ＳＴＮＢＹが“Ｈ”となると、昇圧回路への電源供給は遮断される。これは、電圧転送効率を上げるため、高耐圧ｎチャネルＭＯＳトランジスタＨｎのしきい値を下げると、待機時にリーク電流のため待機消費電力が大きいためである。昇圧されたＶqqは、信号ＣＷＰＭＰＢが“Ｌ”となると、高耐圧ｎチャネルＭＯＳトランジスタＨn10 ，Ｈn11 を介してセルウェルに印加される。
【００８４】
図２１を用いて、セルウェル制御回路１２の動作を説明する。待機時、信号ＳＴＮＢＹは“Ｈ”である。信号ＲＳＴＢ，ＣＷＰＭＰＢも“Ｈ”、ＰＭＰとΦは“Ｌ”である。よって、セルウェルは０Ｖとなっている。
【００８５】
非待機時で消去時以外は、信号ＳＴＮＢＹ，ＲＳＴＢ，ＰＭＰは“Ｌ”、ＣＷＰＭＰＢは“Ｈ”である。信号Φは振動する。電圧ＶqqはＶccとなり、セルウェルは０Ｖである。
【００８６】
消去時には、信号ＲＳＴＢ，ＰＭＰが“Ｈ”となって電圧ＶqqはＶppに昇圧される。続いて、信号ＣＷＰＭＰＢが“Ｌ”となるとセルウェルはＶppとなる。ＣＷＰＭＰＢが“Ｈ”となってセルウェルは０Ｖにリセットされ、信号ＲＳＴＢ，ＰＭＰが“Ｌ”となってＶqqはＶccにリセットされる。
【００８７】
（第２の実施形態）
図２２は、図９、１１に見られるデータ回路８の他の実施形態を示す具体的な構成図である。３値記憶を例に構成されている。図２２（ａ）に示すように、クロック同期式インバータＣＩ１，ＣＩ２とＣＩ３，ＣＩ４でそれぞれ構成される２つのフリップ・フロップＦＦ１，ＦＦ２に、書き込み／読み出しデータをラッチする。また、これらはセンスアンプとしても動作する。クロック同期式インバータＣＩの具体的な構成は、図２２（ｂ）に示される。クロック同期式インバータＣＩの回路しきい値は、例えば電源電圧Ｖcc（例えば５Ｖ）の半分とする。
【００８８】
フリップ・フロップＦＦ１は、「“０”書き込みをするか、“１”又は“２”書き込みをするか」を書き込みデータ情報としてラッチし、メモリセルが「“０”の情報を保持しているか、“１”又は“２”の情報を保持しているか」を読み出しデータ情報としてセンスしラッチする。フリップ・フロップＦＦ２は、「“２”書き込みをするか、“１”又は“０”書き込みをするか」を書き込みデータ情報としてラッチし、メモリセルが「“２”の情報を保持しているか、“１”又は“０”の情報を保持しているか」を読み出しデータ情報としてセンスしラッチする。
【００８９】
データ入出力線ＩＯＡ，ＩＯＢとフリップ・フロップＦＦ１は、ｎチャネルＭＯＳトランジスタＱn101，Ｑn102を介して接続される。データ入出力線ＩＯＣ，ＩＯＤとフリップ・フロップＦＦ２は、ｎチャネルＭＯＳトランジスタＱn103，Ｑn104を介して接続される。データ入出力線ＩＯＡ，ＩＯＢ，ＩＯＣ，ＩＯＤは、図９中のデータ入出力バッファ９にも接続される。ｎチャネルＭＯＳトランジスタＱn101，Ｑn102，Ｑn103，Ｑn104のゲートは、ＮＡＮＤ論理回路Ｇ１０１とインバータＩ１０１で構成されるカラムアドレスデコーダの出力に接続される。ｎチャネルＭＯＳトランジスタＱn105，Ｑn109は、フリップ・フロップＦＦ１，ＦＦ２とＭＯＳキャパシタＱd101の接続を制御する。ｎチャネルＭＯＳトランジスタＱn106，Ｑn107，Ｑn108、ｐチャネルＭＯＳトランジスタＱp102，Ｑp103で構成される回路は、活性化信号ＶＲＦＹＢ或いはＰＲＯによって、フリップ・フロップＦＦ１，ＦＦ２のデータに応じて、ＭＯＳキャパシタＱd101のゲート電圧を変更する。ＭＯＳキャパシタＱd101は、ディプリーション型ｎチャネルＭＯＳトランジスタで構成され、ビット線容量より十分小さくされる。ｐチャネルＭＯＳトランジスタＱp105は、信号ＰＲＥＣによってＭＯＳキャパシタＱd101を充電する。全てのデータ回路８-0，８-1，…，８-mの書き込みデータが“０”書き込みか否かを検出信号ＰＥＮＤに出力するため、フリップ・フロップＦＦ１のデータを検出するｐチャネルＭＯＳトランジスタＱp101が設けられる。
【００９０】
ｎチャネルＭＯＳトランジスタＱn110、ｐチャネルＭＯＳトランジスタＱp104は、信号ＢＬＣＮ，ＢＬＣＰによって、データ回路８とビット線ＢＬの接続を制御する。ｎチャネルＭＯＳトランジスタＱn111は、信号ＰＲＥが“Ｈ”となって、ビット線ＢＬを電圧ＶBLP にする。高耐圧ｎチャネルＭＯＳトランジスタＨn101は、消去時にビット線に印加される高電圧がデータ回路に印加されるのを防ぐためのもので、消去時以外は信号ERSBは“Ｈ”である。
【００９１】
次に、このように構成されたＥＥＰＲＯＭの動作を、図２３、２４、２５に従って説明する。図２３は読み出し時のタイミング、図２４は書き込み時のタイミング、図２５は書き込みベリファイ時のタイミング、をそれぞれ示している。
【００９２】
図２３に従って、読み出し動作を説明する。まず、電圧ＶＢＬＰが電源電圧Ｖcc（例えば５Ｖ）となって、ビット線は“Ｈ”レベルになる。同時に、信号ＢＬＣＮが“Ｌ”、ＢＬＣＰが“Ｈ”となって、ビット線とＭＯＳキャパシタＱd101は切り離される。信号ＰＲＥが“Ｌ”となって、ビット線はフローティング状態になる。続いて、ワード線選択・駆動回路１１によって選択されたブロックの選択された制御ゲートＣＧ２は０Ｖ、非選択制御ゲートＣＧ１，ＣＧ３，ＣＧ４と選択ゲートＳＧ１，ＳＧ２はＶccにされる。信号ＰＲＥＣが“Ｌ”となってＭＯＳキャパシタＱd101はＶccに充電される。
【００９３】
選択されたメモリセルのしきい値が０Ｖ以下なら、ビット線電圧は“Ｌ”となる。選択されたメモリセルのしきい値が０Ｖ以上なら、ビット線電圧は“Ｈ”のままとなる。この後、信号ＢＬＣＮが例えばＶcc以下の１．５Ｖとされる。ｎチャネルＭＯＳトランジスタＱｎ110 のしきい値が１Ｖの場合、もしビット線が０．５Ｖ以下ならｎチャネルＭＯＳトランジスタＱn110は“ＯＮ”で、ノードＮ１０１は０．５Ｖ以下となる。もし、ビット線が０．５Ｖ以上ならｎチャネルＭＯＳトランジスタＱn110は“ＯＦＦ”で、ノードＮ１０１はＶccに保たれる。
【００９４】
再度、信号ＢＬＣＮが“Ｌ”となって、ビット線ＢＬとＭＯＳキャパシタＱd101は切り離される。信号ＬＡＴ１，ＳＥＮ１が“Ｌ”となってフリップ・フロップＦＦ１が非活性化された後、信号ＳＡＣ１が“Ｈ”となる。再度、信号ＳＥＮ１が“Ｈ”となり続いて信号ＬＡＴ１が“Ｈ”となることで、ノードＮ１０１の電圧がセンスされラッチされる。これで、メモリセルのデータが“０”か否かがフリップ・フロップＦＦ１によってセンスされ、その情報はラッチされる。
【００９５】
次に、選択された制御ゲートが２Ｖにされる。選択されたメモリセルのしきい値が２Ｖ以下なら、ビット線電圧は“Ｌ”となる。選択されたメモリセルのしきい値が２Ｖ以上なら、ビット線電圧は“Ｈ”のままとなる。この後、信号ＢＬＣＮが例えばＶcc以下の１．５Ｖとされる。ｎチャネルＭＯＳトランジスタＱn110のしきい値が１Ｖの場合、もしビット線が０．５Ｖ以下ならｎチャネルＭＯＳトランジスタＱn110は“ＯＮ”で、ノードＮ１０１は０．５Ｖ以下となる。もし、ビット線が０．５Ｖ以上ならｎチャネルＭＯＳトランジスタＱn110は“ＯＦＦ”で、ノードＮ１０１はＶccに保たれる。
【００９６】
再度、信号ＢＬＣＮが“Ｌ”となって、ビット線ＢＬとＭＯＳキャパシタＱd101は切り離される。信号ＬＡＴ２，ＳＥＮ２が“Ｌ”となってフリップ・フロップＦＦ２が非活性化された後、信号ＳＡＣ２が“Ｈ”となる。再度、信号ＳＥＮ２が“Ｈ”となり続いて信号ＬＡＴ２が“Ｈ”となることで、ノードＮ１０１の電圧がセンスされラッチされる。これで、メモリセルのデータが“２”か否かがフリップ・フロップＦＦ２によってセンスされ、その情報はラッチされる。
【００９７】
読み出し中、信号ERSBは“Ｈ”、ＶＲＦＹＢは“Ｈ”、ＰＲＯは“Ｌ”である。また、電圧ＶＢＬＭとＶｓは０Ｖとする。
【００９８】
カラムアドレスデコーダに入力されるカラム活性化信号ＣＥＮＢが“Ｈ”となると、アドレス信号によって選択されたデータ回路に保持されているデータがデータ入出力線ＩＯＡ，ＩＯＢ，ＩＯＣ，ＩＯＤに出力され、データ入出力バッファ９を介してＥＥＰＲＯＭ外部へ出力される。
【００９９】
メモリセルに記憶されているデータ、しきい値、データ入出力線ＩＯＡ，ＩＯＢ，ＩＯＣ，ＩＯＤに読み出し後に出力されるレベル、の関係は次の（表５）の通りである。
【０１００】
【表５】

【０１０１】
隣り合う２つのメモリセルで９つの記憶状態ができる。このうち８状態を用いて３ビット分のデータを記憶している。データ入出力線ＩＯＡ，ＩＯＢ，ＩＯＣ，ＩＯＤに出力された信号は、隣り合う偶数、奇数２カラム分の３値情報をもとに３ビットのデータにデータ入出力バッファ９で変換されて出力される。例えば、前記（表２）のように対応させる。
【０１０２】
図２４は、書き込み動作を示している。書き込み動作前に、入力された３ビット分のデータは、前記（表２）のようにデータ入出力バッファ９で２つの３値データに変換されて、隣り合う偶数、奇数カラムのデータ回路８に入力される。３値データとデータ入出力線ＩＯＡ，ＩＯＢ，ＩＯＣ，ＩＯＤの関係は、次の（表６）の通りである。
【０１０３】
【表６】

【０１０４】
変換された３値データは、カラム活性化信号ＣＥＮＢが“Ｈ”で、アドレス信号で指定されたカラム番地のデータ回路に転送される。
【０１０５】
書き込み動作は、まず信号ＰＲＥが“Ｌ”となってビット線がフローティングにされる。
【０１０６】
次に、信号ＶＲＦＹＢが“Ｌ”、信号ＰＲＯが“Ｈ”、電圧ＶＢＬＭが２．５Ｖとされる。これによって、データ“０”が保持されているデータ回路からはＶcc、データ“１”が保持されているデータ回路からは２．５Ｖがビット線に出力される。信号ＳＡＣ２が１．５Ｖとされると、データ“２”が保持されているデータ回路からは０Ｖがビット線に出力される。ｎチャネルＭＯＳトランジスタＱ109 のしきい値を１Ｖとすると、“０”又は“１”書き込み時にはｎチャネルＭＯＳトランジスタＱn109は“ＯＦＦ”、“２”書き込み時には“ＯＮ”となる。高耐圧ｎチャネルＭＯＳトランジスタＨn101のしきい値分の電圧降下分が問題になるときは、信号ＥＲＳＢを昇圧すればよい。
【０１０７】
ワード線選択・駆動回路１１によって、選択されたブロックの選択ゲートＳＧ１、制御ゲートＣＧ１〜ＣＧ４がＶccとなる。選択ゲートＳＧ２は０Ｖである。次に、選択された制御ゲートＣＧ２が高電圧Ｖpp（例えば２０Ｖ）、非選択制御ゲートＣＧ１，ＣＧ３，ＣＧ４がＶＭ（例えば１０Ｖ）となる。データ“２”が保持されているデータ回路に対応するメモリセルでは、０Ｖのチャネル電位と制御ゲートのＶppの電位差によって、浮遊ゲートに電子が注入されしきい値が上昇する。データ“１”が保持されているデータ回路に対応するメモリセルでは、２．５Ｖのチャネル電位と制御ゲートのＶppの電位差によって、浮遊ゲートに電子が注入されしきい値が上昇する。チャネル電位を２．５Ｖにしているのは、“２”データ書き込みより電子の注入量が少なくてよいからである。
【０１０８】
データ“０”が保持されているデータ回路に対応するメモリセルでは、チャネル電位と制御ゲートのＶppの電位差が小さいため、実効的には浮遊ゲートに電子は注入されない。よって、メモリセルのしきい値は変動しない。書き込み中、信号ＳＥＮ１，ＬＡＴ１，ＳＥＮ２，ＬＡＴ２は“Ｈ”、信号ＳＡＣ１は“Ｌ”、信号ＰＲＥＣは“Ｈ”、信号ＢＬＣＮ，ＢＬＣＰはそれぞれ“Ｈ”，“Ｌ”、信号ＥＲＳＢは“Ｈ”である。
【０１０９】
書き込み動作後、メモリセルのしきい値を検出する（書き込みベリファイ）。もし、所望のしきい値に達していれば、データ回路のデータを“０”に変更する。もし、所望のしきい値に達していなければ、データ回路のデータを保持して再度書き込み動作を行う。書き込み動作と書き込みベリファイは全ての選択されたメモリセルが所望のしきい値に達するまで繰り返される。
【０１１０】
図２５を用いて、この書き込みベリファイ動作を説明する。まず、電圧ＶＢＬＰが電源電圧Ｖcc（例えば５Ｖ）となって、ビット線は“Ｈ”レベルになる。同時に、信号ＢＬＣＮが“Ｌ”、ＢＬＣＰが“Ｈ”となって、ビット線とＭＯＳキャパシタＱd101は切り離される。信号ＰＲＥが“Ｌ”となって、ビット線はフローティング状態になる。続いて、ワード線選択・駆動回路１１によって選択されたブロックの選択された制御ゲートＣＧ２は０．５Ｖ、非選択制御ゲートＣＧ１，ＣＧ３，ＣＧ４と選択ゲートＳＧ１，ＳＧ２はＶccにされる。信号ＰＲＥＣが“Ｌ”となってＭＯＳキャパシタＱd101はＶccに充電される。
【０１１１】
選択されたメモリセルのしきい値が０．５Ｖ以下なら、ビット線電圧は“Ｌ”となる。選択されたメモリセルのしきい値が０．５Ｖ以上なら、ビット線電圧は“Ｈ”のままとなる。この後、信号ＢＬＣＮが例えばＶcc以下の１．５Ｖとされる。ｎチャネルＭＯＳトランジスタＱｎ110 のしきい値が１Ｖの場合、もしビット線が０．５Ｖ以下ならｎチャネルＭＯＳトランジスタＱn110は“ＯＮ”で、ノードＮ１０１は０．５Ｖ以下となる。もし、ビット線が０．５Ｖ以上ならｎチャネルＭＯＳトランジスタＱn110は“ＯＦＦ”で、ノードＮ１０１はＶccに保たれる。
【０１１２】
再度、信号ＢＬＣＮが“Ｌ”となって、ビット線ＢＬとＭＯＳキャパシタＱd101は切り離される。信号ＶＲＦＹＢが“Ｌ”となると、“０”書き込みデータが保持されているデータ回路のみ、ｐチャネルＭＯＳトランジスタＱp103が“ＯＮ”であり、ノードＮ１０１はＶccとなる。信号ＳＡＣ２が１．５Ｖとなると、“２”書き込みデータが保持されているデータ回路のみ、ノードＮ１０１が０Ｖにされる。“１”書き込みデータが保持されているデータ回路では、０．５Ｖ以上のノードＮ１０１の電圧は変化しない。０．５Ｖ以下のノードＮ１の電圧は０．５Ｖまでは充電される。信号ＬＡＴ１，ＳＥＮ１が“Ｌ”となってフリップ・フロップＦＦ１が非活性化された後、信号ＳＡＣ１が“Ｈ”となる。再度、信号ＳＥＮ１が“Ｈ”となり続いて信号ＬＡＴ１が“Ｈ”となることで、ノードＮ１０１の電圧がセンスされラッチされる。
【０１１３】
これで、“１”書き込みデータを保持しているデータ回路のみ、対応するメモリセルのデータが十分“１”書き込み状態となったか否かを検出する。メモリセルのデータが“１”であれば、フリップ・フロップＦＦ１でノードＮ１０１の電圧をセンスしラッチすることで書き込みデータは“０”に変更される。メモリセルのデータが“１”でなければ、フリップ・フロップＦＦ１でノードＮ１０１の電圧をセンスしラッチすることで書き込みデータは“１”に保持される。“０”又は“２”書き込みデータを保持しているデータ回路の書き込みデータは変更されない。
【０１１４】
次に、選択された制御ゲートが３Ｖにされる。選択されたメモリセルのしきい値が３Ｖ以下なら、ビット線電圧は“Ｌ”となる。選択されたメモリセルのしきい値が３Ｖ以上なら、ビット線電圧は“Ｈ”のままとなる。この後、信号ＢＬＣＮが例えばＶcc以下の１．５Ｖとされる。ｎチャネルＭＯＳトランジスタＱn110のしきい値が１Ｖの場合、もしビット線が０．５Ｖ以下ならｎチャネルＭＯＳトランジスタＱn110は“ＯＮ”で、ノードＮ１０１は０．５Ｖ以下となる。もし、ビット線が０．５Ｖ以上ならｎチャネルＭＯＳトランジスタＱn110は“ＯＦＦ”で、ノードＮ１０１はＶccに保たれる。
【０１１５】
再度、信号ＢＬＣＮが“Ｌ”となって、ビット線ＢＬとＭＯＳキャパシタＱd101は切り離される。信号ＶＲＦＹＢが“Ｌ”となると、“０”書き込みデータが保持されているデータ回路のみ、ｐチャネルＭＯＳトランジスタＱp103が“ＯＮ”であり、ノードＮ１０１はＶccとなる。信号ＬＡＴ１，ＳＥＮ１が“Ｌ”となってフリップ・フロップＦＦ１が非活性化された後、信号ＳＡＣ１が“Ｈ”となる。再度、信号ＳＥＮ１が“Ｈ”となり続いて信号ＬＡＴ１が“Ｈ”となることで、ノードＮ１０１の電圧がセンスされラッチされる。
【０１１６】
続いて、信号ＰＲＯが“Ｈ”、電圧ＶＢＬＭがＶccとなる。“１”書き込みデータを保持しているデータ回路のみで、そのノードＮ１０１は“Ｈ”に変更される。信号ＬＡＴ２，ＳＥＮ２が“Ｌ”となってフリップ・フロップＦＦ２が非活性化された後、信号ＳＡＣ２が“Ｈ”となる。再度、信号ＳＥＮ２が“Ｈ”となり続いて信号ＬＡＴ２が“Ｈ”となることで、ノードＮ１０１の電圧がセンスされラッチされる。
【０１１７】
これで、“２”書き込みデータを保持しているデータ回路のみ、対応するメモリセルのデータが十分“２”書き込み状態となったか否かを検出する。メモリセルのデータが“２”であれば、フリップ・フロップＦＦ１，ＦＦ２でノードＮ１０１の電圧をセンスしラッチすることで書き込みデータは“０”に変更される。メモリセルのデータが“２”でなければ、フリップ・フロップＦＦ１，ＦＦ２でノードＮ１０１の電圧をセンスしラッチすることで書き込みデータは“２”に保持される。“０”又は“１”書き込みデータを保持しているデータ回路の書き込みデータは変更されない。
【０１１８】
書き込みベリファイ中、信号ERSBは“Ｈ”、電圧Ｖｓは０Ｖとする。
【０１１９】
全ての選択されたメモリセルが所望のしきい値に達したか否かは、信号ＰＥＮＤを検出することで分る。全ての選択されたメモリセルが所望のしきい値に達していれば、書き込みデータが全て“０”となり、個々のデータ回路８-0，８-1，…，８-mのデータ検出用ｐチャネルＭＯＳトランジスタＱp101が全て“ＯＦＦ”となる。電源電圧Ｖccから信号線ＰＥＮＤが切り離されたか否かを検出すると、全ての選択されたメモリセルが所望のしきい値に達したか否かが分る。書き込みベリファイ時の、データ回路のデータ変換則は前記（表４）の通りである。
【０１２０】
図２４、２５で説明したように、ベリファイしながら書き込みを行うことで、“１”データに対応するメモリセルのしきい値はベリファイ参照電圧の０．５Ｖ以上で２Ｖ以下、“２”データに対応するメモリセルのしきい値はベリファイ参照電圧の３Ｖ以上でＶcc以下に制御される。図２３で説明したように、読み出し時の参照電圧は、０Ｖと２Ｖであるから、“１”データのしきい値マージンは０．５Ｖ、“２”データのしきい値マージンは１．０Ｖとされる。“０”データに対応するしきい値は０Ｖ以下である。これは消去状態と同じである。
【０１２１】
（変形例）
なお、本発明は上述した各実施形態に限定されるものではない。実施形態ではＥＥＰＲＯＭを例に説明したが、本発明はＥＰＲＯＭでも同様に実施できる。また、ＮＡＮＤ型メモリセルを用いて説明したが、種々様々なメモリセルでも同様に実施できる。
【０１２２】
ＮＡＮＤ型メモリセルを用いた説明では、読み出し時の参照電位と書き込みベリファイ時の参照電位を制御することでしきい値マージンを確保した。セル電流マージンを確保する場合は、読み出し参照電流とベリファイ時の参照電流を制御することで実施できる。また、実施形態では３値或いは４値記憶を例に説明したが、何値でも同様に実施できる。その他、本発明の要旨を逸脱しない範囲で、種々変形して実施することができる。
【０１２３】
【発明の効果】
以上詳述したように本発明によれば、多値記憶可能なメモリセルにおいて、一時記憶のためのｎ値記憶データ回路をｎ−１個の入力端子を有するｎ個の論理回路で構成することにより、メモリセル以外の制御回路面積の増大を抑えることができる。また、これに加えて、電荷量マージンを電荷量が多いほど多く設定することにより、書き込み時間や書き込み電圧の増加を抑えつつ、信頼性の高いＥＥＰＲＯＭを実現することが可能となる。
【図面の簡単な説明】
【図１】第１の実施形態におけるメモリセルの構成を示す断面図。
【図２】第１の実施形態におけるメモリセルのデータ保持特性を示す図。
【図３】従来のメモリセルのしきい値分布を示す図。
【図４】第１の実施形態におけるメモリセルのしきい値分布を示す図。
【図５】第１の実施形態におけるメモリセルのセル電流分布を示す図。
【図６】第１の実施形態におけるメモリセルのデータ保持特性を示す図。
【図７】第１の実施形態におけるメモリセルのしきい値分布を示す図。
【図８】第１の実施形態におけるメモリセルのセル電流分布を示す図。
【図９】第１の実施形態に係わるＥＥＰＲＯＭの構成を示すブロック図。
【図１０】第１の実施形態におけるＥＥＰＲＯＭの構造を示す断面図。
【図１１】第１の実施形態におけるメモリセルアレイの回路構成を示す図。
【図１２】第１の実施形態におけるデータ回路の具体的な構成を示す図。
【図１３】第１の実施形態におけるデータ読み出し動作を示すタイミング図。
【図１４】第１の実施形態におけるデータ書き込み動作を示すタイミング図。
【図１５】第１の実施形態における書き込みベリファイ動作を示すタイミング図。
【図１６】第１の実施形態における多値記憶データラッチ回路の変形例を示す図。
【図１７】従来のデータラッチ回路を示す図。
【図１８】従来のデータラッチ回路の構成を示す図。
【図１９】第１の実施形態における多値記憶データラッチ回路の構成を示す図。
【図２０】第１の実施形態におけるセルウェル制御回路の具体的な構成を示す図。
【図２１】第１の実施形態におけるセルウェル制御回路の動作を示すタイミング図。
【図２２】第２の実施形態におけるデータ回路の具体的な構成を示す図。
【図２３】第２の実施形態におけるデータ読み出し動作を示すタイミング図。
【図２４】第２の実施形態におけるデータ書き込み動作を示すタイミング図。
【図２５】第２の実施形態における書き込みベリファイ動作を示すタイミング図。
【符号の説明】
１…ｐ型半導体基板
２…ｎ型拡散層
３…絶縁膜
４…浮遊ゲート（電荷蓄積層）
５…ゲート絶縁膜
６…制御ゲート
７…メモリセルアレイ
８…データ回路
９…データ入出力バッファ
１０…アドレスバッファ
１１…ワード線選択・駆動回路
１２…セルウェル制御回路
１３…ｐ型半導体基板
１４…ｎ型ウェル
１５…ｐ型ウェル
１６…電圧リミッタ
Ｍ…メモリセル
ＳＧ…選択ゲート
ＣＧ…制御ゲート
ＢＬ…ビット線
Ｑｎ…ｎチャネルＭＯＳトランジスタ
Ｑｐ…ｐチャネルＭＯＳトランジスタ
Ｈｎ…高耐圧ｎチャネルＭＯＳトランジスタ
Ｑｄ…ディプリーション型ｎチャネルＭＯＳトランジスタ
ＣＩ…クロック同期式インバータ
ＦＦ…フリップ・フロップ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electrically rewritable nonvolatile semiconductor memory device (EEPROM), and more particularly to an EEPROM that performs multi-value storage in which more than one bit of information is stored in one memory cell.
[0002]
[Prior art]
As one of EEPROM memory cells, one having a MOSFET structure in which a charge storage layer and a control gate are stacked on a semiconductor substrate is known. Normally, data “0” or “1” is stored according to the amount of charge stored in the charge storage layer, and 1-bit data is stored in one cell. On the other hand, in order to realize a higher-density EEPROM, a multi-value storage system that stores data for multiple bits in one cell is also known. For example, in the four-value storage system, data “0”, “1”, “2”, and “3” are stored in one cell, so that four charge amounts corresponding to the data are stored in the charge storage layer.
[0003]
An example of a data storage state will be described by taking a four-value system as an example. A state in which the charge amount of the charge storage layer is 0 is defined as a neutral state, and a state in which positive charges are accumulated from the neutral state is defined as an erased state. Further, the erase state is made to correspond to the data “0”. For example, erasing is performed by applying a high voltage (˜20V) to the substrate and setting the control gate to 0V. A state in which negative charges are accumulated from the neutral state is defined as a data “1” state. The state of data “2” is also a state in which a negative charge is stored as compared with the neutral state, but the negative charge amount is made larger than the negative charge amount of the data “1” state. In the state of data “3”, the negative charge amount is further increased. For example, negative charges are stored in the charge storage layer by setting the substrate, source and drain to 0 V, and the control gate to a high voltage (˜20 V).
[0004]
Generally, EEPROM data retention is guaranteed for 10 years. The charge stored in the charge storage layer leaks although it is very small. In order to prevent the data “0”, “1”, “2”, and “3” from being indistinguishable due to this leak, usually, the charge amount corresponding to each data is set discretely. The difference in charge amount is called a charge amount margin.
[0005]
However, if the charge margin is too small, it cannot be guaranteed for 10 years. On the other hand, when the charge amount margin is increased, for example, the charge amount corresponding to the data “3” must be increased. For this reason, the writing time becomes longer or the writing voltage becomes higher. Further, since the leak charge amount increases as the stored charge amount increases, there is a problem that the data guarantee time does not increase as the charge amount margin increases.
[0006]
As one of the EEPROMs, one that writes a plurality of bytes of data at once is known. This is for shortening the writing time, and is provided with a data circuit for temporarily storing data for a plurality of bytes. When multi-value storage is performed with such an EEPROM, the data circuit must also be capable of multi-value storage. For this reason, there has been a problem that the circuit area of the data circuit becomes large.
[0007]
[Problems to be solved by the invention]
As described above, the multi-value storage method is an effective means for increasing the density, but there is a problem that the reliability of data guarantee is lowered. In addition, there is a problem that a control circuit such as a data circuit other than the memory cell becomes large.
[0008]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a multi-value storage type EEPROM capable of suppressing an increase in control circuit area other than memory cells.
[0009]
[Means for Solving the Problems]
(Constitution)
In order to solve the above problems, the present invention adopts the following configuration.
[0010]
That is, according to the present invention (Claim 1), in a nonvolatile semiconductor memory device capable of storing multi-value (n (≧ 3) value) data, a memory cell having a charge storage portion and data for temporarily storing write data The data circuit is composed of n logic circuits having n-1 input terminals. Further, in the n logic circuits having the n-1 input terminals, each output terminal is connected to one input terminal among n-1 input terminals of each of the other n-1 logic circuits. The data circuit is configured by being connected to each other.
[0011]
According to the present invention (claim 2), in a non-volatile semiconductor memory device capable of storing multi-value (n (≧ 3) value) data, a memory cell having a charge storage portion and data stored in the memory cell are stored. A sense circuit for reading and a data circuit for temporarily storing data read by the sense circuit are provided, and the sense circuit includes n-1 switch circuits that are turned on / off according to the value of the read data. The data circuit is composed of n logic circuits having n-1 input terminals. Further, the n-1 switch circuits constitute a sense circuit by connecting in series a first MOS transistor to which a different sense signal is input and a second MOS transistor to which the read data is input, The n logic circuits having the n-1 input terminals are connected to one input terminal among the n-1 input terminals of each of the other n-1 logic circuits. A data circuit is configured by being connected.
[0012]
According to the present invention (Claim 5), in a non-volatile semiconductor memory device capable of storing multi-value (n (≧ 3) value) data, a memory cell array comprising a plurality of memory cells having a charge storage portion, and a plurality of memory cell arrays Bit lines, a plurality of word lines, and a plurality of program control circuits, wherein the plurality of program control circuits hold 1) write control data for determining a write voltage applied to each of the corresponding memory cells, 2) According to the held write control data, the write voltage is simultaneously applied to the corresponding memory cells, 3) the write state of the memory cells is detected, and 4) only the memory cells that are insufficiently written are determined in advance. The write state of the memory cell and the write control so that the write voltage is applied to set the write state. The program control circuit is selectively changed according to a predetermined logical relationship from the data, and each program control circuit includes a data circuit for holding the write control data. To do.
[0013]
Further, preferred embodiments of the present invention include the following.
[0014]
(1) The data circuit is composed of n logic circuits having n−1 input terminals.
[0015]
(2) In the n logic circuits having n−1 input terminals, each output terminal is connected to one input terminal among the n−1 input terminals of each of the other n−1 logic circuits. The data circuits are connected to each other.
[0016]
(3) Each program control circuit includes a sense circuit for changing write control data held in the data circuit in accordance with a bit line signal.
[0017]
(4) Each program control circuit includes n-1 sense circuits for changing data held in the data circuit in accordance with a bit line signal.
[0018]
(5) The sense circuit is composed of n-1 switch circuits that are turned on / off in accordance with a bit line signal.
[0019]
According to another aspect of the present invention, there is provided a non-volatile semiconductor memory device capable of storing multi-value (n (≧ 3) value) data, a memory cell array including a plurality of memory cells having a charge storage portion, and a plurality of memory cell arrays. Bit lines, a plurality of word lines, a plurality of program control circuits, and a plurality of data circuits,
The plurality of program control circuits 1) select the memory cell, 2) apply a write voltage to the selected memory cell, and the plurality of data circuits correspond respectively to 1) selected by the program control circuit. Holds the first, second,..., N logic level write control data for controlling the write control voltage applied to the memory cell, and 2) applies the write control voltage to the corresponding memory cell, 3) selectively detecting only a write state of the memory cell corresponding to the data circuit holding the write control data of a logic level other than the first, and 4) a memory cell that has reached a predetermined write state 5) changing the logic level of the write control data of the data circuit corresponding to the first logic level to 5) 6) holding the logic level of the write control data of the data circuit corresponding to the memory cell that has not reached the read state; 6) the write control data of the data circuit holding the write control data of the first logic level The logic level is maintained at the first logic level.
[0020]
Further, preferred embodiments of the present invention include the following.
[0021]
(1) Each data circuit includes a data holding circuit composed of n logic circuits having n−1 input terminals.
[0022]
(2) In n logic circuits having n-1 input terminals, each output terminal is connected to one input terminal among n-1 input terminals of each of the other n-1 logic circuits. Connected to form a data holding circuit.
[0023]
(3) Each data circuit includes a sense circuit for changing the logic level of the write control data held in the data circuit in accordance with the bit line signal.
[0024]
(4) Each data circuit includes n-1 sense circuits for changing the logic level of data held in the data circuit in accordance with a bit line signal.
[0025]
(5) The sense circuit is composed of n-1 switch circuits that are turned on / off in accordance with a bit line signal.
[0026]
The present invention also provides a memory cell array including a plurality of memory cells having charge storage portions capable of storing multi-value (n (≧ 3) value) data, a plurality of bit lines, a plurality of word lines, and a plurality of A plurality of program control circuits, 1) each holding a write control data for determining a write voltage applied to the corresponding memory cell, and 2) each corresponding according to the held write control data. The write voltage is applied to the memory cells at the same time, 3) the write state of the memory cells is detected, and 4) the write voltage is applied so that only the memory cells with insufficient write are in a predetermined write state. In accordance with a predetermined logical relationship from the write state of the memory cell and the write control data Each of the program control circuits includes a data circuit for holding the write control data, and each of the program control circuits further includes the data according to a signal of the bit line. A non-volatile semiconductor memory device comprising a sense circuit for changing the write control data held in a circuit.
[0027]
Furthermore, the present invention provides a memory cell array including a plurality of memory cells having a charge storage portion capable of storing multi-value (n (≧ 3) value) data, a plurality of bit lines, a plurality of word lines, and a plurality of A plurality of program control circuits, 1) each holding a write control data for determining a write voltage applied to the corresponding memory cell, and 2) each corresponding according to the held write control data. The write voltage is applied to the memory cells at the same time, 3) the write state of the memory cells is detected, and 4) the write voltage is applied so that only the memory cells with insufficient write are in a predetermined write state. As described above, the data is stored in accordance with a logical relationship determined in advance from the write state of the memory cell and the write control data. Each of the program control circuits includes a data circuit for holding the write control data, and each of the program control circuits further includes the data according to a signal of the bit line. A non-volatile semiconductor memory device comprising n-1 sense circuits for changing data held in a circuit.
[0028]
Here, the data circuit is composed of n logic circuits having n-1 input terminals. Further, in the n logic circuits having the n-1 input terminals, each output terminal is connected to one input terminal among the n-1 input terminals of each of the other n-1 logic circuits. The data circuits are connected to each other.
[0029]
The present invention also provides a memory cell array including a plurality of memory cells having charge storage portions capable of storing multi-value (n (≧ 3) value) data, a plurality of bit lines, a plurality of word lines, and a plurality of A program control circuit and a plurality of data circuits, the plurality of program control circuits 1) select the memory cell, 2) apply a write voltage to the selected memory cell, and the plurality of data circuits 1) Holds write control data of the first, second,..., N logic levels for controlling the write control voltages applied to the corresponding memory cells selected by the program control circuit, and 2) the write control. A voltage is applied to the corresponding memory cell, and 3) the data circuit corresponding to the data circuit holding write control data of a logic level other than the first. Only the write state of the memory cell is selectively detected. 4) The logic level of the write control data of the data circuit corresponding to the memory cell that has reached the predetermined write state is changed to the first logic level. A) holding a logic level of the write control data of the data circuit corresponding to a memory cell that has not reached a predetermined write state; and 6) the data holding the write control data of the first logic level. The logic level of the write control data of the circuit is held at the first logic level, and each of the data circuits further changes the logic level of the write control data held in the data circuit according to the signal of the bit line. A non-volatile semiconductor memory device characterized by comprising a sense circuit.
[0030]
Furthermore, the present invention provides a memory cell array including a plurality of memory cells having a charge storage portion capable of storing multi-value (n (≧ 3) value) data, a plurality of bit lines, a plurality of word lines, and a plurality of A program control circuit and a plurality of data circuits, the plurality of program control circuits 1) select the memory cell, 2) apply a write voltage to the selected memory cell, and the plurality of data circuits 1) Holds write control data of the first, second,..., N logic levels for controlling the write control voltages applied to the corresponding memory cells selected by the program control circuit, and 2) the write control. A voltage is applied to the corresponding memory cell, and 3) before the data circuit holding the write control data of a logic level other than the first. Selectively detecting only the write state of the memory cell; 4) changing the logic level of the write control data of the data circuit corresponding to the memory cell that has reached a predetermined write state to the first logic level; 5) Holds the logic level of the write control data of the data circuit corresponding to the memory cell that has not reached the predetermined write state, and 6) Holds the write control data of the first logic level. The logic level of the write control data of the data circuit is held at the first logic level, and each of the data circuits further changes the logic level of the data held in the data circuit according to the signal of the bit line. A non-volatile semiconductor memory device comprising n-1 sense circuits.
[0031]
Here, each of the data circuits includes a data holding circuit including n logic circuits having n−1 input terminals. Further, in the n logic circuits having the n-1 input terminals, each output terminal is connected to one input terminal among the n-1 input terminals of each of the other n-1 logic circuits. The data holding circuits are connected to each other.
[0032]
(Function)
The EEPROM capable of storing multi-value (n (≧ 3) value) data according to the present invention stores n-value data corresponding to n charge amounts stored in the charge storage layer of the memory cell. The n-value storage data circuit for temporarily storing n-value write data is configured by n logic circuits having n−1 input terminals, thereby reducing the control circuit area.
[0033]
Also, n charge amounts are set discretely, and a charge amount margin, which is a difference between the charge amounts, is set to increase as the charge amount increases. Accordingly, the maximum charge amount can be reduced by reducing the charge amount margin for the data corresponding to the relatively small charge amount while ensuring the reliability of the data corresponding to the relatively large charge amount. Therefore, it is possible to realize a highly reliable EEPROM while suppressing an increase in writing time and writing voltage.
[0034]
DETAILED DESCRIPTION OF THE INVENTION
The details of the present invention will be described below with reference to the illustrated embodiments.
[0035]
(First embodiment)
FIG. 1 shows the structure of the memory cell M in the first embodiment of the present invention. A floating gate (charge storage layer) 4 is formed on a p-type semiconductor substrate (or p-type well) 1 via a tunnel insulating film 3, and a control gate 6 is formed thereon via a gate insulating film 5. An n-type diffusion layer 2 is formed on the surface of the substrate 1 as a source / drain. Data is stored in the memory cell M by controlling the amount of charge accumulated in the floating gate 4.
[0036]
For example, data is stored as follows. When the substrate voltage Vsub, the source voltage Vs and the drain voltage Vd are set to a high voltage Vpp (for example, 20 V) and the control gate voltage VCG is set to 0 V, charges move through the insulating film 3 and positive charges are accumulated in the floating gate 4. Is done. This state is made to correspond to the state of data “0”. When the control gate voltage VCG is set to the high voltage Vpp (for example, 20 V), the substrate voltage Vsub, the source voltage Vs, and the drain voltage Vd are set to 0 V from the data “0” state, negative charges are accumulated in the floating gate 4. Data “1”, “2”, and “3” are stored by controlling the negative charge amount in three regions. The threshold value Vt of the memory cell changes depending on the amount of charge of the floating gate 4, and data is actually read by detecting the value of Vt.
[0037]
The electric charge stored in the floating gate 4 leaks over a long time. FIG. 2 shows an example of a change with time of the threshold value Vt of the memory cell M. The threshold value (neutral threshold value) when the charge amount of the floating gate 4 is 0 is Ve. The threshold value Vt increases as the negative charge increases, and three values V1, V2, and V3 (V1 <V2 <V3) are shown as initial values of the threshold value Vt of the memory cell. The leakage of the charge stored in the floating gate 4 stops when the charge amount becomes zero. Therefore, V1, V2, and V3 gradually approach Ve with the standing time. Further, the higher the threshold value, the faster the speed dV / dt approaching Ve. This is because the amount of leakage increases as the amount of charge increases. For example, the amount of change in the threshold value after standing for 10 years is ΔV1 <ΔV2 <ΔV3.
[0038]
FIG. 3 shows the relationship between the threshold value of the memory cell and data. In an EEPROM having a plurality of memory cells, it is difficult to control the threshold values of all the memory cells to the same value. Therefore, in general, a threshold value corresponding to certain data has a certain threshold distribution width. . In FIG. 3, the threshold value corresponding to the data “0” is set to Vr1 or less. Here, it is set to be equal to or less than the neutral threshold Ve and the charge amount of the floating gate is positive. The threshold value corresponding to the data “1” is not less than Vr1 and not more than Vr2. The threshold value corresponding to data “2” is Vr2 or more and Vr3 or less, and the threshold value corresponding to data “3” is Vr3 or more. Here, Ve <Vr1 is satisfied, and the data corresponds to data “3”, “2”, and “1” in descending order of the negative charge amount of the floating gate. The voltages Vr1, Vr2, and Vr3 are called reference voltages. Data is read from the threshold value of the memory cell and the reference voltage.
[0039]
A margin of ΔV is provided between the minimum threshold value corresponding to data “1” and Vr1. This is because when the threshold value corresponding to the data “1” approaches Ve with the standing time and becomes Vr1 or less, the data “1” becomes data “0”, so that the data holding period of the memory cell is lengthened. Similarly, a margin of ΔV is also provided between the minimum threshold value corresponding to data “2” or “3” and Vr2 or Vr3.
[0040]
As described with reference to FIG. 2, as the charge of the floating gate increases, the amount of change with time of the threshold increases. Therefore, in the example shown in FIG. 3, the time until the data “1” becomes “0” is exceeded. The time until the data “2” becomes “1” is shorter, and the time until the data “3” becomes “2” is shorter. This is because the threshold margin ΔV for holding each data is constant.
[0041]
FIG. 4 shows the relationship between the threshold value of the memory cell and the data in the present invention. A margin of ΔV1 is provided between the minimum threshold value corresponding to data “1” and Vr1. A margin of ΔV2 is provided between the minimum threshold value corresponding to data “2” and Vr2. A margin of ΔV3 is provided between the minimum threshold value corresponding to data “3” and Vr3. Here, ΔV1 <ΔV2 <ΔV3. Most ideally, the time required for the data to change from “1” to “0”, “2” to “1”, and “3” to “2” is equal. By setting ΔV1 <ΔV2 <ΔV3, for example, it is not necessary to provide an extra threshold margin ΔV1 for holding data “1”.
[0042]
Thus, by reducing the threshold margin for data with a small change in the corresponding threshold over time, the threshold corresponding to each data can be lowered. Therefore, the amount of charge stored in the floating gate can be reduced, and the writing time can be shortened or the writing voltage can be lowered.
[0043]
In FIG. 4, the neutral threshold value Ve is equal to or lower than the reference voltage Vr1, but for example, consider a case where Ve is located between Vr1 and Vr2. When ΔV2 <ΔV3, the time required for changing from data “2” to data “1” and the time required for changing from data “3” to data “2” can be made substantially equal. Data “1” is not garbled. Therefore, ΔV1 <ΔV2 <ΔV3 is set.
[0044]
As a method of detecting a threshold value of a memory cell and reading data, there is a method of sensing whether a current flows between a drain and a source by applying a reference voltage to a control gate. In this case, voltage stress is applied to the memory cell by applying a reference voltage to the control gate. In some cases, the data may be corrupted by this stress.
[0045]
In FIG. 4, when Vr1 <Vr2 <Vr3 <0V, a negative voltage is applied to the control gate at the time of reading, and if the substrate, source and drain are 0V or a positive potential, the threshold is negative due to this stress. It changes in the direction of. When the threshold change rate due to this voltage stress is more prominent than the rate at which the threshold value of the memory cell gradually approaches the neutral threshold value Ve with the standing time, Ve is Vr3 as well as when Ve is Vr1 or less. Even if it is larger, ΔV1 <ΔV2 <ΔV3 is set. When Ve> Vr3, the threshold value corresponding to the data “1” is lower than the threshold value corresponding to the data “2”, and the positive charge stored in the floating gate is large. Therefore, for the voltage stress as described above, the threshold change rate corresponding to the data “1” is slower than the threshold change rate corresponding to the data “2”. Similarly, the threshold change rate corresponding to data “2” is slower than the threshold change rate corresponding to data “3”.
[0046]
A large threshold margin means a large charge margin. In an actual memory device, in addition to the threshold value of the memory cell, there is a case where correspondence is made by a current flowing through the memory cell (hereinafter referred to as a cell current). For example, a certain voltage is applied to the control gate, and the cell current flowing from the drain to the source is detected. In an n-channel type memory cell, the cell current decreases as the threshold value increases.
[0047]
FIG. 5 shows the relationship between cell current and data in the memory cell. Let Neu be the neutral cell current when the amount of charge stored in the floating gate is zero. A margin of ΔI1 is provided between the maximum value of the cell current corresponding to data “1” and the reference current Ir1. A margin of ΔI2 is provided between the maximum value of the cell current corresponding to the data “2” and the reference current Ir2. A margin of ΔI3 is provided between the maximum value of the cell current corresponding to the data “3” and the reference current Ir3. ΔI1 <ΔI2 <ΔI3. Most ideally, the time required for the data to change from “1” to “0”, “2” to “1”, and “3” to “2” is equal. By setting ΔI1 <ΔI2 <ΔI3, for example, there is no need to provide an extra cell current margin ΔI1 for holding data “1”.
[0048]
As described above, the cell current margin corresponding to each data can be increased by reducing the cell current margin for the data whose corresponding cell current change is small. Therefore, the amount of charge stored in the floating gate can be reduced, and the writing time can be shortened or the writing voltage can be lowered.
[0049]
FIG. 6 shows the change with time of the threshold when positive charges are stored in the floating gate. The greater the positive charge amount, the lower the threshold and the greater the rate of change with time. In FIG. 7, contrary to FIG. 4, data “0”, “1”, “2”, and “3” are set in descending order of the threshold value. Therefore, ΔV1 <ΔV2 <ΔV3. In FIG. 8, the data “0”, “1”, “2”, and “3” are set in ascending order of the cell current, corresponding to FIG. Therefore, ΔI1 <ΔI2 <ΔI3.
[0050]
As described with reference to FIGS. 2, 4, 5 and FIGS. 6, 7, and 8, in order to prevent the stored information from being changed due to various causes, the charge amount margin or threshold stored in the floating gate is prevented. By setting the value margin or cell current margin for each data, the amount of charge stored in the floating gate can be reduced. Accordingly, the writing time can be shortened or the writing voltage can be lowered. Whether the margin is ensured by the charge amount, the threshold value, or the cell current depends on the control circuit of the memory device.
[0051]
Although an n-channel memory cell has been described as an example here, a p-channel memory cell can be similarly implemented.
[0052]
FIG. 9 shows a basic configuration of a multi-value storage type EEPROM constituted by using the memory cell M shown in FIG. Here, a ternary memory type is shown as an example. A word line selection / drive circuit 11 that selects a memory cell and applies a write voltage and a read voltage to a control gate is provided for a memory cell array 7 configured by arranging memory cells M in a matrix. The word line selection / drive circuit 11 is connected to the address buffer 10 and receives an address signal. The data circuit 8 is a circuit for temporarily holding write data and reading data from memory cells. Data circuit 8 is connected to data input / output buffer 9 and receives an address signal from address buffer 10.
[0053]
The data input / output buffer 9 performs data input / output control with the outside of the EEPROM. The memory cell array 7 is formed on the p-type well 15 in the n-type well 14 formed in the p-type substrate 13 as seen in FIG. A cell well control circuit 12 for controlling the voltage of the n-type well 14 and the p-type well 15 is provided.
[0054]
FIG. 11 shows a specific configuration of the memory cell array 7 and a data circuit 8 connected thereto. Memory cells M1 to M4 are connected in series to form a NAND type cell. Both ends thereof are connected to the bit line BL and the source line Vs through selection transistors S1 and S2, respectively. A group of memory cells sharing the control gate CG forms a unit called “page” and is written / read simultaneously. A block is formed by a group of memory cells connected to the four control gates CG1 to CG4. “Page” and “block” are selected by the word line selection / drive circuit 11. Data circuits 8-0 to 8-m are connected to the bit lines BL0 to BLm to temporarily store write data to the corresponding memory cells.
[0055]
FIG. 12 shows a specific configuration of the data circuit 8 seen in FIGS. The NAND logic circuits G1, G2, and G3 constitute a multi-value data latch circuit. Of the nodes N1, N2 and N3, only one is at the “L” level, and the other two are at the “H” level. The ternary data is latched depending on which of the three nodes is at the “L” level.
[0056]
If four 3-input NAND logic circuits are used and their outputs are input to the other three NAND logic circuits and connected to each other, quaternary data can be latched. In general, when n (n-1) input NAND logic circuits are used and their outputs are input to other (n-1) NAND logic circuits and connected to each other, n-value data can be latched. In addition to the NAND logic circuit, a circuit such as a NOR logic circuit as shown in FIG. 16 may be used. In FIG. 16, only one of the three nodes N4, N5 and N6 is at the “H” level.
[0057]
FIG. 17 shows a conventional data latch circuit that latches ternary data with two of a 1-bit data latch circuit composed of inverters I2 and I3 and a 1-bit data latch circuit composed of I4 and I5. . The configuration of the data latch circuit of FIG. 17 is shown in FIG. 18, and the configuration of the multilevel data latch circuit formed of NAND logic circuits G1, G2, and G3 is shown in FIG. The number of wires wired from the p-channel MOS region to the n-channel MOS region is four in the data latch circuit of FIG. 17, but is three in the multi-value data latch circuit composed of NAND logic circuits G1, G2, and G3. It is a book. An advantage of the multi-value data latch circuit composed of NAND logic circuits G1, G2, and G3 is that the circuit area can be reduced by such a small number of wirings.
[0058]
In FIG. 12, the data input / output lines IOA and IOB and the multi-value data latch circuit are connected via n-channel MOS transistors Qn11 and Qn12. Data input / output lines IOA and IOB are also connected to data input / output buffer 9 in FIG. The gates of n-channel MOS transistors Qn11 and Qn12 are connected to the output of a column address decoder composed of NAND logic circuit G4 and inverter I1. In the circuit composed of the n-channel MOS transistors Qn1, Qn2, or Qn3, Qn4, the activation signal SEN1 or SEN2 becomes “H”, respectively, and the data of the multi-value data latch circuit is changed by sensing the bit line voltage. To do.
[0059]
In the circuit constituted by the n-channel MOS transistors Qn5, Qn6, Qn7, Qn8 and the p-channel MOS transistor Qp1, the bit line voltage at the time of writing is changed according to the data of the multilevel data latch circuit because the signal BLC2 becomes “H”. To control. In the n-channel MOS transistor Qn9, the signal BLC1 becomes “H” and connects the data circuit 8 and the bit line BL. In the n-channel MOS transistor Qn10, the signal PRE becomes “H”, and the bit line BL is set to the voltage VBLP. The high breakdown voltage n-channel MOS transistor Hn33 is for preventing a high voltage applied to the bit line BL during erasing from being applied to the data circuit, and the signal ERSB is "H" except during erasing.
[0060]
Next, the operation of the thus configured EEPROM will be described with reference to FIGS. FIG. 13 shows the timing at the time of reading, FIG. 14 shows the timing at the time of writing, and FIG. 15 shows the timing at the time of writing verification.
[0061]
A read operation will be described with reference to FIG. First, the voltage VBLP becomes the power supply voltage Vcc (for example, 5 V), and the bit line becomes “H” level. At the same time, the voltage VSR becomes Vcc, the signals SEN1 and SEN2 become "H", the nodes N1 and N3 are reset to "H", and the node N2 is reset to "L". The signal PRE becomes “L”, and the bit line enters a floating state. Subsequently, the selected control gate CG2 of the block selected by the word line selection / drive circuit 11 is set to 0V, and the non-selection control gates CG1, CG3, CG4 and the selection gates SG1, SG2 are set to Vcc.
[0062]
If the threshold value of the selected memory cell is 0 V or less, the bit line voltage becomes “L”. If the threshold value of the selected memory cell is 0 V or higher, the bit line voltage remains “H”. Thereafter, the signal SEN1 becomes “H”. If the bit line is "L", the n-channel MOS transistor Qn1 is "OFF" and the node N1 remains "H". If the bit line is “H”, the n-channel MOS transistor Qn1 is “ON” and the node N1 is set to “L” by the voltage VSR of 0V.
[0063]
Next, the selected control gate is set to 2V. If the threshold value of the selected memory cell is 2V or less, the bit line voltage becomes “L”. If the threshold value of the selected memory cell is 2 V or more, the bit line voltage remains “H”. Thereafter, the signal SEN2 becomes “H”. If the bit line is “L”, the n-channel MOS transistor Qn3 is “OFF” and the node N3 remains “H”. If the bit line is “H”, the n-channel MOS transistor Qn3 is “ON”, and the node N3 is set to “L” by the voltage VSR of 0V.
[0064]
Finally, when the column activation signal CENB input to the column address decoder becomes “H”, the data held in the data circuit selected by the address signal is output to the data input / output lines IOA and IOB, and the data input The data is output outside the EEPROM via the output buffer 9.
[0065]
The relationship between the data stored in the memory cell, the threshold value, and the read nodes N1, N2, and N3 is as follows (Table 1).
[0066]
[Table 1]

[0067]
Nine memory states can be formed by two adjacent memory cells. Of these, 3 bits of data are stored using 8 states. The signals output to the data input / output lines IOA and IOB are converted into 3-bit data by the data input / output buffer 9 based on the ternary information for the adjacent even and odd two columns and output. For example, the following correspondence is made (Table 2).
[0068]
[Table 2]

[0069]
FIG. 14 shows a write operation. Prior to the write operation, the input 3-bit data is converted into two ternary data by the data input / output buffer 9 as shown in (Table 2), and input to the adjacent even and odd column data circuits. The The relationship between the ternary data, the data input / output lines IOA and IOB, and the nodes N1, N2 and N3 is as follows (Table 3).
[0070]
[Table 3]

[0071]
The converted ternary data is transferred to the data circuit at the column address designated by the address signal when the column activation signal CENB is “H”.
[0072]
In the write operation, first, the signal PRE becomes “L” and the bit line is floated.
[0073]
Next, the signal BLC2 is set to “H”, the voltage VLH is set to 2.5V, and the VLL is set to 0V. As a result, Vcc from the data circuit holding data “0”, VLH from the data circuit holding data “1”, and VLL from the data circuit holding data “2” are bit lines. Is output. When the voltage drop corresponding to the threshold value of the n-channel MOS transistors Qn8 and Qn9 and the high breakdown voltage n-channel MOS transistor Hn33 becomes a problem, the signals BLC1, BLC2 and ERSB may be boosted.
[0074]
The selection gate SG1 and the control gates CG1 to CG4 of the block selected by the word line selection / drive circuit 11 become Vcc. The selection gate SG2 is 0V. Next, the selected control gate CG2 becomes the high voltage Vpp (for example, 20V), and the non-selection control gates CG1, CG3, CG4 and the selection gate SG1 become VM (for example, 10V).
[0075]
In the memory cell corresponding to the data circuit holding data “2”, electrons are injected into the floating gate due to the potential difference between the channel potential of 0 V and the Vpp of the control gate, and the threshold value rises. In the memory cell corresponding to the data circuit holding data “1”, electrons are injected into the floating gate due to the potential difference between the channel potential of 2.5 V and the Vpp of the control gate, and the threshold value rises. The reason why the channel potential is set to 2.5 V is that the injection amount of electrons may be smaller than that of “2” data writing. In the memory cell corresponding to the data circuit holding data “0”, the potential difference between the channel potential and Vpp of the control gate is small, so that electrons are not effectively injected into the floating gate. Therefore, the threshold value of the memory cell does not change.
[0076]
After the write operation, the threshold value of the memory cell is detected (write verify). If the desired threshold value is reached, the data in the data circuit is changed to “0”. If the desired threshold value has not been reached, the data in the data circuit is held and the write operation is performed again. The write operation and write verify are repeated until all selected memory cells reach a desired threshold value.
[0077]
The write verify operation will be described with reference to FIG. First, the voltage VBLP becomes the power supply voltage Vcc (for example, 5 V), and the bit line becomes “H” level. The signal PRE becomes “L”, and the bit line enters a floating state. Subsequently, when the voltage VLH is Vcc, the voltage VLL is 0 V, and the signal BLC2 is “H”, only the bit line BL corresponding to the data circuit in which “2” data is held in the data circuit is set to 0 V.
[0078]
Next, the selected control gate CG2 of the block selected by the word line selection / drive circuit 11 is set to 0.5 V, and the non-selection control gates CG1, CG3, and CG4 and the selection gates SG1 and SG2 are set to Vcc. If the threshold value of the selected memory cell is 0.5 V or less, the bit line voltage becomes “L”. If the threshold value of the selected memory cell is 0.5 V or higher, the bit line voltage remains “H”. Thereafter, the signal SEN1 becomes “H”. If the bit line is "L", the n-channel MOS transistor Qn1 is "OFF" and the node N1 does not change. If the bit line is “H”, the n-channel MOS transistor Qn1 is “ON” and the node N1 is set to “L” by the voltage VSR of 0V. That is, if the data in the data circuit corresponding to the memory cell successfully written “1” is “1” in the “1” data verify operation so far, it is changed to “0”. Other data is not changed.
[0079]
Subsequently, the voltage VBLP becomes the power supply voltage Vcc (for example, 5 V), and the bit line becomes the “H” level. Next, the selected control gate CG2 of the block selected by the word line selection / drive circuit 11 is set to 3V, and the non-selection control gates CG1, CG3, CG4 and the selection gates SG1, SG2 are set to Vcc. If the threshold value of the selected memory cell is 3 V or less, the bit line voltage becomes “L”. If the threshold value of the selected memory cell is 3V or more, the bit line voltage remains “H”. Thereafter, the signal SEN1 becomes “H”. If the bit line is "L", the n-channel MOS transistor Qn1 is "OFF" and the node N1 does not change. If the bit line is “H”, the n-channel MOS transistor Qn1 is “ON” and the node N1 is set to “L” by the voltage VSR of 0V. That is, if the data in the data circuit corresponding to the memory cell successfully written to “2” is “2” in the “2” data verify operation so far, it is changed to “0”. Other data is not changed.
[0080]
When all the memory cells reach the desired threshold value, the node N1 of all the data circuits becomes “L”. Therefore, when the level of the node N1 of all the data circuits becomes “L”, the data is transferred to the memory cell. Writing is terminated. The data conversion rule of the data circuit at the time of write verification is as follows (Table 4).
[0081]
[Table 4]

[0082]
As described with reference to FIGS. 14 and 15, by performing writing while verifying, the threshold value of the memory cell corresponding to “1” data is 0.5 V or more of the verify reference voltage, 2 V or less, and “2” data. The threshold value of the corresponding memory cell is controlled to 3 V or more of the verify reference voltage and Vcc or less. As described with reference to FIG. 13, since the reference voltages at the time of reading are 0 V and 2 V, the threshold margin of “1” data is 0.5 V, and the threshold margin of “2” data is 1.0 V. Is done. The threshold value corresponding to “0” data is 0 V or less, which is the same as in the erased state. Erase is performed by setting the cell well to the high voltage Vpp (for example, 20 V) and the control gate CG to 0 V. Electrons are emitted from the floating gate and the threshold value becomes 0V or less.
[0083]
FIG. 20 shows a specific configuration of the cell well control circuit 12 in FIG. High breakdown voltage n-channel MOS transistors Hn17 to Hn28 constitute a booster circuit. When the pump activation signal PMP is “H” and the oscillating signal Φ is input, the output Vqq becomes a high voltage equal to or higher than Vcc. The voltage Vqq is limited by the voltage limiter 16. When the booster circuit reset signal RSTB becomes “L”, Vqq is reset to Vcc. When the device standby signal STNBY becomes “H”, the power supply to the booster circuit is cut off. This is because if the threshold voltage of the high-breakdown-voltage n-channel MOS transistor Hn is lowered in order to increase the voltage transfer efficiency, standby power consumption is large due to leakage current during standby. The boosted Vqq is applied to the cell well via the high breakdown voltage n-channel MOS transistors Hn10 and Hn11 when the signal CWPMPB becomes "L".
[0084]
The operation of the cell well control circuit 12 will be described with reference to FIG. During standby, the signal STNBY is “H”. The signals RSTB and CWPMPB are also “H”, and PMP and Φ are “L”. Therefore, the cell well is 0V.
[0085]
The signals STNBY, RSTB, and PMP are “L” and CWPMPB is “H” except when not erasing and non-standby. The signal Φ vibrates. The voltage Vqq is Vcc and the cell well is 0V.
[0086]
At the time of erasing, the signals RSTB and PMP become “H” and the voltage Vqq is boosted to Vpp. Subsequently, when the signal CWPMPB becomes “L”, the cell well becomes Vpp. CWPMPB becomes “H” and the cell well is reset to 0V, and signals RSTB and PMP become “L” and Vqq is reset to Vcc.
[0087]
(Second Embodiment)
FIG. 22 is a specific block diagram showing another embodiment of the data circuit 8 seen in FIGS. A ternary storage is used as an example. As shown in FIG. 22 (a), write / read data is latched in two flip-flops FF1 and FF2 each composed of clock synchronous inverters CI1 and CI2 and CI3 and CI4. These also operate as sense amplifiers. A specific configuration of the clock synchronous inverter CI is shown in FIG. The circuit threshold value of the clock synchronous inverter CI is, for example, half of the power supply voltage Vcc (for example, 5V).
[0088]
The flip-flop FF1 latches “whether“ 0 ”is written,“ 1 ”or“ 2 ”is written” ”as write data information, and whether the memory cell holds“ 0 ”information, Whether “1” or “2” information is held ”is sensed and latched as read data information. The flip-flop FF2 latches “whether“ 2 ”is written,“ 1 ”or“ 0 ”is written” ”as write data information, and whether the memory cell holds“ 2 ”information, Whether “1” or “0” information is retained ”is sensed as read data information and latched.
[0089]
Data input / output lines IOA and IOB and flip-flop FF1 are connected via n-channel MOS transistors Qn101 and Qn102. Data input / output lines IOC, IOD and flip-flop FF2 are connected via n-channel MOS transistors Qn103, Qn104. Data input / output lines IOA, IOB, IOC, IOD are also connected to data input / output buffer 9 in FIG. The gates of n-channel MOS transistors Qn101, Qn102, Qn103, Qn104 are connected to the output of a column address decoder composed of NAND logic circuit G101 and inverter I101. N-channel MOS transistors Qn105 and Qn109 control the connection between flip-flops FF1 and FF2 and MOS capacitor Qd101. The circuit constituted by the n-channel MOS transistors Qn106, Qn107, Qn108 and the p-channel MOS transistors Qp102, Qp103 is activated by the activation signal VRFYB or PRO in accordance with the data of the flip-flops FF1, FF2, and the gate voltage of the MOS capacitor Qd101. To change. MOS capacitor Qd101 is formed of a depletion type n-channel MOS transistor, and is made sufficiently smaller than the bit line capacitance. The p-channel MOS transistor Qp105 charges the MOS capacitor Qd101 with the signal PREC. A p-channel MOS transistor for detecting the data of the flip-flop FF1 in order to output to the detection signal PEND whether or not the write data of all the data circuits 8-0, 8-1,. Qp101 is provided.
[0090]
N-channel MOS transistor Qn110 and p-channel MOS transistor Qp104 control connection between data circuit 8 and bit line BL by signals BLCN and BLCP. In the n-channel MOS transistor Qn111, the signal PRE becomes “H” to set the bit line BL to the voltage VBLP. The high breakdown voltage n-channel MOS transistor Hn101 is for preventing the high voltage applied to the bit line during erasing from being applied to the data circuit, and the signal ERSB is "H" except during erasing.
[0091]
Next, the operation of the thus configured EEPROM will be described with reference to FIGS. FIG. 23 shows the timing at the time of reading, FIG. 24 shows the timing at the time of writing, and FIG. 25 shows the timing at the time of writing verification.
[0092]
A read operation will be described with reference to FIG. First, the voltage VBLP becomes the power supply voltage Vcc (for example, 5 V), and the bit line becomes “H” level. At the same time, the signal BLCN becomes “L” and BLCP becomes “H”, and the bit line and the MOS capacitor Qd101 are disconnected. The signal PRE becomes “L”, and the bit line enters a floating state. Subsequently, the selected control gate CG2 of the block selected by the word line selection / drive circuit 11 is set to 0V, and the non-selection control gates CG1, CG3, CG4 and the selection gates SG1, SG2 are set to Vcc. The signal PREC becomes “L” and the MOS capacitor Qd101 is charged to Vcc.
[0093]
If the threshold value of the selected memory cell is 0 V or less, the bit line voltage becomes “L”. If the threshold value of the selected memory cell is 0 V or higher, the bit line voltage remains “H”. Thereafter, the signal BLCN is set to 1.5 V, for example, equal to or lower than Vcc. When the threshold value of n channel MOS transistor Qn110 is 1V, if the bit line is 0.5V or less, n channel MOS transistor Qn110 is "ON" and node N101 is 0.5V or less. If the bit line is 0.5V or higher, the n-channel MOS transistor Qn110 is "OFF" and the node N101 is kept at Vcc.
[0094]
Again, the signal BLCN becomes “L”, and the bit line BL and the MOS capacitor Qd101 are disconnected. After the signals LAT1 and SEN1 become “L” and the flip-flop FF1 is deactivated, the signal SAC1 becomes “H”. Again, the signal SEN1 becomes “H” and subsequently the signal LAT1 becomes “H”, whereby the voltage of the node N101 is sensed and latched. Thus, whether or not the data in the memory cell is “0” is sensed by the flip-flop FF1, and the information is latched.
[0095]
Next, the selected control gate is set to 2V. If the threshold value of the selected memory cell is 2V or less, the bit line voltage becomes “L”. If the threshold value of the selected memory cell is 2 V or more, the bit line voltage remains “H”. Thereafter, the signal BLCN is set to 1.5 V, for example, equal to or lower than Vcc. When the threshold value of n channel MOS transistor Qn110 is 1V, if the bit line is 0.5V or less, n channel MOS transistor Qn110 is "ON" and node N101 is 0.5V or less. If the bit line is 0.5V or higher, the n-channel MOS transistor Qn110 is "OFF" and the node N101 is kept at Vcc.
[0096]
Again, the signal BLCN becomes “L”, and the bit line BL and the MOS capacitor Qd101 are disconnected. After the signals LAT2 and SEN2 become “L” and the flip-flop FF2 is deactivated, the signal SAC2 becomes “H”. Again, the signal SEN2 becomes “H” and then the signal LAT2 becomes “H”, whereby the voltage of the node N101 is sensed and latched. Thus, whether or not the data in the memory cell is “2” is sensed by the flip-flop FF2, and the information is latched.
[0097]
During reading, the signal ERSB is “H”, VRFYB is “H”, and PRO is “L”. The voltages VBLM and Vs are 0V.
[0098]
When the column activation signal CENB input to the column address decoder becomes “H”, the data held in the data circuit selected by the address signal is output to the data input / output lines IOA, IOB, IOC, IOD, and the data The data is output outside the EEPROM via the input / output buffer 9.
[0099]
The relationship between the data stored in the memory cell, the threshold value, and the level output after reading to the data input / output lines IOA, IOB, IOC, and IOD is as follows (Table 5).
[0100]
[Table 5]

[0101]
Nine memory states can be formed by two adjacent memory cells. Of these, 3 bits of data are stored using 8 states. The signals output to the data input / output lines IOA, IOB, IOC, and IOD are converted into 3-bit data by the data input / output buffer 9 based on the ternary information for adjacent even and odd two columns and output. The For example, the correspondence is made as shown in Table 2 above.
[0102]
FIG. 24 shows a write operation. Prior to the write operation, the input 3-bit data is converted into two ternary data by the data input / output buffer 9 as shown in (Table 2), and the data is input to the adjacent even and odd column data circuits 8. Entered. The relationship between the ternary data and the data input / output lines IOA, IOB, IOC, and IOD is as follows (Table 6).
[0103]
[Table 6]

[0104]
The converted ternary data is transferred to the data circuit at the column address designated by the address signal when the column activation signal CENB is “H”.
[0105]
In the write operation, first, the signal PRE becomes “L” and the bit line is floated.
[0106]
Next, the signal VRFYB is set to “L”, the signal PRO is set to “H”, and the voltage VBLM is set to 2.5V. As a result, Vcc is output from the data circuit holding data “0” and 2.5 V is output from the data circuit holding data “1” to the bit line. When the signal SAC2 is set to 1.5V, 0V is output to the bit line from the data circuit holding the data “2”. If the threshold value of the n-channel MOS transistor Q109 is 1V, the n-channel MOS transistor Qn109 is “OFF” when “0” or “1” is written, and “ON” when “2” is written. When the voltage drop corresponding to the threshold voltage of the high breakdown voltage n-channel MOS transistor Hn101 becomes a problem, the signal ERSB may be boosted.
[0107]
The selection gate SG1 and the control gates CG1 to CG4 of the block selected by the word line selection / drive circuit 11 become Vcc. The selection gate SG2 is 0V. Next, the selected control gate CG2 becomes a high voltage Vpp (for example, 20V), and the non-selected control gates CG1, CG3, and CG4 become VM (for example, 10V). In the memory cell corresponding to the data circuit holding data “2”, electrons are injected into the floating gate due to the potential difference between the channel potential of 0 V and the Vpp of the control gate, and the threshold value rises. In the memory cell corresponding to the data circuit holding data “1”, electrons are injected into the floating gate due to the potential difference between the channel potential of 2.5 V and the Vpp of the control gate, and the threshold value rises. The reason why the channel potential is set to 2.5 V is that the injection amount of electrons may be smaller than that of “2” data writing.
[0108]
In the memory cell corresponding to the data circuit holding data “0”, the potential difference between the channel potential and Vpp of the control gate is small, so that electrons are not effectively injected into the floating gate. Therefore, the threshold value of the memory cell does not change. During writing, the signals SEN1, LAT1, SEN2, and LAT2 are “H”, the signal SAC1 is “L”, the signal PREC is “H”, the signals BLCN and BLCP are “H” and “L”, and the signal ERSB is “H”. It is.
[0109]
After the write operation, the threshold value of the memory cell is detected (write verify). If the desired threshold value is reached, the data in the data circuit is changed to “0”. If the desired threshold value has not been reached, the data in the data circuit is held and the write operation is performed again. The write operation and write verify are repeated until all selected memory cells reach the desired threshold value.
[0110]
The write verify operation will be described with reference to FIG. First, the voltage VBLP becomes the power supply voltage Vcc (for example, 5 V), and the bit line becomes “H” level. At the same time, the signal BLCN becomes “L” and BLCP becomes “H”, and the bit line and the MOS capacitor Qd101 are disconnected. The signal PRE becomes “L”, and the bit line enters a floating state. Subsequently, the selected control gate CG2 of the block selected by the word line selection / drive circuit 11 is set to 0.5 V, and the non-selection control gates CG1, CG3, CG4 and the selection gates SG1, SG2 are set to Vcc. The signal PREC becomes “L” and the MOS capacitor Qd101 is charged to Vcc.
[0111]
If the threshold value of the selected memory cell is 0.5 V or less, the bit line voltage becomes “L”. If the threshold value of the selected memory cell is 0.5 V or higher, the bit line voltage remains “H”. Thereafter, the signal BLCN is set to 1.5 V, for example, equal to or lower than Vcc. When the threshold value of n channel MOS transistor Qn110 is 1V, if the bit line is 0.5V or less, n channel MOS transistor Qn110 is "ON" and node N101 is 0.5V or less. If the bit line is 0.5V or higher, the n-channel MOS transistor Qn110 is "OFF" and the node N101 is kept at Vcc.
[0112]
Again, the signal BLCN becomes “L”, and the bit line BL and the MOS capacitor Qd101 are disconnected. When the signal VRFYB becomes “L”, the p-channel MOS transistor Qp103 is “ON” and the node N101 becomes Vcc only in the data circuit holding “0” write data. When the signal SAC2 becomes 1.5V, the node N101 is set to 0V only in the data circuit holding the “2” write data. In the data circuit in which “1” write data is held, the voltage of the node N101 of 0.5 V or higher does not change. The voltage at the node N1 of 0.5V or less is charged up to 0.5V. After the signals LAT1 and SEN1 become “L” and the flip-flop FF1 is deactivated, the signal SAC1 becomes “H”. Again, the signal SEN1 becomes “H” and subsequently the signal LAT1 becomes “H”, whereby the voltage of the node N101 is sensed and latched.
[0113]
As a result, only the data circuit holding the “1” write data detects whether or not the data in the corresponding memory cell is sufficiently in the “1” write state. If the data in the memory cell is “1”, the write data is changed to “0” by sensing and latching the voltage of the node N101 by the flip-flop FF1. If the data in the memory cell is not “1”, the write data is held at “1” by sensing and latching the voltage of the node N101 by the flip-flop FF1. The write data of the data circuit holding “0” or “2” write data is not changed.
[0114]
Next, the selected control gate is set to 3V. If the threshold value of the selected memory cell is 3 V or less, the bit line voltage becomes “L”. If the threshold value of the selected memory cell is 3V or more, the bit line voltage remains “H”. Thereafter, the signal BLCN is set to 1.5 V, for example, equal to or lower than Vcc. When the threshold value of n channel MOS transistor Qn110 is 1V, if the bit line is 0.5V or less, n channel MOS transistor Qn110 is "ON" and node N101 is 0.5V or less. If the bit line is 0.5V or higher, the n-channel MOS transistor Qn110 is "OFF" and the node N101 is kept at Vcc.
[0115]
Again, the signal BLCN becomes “L”, and the bit line BL and the MOS capacitor Qd101 are disconnected. When the signal VRFYB becomes “L”, the p-channel MOS transistor Qp103 is “ON” and the node N101 becomes Vcc only in the data circuit holding “0” write data. After the signals LAT1 and SEN1 become “L” and the flip-flop FF1 is deactivated, the signal SAC1 becomes “H”. Again, the signal SEN1 becomes “H” and subsequently the signal LAT1 becomes “H”, whereby the voltage of the node N101 is sensed and latched.
[0116]
Subsequently, the signal PRO becomes “H” and the voltage VBLM becomes Vcc. The node N101 is changed to “H” only by the data circuit holding “1” write data. After the signals LAT2 and SEN2 become “L” and the flip-flop FF2 is deactivated, the signal SAC2 becomes “H”. Again, the signal SEN2 becomes “H” and then the signal LAT2 becomes “H”, whereby the voltage of the node N101 is sensed and latched.
[0117]
Thus, only the data circuit holding “2” write data detects whether or not the data in the corresponding memory cell is sufficiently in the “2” write state. If the data in the memory cell is “2”, the write data is changed to “0” by sensing and latching the voltage of the node N101 by the flip-flops FF1 and FF2. If the data in the memory cell is not “2”, the write data is held at “2” by sensing and latching the voltage of the node N101 by the flip-flops FF1 and FF2. The write data of the data circuit holding “0” or “1” write data is not changed.
[0118]
During the write verification, the signal ERSB is set to “H” and the voltage Vs is set to 0V.
[0119]
Whether or not all selected memory cells have reached a desired threshold value can be determined by detecting the signal PEND. If all the selected memory cells reach the desired threshold value, all the write data becomes “0”, and the data detection p of each of the data circuits 8-0, 8-1,. All the channel MOS transistors Qp101 are “OFF”. When it is detected whether or not the signal line PEND is disconnected from the power supply voltage Vcc, it is determined whether or not all selected memory cells have reached a desired threshold value. The data conversion rule of the data circuit at the time of write verification is as described above (Table 4).
[0120]
As described with reference to FIGS. 24 and 25, by performing writing while verifying, the threshold value of the memory cell corresponding to “1” data is 0.5 V or more of the verify reference voltage, 2 V or less, and “2” data. The threshold value of the corresponding memory cell is controlled to 3 V or more of the verify reference voltage and Vcc or less. As described with reference to FIG. 23, since the reference voltages at the time of reading are 0V and 2V, the threshold margin of “1” data is 0.5V, and the threshold margin of “2” data is 1.0V. Is done. The threshold value corresponding to “0” data is 0V or less. This is the same as the erased state.
[0121]
(Modification)
The present invention is not limited to the above-described embodiments. Although the embodiment has been described by taking an EEPROM as an example, the present invention can be similarly implemented in an EPROM. Further, although the NAND type memory cell has been described, the present invention can be similarly applied to various kinds of memory cells.
[0122]
In the description using the NAND type memory cell, the threshold margin is secured by controlling the reference potential at the time of reading and the reference potential at the time of writing verification. The cell current margin can be ensured by controlling the read reference current and the reference current during verification. In the embodiment, ternary or quaternary storage has been described as an example, but any number of values can be similarly implemented. In addition, various modifications can be made without departing from the scope of the present invention.
[0123]
【The invention's effect】
As described above in detail, according to the present invention, in a memory cell capable of multi-value storage, an n-value storage data circuit for temporary storage is composed of n logic circuits having n-1 input terminals. Thus, an increase in the area of the control circuit other than the memory cell can be suppressed. In addition to this, by setting the charge amount margin as the charge amount increases, it is possible to realize a highly reliable EEPROM while suppressing an increase in write time and write voltage.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a configuration of a memory cell in a first embodiment.
FIG. 2 is a view showing data retention characteristics of a memory cell in the first embodiment.
FIG. 3 is a diagram showing a threshold distribution of a conventional memory cell.
FIG. 4 is a view showing threshold distributions of memory cells in the first embodiment.
FIG. 5 is a view showing a cell current distribution of a memory cell in the first embodiment.
FIG. 6 is a diagram showing data retention characteristics of the memory cell in the first embodiment.
FIG. 7 is a view showing a threshold distribution of memory cells in the first embodiment.
FIG. 8 is a view showing a cell current distribution of the memory cell in the first embodiment.
FIG. 9 is a block diagram showing a configuration of an EEPROM according to the first embodiment.
FIG. 10 is a cross-sectional view showing the structure of the EEPROM according to the first embodiment.
FIG. 11 is a diagram showing a circuit configuration of a memory cell array in the first embodiment.
FIG. 12 is a diagram showing a specific configuration of a data circuit in the first embodiment.
FIG. 13 is a timing chart showing a data read operation in the first embodiment.
FIG. 14 is a timing chart showing a data write operation in the first embodiment.
FIG. 15 is a timing chart showing a write verify operation in the first embodiment.
FIG. 16 is a view showing a modification of the multi-value storage data latch circuit in the first embodiment.
FIG. 17 shows a conventional data latch circuit.
FIG. 18 is a diagram showing a configuration of a conventional data latch circuit.
FIG. 19 is a diagram showing a configuration of a multi-value storage data latch circuit according to the first embodiment.
FIG. 20 is a diagram showing a specific configuration of the cell well control circuit according to the first embodiment.
FIG. 21 is a timing chart showing the operation of the cell well control circuit in the first embodiment.
FIG. 22 is a diagram showing a specific configuration of a data circuit in the second embodiment.
FIG. 23 is a timing chart showing a data read operation according to the second embodiment.
FIG. 24 is a timing chart showing a data write operation in the second embodiment.
FIG. 25 is a timing chart showing a write verify operation in the second embodiment.
[Explanation of symbols]
1 ... p-type semiconductor substrate
2 ... n-type diffusion layer
3. Insulating film
4 Floating gate (charge storage layer)
5 ... Gate insulation film
6 ... Control gate
7 ... Memory cell array
8 ... Data circuit
9 ... Data I / O buffer
10 ... Address buffer
11. Word line selection / drive circuit
12 ... Cell well control circuit
13 ... p-type semiconductor substrate
14 ... n-type well
15 ... p-type well
16 ... Voltage limiter
M ... Memory cell
SG ... Selection gate
CG ... Control gate
BL ... Bit line
Qn: n-channel MOS transistor
Qp ... p-channel MOS transistor
Hn: High breakdown voltage n-channel MOS transistor
Qd: Depletion type n-channel MOS transistor
CI: Clock synchronous inverter
FF ... Flip flop

Claims (12)

A memory cell having a charge storage portion capable of storing multi-value (n (≧ 3) value) data and a data circuit for temporarily storing write data, the data circuit having n−1 input terminals A nonvolatile semiconductor memory device comprising a plurality of logic circuits. The n logic circuits having the n-1 input terminals are connected to one input terminal among the n-1 input terminals of each of the other n-1 logic circuits. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is connected to form a data circuit. A memory cell having a charge storage section capable of storing multi-value (n (≧ 3) value) data, a sense circuit for reading data stored in the memory cell, and data temporarily read by the sense circuit A data circuit for storing,
The sense circuit is composed of n-1 switch circuits that are turned on / off according to the value of read data, and the data circuit is composed of n logic circuits having n-1 input terminals. A non-volatile semiconductor memory device. The n-1 switch circuits each constitute a sense circuit by connecting in series a first MOS transistor to which a different sense signal is input and a second MOS transistor to which the read data is input. -N logic circuits having -1 input terminals, each output terminal is connected to one input terminal among the n-1 input terminals of each of the other n-1 logic circuits. 4. The nonvolatile semiconductor memory device according to claim 3, wherein a data circuit is configured. A memory cell array composed of a plurality of memory cells having charge storage portions capable of storing multi-value (n (≧ 3) value) data, a plurality of bit lines, a plurality of word lines, and a plurality of program control circuits. Prepared,
The plurality of program control circuits hold write control data for determining a write voltage applied to each corresponding memory cell, and simultaneously apply the write voltage to each corresponding memory cell according to the held write control data And the write state of the memory cell and the write control so that the write voltage is applied so that only the memory cell that is insufficiently written is detected in a predetermined write state. According to a predetermined logical relationship from the data, selectively changing the held write control data,
Each program control circuit includes a data circuit for holding the write control data, and the data circuit is composed of n logic circuits having n-1 input terminals. Semiconductor memory device. The n logic circuits having the n-1 input terminals are connected to one input terminal among the n-1 input terminals of each of the other n-1 logic circuits. 6. The nonvolatile semiconductor memory device according to claim 5, wherein the data circuits are connected to each other. 7. The nonvolatile semiconductor memory device according to claim 6, wherein the program control circuit includes a sense circuit for changing the write control data held in the data circuit in accordance with a signal of the bit line. The program control circuit includes n-1 switch circuits which are turned on / off according to the bit line signal in order to change data held in the data circuit according to the bit line signal. 7. The nonvolatile semiconductor memory device according to claim 6, wherein a first switch element to which a different sense signal is input and a second switch element to which the bit line signal is input are connected in series. . A memory cell array comprising a plurality of memory cells having charge storage portions capable of storing multi-value (n (≧ 3) value) data, a plurality of bit lines, a plurality of word lines, a plurality of program control circuits, A plurality of data circuits,
The plurality of program control circuits select the memory cell, apply a write voltage to the selected memory cell,
The plurality of data circuits hold first, second,. Applying the write control voltage to the corresponding memory cell, and selectively detecting only the write state of the memory cell corresponding to the data circuit holding the write control data of a logic level other than the first, The logic level of the write control data of the data circuit corresponding to a memory cell that has reached a predetermined write state is changed to the first logic level, and it corresponds to a memory cell that has not reached the predetermined write state Holding the logic level of the write control data of the data circuit, and writing the first logic level It holds the logic level of the write control data of said data circuit holds the control data to the first logic level,
Each of the data circuits includes a data holding circuit composed of n logic circuits having n-1 input terminals. The n logic circuits having the n-1 input terminals are connected to one input terminal among the n-1 input terminals of each of the other n-1 logic circuits. The nonvolatile semiconductor memory device according to claim 9, wherein the nonvolatile semiconductor memory device is connected to constitute the data holding circuit. 11. The nonvolatile semiconductor device according to claim 10, wherein the data circuit further comprises a sense circuit for changing a logic level of the write control data held in the data holding circuit in accordance with a signal of the bit line. Storage device. The data circuit includes n−1 switch circuits which are turned on / off according to the bit line signal in order to change data held in the data holding circuit according to the bit line signal. 11. The nonvolatile semiconductor memory device according to claim 10, wherein a first switch element to which a different sense signal is input and a second switch element to which the bit line signal is input are connected in series. .

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