JPH0793979A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To obtain the title memory device which can store multivalued information and which can perform a write verification operation at high speed without causing any erroneous verification by a method wherein a multivalued storage function, a write function and a write-data-content renewal function are installed in a verification circuit. CONSTITUTION:A memory cell array 1 is formed in such a way that memory cells which can be electrically rewritten and which have a plurality of storage states in three or more stated are arranged on a matrix shape. A bit-line control circuit 2 which controls a bit line to control a bit line in a readout/write operation and a word-line drive circuit 7 which controls the potential of a word line are installed with reference to the memory cell array 1. The bit-line control circuit 2 exchanges readout data and write data with an input/output-data conversion circuit 5. The input/output-data conversion circuit 5 converts multivalued information in a read-out memory cell into binary information which is to be output to the outside, and it converts binary information on write data input from the outside into multivalued information in a memory cell.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable non-volatile semiconductor memory device (EEPROM), and more particularly to an EEPROM which performs multi-valued storage for storing information of more than 1 bit in one memory cell.

[0002]

2. Description of the Related Art As one of the EEPROMs, a NAND type EEPROM capable of high integration is known. This is to connect a plurality of memory cells in series so that their sources and drains are shared by adjacent ones and to connect them to a bit line as one unit. The memory cell usually has a FETMOS structure in which a charge storage layer and a control gate are stacked. The memory cell array is integrated and formed in a p-type well formed on a p-type substrate or an n-type substrate. The drain side of the NAND cell is connected to the bit line via the select gate, and the source side is also connected to the common source line via the select gate. The control gates of the memory cells are continuously arranged in the row direction to form word lines.

The operation of this NAND cell type EEPROM is as follows. Data writing is performed in order from the memory cell farthest from the bit line. A high voltage Vpp (= about 20 V) is applied to the control gate of the selected memory cell, and an intermediate voltage Vppm (= 1 is applied to the control gate and the select gate of the memory cell on the bit line side from that.
0V) is applied, and 0V is applied to the bit line according to the data.
Alternatively, an intermediate voltage Vm (= about 8V) is applied. When 0V is applied to the bit line, the potential is transferred to the drain of the selected memory cell, and electron injection occurs in the charge storage stack.
As a result, the threshold value of the selected memory cell shifts in the positive direction. This state is, for example, "1". When Vm is applied to the bit line, electron injection does not effectively occur, so the threshold value does not change and remains negative. This state is an erased state and is "0". Data writing is simultaneously performed on memory cells sharing a control gate.

Data erasing is simultaneously performed on all the memory cells in the NAND cell. That is, all control gates are set to 0V and p-type wells are set to 20V. At this time, the selection gate, the bit line and the source line are also set to 20V. As a result, in all memory cells, the electrons in the charge storage layer are emitted to the p-type well, and the threshold value shifts in the negative direction.

For data reading, the control gates of the selected memory cells are set to 0V, and the control gates and selection gates of the other memory cells are set to the power supply potential Vcc (for example, 5V).
Is performed by detecting whether or not a current flows in the selected memory cell.

Due to the restriction of read operation, the threshold value after writing "1" must be controlled between 0V and Vcc. Therefore, the write verify is performed and "1"
Only the memory cells with insufficient writing are detected, and the rewriting data is set so that the rewriting is performed only on the memory cells with insufficient "1" writing (per-bit verification). A memory cell in which "1" is insufficiently written is detected by setting the selected control gate to, for example, 0.5 V (verify voltage) and reading (verify read).

That is, if the threshold of the memory cell has a margin with respect to 0V and is not more than 0.5V, a current flows through the selected memory cell, and it is detected that "1" write is insufficient. Since a current naturally flows in a memory cell that is set to the "0" write state, a circuit called a verify circuit that compensates the current flowing through the memory cell is provided so that this memory cell is not mistakenly recognized as insufficient "1" write. The write verify is executed at high speed by this verify circuit.

By repeating the write operation and the write verify to write data, the write time is optimized for each memory cell, and the threshold value after "1" write is controlled between 0V and Vcc. It

In order to realize multi-valued storage in this NAND cell type EEPROM, it is considered that the states after writing are set to three states of "0", "1" and "2", for example.
The threshold value is negative in the "0" write state, for example 0V to 1/2 Vcc in the "1" write state, and 1/2 Vcc to Vcc in the "2" write state. In the conventional verify circuit, it is possible to prevent a memory cell in the "0" write state from being erroneously recognized as a memory cell in which "1" or "2" write is insufficient.

However, since the conventional verify circuit is not for multi-value storage, the threshold value of the memory cell in the "2" write state is equal to or higher than the verify voltage for detecting whether "1" write is insufficient. In the case where the write insufficiency state of ½ Vcc or less is present, there is a problem in that no current flows in the memory cell when it is detected whether or not the “1” write is insufficient, and it is erroneously recognized as sufficient write.

In addition, in order to prevent erroneous recognition of insufficient writing and perform multi-valued write verification, memory cells that have become sufficiently "1" written must be rewritten to memory cells that are in the "2" written state. Then, the verify write may be performed by detecting whether or not the state is "2" insufficient write. In this case, however, since the "2" write state is set after the "1" write even for the memory cell to be set to the "2" write state, it takes time to write, and the write speed becomes slow.

[0012]

As described above, the conventional N
When multi-valued storage is performed in the AND cell type EEPROM and bit-by-bit verification is attempted by the conventional verify circuit, there is a problem that erroneous verification occurs.

The present invention has been made in consideration of the above circumstances, and an object thereof is to store multivalued information and to speed up a write verify operation without causing erroneous verification. It is to provide a scaleable EEPROM.

[0014]

In order to solve the above problems, the present invention employs the following configurations. That is, the present invention (Claim 1) enables electrical rewriting in a nonvolatile semiconductor memory device capable of storing multivalued data.
A memory cell array in which memory cells having the above-described plurality of storage states are arranged in a matrix, a plurality of write data circuits for temporarily storing data for controlling the write operation state of the plurality of memory cells, and a memory at the same time Write means for performing a write operation according to the contents of a write data circuit respectively corresponding to a plurality of memory cells in the cell array, and write verify means for simultaneously confirming the state after the write operation of the plurality of memory cells, The contents of the write data circuit, and means for updating the contents of the write data circuit so that rewriting is performed only to the insufficiently written memory cells from the state after the write operation of the memory cells. Write operation based on the Updates, memory cells and performing the electrical data writing by performing repeatedly until a predetermined write state.

The present invention (claim 2) has a memory cell array in which electrically rewritable memory cells are arranged in a matrix, and one memory cell has a plurality of storage states of three or more. Arbitrary data “i” (i = 0,
1, ..., N−1; n ≧ 3), multi-valued storage is performed, and the storage state corresponding to data “0” is the erased state. In the nonvolatile semiconductor storage device, the sensed information functions as a sense amplifier. To perform a write operation according to the contents of a plurality of data circuits having a function of storing as a data for controlling the write operation state of the memory cell and at the same time, the data circuits corresponding to the plurality of memory cells in the memory cell array. Write means, and i-th write verify means for confirming whether or not the state after the write operation of the plurality of memory cells is the storage state of the data “i” at the same time (i = 1, 2, ..., n-1), the data circuit so that rewriting is performed only to the memory cells in which the writing is insufficient due to the contents of the data circuit and the state after the writing operation of the memory cells. Contents, i-th data circuit content batch update means for collectively updating the data circuit corresponding to the memory cell to the data "i" (i = 1, ~, n-
1), the confirmation of the storage state by the i-th write verify means and the batch update by the i-th data circuit content batch update means are performed for data "1" to data "n-1" by n.
-1 time, and the data circuit content updating means for updating the content of all of the plurality of data circuits is provided. The i-th data circuit content batch updating means is configured to change the state after the write operation of the memory cell by the i-th write verifying means. Of the output bit line potentials, the bit line potential corresponding to the memory cell that should be the data “i” (i ≧ 1) is sensed / stored as rewrite data, and should be a state other than the data “i”. The bit line potential corresponding to the cell is sensed / stored so as to retain the contents of the data circuit, and the potential of the bit line from which the state after the write operation of the memory cell is output is modified according to the contents of the data circuit. The data storage state of the data circuit is held until the bit line potential is corrected, and the data circuit is used as a sense amplifier while holding the corrected bit line potential. The data circuit corresponding to the memory cell whose data circuit content should be the data “i” is updated at once, and the memory cell performs the write operation and the data circuit content update based on the content of the data circuit. It is characterized in that the data is electrically written by repeating the process until it becomes.

Here, the following are preferred embodiments of the present invention. (1) The data circuit controls the write operation state of the memory cell according to the data stored in the data circuit during the write operation and changes the state of the memory cell to a predetermined write state, or Controls whether to keep the state of before the write operation. (2) The i-th data circuit content batch updating means controls the data circuit corresponding to the memory cell in which the data “i” should be written to change the memory cell so that the data “i” is written. When the memory cell corresponding to the data circuit in which the data to be stored has reached the write state of the data “i”, the data of the data circuit is controlled to hold the state of the memory cell in the state before the write operation. If the memory cell corresponding to the data circuit storing the data for changing to the data and controlling the memory cell to be in the write state of the data “i” has not reached the write state of the data “i”, , Setting data in the data circuit for controlling the state of the memory cell to change to the write state of the data “i”, If the data for controlling the state of the memory cell to be held in the state before the write operation is stored in, set the data for controlling the state of the memory cell to be held in the state before the write operation in the data circuit, The i-th data circuit content batch updating means should not change the data circuits corresponding to the memory cells other than the data "i" which should be in the written state. (3) The memory cell is formed by stacking a charge storage layer and a control gate on a semiconductor layer, and the memory cell has arbitrary data “i” (i = 0, 1, ...
n-1; n ≧ 3) should be multi-valued stored with a threshold value, and a predetermined i-th verify potential should be applied to the control gate by the i-th write verify means to attain the data “i” state. Verify whether the threshold value of the memory cell is the desired threshold value. (4) The storage state corresponding to the data “0” is the erased state, and the threshold value corresponding to the data “n−1” state has the largest difference from the threshold value corresponding to the data “0” state. The threshold values corresponding to the data "1", "2", ~, "i", ~, "n-2" states are changed from the threshold values corresponding to the data "0" state to the data "n-1" states. It is a value between corresponding threshold values, and data "1", "2", ..., "i", ..., "n" in ascending order from the threshold value corresponding to the data "0" state.
The threshold value corresponding to the -2 "state is set, and the content of the data circuit indicates the state of the memory cell in the bit line potential at which the state after the writing of the memory cell is output by the i-th write verify unit. Only the potential of the bit line corresponding to the data that is controlled to be retained in the state before the write operation, and the data that is controlled to retain the state of the memory cell in the state before the write operation when the data circuit senses And a first bit line potential setting circuit for setting the first corrected bit line potential as follows.
n-2) of the bit line potentials in which the state after writing of the memory cell is output by the write verifying means,
Data for controlling the contents of the data circuit in the bit line corresponding to the memory cell to be in the data “j” (i + 1 ≦ j) state so that the state of the memory cell is changed to the write state of the data “j”. The second correction bit that becomes the data for controlling so that the state of the memory cell is changed to the data “j” write state when the data circuit senses only the bit line potential corresponding to The bit line potential setting circuit for setting the line potential is provided. For updating the data circuit content, the potential of the bit line from which the state after the write operation of the memory cell is output by the i-th write verify is output. Correction by the first, i + 1, i + 2, ..., N−1 bit line potential setting circuits. (5) The data circuit has a first data storage unit that stores as information whether or not to control the state of the memory cell so as to maintain the state before the write operation, and the information of the first data storage unit is the memory cell. In the case of information that is not controlled so as to hold the state of before the write operation, the second information that stores the information indicating the write state “i” (i = 1, 2, ..., N−1) to be stored in the memory cell is stored. A data storage unit, and a first
The data storage section of the memory cell is modified by the first, i + 1, i + 2, ..., N−1 bit line potential setting circuits according to the contents of the data circuit for updating the contents of the data circuit. It also has the function of sensing / storing the potential of the bit line that outputs the state after the write operation. (6) When the information of the first data storage unit is information for controlling the state of the memory cell to be maintained in the state before the write operation, the write protection bit that outputs the write protection bit line voltage to the bit line during the write operation When the information in the line voltage output circuit and the information in the first data storage unit is information that is not controlled to hold the state of the memory cell in the state before the write operation, the write state to be stored in the memory cell in the second data storage unit An i-th write bit line voltage output circuit for outputting a bit line voltage at the i-th write according to information indicating "i" (i = 1, 2, ..., N-1). (7) The first bit line potential setting circuit and the write protection bit line voltage output circuit are the same first bit line voltage control circuit, and the input voltage is the write protection bit line voltage when the output is the write voltage. Is a voltage such that its output becomes the first correction bit line potential when the contents of the data circuit are updated, and the j-th (j = 2, 3, ..., N-1)
The bit line potential setting circuit and the j-th write bit line voltage output circuit are a common j-th bit line voltage control circuit, and the input voltage thereof is the j-th write bit line voltage at the time of writing. Voltage so that the output becomes the second correction bit line potential when updating the contents of the data circuit. (8) The memory cell is configured by stacking a charge storage layer and a control gate on a semiconductor layer, and connecting a plurality of memory cells in series to each other.
Forming an ND cell structure. (9) The memory cell is configured by stacking a charge storage layer and a control gate on a semiconductor layer to form a NOR cell structure.

[0017]

The multi-valued (n-valued) memory type EEPRO according to the present invention
M is configured to perform the verify read operation from n-1 basic operation cycles. Erase state is "0"
If the multi-valued levels are "0", "1", ~, "i", ~, "n-1" in ascending order of the threshold value of the memory cell, is it sufficient to write "i" in the i-th cycle? It is configured to verify only whether or not. Therefore, the selected control gate is provided with a verify potential generation circuit that applies a verify voltage of a predetermined i level in the i-th cycle so that a current flows in the memory cell if “i” programming is insufficient. A sense amplifier that detects whether or not writing is sufficient by detecting the voltage of the bit line is provided. i
In the second cycle, if the bit line of the memory cell to which "0", ~, "i-1" is written has already been detected as being sufficiently written, the current of the memory cell is compensated, and the insufficient writing is detected. If so, the first verify circuit is provided so that the current of the memory cell is not compensated. In the i-th cycle, if the bit line of the memory cell to which "i + 1", ..., "n-1" is written is already detected to be sufficiently written, the first verify circuit compensates the current of the memory cell, A second verify circuit is provided to set the bit line voltage as if the current of the memory cell had flowed if it was detected that the writing was insufficient.

A first register for storing whether or not writing is sufficient as data and a second register for storing any one of the multi-valued levels to be written are "1", ..., "n-1". The first register also has a function of a sense amplifier that detects whether or not writing is sufficient. Furthermore, if there is a memory cell that has not reached the desired write state, rewrite only to that memory cell,
It is characterized in that a bit line write voltage output circuit for outputting a bit line voltage at the time of writing is provided according to a desired write state.

In the present invention, after multi-value data writing is performed, it is detected whether the write state of each memory cell has reached its desired multi-value level state. Then, if there is a memory cell that has not reached the desired multilevel level, the bit line voltage at the time of writing is output according to the desired write state so that rewriting is performed only to that memory cell. This write operation and verify read are repeated, and when it is confirmed that all the memory cells have reached the desired write state, the data write ends.

As described above, according to the present invention, the writing time is shortened once, and the writing operation is repeated in small steps while checking the progress of the writing state, whereby the data writing is finally completed. It is possible to reduce the threshold value of the memory cell at high speed.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a NAND according to the first embodiment of the present invention.
It is a block diagram showing a schematic structure of a cell type EEPROM.

Read / write to the memory cell array 1
A bit line control circuit 2 for controlling a bit line at the time of writing and a word line drive circuit 7 for controlling a word line potential are provided. The bit line control circuit 2 and the word line drive circuit 7 are selected by the column decoder 3 and the row decoder 8, respectively. The bit line control circuit 2 receives the input / output data conversion circuit 5 via the data input / output line (IO line).
And read / write data are exchanged.
The input / output data conversion circuit 5 converts the read multi-valued information of the memory cell into binary information for outputting to the outside, and converts the binary information of the write data input from the outside into the multi-valued information of the memory cell. Convert. The input / output data conversion circuit 5 includes a data input / output buffer 6 for controlling data input / output with the outside.
Connected to. The data write end detection circuit 4 detects whether or not the data write has ended.

2 and 3 show specific configurations of the memory cell array 1 and the bit line control circuit 2. With the memory cells M1 to M8 and the selection transistors S1 and S2,
Construct a D-type cell. One end of the NAND cell is connected to the bit line BL and the other end is connected to the common source line Vs. Select gates SG1 and SG2, control gates CG1 to C
G8 is shared by a plurality of NAND cells, and memory cells sharing one control gate form a page. The memory cell stores data at the threshold value Vt. If Vt is 0V or less, "0" data, Vt is 0V or more.
The data is stored as "1" data when the voltage is 5 V or less and "2" data when Vt is 1.5 V or more and the power supply voltage or less. One memory cell has three states, and two memory cells have 9 states.
You can combine streets. Of these combinations, eight combinations are used to store 3-bit data in two memory cells. In this embodiment, 3-bit data is stored in a set of two adjacent memory cells sharing a control gate. The memory cell array 1 is formed on a dedicated p well.

Clock synchronous inverters CI1 and CI2
And CI3 and CI4 form flip-flops respectively and latch write / read data. They also operate as sense amplifiers. The flip-flop composed of the clock synchronous inverters CI1 and CI2 latches "whether" 0 "is written," 1 "or" 2 "is written" as write data information, and the memory cell is "Hold information" 0 "or information" 1 "or" 2 "?" Is latched as read data information. The flip-flop composed of the clock synchronous inverters CI3 and CI4 latches "whether" 1 "is written or" 2 "is written" as write data information, and the memory cell is "2". Whether information is held or "0" or "1" information is held "is latched as read data information.

Of the n-channel MOS transistors, Q
n1 transfers the voltage VPR to the bit line when the precharge signal PRE becomes "H". In Qn2, the bit line connection signal BLC becomes "H" to connect the bit line to the main bit line control circuit. Qn3 to Qn6, Qn9 to Qn12
Selectively transfers the voltages VBLH, VBLM, and VBLL to the bit lines according to the data latched in the above flip-flop. Qn7 and Qn8 are signal SA
The flip-flop and the bit line are connected when C2 and SAC1 become "H". Qn13 is provided to detect whether or not the data for one page latched by the flip-flops are all the same. Qn14, Qn15 and Q
n16 and Qn17 are column selection signals CSL1 and CS, respectively.
When L2 becomes "H", the corresponding flip-flop and the data input / output lines IOA and IOB are selectively connected.

In FIG. 3, the inverter portion is shown in FIG.
Although omitted as shown in FIG. 9 (a), this has the circuit configuration shown in FIG. 19 (b). Next, the operation of the EEPROM thus configured will be described with reference to FIGS. 4 shows the read operation timing, FIG. 5 shows the write operation timing, and FIG. 6 shows the verify read operation timing. Control gate C
The case where G4 is selected is shown as an example.

The read operation is executed in two basic cycles. In the first read cycle, the voltage VPR is first set to the power supply voltage Vcc to precharge the bit line, and the precharge signal PRE is set to "L" to float the bit line. Then, select gates SG1 and SG2
, Control gates CG1 to CG3, CG5 to CG8 are Vcc
It is said that At the same time, the control gate CG4 is set to 1.5V. Only when the Vt of the selected memory cell is 1.5 V or more, that is, only when the data “2” is written, the bit line is held at the “H” level.

After this, the sense activation signals SEN2, SE
N2B is "L", "H", respectively, and latch activation signal LA
T2 and LAT2B are set to "L" and "H", respectively, and the flip-flop composed of the clock synchronous inverters CI3 and CI4 is reset. The signal SAC2 becomes "H", and clock synchronous inverters CI3 and CI
The flip-flop composed of 4 is connected to the bit line, and the sense activation signals SEN2 and SEN2B are first set to "H" and "L" to sense the bit line potential, and then the latch activation signal LAT2, LAT2B becomes "H" and "L" respectively, and clock synchronous inverter CI
Flip-flop composed of 3 and CI4,
The information ““ 2 ”data, 1” or “0” data ”is latched.

In the second read cycle, the first read cycle, the voltage of the selection control gate CG4 is 0V instead of 1.5V, and the signals SEN2, SEN2B, LAT2,
Signals SEN1 and SEN1 instead of LAT2B and SAC2
The difference is that B, LAT1, LAT1B, and SAC1 are output. Therefore, in the second read cycle, the flip-flop composed of the clock synchronous inverters CI1 and CI2 is used.
Information of ““ 0 ”data,“ 1 ”or“ 2 ”data” ”is latched in the flop.

The data written in the memory cell is read by the two read cycles described above. Prior to data writing, the data in the memory cell is erased, and the threshold Vt of the memory cell is 0 V or less. For erasing, the p-well, the common source line Vs, the select gates SG1 and SG2 are set to 20 V, and the control gates CG1 to CG are set.
8 is set to 0V.

In the write operation, first, the precharge signal PRE becomes "L" and the bit line is floated. Select gate SG1 is Vcc, control gates CG1 to C
G8 is set to Vcc. The select gate SG2 is 0V during the write operation. At the same time, the signals VRFY1, VRFY2,
FIM and FIH become Vcc. In the case of writing "0", since the data is latched in the flip-flop composed of the clock synchronous inverters CI1 and CI2 so that the output of the clock synchronous inverter CI1 becomes "H", the bit line is It is charged by Vcc. "1"
Alternatively, in the case of writing "2", the bit line is at 0V.

Subsequently, the selection gate SG1 and the control gate C
G1 to CG8, signal BLC, signal VRFY1 and voltage VS
A is 10V, voltage VBLH is 8V, and voltage VBLM is 1V. In the case of writing "1", the flip-flop composed of the clock synchronous inverters CI3 and CI4,
Since the data is latched so that the output of the clock synchronous inverter CI3 becomes "H", 1V is applied to the bit line BL. The bit line is 0V when "2" is written, and 8V when "0" is written. After this,
The selected control gate CG4 is brought to 20V.

In the case of writing "1" or "2", electrons are injected into the charge storage layer of the memory cell due to the potential difference between the bit line BL and the control gate CG4, and the threshold value of the memory cell rises. In the case of "1" writing, the amount of charges to be injected into the charge storage layer of the memory cell must be reduced as compared with "2" writing, so that the bit line BL is set to 1
The potential difference with the control gate CG4 is set to V and is relaxed to 19V. However, it can be implemented without alleviating this potential difference. At the time of writing "0", the threshold voltage of the memory cell is not effectively changed by the bit line voltage 8V.

At the end of the write operation, first, the select gate SG1 and the control gates CG1 to CG8 are set to 0 V, and "0" is set.
The voltage 8V of the bit line BL at the time of writing is reset to 0V with a delay. This is because if this order is reversed, the state of the "2" or "1" write operation is temporarily made, and the wrong data is written when the "0" is written.

After the write operation, the write state of the memory cell is confirmed, and the additional write is performed only to the memory cell in which the write is insufficient, so the verify read is performed. During verify read, the voltage VBLH is Vcc and VBLL is 0
V and FIM are 0V.

Verify read is executed from two basic cycles. This basic cycle is similar to the read second cycle. The difference is that the selected control gate C
That is, the voltage of G4 and the signals VRFY1, VRFY2 and FIH are output (only VRFY1 in the verify read first cycle). Signals VRFY1 and VRFY2
, FIH are signals SEN after the select gates SG1, SG2 and the control gates CG1 to CG8 are reset to 0V.
1, SEN1B, LAT1 and LAT1B are "L",
It is output before it becomes "H", "L", "H". In other words, after the potential of the bit line is determined by the threshold value of the memory cell, the clock synchronous inverters CI1, C1
Before the flip-flop composed of I2 is reset. The voltage of the selected control gate CG4 is 2V (first cycle), 0.5V (second cycle) corresponding to 1.5V (first cycle) and 0V (second cycle) at the time of reading, It is set high in order to secure a threshold margin of 0.5V.

Here, the clock synchronous inverter CI
The data (data1) latched in the flip-flop composed of 1 and CI2, the data (data2) latched in the flip-flop composed of the clock synchronous inverters CI3 and CI4, and the selected memory cell The voltage of the bit line BL determined by the threshold value will be described. data1 is “0” write or “1”
Or "2" write "is controlled. When" 0 "is written, Qn3 is" ON ", and when" 1 "or" 2 "is written, Qn6 is" ON ". data2 controls “whether“ 1 ”writing or“ 2 ”writing”,
When writing "1", Qn10 is "ON", "2"
In the case of writing, Qn11 is in the "ON" state.

In the verify read first cycle at the time of writing "0" data (initial write data is "0"), since the data of the memory cell is "0", when the control gate CG4 becomes 2V, the bit line is changed by the memory cell. The potential becomes “L”. After that, the signal VRFY1 becomes "H", so that the bit line BL becomes "H".

In the verify read first cycle at the time of writing "1" data (initial write data is "1"), the data of the memory cell should be "1", so the threshold value of the memory cell is 1.5V. In the following, control gate C
When G4 becomes 2V, the bit line potential becomes "L" depending on the memory cell. After that, when the signal VRFY1 becomes "H", the "1" write is already sufficient and the data1 indicates "0" write, the bit line BL is "H" (see FIG. 6).
(1)), otherwise the bit line BL is "L" ((2) in FIG. 6)
).

In the verify read first cycle at the time of writing "2" data (initial write data is "2"), if the data of the selected memory cell is not "2"("2" write is insufficient), control is performed. Gate CG4 is 2
When it becomes V, the bit line potential becomes "L" by the memory cell ((5) in FIG. 6). When the selected memory cell is sufficiently written with "2", the bit line potential remains "H" even if the control gate CG4 becomes 2V ((3) in FIG. 6).
(Four)). In (3) of FIG. 6, it is already enough to write "2",
This is the case where a1 indicates "0" writing. In this case, since the signal VRFY1 becomes "H", the bit line BL is recharged by the voltage VBH.

In the second verify read cycle at the time of writing "0" data (initial write data is "0"), the data of the memory cell is "0", so that when the control gate CG4 becomes 0.5V, it is determined by the memory cell. The bit line potential becomes "L". After that, the signal VRFY1 becomes "H", and the bit line BL becomes "H".

In the verify read second cycle at the time of writing "1" data (initial write data is "1"), if the data of the selected memory cell is not "1"("1" write is insufficient), control is performed. When the gate CG4 becomes 0.5V, the bit line potential becomes "L" by the memory cell ((8) in FIG. 6). Selected memory cell is "1"
When the writing is sufficient, the bit line potential remains "H" even if the control gate CG4 becomes 0.5V ((6) (7) in FIG. 6). (6) in FIG. 6 is a case where "1" write is already sufficient and data1 indicates "0" write. In this case, since the signal VRFY1 becomes "H", the bit line BL is recharged by the voltage VBH.

In the verify read second cycle at the time of writing "2" data (initial write data is "2"), the data of the memory cell should be "2", so the threshold value of the memory cell is 0.5V. In the above case, the control gate CG4 is 0.5 even if "2" writing is sufficient or insufficient.
Even if it becomes V, the bit line potential remains “H” (FIG. 6).
(9) (10)). When the "2" write is insufficient and the threshold value of the memory cell is 0.5 V or less, the bit line becomes "L" ((11) in FIG. 6).

After that, the signals VRFY1, VRFY2, F
When IH becomes "H", if "2" is already written and data1 indicates "0", bit line BL is "H" ((9) in FIG. 6), otherwise bit line BL.
Is "L" ((10) (11) in FIG. 6). By this verify read operation, rewrite data is set as shown in the following (Table 1) from the write data and the write state of the memory cell.

[0045]

[Table 1] As can be seen from (Table 1), the "1" write is performed again only on the memory cells where the "1" write is insufficient, and the "2" write is performed again only on the memory cells where the "2" write is insufficient. . Further, when the data writing becomes sufficient in all the memory cells, Qn13 of all the columns becomes “OFF”, and the data writing end information is output by the signal PENDB.

FIG. 7 shows data input / output operation timings, (a) is data input timing, and (b) is data output timing. After 3 cycles of data input from the outside, the input / output data conversion circuit 5 generates and inputs the data to be input to the bit line control circuit 2.
External 3-bit data (X1, X2, X3)
Are converted into data (Y1, Y2) of two memory cells, and are effectively registers R1 and C composed of clock synchronous inverters CI1, CI2 of the bit line control circuit 2.
Conversion data is set in the register R2 composed of I3 and CI4 through the data input / output lines IOA and IOB.
The read data latched in the registers R1 and R2 are transferred to the input / output data conversion circuit 5 via the data input / output lines IOA and IOB, converted and output. It is also possible to make the column selection signals CSL1i and CSL2i shown in FIG. 3 the same signal, and instead divide IOA and IOB into two systems to simultaneously access two registers in the same column, and shorten the access time. Is effective for.

The following (Table 2) corresponds to 3-bit data (X1, X2, X3) from the outside and two data (Y1, Y2) and Y1, Y2 of the memory cell at the time of data input. The relationship between the data in the registers R1 and R2 is shown.

[0048]

[Table 2]

The data in the register is represented by the voltage level of the input / output line IOA at the time of data transfer. Since the data input / output line IOB is an inverted signal of IOA, it is omitted. The following (Table 3) is that at the time of data output.

[0050]

[Table 3] In this embodiment, for the same data, the IOA level at the input and the IOA level at the output are inverted.

Since one of the nine combinations of the two data (Y1, Y2) of the memory cell is left over, it is possible to use this for file management information such as pointer information. Here, the pointer information is set to cell data (Y1,
Y2) = (2,2).

FIG. 8 shows the concept of a page, which is a unit of data writing, when viewed from a microprocessor or the like which controls the EEPROM. Here 1
The page is N bytes, and the address (logical address) as viewed from the microprocessor is displayed. For example, when write data is input only to the area 1 (logical addresses 0 to n), n = 3m + 2 (m =
0, 1, 2, ...) Since (X1, X2, X3) is always aligned, there is no problem. When n = 3 m, only X1 is input. Therefore, X2 = 0, X3 = 0 is generated in the EEPROM and (X1, X2, X3) is input / output data conversion circuit 5
To enter. When n = 3m + 1, X3 = 0 is internally generated. The same applies when this n is equal to N.

Data was written in the area 1 (area 2)
When all the write data of (1) are written to “0”) and the data is additionally written to the area 2, the area 1 portion may be read and the write data of the area 2 portion may be added to the data and input. Alternatively, read the part of area 1,
When the start address n + 1 = 3m of the area 2, all the data in the area 1 is “0”, and when n + 1 = 3m + 2, the address n
Add the data of -1, n to X1 and X2 to the data X3 of the address n + 1 and all the data up to the address n-2 of the area 1 is "0". If n + 1 = 3m + 1, the data of the address n is X1 and the address n + 1, Data X of n + 2
2 and X3 may be added and all the data up to the address n-1 of the area 1 may be set to "0". These operations are EEP
It is also easy to do this automatically inside the ROM. In order to be able to write this additional data, as shown in (Table 2) and (Table 3), (X1, X2, X3) and (Y1
, Y2). (X1, X2, X3) and (Y1, Y2) shown in (Table 2) and (Table 3)
) Is an example, and the present invention is not limited to this. Further, additional data can be written in the same manner even if the area is 3 or more.

FIG. 9A shows a data write algorithm. After data loading, write, verify read, and write end detection operations are repeated. The inside of the dotted line is automatically performed in the EEPROM.

FIG. 9B shows an additional data writing algorithm. After read and data loading, verify read, write end detection and write operation are repeated. The inside of the dotted line is automatically performed in the EEPROM. The reason why the verify reading is performed after the data loading is to prevent the writing from being performed where "1" or "2" has already been written.
Otherwise, overwriting may occur.

FIG. 10 shows an EEPR having such a configuration.
The write characteristic of the threshold value of the memory cell in OM is shown. Writing is simultaneously performed in a memory cell in which “1” data is written and a memory cell in which “2” data is written, and the writing time is independently controlled. The following (Table 4) shows the potential of each part of the memory cell array during erase, write, read, and verify read.

[0057]

[Table 4]

FIG. 11 shows a specific configuration of the memory cell array 1 and the bit line control circuit 2 of the NOR cell type EEPROM according to the second embodiment of the present invention. The memory cell M10 alone constitutes a NOR type cell. One end of the NOR type cell is connected to the bit line BL and the other end is connected to the common ground line. The memory cells M sharing one control gate WL form a page. The memory cell M stores data at the threshold value Vt, and is "0" data when Vt is Vcc or more, "1" data when Vt is Vcc or less and 2.5V or more, and Vt is 2.5V or less and 0V or more. In the case of, it is stored as "2" data. One memory cell has three states, and two memory cells can be combined in nine ways. Of these, using 8 combinations, 2
One memory cell stores data of 3 bits. In this embodiment, 3-bit data is stored in a set of two adjacent memory cells sharing a control gate.

Clock synchronous inverters CI5 and CI6
And CI7 and CI8 form flip-flops respectively and latch write / read data. They also operate as sense amplifiers. The flip-flop composed of the clock synchronous inverters CI5 and CI6 latches "whether" 0 "is written," 1 "or" 2 "is written" as write data information, and the memory cell is ""Holdinformation" 0 "or information" 1 "or" 2 "?" Is latched as read data information. The flip-flop composed of the clock synchronous inverters CI7 and CI8 latches "whether" 1 "is written or" 2 "is written" as write data information, and the memory cell is "2". Whether information is held or "0" or "1" information is held "is latched as read data information.

Of the n-channel MOS transistors, Qn
18 is a voltage V when the precharge signal PRE becomes “H”
Transfer PR to bit line. In Qn19, the bit line connection signal BLC becomes "H" to connect the bit line to the main bit line control circuit. Qn20 to Qn23 and Qn25 to Qn28 are
The voltages VBLH, VBLM, and 0V are selectively transferred to the bit lines in accordance with the data latched in the above flip-flops. Qn24 and Q29 are signals SAC2 and S, respectively.
When AC1 becomes "H", the flip-flop and the bit line are connected. Qn30 is provided to detect whether or not the data for one page latched by the flip-flops are all the same. Qn31, Qn32 and Qn33, Q
At n34, the column selection signals CSL1 and CSL2 are set to "H", and the corresponding flip-flops and the data input / output lines IOA and IOB are selectively connected.

Next, the EEPROM configured as described above
The operation will be described with reference to FIGS. FIG. 12 shows a read operation timing, FIG. 13 shows a write operation timing, and FIG. 14 shows a verify read operation timing.

The read operation is executed in two basic cycles. In the first read cycle, the voltage VPR is first set to the power supply voltage Vcc to precharge the bit line, and the precharge signal PRE is set to "L" to float the bit line. Then, the control gate WL is 2.5V
To be Only when Vt of the selected memory cell is 2.5 V or less, that is, when the data “2” is written, the bit line becomes “L” level.

After this, the sense activation signals SEN2, SE
N2B is "L", "H", respectively, and latch activation signal LA
T2 and LAT2B are set to "L" and "H", respectively, and the flip-flop composed of the clock synchronous inverters CI7 and CI8 is reset. The signal SAC2 becomes "H" and clock synchronous inverters CI7 and CI
The flip-flop composed of 8 and the bit line are connected. First, after the sense activation signals SEN2 and SEN2B are set to "H" and "L" to sense the bit line potential, the latch activation signal LAT2, LAT2B becomes "H" and "L" respectively, and clock synchronous inverter CI
In the flip-flop composed of 7 and CI8,
The information ““ 2 ”data,“ 1 ”or“ 0 ”data” ”is latched.

The read second cycle is the read first cycle, and the voltage of the selection control gate WL is V instead of 2.5V.
cc, signals SEN2, SEN2B, LAT2, L
Signals SEN1, SEN1B, instead of AT2B, SAC2
The difference is that LAT1, LAT1B, and SAC1 are output. Therefore, in the second read cycle, the information "" 0 "data," 1 "or" 2 "data" is latched in the flip-flop composed of the clock synchronous inverters CI5 and CI6.

The data written in the memory cell is read by the two read cycles described above. Prior to the data writing, the data in the memory cell is erased, and the threshold Vt of the memory cell is Vcc or more. Erasing is performed by setting the control gate WL to 20V and the bit line to 0V.

In the write operation, first, the precharge signal PRE becomes "L" and the bit line is floated. The signals VRFY1, VRFY2, FIM and FIL become Vcc. In the case of writing "2", since the data is latched in the flip-flop composed of the clock synchronous inverters CI5 and CI6 so that the output of the clock synchronous inverter CI5 becomes "H", the bit line is It is 0V. In the case of writing "1" or "2", the bit line is charged to Vcc.

Then, the signals BLC, VRFY2, FI
M, FIL and the voltage VSA are 10V, the voltage VBLH is 8V, and the voltage VBLM is 7V. In the case of writing "1", the data is latched by the flip-flop composed of the clock synchronous inverters CI7 and CI8 so that the output of the clock synchronous inverter CI7 becomes "H". Is applied with 7V. The bit line is 8V when "2" is written, and 0 when "0" is written.
It becomes V. After that, the selected control gate WL is -12.
V.

In the case of writing "1" or "2", electrons are emitted from the charge storage layer of the memory cell due to the potential difference between the bit line BL and the control gate WL, and the threshold value of the memory cell is lowered. In the case of "1" write, the amount of charge to be discharged from the charge storage layer of the memory cell must be reduced as compared with "2" write, so that the bit line BL is set to 7V and the potential difference from the control gate WL is set. It is relaxed to 19V. At the time of writing "0", the threshold voltage of the memory cell is not effectively changed by the bit line voltage 0V.

After the write operation, the write state of the memory cell is confirmed, and the additional write is performed only to the memory cell in which the write is insufficient, so the verify read is performed. During verify read, voltage VBLH is Vcc and FIM is 0V
Is.

Verify read is executed from two basic cycles. This basic cycle is similar to the read second cycle. The only difference is the selected control gate W
That is, the voltage of L and the signals VRFY1, VRFY2, and FIH are output (only VRFY1 in the verify read first cycle). Signals VRFY1, VRFY2,
The FIH is output after the control gate WL is reset to 0V and before the signals SEN1, SEN1B, LAT1 and LAT1B become "L", "H", "L" and "H", respectively. In other words, after the potential of the bit line is determined by the threshold value of the memory cell and before the flip-flop composed of the clock synchronous inverters CI5 and CI6 is reset. The voltage of the selected control gate WL is 2V (first cycle), 4V corresponding to 2.5V (first cycle) and Vcc (second cycle) at the time of reading.
(2nd cycle), it is lowered to secure a threshold margin.

Here, the clock synchronous inverter CI
5, the data (data1) latched in the flip-flop composed of CI6 and the data (data2) latched in the flip-flop composed of the clock synchronous inverters CI7 and CI8 and the selected memory cell The voltage of the bit line BL determined by the threshold value will be described. data1 is “0” write or “1”
Or "2" write "is controlled. When" 0 "is written, Qn20 is" ON ", and when" 1 "or" 2 "is written, Qn23 is" ON ". data2 controls “whether“ 1 ”writing or“ 2 ”writing”,
When writing "1", Qn26 is "ON", "2"
In the case of writing, Qn27 is in the "ON" state.

In the verify read first cycle at the time of writing "0" data (initial write data is "0"), since the data of the memory cell is "0", even if the control gate WL becomes 2V, the bit line potential is changed. Remains "H". After that, the signal VRFY1 becomes "H", and the bit line BL becomes "L".

In the verify read first cycle at the time of writing "1" data (initial write data is "1"), the data of the memory cell should be "1", so the threshold value of the memory cell is 2.5V. With the above, the control gate W
Even if L becomes 2V, the bit line potential remains "H". After that, when the signal VRFY1 becomes "H", the "1" write is already sufficient and the data1 indicates "0" write, the bit line BL is "L" ((2) in FIG. 14),
Otherwise, the bit line BL becomes "H" ((1) in FIG. 14).

In the verify read first cycle at the time of writing "2" data (initial write data is "2"), if the data of the selected memory cell is not "2"("2" write is insufficient), control is performed. Gate WL is 2V
The bit line potential is still "H" ((3) in FIG. 14).
). When the selected memory cell is sufficiently written with "2", the bit line potential becomes "L" by the memory cell when the control gate WL becomes 2V ((4) (5) in FIG. 14).
In FIG. 14, (5) is a case where "2" write is already sufficient and data1 indicates "0" write. In this case, the signal VRFY1 becomes "H", and the bit line BL is grounded.

In the second verify read cycle at the time of writing "0" data (initial write data is "0"), since the data of the memory cell is "0", even if the control gate CG4 becomes 4V, the bit line potential is 4V. Is "H". After that, the signal VRFY1 becomes "H", and the bit line BL becomes "L".

In the verify read second cycle at the time of writing "1" data (initial write data is "1"), if the data of the selected memory cell is not "1"("1" write is insufficient), control is performed. Gate WL is 4V
The bit line potential is still "H" ((6) in FIG. 14).
). When the selected memory cell is sufficiently written with "1", the bit line potential becomes "L" by the memory cell when the control gate WL becomes 4V ((7) (8) in FIG. 14). FIG. 14 (8) shows a case where "1" write is already sufficient and data1 indicates "0" write. In this case, the signal VRFY1 becomes "H", and the bit line BL is grounded.

In the verify read second cycle at the time of writing "2" data (initial write data is "2"), the data of the memory cell should be "2", so that the threshold value of the memory cell is 4 V or less. If there is enough "2" writing, the bit line potential becomes "L" when the control gate WL becomes 4V ((10) (11) in FIG. 14).
When the "2" write is insufficient and the threshold voltage of the memory cell is 4 V or more, the bit line becomes "H" ((9) in FIG. 14).

After that, the signals VRFY1, VRFY2, F
When IH becomes “H”, “2” write is already sufficient and data1 indicates “0” write, bit line BL is “L” ((11) in FIG. 14), and bit line B is otherwise.
L becomes "H" ((9) (10) in FIG. 14).

By this verify read operation, the write data and the rewrite data from the write state of the memory cell are set as shown in Table 1 as in the first embodiment. In addition, when data writing becomes sufficient in all memory cells, Qn30 in all columns becomes “OFF”,
Data write end information is output by the signal PENDB.

The data input / output operation timing, the data write algorithm, the additional data write algorithm, etc. are as shown in FIGS. 7 to 9 and (Tables 2 to 3).
It is similar to the embodiment of.

FIG. 15 shows an EEPR having such a configuration.
The write characteristic of the threshold value of the memory cell in OM is shown. Writing is simultaneously performed in a memory cell in which “1” data is written and a memory cell in which “2” data is written, and the writing time is independently controlled. The following (Table 5) shows the potential of each part of the memory cell array at the time of erasing, writing, reading, and verify reading.

[0082]

[Table 5]

The circuits shown in FIGS. 3 and 11 can be modified as shown in FIGS. 16 and 17, respectively. In FIG. 16, Qn3 and Qn4 shown in FIG. 3 are replaced with p-channel MOS transistors Qp1 and Qp2. 17 is shown in FIG.
Qn22, Qn23 and Qn25 to Qn28 shown in FIG. 1 are replaced with p-channel MOS transistors Qp3 to Qp8. By doing so, it is possible to prevent a drop in the transferable voltage due to the threshold value of the n-channel MOS transistor, and in this example, it is sufficient to raise the voltage VSA to 8 V at the time of writing to lower the breakdown voltage of the transistor forming the circuit. be able to. VRFY1B in FIG. 16 is V in FIGS.
Inverted signal of RFY1, VRFY2B, FILB,
FIMB is an inverted signal of VRFY2, FIL, and FIM in FIG.

Although the additional data writing has been described with reference to FIG. 8, one effective method is to divide one page in order to facilitate the additional data writing as shown in FIG. 18, for example. In this example, 22 memory cells form one area for every 32 logical addresses. This makes it easy to write additional data in units of areas. That is, when the additional data is written in the area 2, all the write data in the areas other than the area 2 are set to "0", and
It may be performed according to the data writing algorithm shown in (a). The size of one region may be a size other than that shown in FIG. Further, when four or more write states are set in one memory cell, it is possible according to the gist of the present invention.

[0085]

As described above, according to the present invention, it is possible to set three write states in one memory cell while suppressing an increase in circuit area, and to set each write state in each memory cell. It is possible to obtain an EEPROM in which the write time until it is optimized is independently optimized by performing the write verify control, and the threshold distribution of the finally written memory cells can be kept within a small range at high speed. .

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an EEPROM according to first and second embodiments.

FIG. 2 is a diagram showing a specific configuration of a memory cell array in the first embodiment.

FIG. 3 is a diagram showing a specific configuration of a bit line control circuit according to the first embodiment.

FIG. 4 is a timing chart showing a read operation according to the first embodiment.

FIG. 5 is a timing diagram showing a write operation in the first embodiment.

FIG. 6 is a timing chart showing a verify read operation in the first embodiment.

FIG. 7 is a timing chart showing a data input / output operation in the first and second embodiments.

FIG. 8 is a diagram showing a concept of a page of a write / read unit in the first and second embodiments.

FIG. 9 is a diagram showing data writing and additional data writing algorithms in the first and second embodiments.

FIG. 10 is a diagram showing write characteristics of the memory cell in the first embodiment.

FIG. 11 is a diagram showing a configuration of a memory cell array and a bit line control circuit according to a second embodiment.

FIG. 12 is a timing chart showing a read operation in the second embodiment.

FIG. 13 is a timing chart showing a write operation in the second embodiment.

FIG. 14 is a timing chart showing a verify read operation according to the second embodiment.

FIG. 15 is a diagram showing write characteristics of a memory cell in the second embodiment.

FIG. 16 is a diagram showing a modification of the bit line control circuit in the first embodiment.

FIG. 17 is a diagram showing a modification of the bit line control circuit in the second embodiment.

FIG. 18 is a diagram showing a unit of additional data writing in the first and second embodiments.

19 is a circuit diagram of an inverter portion in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Memory cell array 2 ... Bit line control circuit 3 ... Column decoder 4 ... Data write end detection circuit 5 ... Input / output data conversion circuit 6 ... Data input / output buffer 7 ... Word line drive circuit 8 ... Row decoder

Claims (7)

[Claims] 1. A memory cell array in which memory cells, which are electrically rewritable and have a plurality of storage states of 3 or more, are arranged in a matrix, and a write operation state of the plurality of memory cells in the memory cell array. A plurality of data circuits for temporarily storing data to be controlled; a writing unit for performing a write operation according to the contents of the data circuits corresponding to the plurality of memory cells; and a write operation of the plurality of memory cells Write verifying means for confirming the later state, and the contents of the data circuit so that the contents of the data circuit and the state after the write operation of the memory cell are rewritten only to the insufficiently written memory cells. And a write operation based on the contents of the data circuit, a write verify operation, and a data The content update of capacitor circuits, by the plurality of memory cells is performed by repeatedly until a predetermined write state, the non-volatile semiconductor memory device according to claim electrically to perform data writing. 2. A memory cell array in which electrically rewritable memory cells are arranged in a matrix.
One memory cell has a plurality of storage states of 3 or more and has arbitrary data “i” (i = 0, 1, to, n−1; n ≧ 3), and multivalued storage is performed to obtain data “0”. The corresponding memory state is a non-volatile semiconductor memory device having an erased state, and a function of sensing data as a sense amplifier and sensed information as data for controlling a write operation state of a plurality of memory cells in the memory cell array. A plurality of data circuits having a function of storing data, a writing means for performing a write operation according to the contents of the data circuits respectively corresponding to the plurality of memory cells, and a state after the write operation of the plurality of memory cells Of the i-th (i = 1, 2, ..., N-1) write-verify means for confirming whether or not is in the storage state of the data "i", and the contents of the data circuit. The contents of the data circuit are collectively updated with respect to the data circuit corresponding to the memory cell to be the data "i" so that the rewriting is performed only to the insufficiently written memory cell from the state after the write operation of the memory cell. An i-th (i = 1, 2, ..., N-1) data circuit content batch updating means, a storage state confirmation by the i-th write verifying means, and a batch updating by the i-th data circuit content batch updating means. , For data "1" to data "n-1", n-1
Data circuit content updating means for updating the contents of all the data circuits, and the i-th data circuit content batch updating means outputs the state after the write operation of the memory cell by the i-th write verify means. Data "i" of the bit line potential
The bit line potential corresponding to the memory cell to be (i ≧ 1) is sensed / stored as rewrite data, and the bit line potential corresponding to the memory cell to be in a state other than the data “i” is the content of the data circuit. The state of the memory cell after the write operation is output so that it can be sensed / stored so that the potential of the bit line is modified according to the contents of the data circuit. The data circuit is operated as a sense amplifier while holding the memory state and holding the corrected bit line potential, and the contents of the data circuit are collectively updated for those corresponding to the memory cell that should be the data “i”. The writing operation based on the contents of the data circuit and the updating of the contents of the data circuit are repeated until the plurality of memory cells reach a predetermined writing state. A non-volatile semiconductor memory device, which is characterized in that data is electrically written thereby. 3. The data circuit controls a write operation state of the memory cell according to data stored in the data circuit during a write operation so that the state of the memory cell becomes a predetermined write state. It controls whether to change or hold the state of the memory cell in the state before the write operation, and the i-th data circuit content batch updating means corresponds to the memory cell to be in the write state of the data “i”. For the data circuit to be operated, if the memory cell corresponding to the data circuit storing the data for controlling the memory cell to change to the write state of the data “i” has reached the write state of the data “i”, , The data in the data circuit is changed to the data for controlling the state of the memory cell to be held in the state before the write operation, and the memory cell is changed to the data “i”. If the memory cell corresponding to the data circuit that stores the data to be controlled so as to change to the write state of “1” has not reached the write state of the data “i”, the state of the memory cell is written to the data “i”. If the data to be controlled to change to the state is set in the data circuit and the data to store the state of the memory cell to the state before the write operation is stored in the data circuit, change the state of the memory cell. Data to be controlled to be held in the state before the write operation is set in the data circuit, and the i-th data circuit content batch updating means is a data circuit corresponding to a memory cell other than the data "i" to be in the write state. 3. The nonvolatile semiconductor memory device according to claim 2, wherein is not changed. 4. The memory cell is formed by stacking a charge storage layer and a control gate on a semiconductor layer, and has arbitrary data “i” (i = 0, 1, 1) as the three or more storage states.
, N−1; n ≧ 3) is stored in a multi-valued manner with a threshold value, and a predetermined i-th verify potential is applied to the control gate by the i-th write verify means, and data “ i "
4. The non-volatile semiconductor memory device according to claim 3, wherein it is verified whether or not the threshold value of the memory cell to be brought into a state is a desired threshold value. 5. A storage state corresponding to data "0" is an erased state, and a threshold value corresponding to the data "n-1" state is most different from a threshold value corresponding to the data "0" state. Is large, data "1", "2", ~, "i", ~, "n"
The threshold value corresponding to the -2 "state is a value between the threshold value corresponding to the data" 0 "state and the threshold value corresponding to the data" n-1 "state, and the data" 0 "state The threshold values corresponding to the data "1", "2", ..., "i", ..., "n-2" states are arranged in the order of decreasing distance from the threshold value corresponding to. In the bit line potential where the state after writing of the memory cell is output by
When the data circuit senses only the potential of the bit line corresponding to the content of the data circuit that is the data for controlling the state of the memory cell to be kept in the state before the write operation, the write operation of the state of the memory cell is performed. A first bit line potential setting circuit that sets a first correction bit line potential to be data to be controlled to be held in the previous state is provided, and the i-th (1 ≦ i ≦ n−2) write verify is performed. Of the bit line potentials that are output by the means after the writing of the memory cells, the contents of the data circuit are stored in the bit lines corresponding to the memory cells that should be in the data “j” (i + 1 ≦ j) state. When the data circuit senses only the bit line potential corresponding to the data that controls to change the state of No. 2 to the writing state of data “j”. The data circuit, the j-th bit line potential setting circuit for setting the second corrected bit line potential to be data for controlling to change the state of the memory cell to the data “j” written state. In order to update the contents, the potential of the bit line to which the state after the write operation of the memory cell is output by the i-th write verify is changed to the bit of the first, i + 1, i + 2, ..., N−1 according to the contents of the data circuit. The non-volatile semiconductor memory device according to claim 4, wherein the correction is performed by a line potential setting circuit. 6. A first data storage section for storing, as information, whether or not the data circuit controls to hold the state of the memory cell in the state before the write operation, and information of the first data storage section. Is information that is not controlled to hold the state of the memory cell in the state before the write operation, the write state “i” (i = 1, 2, ..., N−) that the memory cell should store.
A second data storage unit for storing information indicating 1), wherein the first data storage unit stores the first, i + 1, i + according to the contents of the data circuit for updating the contents of the data circuit.
(2), (2), (n-1) bit line potential setting circuit, which has a function of sensing / storing the potential of a bit line corrected by the i-th write verify and outputting the state after the write operation of the memory cell The non-volatile semiconductor memory device according to claim 5. 7. A write-prevention bit line voltage is output to a bit line during a write operation when the information in the first data storage section is information for controlling the state of the memory cell to be kept in the state before the write operation. In the case where the information of the write prevention bit line voltage output circuit and the first data storage unit is the information which is not controlled to hold the state of the memory cell in the state before the write operation,
The bit line voltage at the time of the i-th write is output according to the information indicating the write state “i” (i = 1, 2, ..., N−1) to be stored in the memory cell of the second data storage section. 7. The nonvolatile semiconductor memory device according to claim 6, further comprising an i-th write bit line voltage output circuit.