JP3730425B2 - Nonvolatile semiconductor memory device - Google Patents

Description

【００４９】
（表１）から分かるように、“１”書き込み不足のメモリセルのみ再度“１”書き込みが行われ、“２”書き込み不足のメモリセルにのみ再度“２”書き込みが行われるようになっている。また、全てのメモリセルでデータ書き込みが十分になると、全てのカラムのＱｎ１３が“ＯＦＦ”となり、信号ＰＥＮＤＢによってデータ書き込み終了情報が出力される。
【００５０】
図７はデータの入出力動作タイミングを示しており、（ａ）はデータ入力タイミング、（ｂ）はデータ出力タイミングである。外部からのデータ入力３サイクルの後、入出力データ変換回路５によって、ビット線制御回路２に入力するデータが発生され入力される。外部からの３ビット分のデータ（Ｘ1 ，Ｘ2 ，Ｘ3 ）は、２つのメモリセルのデータ（Ｙ1 ，Ｙ2 ）に変換され、実効的にはビット線制御回路２のクロック同期式インバータＣＩ1 ，ＣＩ2 で構成されるレジスタＲ1 とＣＩ3 ，ＣＩ4 で構成されるレジスタＲ2 に、データ入出力線ＩＯＡ，ＩＯＢを介して変換データが設定される。レジスタＲ1 ，Ｒ2 にラッチされている読み出しデータは、データ入出力線ＩＯＡ，ＩＯＢを介して入出力データ変換回路５に転送され変換されて出力される。図３に見られるカラム選択信号ＣＳＬ1iとＣＳＬ2iを同一信号にして、そのかわりＩＯＡ，ＩＯＢを２系統に分けて同一カラムの２つのレジスタを同時にアクセスすることも容易に可能で、アクセス時間を短くするためには効果的である。
【００５１】
下記の（表２）はデータ入力時の、外部からの３ビット分のデータ（Ｘ1 ，Ｘ2 ，Ｘ3 ）、メモリセルの２つのデータ（Ｙ1 ，Ｙ2 ）とＹ1 ，Ｙ2 それぞれに対応するレジスタＲ1 ，Ｒ2 のデータの関係を示している。
【００５２】
【表２】

【００５３】
レジスタのデータはデータ転送時の入出力線ＩＯＡの電圧レベルで表現してある。データ入出力線ＩＯＢはＩＯＡの反転信号であるため省略してある。下記の（表３）は、データ出力時のそれである。
【００５４】
【表３】

【００５５】
この実施例では同じデータに対して、入力時のＩＯＡのレベルと出力時のＩＯＡのレベルが反転するようになっている。
【００５６】
メモリセルの２つデータ（Ｙ1 ，Ｙ2 ）の９つの組み合わせのうち１つは余るため、これを例えばポインタ情報などファイル管理情報に利用することは可能である。ここではポインタ情報をセルデータ（Ｙ1 ，Ｙ2 ）＝（２，２）に対応させている。
【００５７】
図８は、ＥＥＰＲＯＭをコントロールするマイクロプロセッサなどから見たときの、データ書き込みの単位であるページの概念を示している。ここでは１ページをＮバイトとしていて、マイクロプロセッサなどから見たときのアドレス（論理アドレス）を表示している。例えば、領域１（論理アドレス０〜ｎ）だけしか書き込みデータが入力されないとき、ｎ＝３ｍ＋２（ｍ＝０，１，２，…）であれば常に（Ｘ1 ，Ｘ2 ，Ｘ3 ）が揃うので問題ない。ｎ＝３ｍの場合はＸ1 しか入力されないので、ＥＥＰＲＯＭ内部でＸ2 ＝０，Ｘ3 ＝０を発生して（Ｘ1 ，Ｘ2 ，Ｘ3 ）を入出力データ変換回路５に入力する。ｎ＝３ｍ＋１の場合はＸ3 ＝０を内部で発生する。このｎがＮと等しいときも同様である。
【００５８】
領域１にデータ書き込みを行った（領域２の書き込みデータは全て“０”）後、追加的に領域２にデータ書き込みを行う場合、領域１の部分を読み出してそのデータに領域２の部分の書き込みデータを追加して入力すればよい。或いは、領域１の部分を読み出して、領域２の先頭アドレスｎ＋１＝３ｍの場合は領域１のデータを全て“０”、ｎ＋１＝３ｍ＋２の場合アドレスｎ−１、ｎのデータをＸ1 ，Ｘ2 としてアドレスｎ＋１のデータＸ3 に追加し領域１のアドレスｎ−２までのデータを全て“０”、ｎ＋１＝３ｍ＋１の場合アドレスｎのデータをＸ1 としてアドレスｎ＋１、ｎ＋２のデータＸ2 ，Ｘ3 に追加し領域１のアドレスｎ−１までのデータを全て“０”、としてもよい。これらの動作は、ＥＥＰＲＯＭ内部で自動的に行うことも容易である。この追加データ書き込みが可能となるよう、（表２）及び（表３）に示してあるように（Ｘ1 ，Ｘ2 ，Ｘ3 ）と（Ｙ1 ，Ｙ2 ）の関係は組まれている。（表２）及び（表３）に示してある（Ｘ1 ，Ｘ2 ，Ｘ3 ）と（Ｙ1 ，Ｙ2 ）の関係は１つの例であってこれに限るものではない。また、領域は３以上でも同様に追加データ書き込みは行える。
【００５９】
図９（ａ）は、データ書き込みアルゴリズムを示している。データロード後、書き込み、ベリファイ読み出しと書き込み終了検出動作が繰り返し行われる。点線の中はＥＥＰＲＯＭ内で自動的に行われる。
【００６０】
図９（ｂ）は、追加データ書き込みアルゴリズムを示している。読み出しとデータロード後、ベリファイ読み出し、書き込み終了検出と書き込み動作が繰り返し行われる。点線の中はＥＥＰＲＯＭ内で自動的に行われる。データロード後にベリファイ読み出しが行われるのは、既に“１”或いは“２”が書き込まれているところに書き込みが行われないようにするためである。そうないと過剰書き込みされる場合が生じる。
【００６１】
図１０は、このように構成されたＥＥＰＲＯＭでの、メモリセルのしきい値の書き込み特性を示している。“１”データが書き込まれるメモリセルと“２”データが書き込まれるメモリセルは同時に書き込みが行われ、それぞれ独立に書き込み時間が制御される。
【００６２】
下記の（表４）に、消去、書き込み、読み出し、ベリファイ読み出し時のメモリセルアレイ各部の電位を示す。
【００６３】
【表４】

【００６４】
図１１は、本発明の第２の実施例におけるＮＯＲセル型ＥＥＰＲＯＭの、メモリセルアレイ１とビット線制御回路２の具体的な構成を示している。メモリセルＭ10のみで、ＮＯＲ型セルを構成する。ＮＯＲ型セルの一端はビット線ＢＬに接続され、他端は共通接地線と接続される。１本の制御ゲートＷＬを共有するメモリセルＭはページを構成する。メモリセルＭはそのしきい値Ｖｔでデータを記憶し、ＶｔがＶcc以上である場合“０”データ、ＶｔがＶcc以下２．５Ｖ以上の場合“１”データ、Ｖｔが２．５Ｖ以下０Ｖ以上の場合“２”データとして記憶する。１つのメモリセルで３つの状態を持たせ、２つのメモリセルで９通りの組み合わせができる。この内、８通りの組み合わせを用いて、２つのメモリセルで３ビット分のデータを記憶する。この実施例では、制御ゲートを共有する隣合う２つのメモリセルの組で３ビット分のデータを記憶する。
【００６５】
クロック同期式インバータＣＩ5 ，ＣＩ6 とＣＩ7 ，ＣＩ8 でそれぞれフリップ・フロップを構成し、書き込み／読み出しデータをラッチする。また、センス・アンプとしても動作する。クロック同期式インバータＣＩ5 ，ＣＩ6 で構成されるフリップ・フロップは、「“０”書き込みをするか、“１”又は“２”書き込みをするか」、を書き込みデータ情報としてラッチし、メモリセルが「“０”の情報を保持しているか、“１”又は“２”の情報を保持しているか」、を読み出しデータ情報としてラッチする。クロック同期式インバータＣＩ7 ，ＣＩ8 で構成されるフリップ・フロップは、「“１”書き込みをするか、“２”書き込みをするか」、を書き込みデータ情報としてラッチし、メモリセルが「“２”の情報を保持しているか、“０”又は“１”の情報を保持しているか」、を読み出しデータ情報としてラッチする。
【００６６】
ｎチャネルＭＯＳトランジスタの内、Ｑｎ18は、プリチャージ信号ＰＲＥが“Ｈ”となると電圧ＶPRをビット線に転送する。Ｑｎ19は、ビット線接続信号ＢＬＣが“Ｈ”となってビット線と主要なビット線制御回路を接続する。Ｑｎ20〜Ｑｎ23，Ｑｎ25〜Ｑｎ28は、上述のフリップ・フロップにラッチされているデータに応じて、電圧ＶBLH ，ＶBLM ，０Ｖを選択的にビット線に転送する。Ｑｎ24，Ｑ29はそれぞれ信号ＳＡＣ2 ，ＳＡＣ1 が“Ｈ”となることでフリップ・フロップとビット線を接続する。Ｑｎ30は、フリップ・フロップにラッチされている１ページ分のデータが全て同じか否かを検出するために設けられる。Ｑｎ31，Ｑｎ32とＱｎ33，Ｑｎ34はそれぞれカラム選択信号ＣＳＬ1 ，ＣＳＬ2 が“Ｈ”となって、対応するフリップ・フロップとデータ入出力線ＩＯＡ，ＩＯＢを選択的に接続する。
【００６７】
次に、このように構成されたＥＥＰＲＯＭの動作を図１２〜１４に従って説明する。図１２は読み出し動作のタイミング、図１３は書き込み動作のタイミング、図１４はベリファイ読み出し動作のタイミングを示している。
【００６８】
読み出し動作は、２つの基本サイクルで実行される。読み出し第１サイクルは、まず電圧ＶPRが電源電圧Ｖccとなってビット線はプリチャージされ、プリチャージ信号ＰＲＥが“Ｌ”となってビット線はフローティングにされる。続いて、制御ゲートＷＬは２．５Ｖにされる。選択されたメモリセルのＶｔが２．５Ｖ以下の場合のみ、つまりデータ“２”が書き込まれている場合のみ、そのビット線は“Ｌ”レベルになる。
【００６９】
この後、センス活性化信号ＳＥＮ2 ，ＳＥＮ2Bがそれぞれ“Ｌ”，“Ｈ”、ラッチ活性化信号ＬＡＴ2 ，ＬＡＴ2Bがそれぞれ“Ｌ”，“Ｈ”となって、クロック同期式インバータＣＩ7 ，ＣＩ8 で構成されるフリップ・フロップはリセットされる。信号ＳＡＣ2 が“Ｈ”となってクロック同期式インバータＣＩ7 ，ＣＩ8 で構成されるフリップ・フロップとビット線は接続され、まずセンス活性化信号ＳＥＮ2 ，ＳＥＮ2Bがそれぞれ“Ｈ”，“Ｌ”となってビット線電位がセンスされた後、ラッチ活性化信号ＬＡＴ2 ，ＬＡＴ2Bがそれぞれ“Ｈ”，“Ｌ”となり、クロック同期式インバータＣＩ7 ，ＣＩ8 で構成されるフリップ・フロップに、「“２”データか、“１”又は“０”データか」の情報がラッチされる。
【００７０】
読み出し第２サイクルは読み出し第１サイクルと、選択制御ゲートＷＬの電圧が２．５ＶでなくＶccであること、信号ＳＥＮ2 ，ＳＥＮ2B，ＬＡＴ2 ，ＬＡＴ2B，ＳＡＣ2 の代わりに信号ＳＥＮ1 ，ＳＥＮ1B，ＬＡＴ1 ，ＬＡＴ1B，ＳＡＣ1 が出力されることが違う。よって、読み出し第２サイクルでは、クロック同期式インバータＣＩ5 ，ＣＩ6 で構成されるフリップ・フロップに、「“０”データか、“１”又は“２”データか」の情報がラッチされる。
【００７１】
以上説明した２つの読み出しサイクルによって、メモリセルに書き込まれたデータが読み出される。
【００７２】
データ書き込みに先だってメモリセルのデータは消去され、メモリセルのしきい値ＶｔはＶcc以上となっている。消去は、制御ゲートＷＬを２０Ｖとしビット線を０Ｖにして行われる。
【００７３】
書き込み動作では、まずプリチャージ信号ＰＲＥが“Ｌ”となってビット線がフローティングにされる。信号ＶＲＦＹ1 ，ＶＲＦＹ2 ，ＦＩＭ，ＦＩＬがＶccとなる。“２”書き込みの場合は、クロック同期式インバータＣＩ5 ，ＣＩ6 で構成されるフリップ・フロップに、クロック同期式インバータＣＩ5 の出力が“Ｈ”になるようにデータがラッチされているため、ビット線は０Ｖである。“１”又は“２”書き込みの場合は、ビット線はＶccに充電される。
【００７４】
続いて、信号ＢＬＣ，ＶＲＦＹ2 ，ＦＩＭ，ＦＩＬと電圧ＶSAが１０Ｖ、電圧ＶBLH が８Ｖ、電圧ＶBLM が７Ｖとなる。“１”書き込みの場合は、クロック同期式インバータＣＩ7 ，ＣＩ8 で構成されるフリップ・フロップに、クロック同期式インバータＣＩ7 の出力が“Ｈ”になるようにデータがラッチされているため、ビット線ＢＬには７Ｖが印加される。“２”書き込みの場合はビット線は８Ｖ、“０”書き込みの場合は０Ｖとなる。この後、選択された制御ゲートＷＬが−１２Ｖとされる。
【００７５】
“１”又は“２”書き込みの場合は、ビット線ＢＬと制御ゲートＷＬの電位差によって電子がメモリセルの電荷蓄積層から放出され、メモリセルのしきい値は下降する。“１”書き込みの場合は、“２”書き込みに比較してメモリセルの電荷蓄積層から放出すべき電荷量を少なくしなければならないため、ビット線ＢＬを７Ｖにして制御ゲートＷＬとの電位差を１９Ｖに緩和している。“０”書き込み時は、ビット線電圧０Ｖによってメモリセルのしきい値は実効的には変わらない。
【００７６】
書き込み動作後に、メモリセルの書き込み状態を確認し書き込み不足のメモリセルにのみ追加書き込みを行うため、ベリファイ読み出しが行われる。ベリファイ読み出し中は、電圧ＶBLH はＶcc、ＦＩＭは０Ｖである。
【００７７】
ベリファイ読み出しは、２つの基本サイクルから実行される。この基本サイクルは読み出し第１サイクルに似ている。違うのは、選択された制御ゲートＷＬの電圧と、信号ＶＲＦＹ1 ，ＶＲＦＹ2 ，ＦＩＨが出力されることである（ベリファイ読み出し第１サイクルではＶＲＦＹ1 のみ）。信号ＶＲＦＹ1 ，ＶＲＦＹ2 ，ＦＩＨは、制御ゲートＷＬが０Ｖにリセットされた後で信号ＳＥＮ1 ，ＳＥＮ1B，ＬＡＴ1 ，ＬＡＴ1Bがそれぞれ“Ｌ”，“Ｈ”，“Ｌ”，“Ｈ”になる前に出力される。言い替えると、ビット線の電位がメモリセルのしきい値によって決定した後で、クロック同期式インバータＣＩ5 ，ＣＩ6 で構成されるフリップ・フロップがリセットされる前である。選択された制御ゲートＷＬの電圧は、読み出し時の２．５Ｖ（第１サイクル）、Ｖcc（第２サイクル）に対応して、２Ｖ（第１サイクル）、４Ｖ（第２サイクル）と、しきい値マージンを確保するために低くしてある。
【００７８】
ここでは、クロック同期式インバータＣＩ5 ，ＣＩ6 で構成されるフリップ・フロップにラッチされているデータ（ｄａｔａ１）、クロック同期式インバータＣＩ7 ，ＣＩ8 で構成されるフリップ・フロップにラッチされているデータ（ｄａｔａ２）と選択されたメモリセルのしきい値によって決まるビット線ＢＬの電圧を説明する。ｄａｔａ１は「“０”書き込みか、“１”又は“２”書き込みか」を制御し、“０”書き込みの場合はＱｎ20は“ＯＮ”状態、“１”又は“２”書き込みの場合はＱｎ23が“ＯＮ”状態である。ｄａｔａ２は「“１”書き込みか、“２”書き込みか」を制御し、“１”書き込みの場合はＱｎ26は“ＯＮ”状態、“２”書き込みの場合はＱｎ27が“ＯＮ”状態である。
【００７９】
“０”データ書き込み時（初期書き込みデータが“０”）のベリファイ読み出し第１サイクルでは、メモリセルのデータが“０”であるから、制御ゲートＷＬが２Ｖになってもビット線電位は“Ｈ”のままである。その後信号ＶＲＦＹ1 が“Ｈ”となることでビット線ＢＬは“Ｌ”となる。
【００８０】
“１”データ書き込み時（初期書き込みデータが“１”）のベリファイ読み出し第１サイクルでは、メモリセルのデータが“１”となるはずであるからメモリセルのしきい値は２．５Ｖ以上で、制御ゲートＷＬが２Ｖになってもビット線電位は“Ｈ”のままである。その後信号ＶＲＦＹ1 が“Ｈ”となることで、既に“１”書き込み十分でｄａｔａ１が“０”書き込みを示している場合ビット線ＢＬは“Ｌ”（図１４の(2) ）、さもなくばビット線ＢＬは“Ｈ”（図１４の(1) ）となる。
【００８１】
“２”データ書き込み時（初期書き込みデータが“２”）のベリファイ読み出し第１サイクルでは、選択メモリセルのデータが“２”となっていない（“２”書き込み不十分）場合、制御ゲートＷＬが２Ｖになってもビット線電位は“Ｈ”である（図１４の(3) ）。選択メモリセルが“２”書き込み十分になっている場合、制御ゲートＷＬが２Ｖになるとビット線電位はメモリセルによって“Ｌ”となる（図１４の(4)(5)）。図１４の(5) は既に“２”書き込み十分でｄａｔａ１が“０”書き込みを示している場合である。この場合、信号ＶＲＦＹ1 が“Ｈ”となることで、ビット線ＢＬは接地される。
【００８２】
“０”データ書き込み時（初期書き込みデータが“０”）のベリファイ読み出し第２サイクルでは、メモリセルのデータが“０”であるから、制御ゲートＣＧ4 が４Ｖになってもビット線電位は“Ｈ”である。その後、信号ＶＲＦＹ1 が“Ｈ”となることでビット線ＢＬは“Ｌ”となる。
【００８３】
“１”データ書き込み時（初期書き込みデータが“１”）のベリファイ読み出し第２サイクルでは、選択メモリセルのデータが“１”となっていない（“１”書き込み不十分）場合、制御ゲートＷＬが４Ｖになってもビット線電位は“Ｈ”である（図１４の(6) ）。選択メモリセルが“１”書き込み十分になっている場合、制御ゲートＷＬが４Ｖになるとメモリセルによりビット線電位は“Ｌ”となる（図１４の(7)(8)）。図１４の(8) は既に“１”書き込み十分でｄａｔａ１が“０”書き込みを示している場合である。この場合、信号ＶＲＦＹ1 が“Ｈ”となることで、ビット線ＢＬは接地される。
【００８４】
“２”データ書き込み時（初期書き込みデータが“２”）のベリファイ読み出し第２サイクルでは、メモリセルのデータが“２”となるはずであるからメモリセルのしきい値が４Ｖ以下であれば“２”書き込み十分でも不十分でも、制御ゲートＷＬが４Ｖになるとビット線電位は“Ｌ”となる（図１４の(10)(11)）。“２”書き込み不十分でメモリセルのしきい値が４Ｖ以上の場合、ビット線は“Ｈ”になる（図１４の(9) ）。
【００８５】
その後、信号ＶＲＦＹ1 ，ＶＲＦＹ2 ，ＦＩＨが“Ｈ”となることで、既に“２”書き込み十分でｄａｔａ１が“０”書き込みを示している場合ビット線ＢＬは“Ｌ”（図１４の(11)）、さもなくばビット線ＢＬは“Ｈ”（図１４の(9)(10) ）となる。
【００８６】
このベリファイ読み出し動作によって、書き込みデータとメモリセルの書き込み状態から再書き込みデータが、第１の実施例と同様に表１のように設定される。また、全てのメモリセルでデータ書き込みが十分になると、全てのカラムのＱｎ30が“ＯＦＦ”となり、信号ＰＥＮＤＢによってデータ書き込み終了情報が出力される。
【００８７】
データの入出力動作タイミング、データ書き込みアルゴリズム、追加データ書き込みアルゴリズムなどは、図７〜９、（表２〜３）に見られるように第１の実施例と同様である。
【００８８】
図１５は、このように構成されたＥＥＰＲＯＭでの、メモリセルのしきい値の書き込み特性を示している。“１”データが書き込まれるメモリセルと“２”データが書き込まれるメモリセルは同時に書き込みが行われ、それぞれ独立に書き込み時間が制御される。
【００８９】
下記の（表５）は、消去、書き込み、読み出し、ベリファイ読み出し時のメモリセルアレイ各部の電位を示している。
【００９０】
【表５】

【００９１】
図３，１１に示した回路は、例えばそれぞれ図１６，１７のように変形できる。図１６は、図２に見られるＱｎ3 ，Ｑｎ4 をｐチャネルのＭＯＳトランジスタＱｐ1 ，Ｑｐ2 に置き換えてある。図１７は、図１１に見られるＱｎ22，Ｑｎ23，Ｑｎ25〜Ｑｎ28をｐチャネルのＭＯＳトランジスタＱｐ3 〜Ｑｐ8 に置き換えてある。このようにすることで、ｎチャネルＭＯＳトランジスタのしきい値による転送できる電圧の降下を防ぐことができ、この例では、電圧ＶSAを書き込み時に８Ｖまで上げればよく回路を構成するトランジスタの耐圧を下げることができる。図１６のＶＲＦＹ1Bは図２，３のＶＲＦＹ1 の反転信号、図１７のＶＲＦＹ2B，ＦＩＬＢ，ＦＩＭＢは図１１のＶＲＦＹ2 ，ＦＩＬ，ＦＩＭのそれぞれ反転信号である。
【００９２】
図８で、追加データ書き込みについて説明したが、例えば図１８のように追加データ書き込みを容易にするため、１ページを分割しておくことも１つの有効な方法である。この例では論理アドレス３２番地毎にメモリセル２２個で１つの領域を構成する。これによって領域単位での追加データ書き込みは容易となる。つまり領域２に追加データ書き込みをする場合、領域２以外の領域の書き込みデータを全て“０”として、図９（ａ）に見られるデータ書き込みアルゴリズムに従って行えばよい。１つの領域のサイズは図１８に示している以外の大きさでもかまわない。
【００９３】
【発明の効果】
以上説明したように本発明によれば、対応するメモリセルに書き込まれるｎ値の書き込みデータを２以上のバイナリデータの組み合わせで記憶し、対応するメモリセルから読み出されるｎ値の読み出しデータを２以上のバイナリデータの組み合わせで記憶する複数のデータラッチ回路を設けることにより、外部とは実質的に２値でデータの授受を行うことができ、従って２値のデータを基に動作するコンピュータとの整合をとることが可能となる。
【図面の簡単な説明】
【図１】第１及び第２の実施例に係わるＥＥＰＲＯＭの概略構成を示すブロック図。
【図２】第１の実施例におけるメモリセルアレイの具体的構成を示す図。
【図３】第１の実施例におけるビット線制御回路の具体的構成を示す図。
【図４】第１の実施例における読み出し動作を示すタイミング図。
【図５】第１の実施例における書き込み動作を示すタイミング図。
【図６】第１の実施例におけるベリファイ読み出し動作を示すタイミング図。
【図７】第１及び第２の実施例におけるデータの入出力動作を示すタイミング図。
【図８】第１及び第２の実施例における書き込み／読み出し単位のページの概念を示す図。
【図９】第１，第２の実施例におけるデータ書き込み及び追加データ書き込みアルゴリズムを示す図。
【図１０】第１の実施例におけるメモリセルの書き込み特性を示す図。
【図１１】第２の実施例におけるメモリセルアレイとビット線制御回路の構成を示す図。
【図１２】第２の実施例における読み出し動作を示すタイミング図。
【図１３】第２の実施例における書き込み動作を示すタイミング図。
【図１４】第２の実施例におけるベリファイ読み出し動作を示すタイミング図。
【図１５】第２の実施例におけるメモリセルの書き込み特性を示す図。
【図１６】第１の実施例におけるビット線制御回路の変形例を示す図。
【図１７】第２の実施例におけるビット線制御回路の変形例を示す図。
【図１８】第１及び第２の実施例における追加データ書き込みの単位を示す図。
【図１９】図３に示すインバータ部分の具体的構成例を示す図。
【符号の説明】
１…メモリセルアレイ
２…ビット線制御回路
３…カラム・デコーダ
４…データ書き込み終了検知回路
５…入出力データ変換回路
６…データ入出力バッファ
７…ワード線駆動回路
８…ロウ・デコーダ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electrically rewritable nonvolatile semiconductor memory device (EEPROM), and more particularly to an EEPROM that performs multi-value storage in which more than one bit of information is stored in one memory cell.
[0002]
[Prior art]
As one type of EEPROM, a NAND type EEPROM capable of high integration is known. In this method, a plurality of memory cells are connected in series in such a manner that their sources and drains are shared by adjacent ones, and connected as a unit to a bit line. A memory cell usually has a FETMOS structure in which a charge storage layer and a control gate are stacked. The memory cell array is integrated in a p-type well formed on a p-type substrate or an n-type substrate. The drain side of the NAND cell is connected to the bit line via the selection gate, and the source side is also connected to the common source line via the selection gate. The control gates of the memory cells are continuously arranged in the row direction to become word lines.
[0003]
The operation of this NAND cell type EEPROM is as follows. Data writing is performed in order from the memory cell farthest from the bit line. A high voltage Vpp (about 20V) is applied to the control gate of the selected memory cell, and an intermediate voltage Vppm (= about 10V) is applied to the control gate and the selection gate of the memory cell on the bit line side. The bit line is supplied with 0V or an intermediate voltage Vm (= about 8V) according to the data. When 0V is applied to the bit line, the potential is transferred to the drain of the selected memory cell, and electrons are injected into the charge stack. As a result, the threshold value of the selected memory cell is shifted in the positive direction. This state is, for example, “1”. When Vm is applied to the bit line, electron injection does not occur effectively, so the threshold value does not change and remains negative. This state is "0" in the erased state. Data writing is performed simultaneously on the memory cells sharing the control gate.
[0004]
Data erasure is performed simultaneously on all the memory cells in the NAND cell. That is, all control gates are set to 0V, and the p-type well is set to 20V. At this time, the selection gate, bit line, and source line are also set to 20V. As a result, electrons in the charge storage layer are emitted to the p-type well in all the memory cells, and the threshold value is shifted in the negative direction.
[0005]
In data reading, the control gate of the selected memory cell is set to 0 V, and the control gate and select gate of the other memory cells are set to the power supply potential Vcc (for example, 5 V) to detect whether a current flows in the selected memory cell. Is done.
[0006]
Due to restrictions on the read operation, the threshold value after writing “1” must be controlled between 0 V and Vcc. For this reason, write verify is performed, only the memory cells insufficiently written “1” are detected, and rewrite data is set so that only the memory cells insufficiently written “1” are rewritten (bit-by-bit verification). . A memory cell in which “1” is insufficiently written is detected by reading the selected control gate at 0.5 V (verify voltage) (verify read).
[0007]
That is, if the threshold value of the memory cell is not 0.5 V or more with a margin with respect to 0 V, a current flows in the selected memory cell, and it is detected that “1” writing is insufficient. Since a current naturally flows in the memory cell in the “0” write state, a circuit called a verify circuit that compensates the current flowing through the memory cell is provided so that the memory cell is not mistaken for “1” write shortage. This verify circuit executes write verify at high speed.
[0008]
By writing data while repeating the write operation and the write verify, the write time is optimized for each memory cell, and the threshold value after writing “1” is controlled between 0V and Vcc.
[0009]
In order to realize multi-value storage with this NAND cell type EEPROM, for example, it is considered that there are three states after writing, “0”, “1”, and “2”. The threshold value is negative in the “0” write state, the threshold value is 0 V to 1/2 Vcc, for example, in the “1” write state, and the threshold value is 1/2 Vcc to Vcc in the “2” write state. In the conventional verify circuit, it is possible to prevent a memory cell to be in a “0” write state from being mistaken as a memory cell insufficiently written to “1” or “2”.
[0010]
However, since the conventional verify circuit is not for multi-value storage, the threshold value of the memory cell in the “2” write state is equal to or higher than the verify voltage for detecting whether or not “1” write is insufficient. In the case of a write shortage state of 2 Vcc or less, there is a problem in that when detecting whether or not “1” write is short, current does not flow in the memory cell, and it is mistakenly recognized that writing is sufficient.
[0011]
Further, in order to prevent misidentification of insufficient writing and to perform multi-valued write verification, rewriting is performed on a memory cell that is in a “2” write state with respect to a memory cell in which “1” is sufficiently written, and “ It is only necessary to perform verify writing by detecting whether or not 2 "writing is insufficient. However, in this case, since the “2” write state is set to the “2” write state after the “1” write, the write operation takes time and the write speed is slowed down.
[0012]
In addition, there is a problem that the multi-value storage EEPROM is difficult to be compatible with a computer that operates based on binary data, and this also causes a decrease in the operation speed of the EEPROM.
[0013]
[Problems to be solved by the invention]
As described above, when multi-value storage is performed in the conventional NAND cell type EEPROM and the bit-by-bit verification is performed by the conventional verify circuit, there is a problem that erroneous verification occurs. Further, in the case of a multi-value EEPROM, there is a problem in that data exchange with a computer that processes binary data becomes complicated, and as a result, the operation speed of the EEPROM decreases.
[0014]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an EEPROM that can store multi-level information and can exchange data with the outside in binary. It is to provide.
[0015]
[Means for Solving the Problems]
(Constitution)
In order to solve the above problems, the present invention employs the following configuration.
[0016]
That is, according to the present invention, in a multi-value storage nonvolatile semiconductor memory device, a plurality of memory cells that can be electrically rewritten and have n storage states (n ≧ 3) are arranged in a matrix. A memory cell array, a plurality of bit lines connected to the memory cell array, a plurality of word lines connected to the memory cell array, each provided for each bit line, each of two or more binary data Composed of a latch circuit, n-value write data written to the corresponding memory cell is stored as a combination of two or more binary data, and n-value read data read from the corresponding memory cell is a combination of two or more binary data And a plurality of data latch circuits for storing the data.
[0017]
Further, according to the present invention, in a multi-value storage nonvolatile semiconductor memory device, a plurality of memory cells that can be electrically rewritten and have n storage states (n ≧ 3) are arranged in a matrix. A memory cell array; a plurality of bit lines connected to the memory cell array; a plurality of word lines connected to the memory cell array; a data input buffer to which write data is input; and two or more write data to be written A data conversion circuit for converting to binary data, each provided for each bit line, each composed of two or more binary data latch circuits, and writing n-value write data written in the corresponding memory cell A plurality of data latch circuits for storing a combination of two or more write binary data; To.
[0018]
Further, according to the present invention, in a multi-value storage nonvolatile semiconductor memory device, a plurality of memory cells that can be electrically rewritten and have n storage states (n ≧ 3) are arranged in a matrix. A memory cell array, a plurality of bit lines connected to the memory cell array, a plurality of word lines connected to the memory cell array, each provided for each bit line, each of two or more binary data A plurality of data latch circuits configured by a latch circuit and storing n-value read data read from corresponding memory cells as a combination of two or more read binary data, and the two or more read binary data read data And a data output circuit for outputting the read data. To.
[0019]
(Function)
In the multi-value (n-value) storage type EEPROM according to the present invention, n-value write data written to the corresponding memory cell is stored as a combination of two or more binary data, and the n-value read from the corresponding memory cell is read. By providing a plurality of data latch circuits that store data in a combination of two or more binary data, data can be exchanged with the outside in binary. Therefore, matching with a computer that operates based on binary data can be achieved.
[0020]
【Example】
Embodiments of the present invention will be described below with reference to the drawings.
[0021]
FIG. 1 is a block diagram showing a schematic configuration of a NAND cell type EEPROM according to the first embodiment of the present invention.
[0022]
The memory cell array 1 is provided with a bit line control circuit 2 for controlling a bit line at the time of reading / writing and a word line driving circuit 7 for controlling a word line potential. The bit line control circuit 2 and the word line drive circuit 7 are selected by the column decoder 3 and the row decoder 8, respectively. The bit line control circuit 2 exchanges read data / write data with the input / output data conversion circuit 5 via a data input / output line (IO line). The input / output data conversion circuit 5 converts the read multi-value information of the memory cell into binary information for output to the outside, and converts the binary information of the write data input from the outside into the multi-value information of the memory cell. Convert. The input / output data conversion circuit 5 is connected to a data input / output buffer 6 that controls data input / output with the outside. The data writing end detection circuit 4 detects whether or not the data writing has ended.
[0023]
2 and 3 show specific configurations of the memory cell array 1 and the bit line control circuit 2. The memory cells M1 to M8 and the select transistors S1 and S2 constitute a NAND cell. One end of the NAND cell is connected to the bit line BL, and the other end is connected to the common source line Vs. The selection gates SG1 and SG2 and the control gates CG1 to CG8 are shared by a plurality of NAND cells, and the memory cells sharing one control gate constitute a page. The memory cell stores data at the threshold value Vt. When Vt is 0 V or less, “0” data, when Vt is 0 V or more and 1.5 V or less, “1” data, Vt is 1.5 V or more and power supply voltage or less. In this case, it is stored as “2” data. One memory cell has three states, and two memory cells can be combined in nine ways. Of these, eight combinations are used to store 3-bit data in two memory cells. In this embodiment, 3-bit data is stored in a set of two adjacent memory cells sharing a control gate. The memory cell array 1 is formed on a dedicated p-well.
[0024]
The clock synchronous inverters CI1, CI2, CI3, and CI4 constitute a flip-flop, and latch write / read data. They also operate as sense amplifiers. The flip-flop composed of the clock synchronous inverters CI1 and CI2 latches “whether“ 0 ”is written,“ 1 ”or“ 2 ”is written” ”as write data information, and the memory cell“ Whether “0” information is held or “1” or “2” information is held ”is latched as read data information. The flip-flop composed of the clock synchronous inverters CI3 and CI4 latches “1” or “2” write ”as write data information, and the memory cell is“ 2 ”. Whether information is held or “0” or “1” is held ”is latched as read data information.
[0025]
Among the n-channel MOS transistors, Qn1 transfers the voltage VPR to the bit line when the precharge signal PRE becomes "H". In Qn2, the bit line connection signal BLC becomes "H" to connect the bit line and the main bit line control circuit. Qn3 to Qn6 and Qn9 to Qn12 selectively transfer the voltages VBLH, VBLM, and VBLL to the bit lines in accordance with the data latched by the flip-flop. Qn7 and Qn8 connect the flip-flop and the bit line when the signals SAC2 and SAC1 become "H", respectively. Qn13 is provided for detecting whether or not the data for one page latched in the flip-flop is all the same. Qn14, Qn15 and Qn16, Qn17 are respectively connected to the corresponding flip-flops and data input / output lines IOA, IOB by the column selection signals CSL1, CSL2 being "H".
[0026]
In FIG. 3, the inverter portion is omitted as shown in FIG. 19A, but this has the circuit configuration shown in FIG. 19B.
[0027]
Next, the operation of the thus configured EEPROM will be described with reference to FIGS. 4 shows the timing of the read operation, FIG. 5 shows the timing of the write operation, and FIG. 6 shows the timing of the verify read operation. In either case, the control gate CG4 is selected as an example.
[0028]
A read operation is performed in two basic cycles. In the first read cycle, first, the voltage VPR becomes the power supply voltage Vcc and the bit line is precharged, and the precharge signal PRE becomes “L” and the bit line is floated. Subsequently, the selection gates SG1 and SG2, and the control gates CG1 to CG3 and CG5 to CG8 are set to Vcc. At the same time, the control gate CG4 is set to 1.5V. Only when the Vt of the selected memory cell is 1.5 V or more, that is, only when data “2” is written, the bit line is held at the “H” level.
[0029]
Thereafter, the sense activation signals SEN2 and SEN2B become "L" and "H", respectively, and the latch activation signals LAT2 and LAT2B become "L" and "H", respectively, and are constituted by clock synchronous inverters CI3 and CI4. The flip-flop that is reset is reset. The signal SAC2 becomes "H" and the flip-flop composed of the clock synchronous inverters CI3 and CI4 and the bit line are connected. First, the sense activation signals SEN2 and SEN2B become "H" and "L", respectively. After the bit line potential is sensed, the latch activation signals LAT2 and LAT2B become “H” and “L”, respectively, and “2” data is supplied to the flip-flop formed by the clock synchronous inverters CI3 and CI4. Information of “1” or “0” data ”is latched.
[0030]
The second read cycle is the same as the first read cycle, and the voltage of the selection control gate CG4 is 0V instead of 1.5V. Signals SEN1, SEN1B, LAT1, LAT1B, LAT2B, SAC2 instead of the signals SEN2, SEN2B, LAT2, LAT2B, SAC2 The difference is that SAC1 is output. Therefore, in the second read cycle, the information “0”, “1” or “2” data ”is latched in the flip-flop formed by the clock synchronous inverters CI1 and CI2.
[0031]
The data written in the memory cell is read by the two read cycles described above.
[0032]
Prior to data writing, the data in the memory cell is erased, and the threshold value Vt of the memory cell is 0 V or less. Erasing is performed with the p-well, common source line Vs and select gates SG1 and SG2 set to 20V, and the control gates CG1 to CG8 set to 0V.
[0033]
In the write operation, first, the precharge signal PRE becomes “L” and the bit line is floated. The selection gate SG1 is set to Vcc, and the control gates CG1 to CG8 are set to Vcc. Select gate SG2 is at 0V during the write operation. At the same time, the signals VRFY1, VRFY2, FIM and FIH become Vcc. In the case of writing “0”, the data is latched in the flip-flop composed of the clock synchronous inverters CI1 and CI2 so that the output of the clock synchronous inverter CI1 becomes “H”. Charged by Vcc. In the case of “1” or “2” writing, the bit line is 0V.
[0034]
Subsequently, the selection gate SG1, the control gates CG1 to CG8, the signal BLC, the signal VRFY1 and the voltage VSA are 10V, the voltage VBLH is 8V, and the voltage VBLM is 1V. In the case of writing “1”, since the data is latched in the flip-flop composed of the clock synchronous inverters CI3 and CI4 so that the output of the clock synchronous inverter CI3 becomes “H”, the bit line BL 1V is applied to. When “2” is written, the bit line is 0V, and when “0” is written, 8V. Thereafter, the selected control gate CG4 is set to 20V.
[0035]
In the case of “1” or “2” writing, electrons are injected into the charge storage layer of the memory cell due to the potential difference between the bit line BL and the control gate CG4, and the threshold value of the memory cell rises. In the case of “1” writing, since the amount of charge to be injected into the charge storage layer of the memory cell has to be reduced compared to “2” writing, the bit line BL is set to 1 V and the potential difference from the control gate CG4 is set. Relaxed to 19V. However, this can be done without reducing the potential difference. When "0" is written, the threshold value of the memory cell is not effectively changed by the bit line voltage 8V.
[0036]
At the end of the write operation, first, the selection gate SG1 and the control gates CG1 to CG8 are set to 0V, and the voltage 8V of the bit line BL when "0" is written is reset to 0V with a delay. This is because if this order is reversed, a state of “2” or “1” write operation is temporarily created, and wrong data is written when “0” is written.
[0037]
After the write operation, verify read is performed because the write state of the memory cell is confirmed and additional write is performed only to the memory cell that is insufficiently written. During the verify read, the voltage VBLH is Vcc, VBLL is 0V, and FIM is 0V.
[0038]
The verify read is executed from two basic cycles. This basic cycle is similar to the second read cycle. The difference is that the voltage of the selected control gate CG4 and the signals VRFY1, VRFY2, and FIH are output (only VRFY1 in the first verify read cycle). The signals VRFY1, VRFY2, and FIH are the signals SEN1, SEN1B, LAT1, and LAT1B that are "L", "H", "L", and "LAT", respectively, after the selection gates SG1 and SG2 and the control gates CG1 to CG8 are reset to 0V. Output before H ”. In other words, after the potential of the bit line is determined by the threshold value of the memory cell, it is before the flip-flop composed of the clock synchronous inverters CI1 and CI2 is reset. The voltage of the selected control gate CG4 is 2V (first cycle), 0.5V (second cycle) corresponding to 1.5V (first cycle) and 0V (second cycle) at the time of reading, The threshold is increased to ensure a threshold margin of 0.5V.
[0039]
Here, data latched in the flip-flop composed of clock synchronous inverters CI1, CI2 (data1) and data latched in the flip-flop composed of clock synchronous inverters CI3, CI4 (data2) The voltage of the bit line BL determined by the threshold value of the selected memory cell will be described. data1 controls whether “0” write, “1” or “2” write is performed. Qn3 is in the “ON” state for “0” write, and Qn6 is set for “1” or “2” write. “ON” state. Data 2 controls ““ 1 ”writing or“ 2 ”writing”. In the case of “1” writing, Qn 10 is in the “ON” state, and in the case of “2” writing, Qn 11 is in the “ON” state.
[0040]
In the first verify read cycle when “0” data is written (initial write data is “0”), the data in the memory cell is “0”. Therefore, when the control gate CG4 becomes 2V, the bit line potential is “ L ". Thereafter, the signal VRFY1 becomes "H", so that the bit line BL becomes "H".
[0041]
In the first cycle of verify read when “1” data is written (initial write data is “1”), the memory cell data should be “1”, so the threshold value of the memory cell is 1.5 V or less. When the control gate CG4 becomes 2V, the bit line potential becomes "L" by the memory cell. After that, when the signal VRFY1 becomes "H", if "1" writing is sufficient and data1 indicates "0" writing, the bit line BL is "H" ((1) in FIG. 6). The line BL becomes “L” ((2) in FIG. 6).
[0042]
In the first verify read cycle when “2” data is written (initial write data is “2”), if the data in the selected memory cell is not “2” (“2” write is insufficient), the control gate CG4 When the voltage becomes 2 V, the bit line potential becomes “L” by the memory cell ((5) in FIG. 6). When the selected memory cell is sufficiently “2” written, the bit line potential remains “H” even when the control gate CG4 becomes 2V ((3) and (4) in FIG. 6). FIG. 6 (3) shows a case where “2” writing is already sufficient and data1 indicates “0” writing. In this case, when the signal VRFY1 becomes "H", the bit line BL is recharged by the voltage VBH.
[0043]
In the second verify read second cycle when “0” data is written (initial write data is “0”), the data in the memory cell is “0”. Therefore, when the control gate CG4 becomes 0.5 V, the bit line potential is set by the memory cell. Becomes “L”. Thereafter, the signal line VRFY1 becomes "H", so that the bit line BL becomes "H".
[0044]
In the second verify read second cycle when “1” data is written (initial write data is “1”), if the data of the selected memory cell is not “1” (“1” is insufficiently written), the control gate CG4 When the voltage reaches 0.5 V, the bit line potential becomes “L” by the memory cell ((8) in FIG. 6). When the selected memory cell is sufficiently “1” written, the bit line potential remains “H” even when the control gate CG4 becomes 0.5 V ((6) and (7) in FIG. 6). FIG. 6 (6) shows a case where “1” writing is already sufficient and data1 indicates “0” writing. In this case, when the signal VRFY1 becomes "H", the bit line BL is recharged by the voltage VBH.
[0045]
In the second cycle of verify read when “2” data is written (initial write data is “2”), the memory cell data should be “2”. For example, even if “2” writing is sufficient or insufficient, the bit line potential remains “H” even when the control gate CG4 becomes 0.5 V ((9) (10) in FIG. 6). When “2” writing is insufficient and the threshold value of the memory cell is 0.5 V or less, the bit line becomes “L” ((11) in FIG. 6).
[0046]
Thereafter, when the signals VRFY1, VRFY2, and FIH become "H", "2" writing is sufficient and data1 indicates "0" writing, the bit line BL is "H" ((9) in FIG. 6). Otherwise, the bit line BL becomes “L” ((10) (11) in FIG. 6).
[0047]
By this verify read operation, rewrite data is set as shown in the following (Table 1) from the write data and the write state of the memory cell.
[0048]
[Table 1]

[0049]
As can be seen from (Table 1), “1” write is performed again only for the memory cells that are insufficiently written “1”, and “2” is rewritten only for the memory cells that are insufficiently written “2”. . When data writing is sufficient in all memory cells, Qn13 of all columns is turned “OFF”, and data writing end information is output by a signal PENDB.
[0050]
FIG. 7 shows the data input / output operation timing, where (a) is the data input timing and (b) is the data output timing. After three cycles of data input from the outside, the input / output data conversion circuit 5 generates and inputs data to be input to the bit line control circuit 2. Data (X1, X2, X3) for 3 bits from the outside is converted into data (Y1, Y2) of two memory cells, and is effectively converted by the clock synchronous inverters CI1, CI2 of the bit line control circuit 2. Conversion data is set via the data input / output lines IOA and IOB in the register R2 including the register R1 and CI3 and CI4. The read data latched in the registers R1 and R2 is transferred to the input / output data conversion circuit 5 via the data input / output lines IOA and IOB, converted and output. The column selection signals CSL1i and CSL2i shown in FIG. 3 can be made the same signal, and instead, IOA and IOB can be divided into two systems and two registers in the same column can be easily accessed simultaneously to shorten the access time. It is effective for this purpose.
[0051]
The following (Table 2) shows three bits of data (X1, X2, X3) from the outside at the time of data input, two data (Y1, Y2) of the memory cells, and registers R1, Y2 corresponding to Y1, Y2, respectively. The relationship of R2 data is shown.
[0052]
[Table 2]

[0053]
The register data is represented by the voltage level of the input / output line IOA at the time of data transfer. The data input / output line IOB is omitted because it is an inverted signal of IOA. The following (Table 3) is that at the time of data output.
[0054]
[Table 3]

[0055]
In this embodiment, for the same data, the IOA level at the time of input and the IOA level at the time of output are inverted.
[0056]
One of the nine combinations of the two data (Y1, Y2) of the memory cells is left, so that it can be used for file management information such as pointer information. Here, the pointer information is made to correspond to the cell data (Y1, Y2) = (2, 2).
[0057]
FIG. 8 shows the concept of a page which is a unit of data writing when viewed from a microprocessor or the like that controls the EEPROM. Here, one page is N bytes, and an address (logical address) as viewed from a microprocessor or the like is displayed. For example, when write data is input only in the area 1 (logical addresses 0 to n), there is no problem because (X1, X2, X3) is always provided if n = 3m + 2 (m = 0, 1, 2,...). . When n = 3 m, only X1 is input. Therefore, X2 = 0 and X3 = 0 are generated in the EEPROM and (X1, X2, X3) is input to the input / output data conversion circuit 5. When n = 3m + 1, X3 = 0 is generated internally. The same applies when n is equal to N.
[0058]
When data is written to area 1 (all data written in area 2 is “0”), when data is additionally written to area 2, the area 1 is read and the area 2 is written to that data. You can add additional data. Alternatively, the part of area 1 is read out, and if the first address of area 2 is n + 1 = 3m, all the data in area 1 is “0”, and if n + 1 = 3m + 2, the data of addresses n−1 and n are addressed as X1 and X2. In addition to the n + 1 data X3, all the data up to the address n-2 in the area 1 is "0". All data up to the address n−1 may be “0”. These operations can be easily performed automatically in the EEPROM. The relationship between (X1, X2, X3) and (Y1, Y2) is established as shown in (Table 2) and (Table 3) so that this additional data can be written. The relationship between (X1, X2, X3) and (Y1, Y2) shown in (Table 2) and (Table 3) is one example and is not limited to this. Also, additional data can be written in the same manner even if the area is three or more.
[0059]
FIG. 9A shows a data writing algorithm. After the data load, the write, verify read and write end detection operations are repeated. The dotted line is automatically performed in the EEPROM.
[0060]
FIG. 9B shows an additional data writing algorithm. After reading and data loading, verify read, write end detection and write operation are repeated. The dotted line is automatically performed in the EEPROM. The reason why the verify read is performed after the data load is to prevent the write from being performed where “1” or “2” has already been written. Otherwise, overwriting may occur.
[0061]
FIG. 10 shows the write characteristics of the threshold value of the memory cell in the thus configured EEPROM. A memory cell to which “1” data is written and a memory cell to which “2” data is written are simultaneously written, and the writing time is controlled independently.
[0062]
Table 4 below shows the potential of each part of the memory cell array at the time of erasing, writing, reading, and verify reading.
[0063]
[Table 4]

[0064]
FIG. 11 shows a specific configuration of the memory cell array 1 and the bit line control circuit 2 of the NOR cell type EEPROM according to the second embodiment of the present invention. Only the memory cell M10 constitutes a NOR type cell. One end of the NOR type cell is connected to the bit line BL, and the other end is connected to the common ground line. The memory cells M sharing one control gate WL constitute a page. The memory cell M stores data at the threshold value Vt. When Vt is Vcc or higher, “0” data, when Vt is Vcc or lower and 2.5 V or higher, “1” data, Vt is 2.5 V or lower and 0 V or higher In this case, it is stored as “2” data. One memory cell has three states, and two memory cells can be combined in nine ways. Of these, eight combinations are used to store 3-bit data in two memory cells. In this embodiment, 3-bit data is stored in a set of two adjacent memory cells sharing a control gate.
[0065]
The clock synchronous inverters CI5 and CI6 and CI7 and CI8 constitute flip-flops, respectively, and latch write / read data. It also operates as a sense amplifier. The flip-flop composed of the clock synchronous inverters CI5 and CI6 latches “whether“ 0 ”is written,“ 1 ”or“ 2 ”is written” ”as write data information, and the memory cell“ Whether “0” information is held or “1” or “2” information is held ”is latched as read data information. The flip-flop composed of clock synchronous inverters CI7 and CI8 latches “1” or “2” write ”as write data information, and the memory cell is“ 2 ”. Whether information is held or “0” or “1” is held ”is latched as read data information.
[0066]
Among the n-channel MOS transistors, Qn18 transfers the voltage VPR to the bit line when the precharge signal PRE becomes “H”. In Qn19, the bit line connection signal BLC becomes “H” to connect the bit line and the main bit line control circuit. Qn20 to Qn23 and Qn25 to Qn28 selectively transfer voltages VBLH, VBLM, and 0V to the bit lines in accordance with the data latched in the flip-flop. Qn24 and Q29 connect the flip-flop and the bit line when the signals SAC2 and SAC1 become "H", respectively. Qn30 is provided for detecting whether or not the data for one page latched in the flip-flop is all the same. In Qn31, Qn32 and Qn33, Qn34, the column selection signals CSL1, CSL2 become "H", respectively, and the corresponding flip-flops and the data input / output lines IOA, IOB are selectively connected.
[0067]
Next, the operation of the thus configured EEPROM will be described with reference to FIGS. 12 shows the timing of the read operation, FIG. 13 shows the timing of the write operation, and FIG. 14 shows the timing of the verify read operation.
[0068]
A read operation is performed in two basic cycles. In the first read cycle, first, the voltage VPR becomes the power supply voltage Vcc and the bit line is precharged, and the precharge signal PRE becomes “L” and the bit line is floated. Subsequently, the control gate WL is set to 2.5V. Only when Vt of the selected memory cell is 2.5 V or less, that is, only when data “2” is written, the bit line becomes “L” level.
[0069]
Thereafter, the sense activation signals SEN2 and SEN2B become "L" and "H", respectively, and the latch activation signals LAT2 and LAT2B become "L" and "H", respectively, and are constituted by clock synchronous inverters CI7 and CI8. The flip-flop that is reset is reset. The signal SAC2 becomes "H" and the flip-flop constituted by the clock synchronous inverters CI7 and CI8 and the bit line are connected. First, the sense activation signals SEN2 and SEN2B become "H" and "L", respectively. After the bit line potential is sensed, the latch activation signals LAT2 and LAT2B become “H” and “L”, respectively, and “2” data is supplied to the flip-flop constituted by the clock synchronous inverters CI7 and CI8. Information of “1” or “0” data is latched.
[0070]
The second read cycle is the same as the first read cycle, the voltage of the selection control gate WL is Vcc instead of 2.5V, and the signals SEN1, SEN1B, LAT1, LAT1B, The difference is that SAC1 is output. Accordingly, in the second read cycle, the information “0 data,“ 1 ”or“ 2 ”data” is latched in the flip-flop formed by the clock synchronous inverters CI5 and CI6.
[0071]
The data written in the memory cell is read by the two read cycles described above.
[0072]
Prior to data writing, the data in the memory cell is erased, and the threshold value Vt of the memory cell is equal to or higher than Vcc. Erasing is performed by setting the control gate WL to 20V and the bit line to 0V.
[0073]
In the write operation, first, the precharge signal PRE becomes “L” and the bit line is floated. The signals VRFY1, VRFY2, FIM, and FIL become Vcc. In the case of writing “2”, the data is latched so that the output of the clock synchronous inverter CI5 becomes “H” in the flip-flop composed of the clock synchronous inverters CI5 and CI6. 0V. In the case of writing “1” or “2”, the bit line is charged to Vcc.
[0074]
Subsequently, the signals BLC, VRFY2, FIM, FIL and the voltage VSA are 10V, the voltage VBLH is 8V, and the voltage VBLM is 7V. In the case of writing “1”, the data is latched in the flip-flop composed of the clock synchronous inverters CI7 and CI8 so that the output of the clock synchronous inverter CI7 becomes “H”. 7V is applied to. In the case of “2” writing, the bit line is 8V, and in the case of “0” writing, it is 0V. Thereafter, the selected control gate WL is set to −12V.
[0075]
In the case of “1” or “2” writing, electrons are released from the charge storage layer of the memory cell due to the potential difference between the bit line BL and the control gate WL, and the threshold value of the memory cell decreases. In the case of “1” writing, the amount of charge to be released from the charge storage layer of the memory cell has to be reduced as compared with “2” writing. Relaxed to 19V. When "0" is written, the threshold value of the memory cell is not effectively changed by the bit line voltage 0V.
[0076]
After the write operation, verify read is performed because the write state of the memory cell is confirmed and additional write is performed only to the memory cell that is insufficiently written. During the verify read, the voltage VBLH is Vcc and the FIM is 0V.
[0077]
The verify read is executed from two basic cycles. This basic cycle is similar to the first read cycle. The difference is that the voltage of the selected control gate WL and the signals VRFY1, VRFY2, and FIH are output (only VRFY1 in the first verify read cycle). The signals VRFY1, VRFY2, and FIH are output after the control gate WL is reset to 0 V and before the signals SEN1, SEN1B, LAT1, and LAT1B become “L”, “H”, “L”, and “H”, respectively. The In other words, after the bit line potential is determined by the threshold value of the memory cell, it is before the flip-flop composed of the clock synchronous inverters CI5 and CI6 is reset. The voltage of the selected control gate WL is 2V (first cycle) and 4V (second cycle) corresponding to 2.5 V (first cycle) and Vcc (second cycle) at the time of reading. The value is lowered to ensure a value margin.
[0078]
Here, the data latched in the flip-flop composed of clock synchronous inverters CI5 and CI6 (data1) and the data latched in the flip-flop composed of clock synchronous inverters CI7 and CI8 (data2) The voltage of the bit line BL determined by the threshold value of the selected memory cell will be described. Data1 controls whether “0” write, “1” or “2” write ”. In the case of“ 0 ”write, Qn20 is in the“ ON ”state, and in the case of“ 1 ”or“ 2 ”write, Qn23 is “ON” state. Data 2 controls ““ 1 ”write or“ 2 ”write”. In the case of “1” write, Qn 26 is in the “ON” state, and in the case of “2” write, Qn 27 is in the “ON” state.
[0079]
In the first verify read cycle when “0” data is written (initial write data is “0”), the data in the memory cell is “0”, so that the bit line potential is “H” even when the control gate WL becomes 2V. " Thereafter, the signal VRFY1 becomes "H", so that the bit line BL becomes "L".
[0080]
In the first verify read cycle when “1” data is written (initial write data is “1”), the memory cell threshold should be 2.5 V or more because the data in the memory cell should be “1”. Even when the control gate WL becomes 2V, the bit line potential remains “H”. Thereafter, when the signal VRFY1 becomes "H", "1" writing is sufficient and data1 indicates "0" writing, the bit line BL is "L" ((2) in FIG. 14), otherwise the bit The line BL becomes “H” ((1) in FIG. 14).
[0081]
In the first cycle of verify read when “2” data is written (initial write data is “2”), if the data of the selected memory cell is not “2” (“2” write is insufficient), the control gate WL Even if it becomes 2V, the bit line potential is "H" ((3) in FIG. 14). When the selected memory cell is sufficiently “2” written, when the control gate WL becomes 2V, the bit line potential becomes “L” by the memory cell ((4) and (5) in FIG. 14). (5) in FIG. 14 is a case where “2” writing is already sufficient and data1 indicates “0” writing. In this case, the bit line BL is grounded when the signal VRFY1 becomes "H".
[0082]
In the second verify read cycle when “0” data is written (initial write data is “0”), the data in the memory cell is “0”. Therefore, even if the control gate CG4 becomes 4V, the bit line potential is “H”. ". Thereafter, the signal line VRFY1 becomes "H", so that the bit line BL becomes "L".
[0083]
In the second verify read second cycle when “1” data is written (initial write data is “1”), if the data in the selected memory cell is not “1” (“1” is insufficiently written), the control gate WL Even if it becomes 4V, the bit line potential is "H" ((6) in FIG. 14). When the selected memory cell is sufficiently “1” written, the bit line potential is set to “L” by the memory cell when the control gate WL becomes 4 V ((7) and (8) in FIG. 14). (8) in FIG. 14 is a case where “1” writing is already sufficient and data1 indicates “0” writing. In this case, the bit line BL is grounded when the signal VRFY1 becomes "H".
[0084]
In the second verify read second cycle when “2” data is written (initial write data is “2”), the memory cell data should be “2”. Whether the 2 "write is sufficient or insufficient, the bit line potential becomes" L "when the control gate WL becomes 4V ((10) and (11) in FIG. 14). When “2” writing is insufficient and the threshold value of the memory cell is 4 V or more, the bit line becomes “H” ((9) in FIG. 14).
[0085]
After that, when the signals VRFY1, VRFY2, and FIH become "H", "2" writing is already sufficient and data1 indicates "0" writing, the bit line BL is "L" ((11) in FIG. 14). Otherwise, the bit line BL becomes "H" ((9) (10) in FIG. 14).
[0086]
By this verify read operation, the rewrite data is set as shown in Table 1 from the write data and the write state of the memory cell as in the first embodiment. When data writing is sufficient in all memory cells, Qn30 of all columns is turned “OFF”, and data writing end information is output by the signal PENDB.
[0087]
The data input / output operation timing, the data write algorithm, the additional data write algorithm, and the like are the same as those in the first embodiment as shown in FIGS.
[0088]
FIG. 15 shows the threshold value write characteristics of the memory cell in the thus configured EEPROM. A memory cell to which “1” data is written and a memory cell to which “2” data is written are simultaneously written, and the writing time is controlled independently.
[0089]
Table 5 below shows the potential of each part of the memory cell array at the time of erasing, writing, reading, and verify reading.
[0090]
[Table 5]

[0091]
The circuits shown in FIGS. 3 and 11 can be modified as shown in FIGS. 16 and 17, for example. In FIG. 16, Qn3 and Qn4 seen in FIG. 2 are replaced with p-channel MOS transistors Qp1 and Qp2. In FIG. 17, Qn22, Qn23, Qn25 to Qn28 shown in FIG. 11 are replaced with p-channel MOS transistors Qp3 to Qp8. By doing so, it is possible to prevent a drop in the voltage that can be transferred due to the threshold value of the n-channel MOS transistor. be able to. 16 is an inverted signal of VRFY1 in FIGS. 2 and 3, and VRFY2B, FILB, and FIMB in FIG. 17 are inverted signals of VRFY2, FIL, and FIM in FIG. 11, respectively.
[0092]
Although the additional data writing has been described with reference to FIG. 8, for example, dividing one page in order to facilitate additional data writing as shown in FIG. 18 is one effective method. In this example, one area is constituted by 22 memory cells for every 32 logical addresses. This makes it easy to write additional data in units of areas. That is, when additional data is written to the area 2, all the write data in the areas other than the area 2 are set to “0”, and the data writing algorithm shown in FIG. The size of one area may be other than that shown in FIG.
[0093]
【The invention's effect】
As described above, according to the present invention, n-value write data to be written to the corresponding memory cell is stored as a combination of two or more binary data, and two or more n-value read data to be read from the corresponding memory cell is stored. By providing a plurality of data latch circuits that store a combination of binary data, data can be exchanged with the outside in binary, so that it is compatible with a computer that operates based on binary data. It becomes possible to take.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of an EEPROM according to first and second embodiments.
FIG. 2 is a diagram showing a specific configuration of a memory cell array in the first embodiment.
FIG. 3 is a diagram showing a specific configuration of a bit line control circuit in the first embodiment.
FIG. 4 is a timing chart showing a read operation in the first embodiment.
FIG. 5 is a timing chart showing a write operation in the first embodiment.
FIG. 6 is a timing chart showing a verify read operation in the first embodiment.
FIG. 7 is a timing chart showing data input / output operations in the first and second embodiments.
FIG. 8 is a diagram showing the concept of a page of a write / read unit in the first and second embodiments.
FIG. 9 is a diagram showing data writing and additional data writing algorithms in the first and second embodiments.
FIG. 10 is a diagram showing the write characteristics of the memory cell in the first embodiment.
FIG. 11 is a diagram showing a configuration of a memory cell array and a bit line control circuit in a second embodiment.
FIG. 12 is a timing chart showing a read operation in the second embodiment.
FIG. 13 is a timing chart showing a write operation in the second embodiment.
FIG. 14 is a timing chart showing a verify read operation in the second embodiment.
FIG. 15 is a diagram showing a write characteristic of a memory cell in a second embodiment.
FIG. 16 is a diagram showing a modification of the bit line control circuit in the first embodiment.
FIG. 17 is a diagram showing a modification of the bit line control circuit in the second embodiment.
FIG. 18 is a diagram showing a unit for writing additional data in the first and second embodiments.
19 is a diagram showing a specific configuration example of the inverter part shown in FIG. 3;
[Explanation of symbols]
1 ... Memory cell array
2. Bit line control circuit
3 ... Column decoder
4 ... Data write end detection circuit
5 ... I / O data conversion circuit
6. Data input / output buffer
7. Word line drive circuit
8 ... Row decoder

Claims (1)

A memory cell array in which a plurality of memory cells that can be electrically rewritten and have n memory states (n ≧ 3) are arranged in a matrix;
A plurality of bit lines connected to the memory cell array;
A plurality of word lines connected to the memory cell array;
Each is provided for each bit line, each of which is composed of two or more binary data storage circuits, and n-valued write data written in the corresponding memory cell includes two or more including the first write binary data It is stored as a combination of write binary data, and it is controlled whether the write to the corresponding memory cell is promoted or suppressed by the first write binary data, and the write amount of the remaining write binary data is (n−1) values. A plurality of data storages that control and read n-value read data from corresponding memory cells using two or more reference signals, and store the results read using the respective reference signals in each of two or more binary data Circuit,
A non-volatile semiconductor memory device comprising:

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