JPH11250683A - Nonvolatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an EEPROM for intending to accelerate a write verifying operation without introducing an erroneous verify by storing a tertiary information. SOLUTION: The EEPROM having a memory cell array 1 including electrically rewritable memory cells disposed in a matrix so that three memory states are provided in one memory cell comprises a plurality of bit lines connected to the array 1, a plurality of word lines connected to the array 1, and a plurality of data latched circuits respectively provided for the bit lines, each having two or more binary data latched circuits to store n-value of write data written in the corresponding cell as a combination of two or more binary data and read data of the n value read from the corresponding cell as a combination of two or more binary data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an electrically rewritable nonvolatile semiconductor memory device (EEPROM),
In particular, the present invention relates to an EEPROM that performs multi-value storage in which more than one bit of information is stored in one memory cell.

[0002]

2. Description of the Related Art As one type of EEPROM, a NAND type EEPROM which can be highly integrated is known. In this method, a plurality of memory cells are connected in series in such a manner that their sources and drains are shared by adjacent ones, and are connected to bit lines as one unit. The memory cell usually has a FETMOS structure in which a charge storage layer and a control gate are stacked. The memory cell array is integrally formed in a p-type well formed on a p-type substrate or an n-type substrate. The drain side of the NAND cell is connected to a bit line via a selection gate, and the source side is also connected to a common source line via a selection gate. The control gates of the memory cells are arranged continuously in the row direction to form word lines.

The operation of this NAND cell type EEPROM is as follows. Data writing is performed sequentially from the memory cell located farthest from the bit line. The high voltage Vpp (= about 20 V) is applied to the control gate of the selected memory cell, and the intermediate voltage Vppm (= 1) is applied to the control gate and the selection gate of the memory cell on the bit line side from the high voltage Vpp.
0V) and apply 0V to the bit line according to the data.
Alternatively, an intermediate voltage Vm (= about 8 V) is applied. When 0 V is applied to the bit line, the potential is transferred to the drain of the selected memory cell, and electron injection occurs in the charge storage layer.
As a result, the threshold value of the selected memory cell shifts in the positive direction. This state is, for example, “1”. When Vm is applied to the bit line, electron injection does not occur effectively, so that the threshold value does not change and remains negative. This state is "0" in the erase state. Data writing is performed simultaneously on the memory cells sharing the control gate.

[0004] Data erasure is performed simultaneously for all memory cells in a NAND cell. That is, all control gates are set to 0V, and the p-type well is set to 20V. At this time, the selection gate, bit line and source line are also set to 20V. As a result, in all the memory cells, electrons in the charge storage layer are emitted to the p-type well, and the threshold value shifts in the negative direction.

For data reading, the control gate of the selected memory cell is set to 0 V, and the control gates and select gates of the other memory cells are set to the power supply potential Vcc (for example, 5 V).
This is performed by detecting whether or not a current flows in the selected memory cell.

Due to the restrictions on the read operation, the threshold value after writing "1" must be controlled between 0 V and Vcc. Therefore, the write verify is performed, and "1"
Only the memory cells with insufficient writing are detected, and rewriting data is set so that rewriting is performed only on the memory cells with insufficient writing of “1” (bit-by-bit verification). A memory cell with insufficient writing of “1” is detected by setting the selected control gate to, for example, 0.5 V (verify voltage) and reading (verify read).

That is, if the threshold value of the memory cell is not 0.5 V or more with a margin with respect to 0 V, a current flows in the selected memory cell and it is detected that "1" is insufficiently written. Since a current naturally flows in the memory cell set to the "0" write state, a circuit called a verify circuit for compensating the current flowing through the memory cell is provided so that the memory cell is not mistaken for "1" write shortage. This verify circuit executes write verify at high speed.

By performing data writing while repeating the write operation and the write verify, the write time is optimized for each memory cell, and the threshold value after “1” write is controlled between 0 V and Vcc. You.

In order to realize multi-value storage in this NAND cell type EEPROM, for example, it is considered that the state after writing is set to three states "0", "1", and "2".
The "0" write state has a negative threshold value, the "1" write state has a threshold value of, for example, 0 V to 1/2 Vcc, and the "2" write state has a threshold value of 1/2 Vcc to Vcc. In the conventional verify circuit, it is possible to prevent a memory cell to be written into "0" from being erroneously recognized as a memory cell with insufficient writing of "1" or "2".

However, since the conventional verify circuit is not for multi-value storage, the threshold value of the memory cell to be set to the "2" write state is higher than the verify voltage for detecting whether the "1" write is insufficient. In the case of a write shortage of Ｖ Vcc or less, there is a problem that when detecting whether or not write “1” is insufficient, a current does not flow in the memory cell and it is erroneously recognized that write is sufficient.

In order to perform multi-level write verification while preventing misunderstanding of insufficient writing, rewriting is performed for memory cells that have been sufficiently written for “1” and for memory cells that are to be written to “2”. Then, it is sufficient to detect whether or not the state of “2” writing is insufficient and perform the verify writing. However, in this case, the "2" write state is also set for the memory cell to be set to the "2" write state after the "1" write.

In addition, the multi-value storage EEPROM is difficult to match with a computer operating based on binary data.
This also causes a problem that the operation speed of the EEPROM is reduced.

[0013]

As described above, the conventional N
When multi-value storage is performed in an AND cell type EEPROM and bit-by-bit verification is performed by a conventional verification circuit, there is a problem that erroneous verification occurs. Further, in the case of a multi-valued EEPROM, data transmission / reception with a computer that processes binary data is complicated, and as a result, there is a problem that the operation speed of the EEPROM is reduced.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to store multi-valued information and exchange data with the outside in binary. An object of the present invention is to provide an EEPROM that can be used.

[0015]

(Structure) The present invention employs the following structure in order to solve the above problems.

That is, according to the present invention, in a multi-valued nonvolatile semiconductor memory device, a plurality of memory cells which can be electrically rewritten and have n storage states (n ≧ 3) are arranged in a matrix. An arranged memory cell array, a plurality of bit lines connected to the memory cell array, a plurality of word lines connected to the memory cell array, each provided for each bit line, each having two or more , And stores n-value write data to be written to a corresponding memory cell in a combination of two or more binary data, and stores n-value read data read from a corresponding memory cell in two or more binary data latch circuits. And a plurality of data latch circuits that store data in combination.

According to the present invention, in a multi-valued nonvolatile semiconductor memory device, a plurality of memory cells which can be electrically rewritten and have n storage states (n ≧ 3) are arranged in a matrix. An arranged memory cell array, a plurality of bit lines connected to the memory cell array, a plurality of word lines connected to the memory cell array, a data input buffer into which write data is input, and two write data. A data conversion circuit for converting into the above-described write binary data, and n-value writing which is provided for each bit line, each of which is composed of two or more binary data latch circuits, and which is written into a corresponding memory cell A plurality of data latch circuits for storing data as a combination of the two or more write binary data. It is characterized in.

According to the present invention, in a multi-valued nonvolatile semiconductor memory device, a plurality of memory cells which can be electrically rewritten and have n storage states (n ≧ 3) are arranged in a matrix. An arranged memory cell array, a plurality of bit lines connected to the memory cell array, a plurality of word lines connected to the memory cell array, each provided for each bit line, each having two or more And the n-valued read data read from the corresponding memory cell
A plurality of data latch circuits that store a combination of one or more read binary data, a data conversion circuit that converts the two or more read binary data into read data, and a data output buffer that outputs the read data. It is characterized by having.

(Operation) In the multi-valued (n-valued) storage type EEPROM according to the present invention, n-valued write data to be written to the corresponding memory cell is stored in a combination of two or more binary data, By providing a plurality of data latch circuits for storing n-value read data to be read in a combination of two or more binary data, data can be transmitted and received in substantially two values with the outside. Therefore, it is possible to match with a computer that operates based on the binary data.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of the present invention.
FIG. 2 is a block diagram illustrating a schematic configuration of an AND cell type EEPROM.

For the memory cell array 1,
A bit line control circuit 2 for controlling a bit line at the time of writing and a word line drive circuit 7 for controlling a word line potential are provided. The bit line control circuit 2 and the word line drive circuit 7 are selected by a column decoder 3 and a row decoder 8, respectively. The bit line control circuit 2 includes an input / output data conversion circuit 5 via a data input / output line (IO line).
And read data / write data are exchanged.
The input / output data conversion circuit 5 converts the read multi-value information of the memory cell into binary information for outputting to the outside, and converts the binary information of the write data input from outside into the multi-value information of the memory cell. Convert. The input / output data conversion circuit 5 includes a data input / output buffer 6 for controlling data input / output with the outside.
Connected to. The data write end detection circuit 4 detects whether the data write has ended.

FIGS. 2 and 3 show a specific configuration of the memory cell array 1 and the bit line control circuit 2. FIG. With the memory cells M1 to M8 and the selection transistors S1 and S2, NAN
Construct a D-type cell. One end of the NAND type cell is connected to the bit line BL, and the other end is connected to the common source line Vs. Select gates SG1 and SG2, control gates CG1 to CG
G8 is shared by a plurality of NAND cells, and a memory cell sharing one control gate constitutes a page. The memory cell stores data at the threshold value Vt. When Vt is 0 V or less, "0" data, and when Vt is 0 V or more.
The data is stored as "1" data when the voltage is 5 V or less, and as "2" data when Vt is 1.5 V or more and the power supply voltage or less. One memory cell has three states, and two memory cells have 9 states.
There are different combinations. Of these, eight combinations are used to store 3-bit data in two memory cells. In this embodiment, a set of two adjacent memory cells sharing a control gate stores 3-bit data. The memory cell array 1 is formed on a dedicated p-well.

Clock synchronous inverters CI1 and CI2
, CI3 and CI4 form flip-flops, respectively, and latch write / read data. They also operate as sense amplifiers. The flip-flop composed of the clock synchronous inverters CI1 and CI2 latches "whether to write" 0 "or" 1 "or" 2 "" as write data information, and the memory cell " Whether the information “0” is held or the information “1” or “2” is held ”is latched as read data information. The flip-flop composed of the clock synchronous inverters CI3 and CI4 latches "whether" 1 "write or" 2 "write" as write data information, and the memory cell is "2". Whether information is held or whether “0” or “1” is held ”is latched as read data information.

Q of the n-channel MOS transistors
n1 transfers the voltage VPR to the bit line when the precharge signal PRE becomes "H". Qn2 connects the bit line to the main bit line control circuit when the bit line connection signal BLC becomes "H". Qn3 to Qn6, Qn9 to Qn12
Selectively transfers the voltages VBLH, VBLM and VBLL to the bit lines according to the data latched in the flip-flop. Qn7 and Qn8 are signals SA, respectively.
When C2 and SAC1 become "H", the flip-flop is connected to the bit line. Qn13 is provided for detecting whether or not all the data for one page latched in the flip-flop are the same. Qn14, Qn15 and Q
n16 and Qn17 are column selection signals CSL1 and CS, respectively.
L2 changes to "H" to selectively connect the corresponding flip-flop to the data input / output lines IOA and IOB.

In FIG. 3, the inverter part is shown in FIG.
Although it is omitted as shown in FIG. 9A, it has the circuit configuration shown in FIG. 19B.

Next, the EEPROM constructed as above will be described.
Will be described with reference to FIGS. 4 shows the timing of the read operation, FIG. 5 shows the timing of the write operation,
FIG. 6 shows the timing of the verify read operation. In each case, the case where the control gate CG4 is selected is shown as an example.

The read operation is performed in two basic cycles. In the first read cycle, first, the voltage VPR becomes the power supply voltage Vcc, the bit line is precharged, and the precharge signal PRE becomes "L", and the bit line is floated. Subsequently, select gates SG1, SG2
, And the control gates CG1 to CG3 and CG5 to CG8 are set to Vcc. At the same time, the control gate CG4 is set to 1.5V.
Only when Vt of the selected memory cell is 1.5 V or more, that is, only when data "2" is written,
The bit line is kept at "H" level.

Thereafter, sense activation signals SEN2, SE
N2B is "L" and "H" respectively, and the latch activation signal LA
T2 and LAT2B become "L" and "H", respectively, and the flip-flop constituted by the clock synchronous inverters CI3 and CI4 is reset. The signal SAC2 becomes "H" and the clock synchronous inverters CI3 and CI4
And the bit lines are connected. First, after the sense activation signals SEN2 and SEN2B become "H" and "L", respectively, and the bit line potential is sensed, the latch activation signals LAT2 and LAT2B Become “H” and “L”, respectively, and the clock synchronous inverter CI
3 and CI4 flip flop,
The information “whether“ 2 ”data, 1” or “0” data is latched.

The second read cycle includes the first read cycle, the fact that the voltage of the selection control gate CG4 is 0V instead of 1.5V, and the signals SEN2, SEN2B, LAT2,
Instead of LAT2B and SAC2, signals SEN1 and SEN1
The difference is that B, LAT1, LAT1B, and SAC1 are output. Therefore, in the second read cycle, the flip-flop composed of the clock synchronous inverters CI1 and CI2 is used.
The information “whether“ 0 ”data,“ 1 ”or“ 2 ”data” is latched in the flop.

The data written in the memory cell is read by the two read cycles described above.

Prior to data writing, the data in the memory cell is erased, and the threshold value Vt of the memory cell is 0 V or less. For erasing, the p-well, the common source line Vs, the selection gates SG1 and SG2 are set to 20V, and the control gate CG
1 to CG8 are set to 0V.

In the write operation, first, the precharge signal PRE becomes "L" and the bit line is floated. The selection gate SG1 is at Vcc and the control gates CG1 to CG
G8 is set to Vcc. The select gate SG2 is at 0 V during the write operation. At the same time, the signals VRFY1, VRFY2,
FIM and FIH become Vcc. In the case of writing "0", since the data is latched in the flip-flop constituted by the clock synchronous inverters CI1 and CI2 so that the output of the clock synchronous inverter CI1 becomes "H", the bit line is It is charged by Vcc. “1”
Alternatively, in the case of "2" write, the bit line is at 0V.

Subsequently, the selection gate SG 1 and the control gate C
G1 to CG8, signal BLC, signal VRFY1 and voltage VS
A is 10V, voltage VBLH is 8V, and voltage VBLM is 1V. In the case of writing "1", the flip-flop constituted by the clock synchronous inverters CI3 and CI4
Since the data is latched so that the output of the clock synchronous inverter CI3 becomes "H", 1 V is applied to the bit line BL. In the case of "2" writing, the bit line is at 0V, and in the case of "0" writing, it is at 8V. After this,
The selected control gate CG4 is set to 20V.

In the case of writing "1" or "2", electrons are injected into the charge storage layer of the memory cell due to the potential difference between the bit line BL and the control gate CG4, and the threshold value of the memory cell rises. In the case of “1” write, the amount of charge to be injected into the charge storage layer of the memory cell must be reduced as compared with “2” write, so that the bit line BL is set to 1
V to reduce the potential difference from the control gate CG4 to 19V. However, the present invention can be implemented without easing the potential difference. At the time of writing "0", the threshold value of the memory cell is not effectively changed by the bit line voltage of 8V.

At the end of the write operation, first, the selection gate SG1 and the control gates CG1 to CG8 are set to 0V, and "0" is set.
The voltage 8V of the bit line BL at the time of writing is reset to 0V with a delay. This is because if this order is reversed, a state of a "2" or "1" write operation is temporarily created, and incorrect data is written when "0" is written.

After the write operation, the verify read is performed to confirm the write state of the memory cell and perform additional write only to the memory cell with insufficient write. During the verify read, the voltage VBLH is Vcc and VBLL is 0.
V and FIM are 0V.

The verify read is executed from two basic cycles. This basic cycle is similar to the second read cycle. The difference is that the selected control gate C
That is, the voltage of G4 and the signals VRFY1, VRFY2, and FIH are output (only VRFY1 in the first cycle of the verify read). Signals VRFY1, VRFY2
, FIH output the signal SEN1 after the selection gates SG1 and SG2 and the control gates CG1 to CG8 are reset to 0V.
, SEN1B, LAT1, LAT1B are "L",
It is output before it becomes “H”, “L”, or “H”. In other words, after the potential of the bit line is determined by the threshold value of the memory cell, the clock synchronous inverters CI1 and C1
Before the flip-flop constituted by I2 is reset. The voltages of the selected control gates CG4 are 2V (first cycle) and 0.5V (second cycle) corresponding to 1.5V (first cycle) and 0V (second cycle) at the time of reading. The height is increased to secure a threshold margin of 0.5V.

Here, the clock synchronous inverter CI
1 and CI2, the data (data1) latched in the flip-flop constituted by the clock synchronous inverters CI3 and CI4, and the data (data2) latched in the flip-flop constituted by the clock synchronous inverters CI3 and CI4. The voltage of the bit line BL determined by the threshold will be described. data1 is “0” write or “1”
Or "2" write ". In the case of" 0 "write, Qn3 is in the" ON "state, and in the case of" 1 "or" 2 "write, Qn6 is in the" ON "state. data2 controls “whether“ 1 ”write or“ 2 ”write”
In the case of "1" write, Qn10 is in "ON" state, "2"
In the case of writing, Qn11 is in the "ON" state.

In the first verify-read cycle when "0" data is written (initial write data is "0"), the data in the memory cell is "0". Therefore, when the control gate CG4 becomes 2V, the bit line is set by the memory cell. The potential becomes "L". After that, when the signal VRFY1 becomes "H", the bit line BL becomes "H".

In the first verify-read cycle when writing “1” data (initial write data is “1”), the memory cell data should be “1”, so the threshold value of the memory cell is 1.5 V Below, control gate C
When G4 becomes 2V, the bit line potential becomes "L" by the memory cell. After that, when the signal VRFY1 becomes "H", the bit line BL becomes "H" (FIG. 6) when "1" has already been sufficiently written and data1 indicates "0" write.
(1)), otherwise, the bit line BL is "L" ((2) in FIG. 6).
).

In the first verify-read cycle when "2" data is written (initial write data is "2"), if the data of the selected memory cell is not "2"("2" write is insufficient), control is performed. Gate CG4 is 2
When it becomes V, the bit line potential becomes "L" by the memory cell ((5) in FIG. 6). When "2" is sufficiently written in the selected memory cell, the bit line potential remains "H" even when the control gate CG4 becomes 2V ((3) in FIG. 6).
(Four)). (3) of FIG.
This is the case where a1 indicates “0” writing. In this case, the bit line BL is recharged by the voltage VBH when the signal VRFY1 becomes "H".

In the second verify-read cycle when "0" data is written (initial write data is "0"), the data in the memory cell is "0". The bit line potential becomes "L". Thereafter, when the signal VRFY1 becomes "H", the bit line BL becomes "H".

In the second verify-read cycle at the time of writing “1” data (initial write data is “1”), if the data of the selected memory cell is not “1” (“1” write is insufficient), control is performed. When the gate CG4 becomes 0.5 V, the bit line potential becomes "L" by the memory cell ((8) in FIG. 6). Selected memory cell is "1"
When writing is sufficient, the bit line potential remains "H" even when the control gate CG4 becomes 0.5 V (FIGS. 6 (6) (7)). FIG. 6 (6) shows a case where "1" has already been sufficiently written and data1 indicates "0" write. In this case, when the signal VRFY1 becomes "H", the bit line BL is recharged by the voltage VBH.

In the second verify-read cycle when writing "2" data (initial write data is "2"), the threshold value of the memory cell is 0.5 V because the data of the memory cell should be "2". If this is the case, the control gate CG4 is set to 0.5
V, the bit line potential remains "H" (FIG. 6).
(9) (10)). When "2" is insufficiently written and the threshold value of the memory cell is 0.5 V or less, the bit line becomes "L" ((11) in FIG. 6).

Thereafter, the signals VRFY1, VRFY2, F
When IH is set to "H", the bit line BL is set to "H" ((9) in FIG. 6) if "2" has already been sufficiently written and data1 indicates "0", otherwise the bit line BL
Becomes "L" ((10) (11) in FIG. 6).

By this verify read operation, rewrite data is set as shown in the following (Table 1) from the write data and the write state of the memory cell.

[0048]

[Table 1]

As can be seen from Table 1, "1" writing is performed again only on the memory cells for which "1" writing is insufficient.
The "2" writing is performed again only on the memory cells for which the "2" writing is insufficient. When data writing is sufficient in all memory cells, Qn13 in all columns is turned "OFF", and data write end information is output by the signal PENDB.

FIGS. 7A and 7B show data input / output operation timing. FIG. 7A shows data input timing, and FIG. 7B shows data output timing. After three cycles of external data input, the input / output data conversion circuit 5 generates and inputs data to be input to the bit line control circuit 2.
3-bit data from outside (X1, X2, X3)
Are converted into data (Y1, Y2) of two memory cells, and are effectively registers R1 and C2 composed of clock synchronous inverters CI1 and CI2 of the bit line control circuit 2.
Conversion data is set in a register R2 composed of I3 and CI4 via data input / output lines IOA and IOB.
The read data latched by the registers R1 and R2 are transferred to the input / output data conversion circuit 5 via the data input / output lines IOA and IOB, converted and output. It is also possible to make the column selection signals CSL1i and CSL2i shown in FIG. 3 the same signal, and instead divide the IOA and IOB into two systems to simultaneously access two registers in the same column simultaneously, thereby shortening the access time. In order to be effective.

The following (Table 2) corresponds to external three-bit data (X1, X2, X3), two data (Y1, Y2) and Y1, Y2 of a memory cell at the time of data input. The relationship between the data in the registers R1 and R2 is shown.

[0052]

[Table 2]

The data of the register is represented by the voltage level of the input / output line IOA at the time of data transfer. The data input / output line IOB is omitted because it is an inverted signal of IOA. The following (Table 3) is that at the time of data output.

[0054]

[Table 3]

In this embodiment, for the same data, the level of the IOA at the time of input and the level of the IOA at the time of output are inverted.

Since one of the nine combinations of the two data (Y1, Y2) of the memory cell remains, it can be used for file management information such as pointer information. Here, the pointer information is stored in the cell data (Y1,
Y2) = (2,2).

FIG. 8 shows the concept of a page as a unit of data writing when viewed from a microprocessor or the like controlling the EEPROM. Here 1
The page has N bytes, and an address (logical address) as viewed from a microprocessor or the like is displayed. For example, when write data is input only to the area 1 (logical addresses 0 to n), n = 3m + 2 (m = 3m + 2)
0, 1, 2,...), There is no problem since (X1, X2, X3) are always aligned. When n = 3 m, only X1 is input, so that X2 = 0, X3 = 0 is generated inside the EEPROM and (X1, X2, X3) is input to the input / output data conversion circuit 5.
To enter. When n = 3m + 1, X3 = 0 is generated internally. The same applies when n is equal to N.

Data was written to area 1 (area 2
In the case where data is additionally written to the area 2 after all the write data "0"), it is sufficient to read the area 1 and add the write data of the area 2 to the data. Alternatively, read the portion of area 1 and
If the start address n + 1 = 3m of the area 2, all data in the area 1 is “0”, and if n + 1 = 3m + 2, the address n
The data of -1 and n are added to the data X3 of the address n + 1 as X1 and X2, and all the data up to the address n-2 of the area 1 are "0". Data X of n + 2
2 and X3, all data up to the address n-1 of the area 1 may be set to "0". These operations are based on the EEP
It is also easy to perform this automatically inside the ROM. (X1, X2, X3) and (Y1) as shown in (Table 2) and (Table 3) so that the additional data can be written.
, Y2) are established. (X1, X2, X3) and (Y1, Y2) shown in (Table 2) and (Table 3).
The relationship in parentheses) is one example and is not limited to this. Further, additional data can be written in the same manner even when the area is three or more.

FIG. 9A shows a data writing algorithm. After data loading, writing, verify reading, and writing end detection are repeatedly performed. The operation within the dotted line is performed automatically in the EEPROM.

FIG. 9B shows an additional data writing algorithm. After reading and data loading, verify reading, writing end detection, and writing operation are repeatedly performed. The operation within the dotted line is performed automatically in the EEPROM. The reason why the verify read is performed after the data load is to prevent the write from being performed where “1” or “2” has already been written.
Otherwise, overwriting may occur.

FIG. 10 shows the EEPR constructed as described above.
The write characteristics of the threshold value of the memory cell in the OM are shown. The memory cells to which "1" data is written and the memory cells to which "2" data are written are written at the same time, and the writing time is controlled independently.

The following (Table 4) shows the potential of each part of the memory cell array at the time of erasing, writing, reading and verify reading.

[0063]

[Table 4]

FIG. 11 shows a specific configuration of the memory cell array 1 and the bit line control circuit 2 of the NOR cell type EEPROM according to the second embodiment of the present invention. A NOR type cell is constituted only by the memory cell M10. One end of the NOR type cell is connected to the bit line BL, and the other end is connected to a common ground line. The memory cells M sharing one control gate WL constitute a page. The memory cell M stores data at the threshold value Vt, “0” data when Vt is equal to or higher than Vcc, “1” data when Vt is equal to or lower than Vcc and 2.5 V or higher, and Vt is equal to or lower than 2.5 V and 0 V or higher. Is stored as "2" data. One memory cell has three states, and two memory cells can have nine combinations. Of these, using 8 combinations, 2
One memory cell stores data of 3 bits. In this embodiment, a set of two adjacent memory cells sharing a control gate stores 3-bit data.

Clock synchronous inverters CI5 and CI6
, CI7 and CI8 form flip-flops, respectively, and latch write / read data. It also operates as a sense amplifier. The flip-flop composed of the clock synchronous inverters CI5 and CI6 latches "whether to write" 0 "or" 1 "or" 2 "" as write data information, and the memory cell " Whether it holds the information “0”
"Whether the information of" 1 "or" 2 "is held" is latched as read data information. The flip-flop composed of the clock synchronous inverters CI7 and CI8 latches "whether" 1 "write or" 2 "write" as write data information, and the memory cell is "2". Whether information is held or whether “0” or “1” is held ”is latched as read data information.

Of the n-channel MOS transistors, Qn
18 is a voltage V when the precharge signal PRE becomes “H”.
Transfer PR to bit line. Qn19 connects the bit line to the main bit line control circuit when the bit line connection signal BLC becomes "H". Qn20 to Qn23 and Qn25 to Qn28 are
The voltages VBLH, VBLM, and 0 V are selectively transferred to the bit lines according to the data latched in the flip-flop. Qn24 and Q29 are signals SAC2 and SAC, respectively.
When AC1 becomes "H", the flip-flop is connected to the bit line. Qn30 is provided for detecting whether or not all data of one page latched in the flip-flop is the same. Qn31, Qn32 and Qn33, Q
In n34, the column selection signals CSL1 and CSL2 become "H", respectively, to selectively connect the corresponding flip-flop to the data input / output lines IOA and IOB.

Next, the EEPROM constructed as described above will be described.
Will be described with reference to FIGS. 12 shows the timing of the read operation, FIG. 13 shows the timing of the write operation, and FIG. 14 shows the timing of the verify read operation.

The read operation is executed in two basic cycles. In the first read cycle, first, the voltage VPR becomes the power supply voltage Vcc, the bit line is precharged, and the precharge signal PRE becomes "L", and the bit line is floated. Subsequently, the control gate WL is set to 2.5 V
To be. Only when Vt of the selected memory cell is 2.5 V or less, that is, only when data “2” is written, the bit line goes to “L” level.

Thereafter, sense activation signals SEN2, SE
N2B is "L" and "H" respectively, and the latch activation signal LA
T2 and LAT2B become "L" and "H", respectively, and the flip-flop constituted by the clock synchronous inverters CI7 and CI8 is reset. The signal SAC2 becomes "H" and the clock synchronous inverters CI7 and CI8
And the bit lines are connected. First, after the sense activation signals SEN2 and SEN2B become "H" and "L", respectively, and the bit line potential is sensed, the latch activation signals LAT2 and LAT2B Become “H” and “L”, respectively, and the clock synchronous inverter CI
7 and CI8 flip-flop,
Information “whether“ 2 ”data,“ 1 ”or“ 0 ”data” is latched.

The second read cycle is the same as the first read cycle, except that the voltage of the selection control gate WL is not 2.5 V but V
cc, the signals SEN2, SEN2B, LAT2, L
Instead of AT2B and SAC2, signals SEN1, SEN1B,
The difference is that LAT1, LAT1B, and SAC1 are output. Therefore, in the second read cycle, the information of "whether" 0 "data," 1 "or" 2 "data is latched in the flip-flop constituted by the clock synchronous inverters CI5 and CI6.

The data written in the memory cell is read by the two read cycles described above.

Prior to data writing, the data in the memory cell is erased, and the threshold value Vt of the memory cell is higher than Vcc. Erasing is performed by setting the control gate WL to 20V and the bit line to 0V.

In the write operation, first, the precharge signal PRE becomes "L", and the bit line is floated. The signals VRFY1, VRFY2, FIM and FIL become Vcc. In the case of writing "2", since the data is latched in the flip-flop constituted by the clock synchronous inverters CI5 and CI6 so that the output of the clock synchronous inverter CI5 becomes "H", the bit line is 0V. In the case of "1" or "2" writing, the bit line is charged to Vcc.

Subsequently, the signals BLC, VRFY2, FI
M, FIL and voltage VSA are 10V, voltage VBLH is 8V, and voltage VBLM is 7V. In the case of writing "1", since the data is latched in the flip-flop constituted by the clock synchronous inverters CI7 and CI8 so that the output of the clock synchronous inverter CI7 becomes "H", the bit line BL Is applied with 7V. In the case of “2” write, the bit line is 8V, and in the case of “0” write,
V. After this, the selected control gate WL becomes -12
V.

In the case of "1" or "2" writing, electrons are emitted from the charge storage layer of the memory cell due to the potential difference between the bit line BL and the control gate WL, and the threshold value of the memory cell decreases. In the case of “1” write, the amount of charge to be released from the charge storage layer of the memory cell must be reduced as compared with “2” write, so that the potential difference between the bit line BL and the control gate WL is set to 7 V by setting the bit line BL to 7V. It has eased to 19V. At the time of writing “0”, the threshold value of the memory cell is not effectively changed by the bit line voltage 0V.

After the write operation, the verify read is performed in order to confirm the write state of the memory cell and to perform additional write only to the insufficiently written memory cell. During the verify read, the voltage VBLH is Vcc and FIM is 0V
It is.

The verify read is executed from two basic cycles. This basic cycle is similar to the first read cycle. The difference is that the selected control gate W
That is, the voltage of L and the signals VRFY1, VRFY2, and FIH are output (only VRFY1 in the first cycle of the verify read). The signals VRFY1, VRFY2,
FIH is output before the signals SEN1, SEN1B, LAT1, and LAT1B become "L", "H", "L", and "H", respectively, after the control gate WL is reset to 0V. In other words, after the potential of the bit line is determined by the threshold value of the memory cell, but before the flip-flop constituted by the clock synchronous inverters CI5 and CI6 is reset. The voltages of the selected control gate WL are 2 V (first cycle) and 4 V corresponding to 2.5 V (first cycle) and Vcc (second cycle) at the time of reading.
(Second cycle) and lower to ensure a threshold margin.

Here, the clock synchronous inverter CI
5 and CI6, the data (data1) latched in the flip-flop comprised of the clock synchronous inverters CI7 and CI8, and the data (data2) latched in the flip-flop comprised of the inverters CI7 and CI8. The voltage of the bit line BL determined by the threshold will be described. data1 is “0” write or “1”
Or "2" write ", and in the case of" 0 "write, Qn20 is in the" ON "state, and in the case of" 1 "or" 2 "write, Qn23 is in the" ON "state. data2 controls “whether“ 1 ”write or“ 2 ”write”
In the case of "1" write, Qn26 is in "ON" state, "2"
In the case of writing, Qn27 is in the "ON" state.

In the first verify-read cycle at the time of writing “0” data (initial write data is “0”), since the data of the memory cell is “0”, even if the control gate WL becomes 2V, the bit line potential Remains "H". Thereafter, when the signal VRFY1 becomes "H", the bit line BL becomes "L".

In the first verify-read cycle when "1" data is written (initial write data is "1"), the threshold value of the memory cell is 2.5 V since the data of the memory cell should be "1". With the above, the control gate W
Even when L becomes 2V, the bit line potential remains "H". After that, the signal VRFY1 becomes "H", so that "1" has already been sufficiently written and data1 indicates "0" write, and the bit line BL becomes "L" ((2) in FIG. 14).
Otherwise, the bit line BL becomes "H" ((1) in FIG. 14).

In the first verify-read cycle when writing “2” data (initial write data is “2”), if the data of the selected memory cell is not “2” (“2” write is insufficient), control is performed. Gate WL is 2V
, The bit line potential is still "H" ((3) in FIG. 14).
). When "2" is sufficiently written in the selected memory cell, when the control gate WL becomes 2 V, the bit line potential becomes "L" by the memory cell ((4) (5) in FIG. 14).
FIG. 14 (5) shows a case where "2" has already been sufficiently written and data1 indicates "0" write. In this case, when the signal VRFY1 becomes "H", the bit line BL is grounded.

In the verify-read second cycle at the time of writing "0" data (initial write data is "0"), since the data of the memory cell is "0", even if the control gate CG4 becomes 4V, the bit line potential Is "H". Thereafter, when the signal VRFY1 becomes "H", the bit line BL becomes "L".

In the second verify-read cycle at the time of writing “1” data (initial write data is “1”), if the data of the selected memory cell is not “1” (“1” write is insufficient), control is performed. Gate WL is 4V
, The bit line potential is still "H" ((6) in FIG. 14).
). When "1" is sufficiently written in the selected memory cell, the bit line potential is set to "L" by the memory cell when the control gate WL becomes 4V ((7) (8) in FIG. 14). FIG. 14 (8) shows a case where "1" has already been sufficiently written and data1 indicates "0" write. In this case, when the signal VRFY1 becomes "H", the bit line BL is grounded.

In the second verify-read cycle when "2" data is written (the initial write data is "2"), the data in the memory cell should be "2". If there is enough or insufficient writing of “2”, the bit line potential becomes “L” when the control gate WL becomes 4V ((10) (11) in FIG. 14).
When "2" is insufficiently written and the threshold value of the memory cell is 4 V or more, the bit line becomes "H" ((9) in FIG. 14).

Thereafter, the signals VRFY1, VRFY2, F
When IH becomes “H”, the bit line BL becomes “L” ((11) in FIG. 14) if “2” has already been sufficiently written and data1 indicates “0” write; otherwise, the bit line B
L becomes "H" ((9) (10) in FIG. 14).

By this verify read operation, the rewrite data is set as shown in Table 1 from the write data and the write state of the memory cell as in the first embodiment. Also, when data writing is sufficient in all memory cells, Qn30 in all columns is turned off,
Data write end information is output by the signal PENDB.

The data input / output operation timing, the data writing algorithm, the additional data writing algorithm, etc. are the same as those shown in FIGS. 7 to 9 and (Tables 2 to 3).
This is the same as the embodiment.

FIG. 15 shows the EEPR constructed as described above.
The write characteristics of the threshold value of the memory cell in the OM are shown. The memory cells to which "1" data is written and the memory cells to which "2" data are written are written at the same time, and the writing time is controlled independently.

The following (Table 5) shows the potential of each part of the memory cell array at the time of erasing, writing, reading and verify reading.

[0090]

[Table 5]

The circuits shown in FIGS. 3 and 11 can be modified as shown in FIGS. 16 and 17, respectively. In FIG. 16, Qn3 and Qn4 shown in FIG. 2 are replaced by p-channel MOS transistors Qp1 and Qp2. FIG.
Qn22, Qn23, Qn25 to Qn28 in FIG. 1 are replaced by p-channel MOS transistors Qp3 to Qp8. By doing so, it is possible to prevent a drop in the transferable voltage due to the threshold value of the n-channel MOS transistor. In this example, the voltage VSA may be increased to 8 V at the time of writing, and the withstand voltage of the transistors constituting the circuit is reduced. be able to. VRFY1B in FIG. 16 is VRFY in FIGS.
The inverted signal of RFY1, VRFY2B, FILB,
FIMB is an inverted signal of each of VRFY2, FIL, and FIM in FIG.

Although the additional data writing has been described with reference to FIG. 8, it is one effective method to divide one page in order to facilitate the writing of the additional data as shown in FIG. 18, for example. In this example, one area is constituted by 22 memory cells for every 32 logical addresses. This makes it easy to write additional data in area units. That is, when additional data is written in the area 2, all the write data in the area other than the area 2 is set to “0”, and FIG.
This may be performed according to the data writing algorithm shown in FIG. The size of one area may be a size other than that shown in FIG.

[0093]

As described above, according to the present invention, the n-value write data to be written to the corresponding memory cell is stored in a combination of two or more binary data, and the n-value write data read from the corresponding memory cell is stored. By providing a plurality of data latch circuits for storing read data as a combination of two or more binary data, data can be transmitted and received in a binary manner with an external device, and therefore, operation is performed based on the binary data. It is possible to match with a computer that performs the processing.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of an EEPROM according to first and second embodiments.

FIG. 2 is a diagram showing a specific configuration of a memory cell array in the first embodiment.

FIG. 3 is a diagram showing a specific configuration of a bit line control circuit according to the first embodiment.

FIG. 4 is a timing chart showing a read operation in the first embodiment.

FIG. 5 is a timing chart showing a write operation in the first embodiment.

FIG. 6 is a timing chart showing a verify read operation in the first embodiment.

FIG. 7 is a timing chart showing data input / output operations in the first and second embodiments.

FIG. 8 is a view showing the concept of a page of a write / read unit in the first and second embodiments.

FIG. 9 is a diagram showing a data write and additional data write algorithm in the first and second embodiments.

FIG. 10 is a diagram showing write characteristics of a memory cell in the first embodiment.

FIG. 11 is a diagram showing a configuration of a memory cell array and a bit line control circuit in a second embodiment.

FIG. 12 is a timing chart showing a read operation in the second embodiment.

FIG. 13 is a timing chart showing a write operation in the second embodiment.

FIG. 14 is a timing chart showing a verify read operation in the second embodiment.

FIG. 15 is a diagram showing write characteristics of a memory cell in the second embodiment.

FIG. 16 is a diagram showing a modification of the bit line control circuit in the first embodiment.

FIG. 17 is a diagram showing a modification of the bit line control circuit in the second embodiment.

FIG. 18 is a diagram showing units of additional data writing in the first and second embodiments.

FIG. 19 is a diagram showing a specific configuration example of an inverter section shown in FIG. 3;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 memory cell array 2 bit line control circuit 3 column decoder 4 data write end detection circuit 5 input / output data conversion circuit 6 data input / output buffer 7 word line drive circuit 8 row decoder

Claims (3)

[Claims] 1. A memory cell array in which a plurality of memory cells which can be electrically rewritten and have n storage states (n ≧ 3) are arranged in a matrix, and are connected to the memory cell array. A plurality of bit lines; a plurality of word lines connected to the memory cell array; each provided for each bit line;
It is composed of one or more binary data latch circuits, stores n-value write data written to corresponding memory cells in a combination of two or more binary data, and stores two or more n-value read data read from corresponding memory cells. And a plurality of data latch circuits for storing a combination of the binary data. 2. A memory cell array in which a plurality of memory cells which can be electrically rewritten and have n storage states (n ≧ 3) are arranged in a matrix, and are connected to the memory cell array. A plurality of bit lines, a plurality of word lines connected to the memory cell array, a data input buffer for inputting write data, a data conversion circuit for converting the write data into two or more write binary data, Are provided for each bit line, and
And a plurality of data latch circuits configured of at least one binary data latch circuit and storing n-value write data to be written to a corresponding memory cell in a combination of the two or more write binary data. A nonvolatile semiconductor memory device characterized by the above-mentioned. 3. A memory cell array in which a plurality of memory cells which can be electrically rewritten and have n storage states (n ≧ 3) are arranged in a matrix, and are connected to the memory cell array. A plurality of bit lines; a plurality of word lines connected to the memory cell array; each provided for each bit line;
A plurality of data latch circuits each including at least one binary data latch circuit and storing n-value read data read from a corresponding memory cell in a combination of two or more read binary data; A nonvolatile semiconductor memory device, comprising: a data conversion circuit that converts binary data into read data; and a data output buffer that outputs the read data.