KR970017668A

KR970017668A - Semiconductor nonvolatile memory and computer system using same

Info

Publication number: KR970017668A
Application number: KR1019960041545A
Authority: KR
Inventors: 도시히로 다나카; 마사타카 가토; 데츠오 아다치
Original assignee: 가나이 츠토무; 히다치세사쿠쇼 가부시키가이샤
Priority date: 1995-09-29
Filing date: 1996-09-23
Publication date: 1997-04-30
Also published as: JPH0991978A; TW310432B

Abstract

임계값전압을 전기적으로 리라이트하는 것이 가능한 트랜지스터로 이루어지는 반도체 불휘발성 기억장치에 관한 것으로서, 전기적 리라이트가 가능한 반도체 불휘발성 기억장치에 있어서 장치내부에서 2개의 기억정보에 대응하는 메모리셀의 임계값전압의 분포를 억제하고 리라이트 내성을 향상시킨 반도체 불휘발성 기억장치 및 그것을 사용한 컴퓨터시스템을 제공하기 위해, 반도체 불휘발성 기억장치의 리라이트(라이트 또는 소거) 동작 후에 있어서 반도체 불휘발성 기억장치의 메모리셀 중 임계값전압이 검증워드선전압에 도달하고 있지 않은 메모리셀에 대해서 리라이트동작이 계속되고, 그것에 따라서 반도체 불휘발성 기억장치의 리라이트 내성이 향상한다.A semiconductor nonvolatile memory device comprising a transistor capable of electrically rewriting a threshold voltage. A semiconductor nonvolatile memory device capable of electrically rewriting a threshold voltage, wherein the threshold value of a memory cell corresponding to two pieces of storage information is provided within the device. In order to provide a semiconductor nonvolatile memory device with a suppressed voltage distribution and improved rewrite resistance and a computer system using the same, a memory of a semiconductor nonvolatile memory device after a rewrite (write or erase) operation of the semiconductor nonvolatile memory device. The rewrite operation continues for the memory cell in which the threshold voltage of the cell does not reach the verification word line voltage, thereby improving the rewrite resistance of the semiconductor nonvolatile memory device.

Description

Semiconductor nonvolatile storage and computer system using same

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 1실시예에 의한 반도체 블휘발성 기억장치의 라이트 동작의 흐름도,1 is a flowchart of a write operation of a semiconductor nonvolatile memory device according to an embodiment of the present invention;

제21도는 본 발명의 1실시예에 의한 반도체 불휘발성 기억장치를 사용한 PC(퍼스널 컴퓨터)카드를 도시한 블럭도.21 is a block diagram showing a personal computer (PC) card using a semiconductor nonvolatile memory device according to one embodiment of the present invention.

Claims

A plurality of nonvolatile semiconductor memory cells each having a control gate, a drain, and a source, a word line to which the control gates of the plurality of nonvolatile semisolid memory cells are commonly connected, and a drain of the plurality of nonvolatile semiconductor memory cells are respectively connected. In a semiconductor nonvolatile memory device having a plurality of bit lines and controlling the write to be continued only for a nonvolatile semiconductor memory cell in which the write is insufficient when the write is performed on the plurality of nonvolatile semiconductor memory cells, And means for controlling the erase to continue only for the nonvolatile semiconductor memory cells in which the erase is insufficient when the erase is performed for the plurality of nonvolatile semiconductor memory cells.

A plurality of nonvolatile semiconductor memory cells each having a control gate, a drain, and a source, a word line to which the control gates of the plurality of nonvolatile semiconductor memory cells are commonly connected, and a drain of the plurality of nonvolatile semiconductor memory cells are respectively connected And a plurality of latch circuits each connected to a plurality of bit lines and the plurality of 1 bit lines, each of which holds rewrite data of each of the nonvolatile semiconductor memory cells of the plurality of nonvolatile semiconductor memory cells. When the rewrite data is set in a latch circuit and a write operation is performed for the plurality of nonvolatile semiconductor memory cells, the plurality of latch circuits are used according to the state of each nonvolatile semiconductor memory cell of the plurality of nonvolatile semiconductor memory cells. The rewrite data of is reset and the reset A semiconductor nonvolatile memory device for controlling the continuation or stop of the write operation for each nonvolatile semiconductor memory cell of the plurality of nonvolatile semiconductor memory cells in accordance with rewrite data, wherein the rewrite data is stored in the plurality of latch circuits. And the rewrite data is reset according to the state of each nonvolatile semiconductor memory cell of the plurality of nonvolatile semiconductor memory cells when an erase operation is performed on the plurality of nonvolatile semiconductor memory cells. And a means for controlling the continuation or stop of the erase operation for each nonvolatile semiconductor memory cell of the plurality of nonvolatile semiconductor memory cells in accordance with rewrite data.

3. The bits of the plurality of bit lines according to claim 2, wherein the rewrite data held in the plurality of latch circuits reads the information of the plurality of nonvolatile semiconductor memory cells collectively into the plurality of bit lines. The semiconductor nonvolatile memory device is reset in the device in accordance with the change of the potential of the line.

The semiconductor device of claim 1, wherein the plurality of nonvolatile semiconductor memory cells have a first threshold voltage and a second threshold voltage different from the first threshold voltage, and the first threshold voltage and the second threshold value. A semiconductor nonvolatile memory device having a voltage variation of 1 V or less.

A computer system having a semiconductor nonvolatile memory device and a central processing unit according to claim 1, wherein the rewriting or erasing of the semiconductor nonvolatile memory device is executed irrespective of a command of the central processing unit.

※ Note: The disclosure is based on the initial application.