310432 A 7 經濟部中央標準局貝工消费合作社印製 五、發明说明（1 ) 本發明係關於由可利用氰氣方式改寫醮限值«壓之電 晶體所構成之半導體非揮發性記憶裝置，尤關於利用電氣 方式頻繁的改寫臨限值電壓之非揮發性記憶裝置及使用該 裝置之電腦系統。 快閃記憶體係可利用電氣方式整批的抹消記慷內容之 單電晶體/晶胞方式之一種半導體非揮發性記億裝置•因 爲快閃記憶體中，每一位元之佔有面稹小，可實現高稹體 化，故最近受到囑目，已有許多有關其構造，連接方法* 及驅動方法之研究開發· 目前已有刊載於 Symposium on VLSI Circuits Digest of Technical Papers pp97-98 1993之 DIN0R( Divided bit Line NOR)方式，同樣刊載於骸報告中p p 99 — 100，1993之NOR方式，同樣刊載於該報 告中PP61 — 62 1994中之AND方式，刊載於 International Electron Devices Meeting Tech. Dig. pp-19-22 1993中之HICR (High Capacity-Coupling Ratio 方式，及刊載於 Symposiun on VLSI Circuits Digest of Technical Papers pp2 0 - 2 1 1 992 中之 N A N D方式· 第7，8，9，10及1 1圓分別爲利用NOR方式 ，D I NOR方式，HI CR方式及NAND方式之記憶 體晶胞之連接例圓·第7，8 * 9，10及11_中， W 1 ..........Wm爲字線《Β1，B2爲位元線，各記憶 體晶胞係由具有控制閘極及漂浮閘極之1個電晶鼉所構成 (請先閲辣背面之法意事項再填寫本頁) Γ 裝. -s :線 本紙張尺度適用中國國家樣準（CNS ) A4说格（210X297公釐）4 - 310432 A7 _ B7 五、發明説明（2 ) 。上述各方式可根據記憶體晶胞之連接狀態分類成N 0 R ，D I NOR，AND，Η I CR方式之NOR型連接時 與N A N D方式· 依照第7圖所示之NOR型連接，讀出時之遢揮字線 電應係電源電壓V c C。在電子儲存於灌浮關極之狀態下 ，來自控制閘極之記憶體晶胞臨限值電壓昇高，即使選擇 字線而在控制閘極上施加Vc c亦不會有記镰體晶胞電流 通過。在電子未注入漂浮閘極之狀態（放出電子）下，記 憶體晶胞臨限值電壓低，有選擇字線之記慷镰晶胞電流通 過。以偵測放大器接受記憶體晶胞電流而判定資訊之 ，或 ' 1 ,。 第1 2 a圓表示NOR型連接時對應於2個記憶賫訊 之記憶體晶胞之臨限值電壓V t hL與V t hH之分佈· V t h L表示電子未注入漯浮閘極時之記憶體晶胞之瞌限 值電壓，V t h Η表示電子儲存於漂浮閘極時之記憶臁晶 胞之臨限值m壓· 經濟部中央標準局貝工消费合作社印製 (請先閲讀背面之注意事項再填寫本頁) 因爲在N 0 R型連接時，讀出時之非選擇字線之施加 電壓爲接地電壓V s s，故若記慷體晶胞之醮限值電壓成 爲負電壓時，即成爲誤讀出之原因*因此*必須以高精確 度進行控制以免V t h L成爲負電壓· 以下參照第1圖說明第9圔所示NOR型連接時之 AND方式之寫入動作（將睡限值電壓改寫成V t h L之 動作）程序之一實施例•在NAND方式之寫入動作時， 從C P U输入寫入指令，連接於記慷體晶胞陣列之所需字 本紙張尺度適用t國國家標準（CNS ) A4規格（210X297公釐）_ 5 - 3ί〇432 經濟部中央標準局貝工消费合作社印製 Α7 _Β7 _ 五、發明説明（3 ) 線之記憶《晶胞群（以後稱爲片段（sector))之位址* 及寫入賫料於記憶裝置中*設定單位寫入時間而在對應於 被選擇之片段之寫入資料之記憶《晶胞上整批的寫入之後 進行核對•核對結果若有寫入不充分之記憶體晶胞，亦即 尙未達到寫入鷗限值電壓（V v )之記憶體晶胞時，改寫 裝置內部之寫入資料，以便只對寫入不充分之記镰镰晶胞 繼績進行寫入動作•寫入，核對，賫料寫入動作一直重複 進行至全部寫入對象之記憧《晶胞之醮限值電壓達到寫入 臨限值電壓（Vv)爲止· 因爲依照道種動作程序於每一位元控制片段內之記憶 體晶胞之寫入側之臨限值竃壓V t h L，故寫入後可使 V t h L側之記憶髏晶胞之臨限值電壓成爲一致* 在考慮V t h L之分佈範圓之下*將寫入睡限值電壓 (Vv )設定爲V t h L對全部寫入狀態之記億體晶胞不 會成爲負值之狀態，例如1. 5V左右* 第12 (b)圖表示對應於NAND方式時之2個記 憶賫訊之記憶鼈晶胞之臨限值電壓V t h L與V t hH之 分佈•在NAND方式時•將黷出時之非選揮字線做爲電 源電壓V c c使用，而無論臨限值m應之高低賫訊如何， 將全部非選擇記憶體晶胞做爲通過《晶體使用•黷出時之 選擇字線上施加之電壓爲接地《KV s s ·因此· V t h L係設定在因接地電壓Vs s而有記憶«晶胞電流通遇之 數值，而v t h η係設定在非邇揮字線m壓之m源《壓 V c c與選擇字線電壓之接地亀歷V s s之間· 本紙張尺度逋用中國國家標準（CNS ) A4規格(210X 297公着Γ _ 6 _ --------「裝-----訂.------ (請先閲is背面之注意事項再填寫本頁) 經濟部中央標準局貝工消费合作社印製 A7 _B7_ _ 五、發明説明（4 ) 因爲在N A N D方式時係將全部非選揮記憶體晶胞做 爲通過電晶髖使用·故必須以高精確度控制閘極m壓較高 之Vt hH (寫入側），以免其超過電源電壓Vc c ·因 此，在NAND方式中亦重複的進行寫入，核對，資料改 寫動作，並於每一位元控制記憶體晶胞之寫入醮限值，一 直到與上述AND方式時相同的，全部寫入對象之記憶髖 晶胞之臨限值電壓達到寫入臨限值電壓（Vv)爲止· 考慮V t hH之分佈範·，將寫入隳限值電壓（Vv )設定爲寫入對象之全部記憶體晶胞之睡限值電壓不會成 爲高於電源電壓V c c之電壓值，例如2 5V左右· 在上述習用之NOR型連接及NAND型連接時•皆 對每一記億體晶胞控制片段內之記慷«晶胞之寫入側瞄限 值電壓，但卻未充分進行抹消側之禳限值霉壓控制*亦即 只確保成爲最大或最小之臨限值電懕，以便在NOR型連 接時成爲高於電源電壓V c c，在NAND方式時成爲低 於接地電壓V s s。 以下參照第3圓說明習用之NAND方式之抹消（昇 高臨限值電應）之動作程序之一實施例•首先半導體非揮 發性記憶裝置從C P U接受抹消指令及執行抹消之片段之 位址。然後，在裝置內部設定賫料，重複進行抹消，核對 ，及整批判定動作。在片段內全部記慷馥晶胞之臨限值電 壓成爲髙於核對時之字線電壓時，完成抹消動作*亦即， 雖然已保證抹消側之臨限值電屋成爲高於核對時之字線氰 壓，亦即昇高臨限值之動作，但因爲未對片段內之每一記 本紙張尺度適用中國國家榡準（CNS > A4规格（210X297公釐} (請先閲讀背面之'ΪΪ-意事項再填窍本頁) -裝. -·* 經濟部中央標準局属工消費合作社印装 A7 B7 五、發明説明（5 ) 憶體晶胞控制抹消側之臨限值電壓，故如第1 2 ( a )圖 所示，較高側之睡限值電壓V t h Η之分佈具有大約2V 左右之範園* 同樣的ν在NAND方式中亦與第1 2 ( b )圓相同 的具有臨限值氰壓低側V t h L之臨限值電應分佈範園· 如上所述，NOR型連接（NCR，D I NOR， AND，Η I CR等）或任何一種NAND方式中，抹消 側之記憶體晶胞之臨限值電壓（NCR，NAND爲低側 之臨限值霉壓Vt hL，而D i NOR，AND， Η I CR爲高側之臨限值電壓V t hH)之分佈皆有其範 園，故記憶體晶胞之2個狀態之睡限值電壓差之絕對值丨 VthH — VthL丨大，不能降低改寫動作時之絕緣膜 之總通過電荷置（與2種狀態時之臨限值電壓差之絕對值 成比例）。因此，損傷絕緣膜，又產生膜質劣化，故其可 改寫之次數有限》 本發明之一個目的爲提供一種可利用電氣方式改寫之 半導體非揮發性記憶裝置中•可抑制對應於裝置內部之2 個記憶資訊之記憶體晶胞之臨限值電壓之分佈，可提高改 寫耐性之半導體非揮發性記憶裝置，及使用該裝置之電腦 系統β 依照本發明之半導髓非揮發性裝置*係一種包括分別 具有控制閘極，吸極及源極之許多非揮發性半導體記慷镰 晶胞，上述許多非揮發性半導體記憶體晶胞之控制閘極互 相共同連接之字線，及分別與上述許多非揮發性半導髏記 (請先閲说背面之>χ·意Ϋ項再填窍本頁) -裝. -訂 線 本紙張尺度適用中國國家標準（CNS〉Α4規格（210Χ297公f } Α7 Β7 五、發明説明（6 憶髖晶胞之各吸 性半導體記憶體 發性半導體記憶 性記憶裝置，其 進行抹消時*只 髓晶胞繼績進行 以下說明以 寫入動作係將臨 經濟部中央標準局貝工消费合作社印製 V t h L 施加一 1 極端子儷 選擇記憶 閘極內之 現象而被 浮閘極與 釋出。 抹消 V t h Η 施加1 6 極端子電 電壓。在 ，通道內 內。因爲 入漂浮閘 •例如 Ο V左 壓爲例 體晶胞 電子因 吸引至 吸極間 係將臨 。例如 V左右 壓成爲 選擇記 之電子 非選擇 極內。 極連接之許多位元線，對上述許多非揮發 晶胞寫入時，只對上述寫入不充分之非揮 體晶胞繼績進行上述寫入之半導體非揮發 中對上述許多非揮發性半導讎記慷體晶胞 對上述抹消不充分之非揮發性半導體記憶 上述抹消· A N D型記慷體晶胞寫入及抹消之動作· 限值電壓降低至低側之臨限值電壓 在記慷體晶胞之控制閘極上，亦即字線上 右之負竃壓，選擇晶胞中記憶體晶胞之吸 如5 V左右，而非選擇晶胞則爲Ο V ·在 之漂浮閘極與吸極之間產生電壓差，漂浮 佛拉·諾徳茵（Fowler-Nordheim)隧道 吸極側•在非選擇記慷髗晶胞中，因爲漂 之氰壓差小，故可防止電子從漂浮閘極內 限值電壓昇高至高側之臨限值電壓 在記憶髖晶胞之控制閘極*亦即在字線上 之高電.應，選擇晶胞中，記憶《晶胞之吸 0 V，而非選擇晶胞中則成爲大約8 V之 憶體晶胞之漂浮閘極與通道間產生電蜃差 因佛拉•諾德茵隧道現象而注入漂浮閘極 記憶髖晶胞之鼇壓差小，故可防止電子注 請 先 閱 背 之 注 項 再# 填I裝 頁 •訂 線 本纸張尺度適用t國國家標準（CNS ) Α4规格（21〇Χ297公釐）_ 9 _ ^ί〇432 Α7 Β7 經濟部中*標準局貝工消费合作社印製 五 、發明说明 σ ) 上 述 半 導 m 非揮 m 性 記 憶 裝 tsm 麗 中 因 磁 两 檢 測 已 iMs 進 行 你 入 之 非 揮 發 性 半 導 體 記 憶 體 晶 胞 之 狀 態 而 只 對 上 述 寫 入 不 充 分 之 非 揮 發 性 半 導 體 記 憶 餹 晶 胞 繼 績 進 行 入 而 且 檢 測 已 進 行 抹 消 之 非 揮 發 性 半 導 體 記 憶 體 晶 胞 之 狀 態 只 對 上 述 抹 消 不 充 分 之 非 揮發 性 半 導體 記 憶 镰 晶 胞 繼 績 進 行 抹 消 故 可 抑 制 谊 入 側 非 揮 發 性 半 導 體 記 憶 flft 晶 胞 之 m 限 值 電 壓 分 佈 之 不 均 勻 及 抹 消 側 非 揮 發 性 半 導 镰 記 JlgAe 憶 體 晶 胞 之 臨 限 值 電 壓 分 佈 之 不 均 勻 〇 m 因 此 可 滅 少 寫 入 側 m 限 值 電 壓 與 抹 消 側 臨 限 值 電 壓 間 之 電 iBs 差 絕 對 值 可 減 少 改 記 憶髖 晶 胞 之 臨 限 值 甩 壓 之 動 作 時 通 <?JEBL m 粑 緣膜 之 總 霪 荷 1: 〇 依 照 本 發 明 之 電 腦 系 統 具 有 上 述 半 導 體 非 揮 發 性 記 億裝 置 與 中 央 處理裝 置 而 且 不 依 照 中 央 處 理 裝 S 之 指 令 執 行 上 述 半 導 體 非 揮 發 性 記 憶 裝 置 之 上 述 再 寫 入 或 上 述 再 抹 消 〇 依 照 上 述 電 腦 系 統 9 因 爲 不 根 據 中 央 處 理 裝 S 之 指 令 執 行 上 述 半 導 髖 非 揮 發 性 記 憶 裝 置 之 上 述 再 寫 入 及 上 述 再 抹 消 故 系 統 不 會 變 成 複 雜 9 因 爲 在 非 揮 發 性 半 導 髄 記 憶 體 晶 胞 醮 限 值 電 壓 之 改 寫 動 作 時 可 利 用 佛 拉 • 諾 德 茵 隧 Μ m 故 可 實 現 低 m 壓 之 單 —. 電 源 化 〇 如 此 在 使 用 該 裝 gea 之 電 腦 系 統 中 可 因 低 電 壓 化 而 降 低 消 耗 電 路 及 提 高 可 靠 性 〇 以 下 參 照 圖 式 說 明 本 發 明 今 實 施 例 0 首 先 參 照 第 1 4 圖 銳 明 本 實 施 例 之半 導雠 非 揮 發 性裝 訂 線 本紙張尺度適用中國國家標準（CNS ) Α4規格(210X297公f ) _ 請 先 閲 讀 背 面 之 注 意 事 項 再，· 填 寫裝 本衣 頁 經濟部中央標準局員工消费合作社印製 A7 B7五、發明说明（8 ) 置之構造· 本發明之半導體非揮發性記憶裝置包括記憶艚晶胞陣 列JJL·，盖_，行位址緩衝器XADB ·行位址解碼器 XDCR，偵測器放大器與賫料閂鏔器共用之偵測閂鎖電 路SL及閘極陣列電路YG，列位址緩衝器YADB，列 位址解碼器YDCR，输入緩衝氰路D I B，输出緩衝器 DOB，多工器MP，模態控制電路MC，控制信號緩衡 器CSB，及內部電源電壓VS等。記憶臁晶胞係由可利 用電氣方式改寫記憶《晶胞之鼷限值電壓之E E P R 0M 所構成。 雖然無特別限制，但在控制信猇緩衝器c S B之外部 端子n，01，分別输入晶粒啓動信號，输 出啓動信號，寫入啓動僧號，及串聯時鐘信號等，配合各 信號產生內部控制僧號之時序信號β 就緒（Ready) /忙線（Busy)信號從外部端子R/ 输入模態控制器MC中。 本實施例中之"ϋΐ，ϋΐ，等之符號「一」表示 相補信號。 雖然無特別限制，但內部m源電壓v s從外部输入m 源電壓V c c而產生讀出字線電壓V r ，昇高臨限值m壓 之動作時之字線電壓Vh，其核對字線電壓Vhv，降低 臨限值電壓之動作時之字線電壓V 1，其核對字線電壓 Vlv，讀出位元線《壓Vrb，讀出基準位元線電應 V r r，昇高臨限值竃應之動作時之吸極端子《壓Vh d (請先閱讀背面之注f項再填寫本頁) -裝. -* 成 本紙張尺度適用中國國家橾準（CNS ) A4規格（210X297公釐）_ 11 _ 經濟部中央標準局負工消費合作社印製 A7 B7五、發明説明（9 ) ’其轉換閘極電壓V h t，降低臨限值電懕之動作時之吸 極端子m壓v 1 d，及其轉換閘極霪壓v1 t ·上述各電 壓亦可從外部供給· 從內部電海電壓VS產生之字線電壓Vr，Vh， Vhv，V1，viv，及轉換閑極電壓Vht ·νΐ t 输入行位址解碼器XDCR，而位元線電壓Vrb， Vr r，Vwd，Vhd及轉換閘極電壓Vh t，VI t 输入偵測閂鎖器S L · 內部重源電壓亦可共用氰源電壓•例如亦可共用昇髙 臨限值電壓之動時之吸極端子電壓V h d與降低酶限值電 壓之動作時之吸極端子電應V 1 d，或共用轉換閘極電壓 V h t 與 V 1 t。 雖然無特別限制，但行，列位址緩衝器XADB， Y A D B係被裝置內部之晶粒啓動選擇信號ΓΊΓ活化，從 外部端子输入位址信號ΑΧ，AY，形成由與從外部端子 供給之位址信號同相之內部位址信號，及相位相反之位址 信號所構成之相補位址信號·行位址解碼器XD C R形成 對應於行位址緩衝器X A D B之相補位址信號之記慷體晶 胞群之字線W之選擇信猇，而列位址解碼器YD C R形成 對應於列位址緩衝器Y A D B之相補位址信號之記憶镰晶 胞群之位元線B之選擇倌號。上述各選擇信號選揮記憶體 墊塊（Mat)內之任意字線W及位元線B，並選擇所需之 記憶體晶胞。 雖然無特別限制，但記憶體晶胞陣列I’ I內之記慷 (請先ΜΪ#-背面之ίΐ·意事項再填寫本頁) -裝· 、va 線 本紙張尺度適用中國國家標準（〇阳）八4规格（2丨0乂297公釐）-12__ ό^〇432 Α7 Β7 五、發明説明（1(1 ) 髖晶胞由例如行位址解碼器X D C R及列位址解碼器 YDCR以8位元或1 6位元之單位選揮*並進行寫入及 讀出。假設1個資料塊之記憶體晶胞在字線方向（行方向 )有m個，在位元線方向（列方向）有η個時，則由8個 或1 6個構成mx η個記憶《晶胞群之賫料塊* 如上所述•記憶«晶胞陣列且ϋ內之記憶臁晶胞之 構造與E P ROM之記憶體晶胞類似，而使用具有控制鬧 極與漂浮閘極之公知之記憶镰晶胞構造，或具有控制閘極 與漂浮閘極，及選擇閘極之公知之記憶體晶胞構造•以下 參照第4圓說明具有控制閘極及漂浮閘極之記憶髗晶胞之 構造。 第4圖所示非揮發性記憶體晶胞之構造與1 9 8 7年 發表之 International. Electron Devices Meeting Tech. Dig. pp. 560-563中之快閃記慷體之記憶體晶胞之電晶體 相同。雖然無特別限制，該記億鼸晶胞係形成於由單結晶 P型矽所構成之半導雔基板上》 經濟部中央標準局貝工消费合作社印| (請先閲讀背面之注意事項再填寫本頁) 該非揮發性記憶髖晶胞係由包括控制閘極1 ，吸極2 ，源極3，漂浮閘極5，層間絕緣膜4，隧道絕緣膜6， P型基板7，吸極與源極領域之高不純物澳度之N型擴散 層8，9，吸極側之低不純物濃度之N型擴散層1 0，及 源極側之低不純物漉度之P型擴散層11之電晶體元件構 成1個快閃抹消型EEPROM晶胞· 上述各記憶體晶胞係以例如從第7圖至第11圖所示 之NOR型，D I NOR型，AND型，H I CR型或 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）_ 13 - 經濟部中央標準局貝工消費合作社印製 ΑΊ ________Β7_ 五、發明説明（11 ) N A N D型等方式連接而構成記慷體晶胞陣列部1及止_。 以下參照第5a ，5b，6a ，6b圖之記憶體晶胞 之斷面模式圈及端子施加鬣壓說明將記慷镰晶胞之臨限值 電壓選擇性的昇高及降低之動作，亦即改寫動作手法。 第5a ，5b圖中表示選擇性的降低片段內之記憶體 晶胞之臨限值電壓之動作•在連接於片段上之字線上施加 例如- 1 0 V左右之負壓而在片段內之全部記憶體晶胞之 控制閘極上施加—1 0V之電壓•如第5 a _所示，在希 望降低臨限值電壓之記慷體晶胞上，亦即被還擇之記慷髏 晶胞之吸極端子上選擇性的施加例如5 V左右之電壓，即 可在漂浮閘極與吸極之間產生電壓差，利用佛拉·諾德茵 陲道現象將漂浮閘極內之電子吸引至吸極側。另外，如第 5 b圖所示，在非選擇記憶體晶胞之吸極端子施加Ο V即 可消除漂浮閘極與吸極間之電位差，防止電子從漂浮閘極 內釋出· 第6 a ，6 b_表中將片段內之記憶體晶胞之睡限值 電壓選擇性的昇高之動作。在連接於片段之字線上施加例 如1 6 V左右之正電壓而在片段內之全部記憶體晶胞之控 制閘極上施加16V之電壓•如第6a_所示，在希望昇 高臨限值電壓之記憶體晶胞上，亦即被選揮之記憶證晶胞 之吸極端子上選擇性的施加0 V之電壓，即可在漂浮閘極 與頻道之間產生電壓差*可利用佛拉•諾德茵隧道現象將 通道內之«子吸引至漂浮閘極內。另外，如第6 b匯所示 ，在非選揮記憶«晶胞之吸極端子上施加例如8 V左右之 本紙張尺度適用中國國家標準（€阳>六4規格（2丨0父297公釐）_14 (請先閱讀背面之注意Ϋ項再填寫本頁) -裝. 訂 A7 ____B7 _ 五、發明説明（12 ) 電壓，即可滅少漂浮閘極與通道間之電位差，防止電子注 入漂浮閘極內· 請 先 閲 讀- 背 之 注· 意 事 項 再一 填 I裝 頁 在降低睡限值電壓之動作時施加於非選揮字線上之竃 壓係施加正電壓*以防止因吸極《壓所造成之干擬（ Disturbance，電子之放電）·因此*在改寫動作時將源 極開放而防止正常電流之通過。亦可將昇高記憶體晶胞之 臨限值電壓之動作時之吸極電壓，亦即通道電壓設定爲負 電壓而降低控制閘極之電壓，亦即字線電壓· 訂 由第a，5b，6a，6b圓可知，片段內之記憶髖 晶胞之臨限值電壓可藉著對每一記慷饞晶胞設定施加於其 吸極端子之《壓值而選擇性的改寫·爲了對每一記憶髖晶 胞設定施加於片段內之記憶體晶胞之吸極端子上之電壓， 可如後文中所述，使設在毎一位元線之偵測閂鎖電路S L 內之正反器具有施加於各記憶«晶胞之吸極端子上之電壓 資訊。 線 經濟部中央標準局貝工消费合作社印製 以下參照第1 7圖說明偵測閂鎖電路SL ·第1 7圖 爲以第1 4園之開放位元線方式配置記憶置晶胞陣列部i ，立_與偵測閂鎖電路S L之連接之一電路圖· 第1 7圖中，只在設置於記憶體晶胞陣列部卫_內之位 元線B u 1與記憶髗墊片記憶髗晶胞陣列部止_內之位元線 B d 1間之包含正反器之偵測閂鎖電路上附加符號S L 1 ，而對其他位元線B u η及B d η亦連接相同（等效）之 偵測閂鎖《路。偵測閂鎖電路S L之控制信號依照位元線 之偶數/奇數分開》其理由爲防止位元線之寄生線間之電 本紙張尺度逋用中國國家標準（CNS > Α4规格（210X297公釐）_ - 310432 Μ Β7 經濟部中央標隼局貝工消费合作社印装 五、發明説明（13 ) 容量對偵測動作發生不良之影響•例如在連接於偶數位元 線（Bu2，Bu4或Bd2，Bd4)之記慷臁晶胞正 在進行偵測動作時，將奇數位元線（Bui，Bu3或 Bd 1 ，Bd3)之電位設定爲Vs s而使寄生線間電容 置成爲一定值，並讀出連接於偶數位元線側之記憶髏晶胞 • 記憶《晶胞陣列部JL_內之奇數位元線Bun (n=l • 3 )連接於以閘極信號BD e u爲输入，將位元線之電 位放電成爲接地電壓Vs s之MOS電晶藿Ml ，以閘極 信號R C e u爲输入而預先電位元線之電位之MO S電晶 體M2，以預充電信號PCeu爲閘極输入信號之MOS 電晶體M3 *及以正反器之資訊爲閘極输入信號之MOS 電晶體M4·M3與M4之連接不限定於第17圖所示之 方式，亦可爲電源電壓Vcc側爲M3，位元線Bun側 爲M4·奇數位元線BuN連接於配線Bunf ，而配線 B u n f連接於以閘極信號TR e u爲输入之MO S電晶 ®M5 ·正反器側配線B u 1 f連接於以將正反器之電位 放電成爲接地電應V s s之閘極僧號R S L e u爲輸入之 MO S電晶镰M6，以配合列位址之列閘極信號Y a d d 爲输入而產生正反器內之賫訊之MO S電晶體Μ 7，及以 正反器內之資訊爲閘極输入信號之MO S電晶體Μ8。連 接於第奇數條配線B u n f之MO S電晶體M8之吸極連 接於共用信號AL e u ·源極連接於接地竃壓V s s而組 成多段输入NOR電路連接•亦即MO S電晶«Μ8係判 本紙張尺度逋用中國國家樣隼（CNS > A4規格（210乂297公釐> _ _ (請先閲讀背面之注意事項再填寫本頁) -裝. 訂 線 經濟部中央標準局負工消費合作社印掣 A7 ____B7 _ 五、發明説明（14 ) 定連接於第奇數條配線B u n f之全部正反器之資訊是否 成爲接地電屋v s s之mo sm晶髏· 在記億«晶胞陣列及_內之偶數位元線Bun (n = 2 ，4 )及記億體晶胞陣列部止_內之奇數位元線Bdn (η =1，3)及偶數位元線Bdn (η = 2，4)上亦連接 構造相同之電路· 以上說明本實施例之半導體非揮發性記億裝置之構造 。以下參照第1，2圖說明本實施例特徽之醱限值電懕之 改寫動作程序•有關本實施例之寫入動作程序•係與上述 表示習用之寫入動作之程序相同。亦即半導體非揮發性記 憶裝置從C P U接受指示寫入之指令，進行寫入之片段內 之記憶體晶胞群之位址，及寫入資料（步驟S 1 — S 3 ) 。然後，在對每一位元線設置之偵測閂鎖電路S L內之正 反器內設定寫入賫料，配合該寫入資料對片段內之記慷髖 晶胞選擇性的進行寫入動作（步驟S4)。然後*整批的 將臨限值電壓核對（步驟S 5) *改寫正反器內之資料， 以便只對寫入不充分之記慷髄晶胞繼績進行寫入動作（步 驟S6)。然後重複進行寫入動作，核對，及資料改寫動 作，一直到全部寫入對象之記慷體晶胞之臨限值亀壓達到 一定之臨限值電壓爲止（步驟7)。 以下說明第2圓之抹消動作程序》 半導髏非揮發性記憶裝置從C P U接受指示抹消之指 令，及進行抹消之片段內之記慷《晶胞群之位址（步蹰 S11及S12) ·然後，在對每一位元線設置之偵測閂 本紙張纽適用中家辟（CNS ) Α4規格（2丨GX297公S ) _ 17 _ "~~~ --------ΙΊ裝------丨訂-----Η線 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消費合作社印犁 A7 __ 五、發明説明（15 ) 鎖電路S L內之正反器上設定一定之資料（步屬[S 1 3 ) ，對片段內之記慷體晶胞進行聱批之抹消動作（步騄 S1 4) ·然後，以片段單位整批的將臨限值電蹏核對（ 步驟15)，改寫正反器之資料（步驟S16)以便只對 抹消不充分之記慷《晶胞繼績進行抹消動作。然後，重複 進行抹消動作，核對，資料改寫動作* 一直到全部寫入對 象之記憶體晶胞之睡限值電壓達到一定之醮限值霉壓爲止 *亦即本實施例之改寫動作程序因爲在核對動作後與雎限 值電壓整批判定動作之間必定進行資料改寓動作，故可對 毎一記慊體晶胞進行高精確度之控制。 第1 3 a _表示執行本實施例之改寫動作程序時之記 憶體晶胞臨限值電壓之分布*由第13 (a)圈可知，執 行本實施例之改寫動作程序即可使高臨限值電壓V t hH 之分佈範園與低臨限值儷壓V t h L之分佈成爲一致· 本實施例之改寫動作程序係假設記慷髗晶胞具有高臨 限值電壓與低臨限值電壓，亦即具有雙值之資訊，但在記 憶體晶胞具有多值資訊時亦可執行本實施例之改寫動作程 序》以下參照第1 3 ( b )圆說明記憶镰晶胞具有4值資 訊時之實施例•依照本實施例之抹消動作，控制每一位元 之記憶體晶胞之臨限值電壓t h4 (或V t h 1 )而使臨 限值電壓分佈成爲整齊，並且於毎三個其他臨限值電壓 Vthl (或 Vth4) ，Vth2，Vth3 執行本實 施例之寫入動作程序，即可如第1 3 b圓所示的使四個臨 限值電壓之分佈成爲一致》 本紙張尺度適用t國國家標準（CNS ) A4規格(_2丨0X297公釐）— (請先閱靖背面之注意事項再填寫本頁) -裝 訂 經濟部中央標準局貝工消费合作社印製 A7 ___ B7 五、發明説明（16 ) 執行本實施例之改寫動作程序後，各臨限值電壓對半 導體非揮發性記慷裝置之記慷賫訊之不均勻成爲1V以下 •該臨限值電壓之不均匀係依存因一次寫入或抹消動作而 改變記憶體晶胞瞄限值電壓之數值Δν t h *及核對動作 時通過晶胞電流之記億鼸晶胞之數置之背部偏壓效果之數 值。爲了更進一步抑制臨限值電壓之不均句，最有效之方 法係減小寫入或抹消時之臨限值電壓變化置Δν t h，改 善源極側之電阻值。 第1 5，1 6圖表示執行以片段單位改寫記憶體晶胞 之臨限值電壓之動作程序時之偵測閂鎖電路S L內之正反 器之資料· 第1 5，1 6圖所示之正反器之賫料將連接於 正反器之記憶髖晶胞之鼸限值電屋定義爲高電壓狀態之臨 限值電壓，而正反器之賫料之電懕爲接地電壓V s s ·正 反器之資料'1#將記慷髗晶胞之臨限值電壓定義爲低電 壓狀態之臨限值電壓•正反器之資料例如爲外部電源m壓 V c c，在改寫動作時成爲內部昇壓電位之吸極端子電壓 V h d，V 1 d。 首先參照第1 5 Η說明降低記憶髄晶胞之睡限值電壓 之動作程序•若降低記憶髏晶胞之臨限值電壓之動作爲寫 入動作時*則输入將連接於保持高臨限值幫懕（抹消狀態 )之記憶髖晶胞之偵測閂鎖電路內之正反器設定爲'0' ，而將連接於改寫成低瞄限值電壓之記憶體晶胞之正反器 設定爲'1#之黉料•若降低記憶«晶胞之臨限值電壓之 本紙張尺度適用中國國家標準（CNS ) Λ4規格< 210 X 297^# ) _ jg _ (請先閲娇背面之注意事項再填寫本頁) -裝· 丁 . -'β 線 經濟部中央標準局負工消費合作社印製 A7 ___B7_ 五、發明説明（17 ) 動作爲抹消動作時，則將正反器之全部賫料設定爲' 1 # •然後，對連接於因第5a，5b圓所示之吸極邊緣佛拉 •諾德茵》道現象而設定'1#之正反器之記憶*晶胞進 行改寫動作•亦即，使連接於被邐揮之片段之選揮字線之 電應成爲5 V，使連接於設定之正反器之位元線之 «壓成爲V s s，只對連接於設定'1'之正反器之記憶 體晶胞吸出其漂浮閘極內之電子。 在核對時，將選禪字線之電壓設定爲例如1. 5V， 只對連接於設定爲之正反器之位元線進行遢揮性預 充《•在改寫臨限值竃壓達到與核對字線電廳闻值之 1. 5V之記慷體晶胞中*晶胞電流通過而成爲通路，將 位元線之電位放《·因此，將正反器之資料改寫成 •在瞄限值電壓未達到1. 5V之記憧體晶胞中無晶胞《 流通過而成爲睛路，位元線之鬣位保持預充電時之電壓而 保持正反器之賫料爲'1# •將核對後之正反器之賫料做 爲再改寫資料*重複進行改寫及核對動作*正反器之全部 資料成爲'0#時，即完成降低臨限值《壓之動作*該整 批判定係在晶胞內自動的進行<* 以下參照第16圓說明昇高記慷觼晶胞之臨限值電壓 之動作程序。若昇高記憶體晶胞之釀限值電壓之動作爲寫 入動作時，則输入使連接於保持低臨限值電壓（抹消狀態 )之記憶髗晶胞之偵測閂鏔電路內之正反器成爲， 使連接於改寫成高醮限值m壓之記憧體晶胞之正反器成爲 之資料•若昇高記憶體晶胞之醮限值亀壓之動作爲 本紙張尺度適用中國國家梂準（CNS )八4规格（210X297公嫠）_ 2〇 _ --------丨 — (請先閲讀背面之注意事項再填寫本頁) 訂 7 旅 經濟部中央梂準局貝工消费合作社印製 A 7 __ B7 五、發明説明（18 ) 抹消動作時，則將正反器之全部賫料殷定爲*〇〃 •然後 ’對連接於第6圓所示之因吸極邊緣佛拉·諾德茵鼸道現 象而設定爲II#之正反器之記憶體晶胞進行改寫動作。 亦即將連接於被選擇之片段之選擇字線之電壓設定爲 1 6V，將連接於設定爲之正反器之位元線電壓設 定爲Vs s，將連接於設定爲'1·之正反器之位元線電 壓設定爲8 V，只對連接於設定爲之正反器之記憶 體晶胞之漂浮閘極內注入電子· 在核對時，將選擇字線之電壓設定爲例如4. Ο V . 以全部位元線爲對象進行預充電•因此改寫臨限值電壓未 達到與核對字線電壓同值之40V之記慷體晶胞中通過 晶胞電流而成爲斷路，將位元線之電位放電•因此，正反 器之資料保持*另一方面，臨限值蕙壓達到4. 0 V之記«體晶胞中無晶胞電流通過，故成爲導通*位元線 之電位保持預充電之電壓，被改寫成正反器之資料' 1 # 。然後.以核對後之正反器之賫料做爲再改寫資料，反複 進行改寫及核對動作•當正反器之全部資料成爲時 ，降低臨限值電壓之動作即告完成，該整批判定係在晶粒 內自動的進行·310432 A 7 Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of the invention (1) The present invention relates to a semiconductor non-volatile memory device composed of transistors that can be rewritten with a cyanide method, Especially about the non-volatile memory device that frequently rewrites the threshold voltage by electrical means and the computer system using the device. The flash memory system can use the entire batch of electrical methods to erase the generous content of the single transistor / cell method of a non-volatile semiconductor memory device. Because in the flash memory, each bit has a small footprint, It is possible to achieve high-density, so it has recently been asked to do a lot of research and development on its structure, connection method * and driving method. Currently it has been published in Symposium on VLSI Circuits Digest of Technical Papers pp97-98 1993 DIN0R ( Divided bit Line NOR) method, also published in the skeletal report pp 99-100, the NOR method in 1993, and the AND method in PP61-62 1994, also published in the International Electron Devices Meeting Tech. Dig. Pp- 19-22 1993 HICR (High Capacity-Coupling Ratio method, and the NAND method published in Symposiun on VLSI Circuits Digest of Technical Papers pp2 0-2 1 1 992 · 7th, 8th, 9th, 10th and 11th round Connection examples of memory cells using the NOR method, DI NOR method, HI CR method, and NAND method, respectively. No. 7, 8 * 9, 10, and 11_, W 1 ......... .Wm is the word line " Β1, B2 are bit lines, each memory cell is composed of an electric crystal with control gate and floating gate (please read the legal matters on the back side and then fill out this page) Γ loaded.- s: The size of the line paper is applicable to the Chinese National Standard (CNS) A4 format (210X297 mm) 4-310432 A7 _ B7 5. Description of the invention (2). The above methods can be classified according to the connection state of the memory cell N 0 R, DI NOR, AND, HI type NOR type connection and NAND type connection • According to the NOR type connection shown in Figure 7, the word line power during reading should be the power supply voltage V c C. In the state where electrons are stored in the floating gate, the threshold voltage of the memory cell from the control gate rises, and even if the word line is selected and Vc c is applied to the control gate, there will be no sickle cell current. Pass. In a state where electrons are not injected into the floating gate (emission of electrons), the threshold voltage of the memory cell is low, and there is a selection of word lines to pass through the cell current. To detect the amplifier to accept the memory cell current And the judgment information, or '1,. The 1 2 a circle indicates that the NOR connection corresponds to 2 The distribution of the threshold voltages V t hL and V t hH of the memory cell of Yixun · V th L represents the threshold voltage of the memory cell when electrons are not injected into the floating gate, V th Η represents The memory of electronic storage in the floating gate is the threshold value of the cell. Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling in this page) because it is connected in the N 0 R type At the time of reading, the applied voltage of the unselected word line at the time of reading is the ground voltage V ss, so if the voltage limit value of the cell of the generous body becomes a negative voltage, it becomes the cause of misreading * so * must be highly accurate Control to prevent V th L from becoming a negative voltage. The following describes one of the writing operations in the AND mode (the operation of rewriting the sleep limit voltage to V th L) with the NOR connection shown in Figure 9 with reference to FIG. 1 Example • When writing in the NAND mode, input a write command from the CPU, and connect the required text to the memory cell array. The paper size is applicable to the national standard (CNS) A4 specification (210X297mm) _ 5-3ί〇432 Printed by Beigong Consumer Cooperatives, Central Bureau of Standards, Ministry of Economic Affairs Α7 _Β7 _ Fifth, the description of the invention (3) The address of the line "the address of the unit cell group (hereinafter referred to as the sector) * and the writing material in the memory device * Set the unit writing time and correspond to the Memory for writing data of the selected segment "Check after the entire batch of writing on the unit cell • If the result of the checking is that there is insufficiently written memory unit cell, it means that the writing gull limit voltage has not been reached (V v ) Of the memory cell, rewrite the write data inside the device, so that only the incompletely written memory of the sickle cell succeeds the write operation. • Write, check, and write operations are repeated until Note of all writing objects "Until the threshold voltage of the cell reaches the writing threshold voltage (Vv) · Because the writing side of the memory cell within each bit control segment is controlled according to the channel operation procedure The threshold value of the threshold voltage V th L, so after writing, the threshold voltage of the memory skull cell on the V th L side can be made to be the same * Under the consideration of the distribution circle of V th L * the sleep limit value will be written The voltage (Vv) is set to V th L for all the writing state of the memory cell will not become negative The state, for example, about 1.5V * Figure 12 (b) shows the distribution of the threshold voltages V th L and V t hH of the memory turtle cells corresponding to the two memory bits in the NAND mode • In the NAND mode When using the non-selective wavy line at the time of turning out as the power supply voltage V cc, no matter how high or low the threshold m should be, all the non-selecting memory cells are used for "Crystal Use The voltage applied to the time selection word line is grounding "KV ss · Therefore · V th L is set at a value that is memorized by the ground voltage Vs s" and the cell current encounters, and vth η is set at the non-smooth word line The m source of the m voltage "between the voltage V cc and the ground of the selected word line voltage V ss · This paper standard uses the Chinese National Standard (CNS) A4 specification (210X 297 public Γ _ 6 _ ----- --- "Pack ----- Order .------ (please read the notes on the back of is before filling in this page) A7 _B7_ _ printed by Beigong Consumer Cooperative of Central Bureau of Standards of the Ministry of Economic Affairs (4) Since all non-selective memory cells are used as electric crystal hips in the NAND mode, the gate m voltage must be controlled with high accuracy Vt hH (write side), so as not to exceed the power supply voltage Vc c. Therefore, the NAND mode also repeatedly writes, checks, data rewrites, and controls the writing of the memory cell in each bit The limit value is the same as in the above AND method, until the threshold voltage of all the memory hip cells written to the object reaches the writing threshold voltage (Vv). Consider the distribution range of V t hH. The writing limit voltage (Vv) is set so that the sleeping limit voltage of all memory cells to be written does not become a voltage value higher than the power supply voltage V cc, for example, about 25V. In the above-mentioned conventional NOR connection When connected with NAND type, all of them are in the control section of the billion cell unit. The writing voltage of the writing side of the unit is aimed at the limit voltage, but the erasure limit of the erasing side is not sufficiently controlled. Only the maximum or minimum threshold voltage is ensured so as to be higher than the power supply voltage V cc in the NOR connection and lower than the ground voltage V ss in the NAND mode. The following describes one embodiment of the operation procedure of the conventional NAND method of erasing (increasing the threshold response) with reference to circle 3. First, the semiconductor non-volatile memory device receives the erasure command from the CPU and the address of the segment where the erasure is performed. Then, set the paste inside the device, repeat erasing, checking, and the whole batch of judgment actions. When the threshold voltage of the generous unit cell becomes the zigzag line voltage at the time of verification, the erasing operation is completed * That is, although it has been guaranteed that the electrical house at the erasure side becomes higher than the word at the time of verification Line cyanide pressure, that is, the action of raising the threshold, but because each paper standard in the clip is not applicable to the Chinese National Standard (CNS > A4 specification (210X297 mm) (please read the back of the first ΪΪ-Issues and refill this page) -Installation.-· * Printed by the Ministry of Economic Affairs, Central Standards Bureau, Industrial and Consumer Cooperatives A7 B7 5. Description of the invention (5) The memory cell controls the threshold voltage on the erasure side, so As shown in Fig. 12 (a), the distribution of the upper limit of the sleep limit voltage V th Η has a range of about 2V * The same ν is also the same as the circle 1 2 (b) in the NAND method The threshold value of V th L on the low-side cyanide voltage threshold should be distributed. As mentioned above, in the NOR connection (NCR, DI NOR, AND, H I CR, etc.) or any NAND method, the side The threshold voltage of the memory cell (NCR, NAND is the threshold of the low-side mildew Vt hL, and D i NOR, AND, HI CR The distribution of the threshold voltage V t hH) on the high side has its own range, so the absolute value of the difference in the sleep limit voltage between the two states of the memory cell is large 丨 VthH — VthL 丨 can not reduce the time of rewriting action The total pass charge of the insulating film (proportional to the absolute value of the threshold voltage difference in the two states). Therefore, the insulating film is damaged and the film quality is deteriorated, so it can be rewritten a limited number of times. "An object of the present invention In order to provide a semiconductor non-volatile memory device that can be electrically rewritten • The distribution of the threshold voltage of the memory cell corresponding to the two memory information inside the device can be suppressed, and the semiconductor non-volatile memory that can improve rewriting resistance Memory device and computer system using the device β The semi-conducting non-volatile device according to the present invention is a kind of non-volatile semiconductor memory cell including a control gate, a sink and a source. The control gates of many non-volatile semiconductor memory cells are connected to each other, and the above-mentioned many non-volatile semiconductor skulls (please read the ">" Ϋ Item refill this page) -Installation. -The paper size of the binding book is applicable to the Chinese national standard (CNS> Α4 specification (210Χ297 public f) Α7 Β7. Fifth, the invention description (6 memory of each absorbent semiconductor memory of hip cell In the case of erasing semiconductor memory devices, only the medullary cell succeeds in the erasing. The following instructions are used to write the system. The Vth L will be printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. The phenomenon in the memory gate is released by the floating gate. Erasing V th Η Apply a 16-terminal electric voltage. Within, within the channel. Because it enters the floating gate • For example, Ο V left pressure is taken as an example. The cell is attracted to the inter-electrode system due to attraction. For example, the voltage around V becomes the electronic non-selective pole of the selection record. When writing to many of the non-volatile unit cells of the many bit lines connected to the pole, only the non-swinging unit cells whose writing is insufficient are used to perform the writing. The memory of the non-volatile semiconductor with the above-mentioned incomplete erasure of the above-mentioned erasing by the lead cell is the above-mentioned operation of writing and erasing of the AND-type cell of the gene body. The threshold voltage is lowered to the lower side of the threshold voltage. On the control gate of the body cell, that is, the negative negative pressure on the right of the word line, the memory cell in the selected cell is sucked like 5 V, but the non-selected cell is Ο V. The floating gate and the suction in the cell There is a voltage difference between the poles, floating the suction side of the Fowler-Nordheim tunnel • In the non-selective Kang Kang cell, because the pressure difference of the floating cyanide is small, it can prevent electrons from floating gate The internal limit voltage rises to the high side of the threshold voltage at the memory gate of the control cell of the hip * that is, the high current on the word line. Should be selected in the cell, the memory "the cell sucks 0 V, not In the selected cell, it becomes the floating gate and channel of the memory cell of about 8 V. The difference in electricity generation is small due to the Fula Norden tunnel phenomenon. The pressure difference between the hip and the memory cell of the floating gate is small, so you can prevent the electronic note. Please read the back note first # Fill in the I page • book The paper standard is applicable to the National Standards (CNS) Α4 specifications (21〇Χ297 mm) _ 9 _ ^ ί〇432 Α7 Β7 Printed by the Ministry of Economic Affairs * Bureau of Standards, Beigong Consumer Cooperatives V. Invention description σ) m Non-volatility memory device tsm Li Zhong only conducts follow-up on the non-volatile semiconductor memory cells with insufficient writing due to the status of the non-volatile semiconductor memory cells that iMs has entered into you. Enter and detect the state of the non-volatile semiconductor memory cell that has been erased. Only the non-sufficient non-volatile semiconductor memory sickle cell that has been erased above will be erased. This can suppress the entry of the non-volatile semiconductor memory flft cell The uneven distribution of the m limit voltage and The non-volatile semiconducting sickle on the erasing side JlgAe memory cell has a non-uniform threshold voltage distribution of 0m, so it can eliminate the absolute value of the difference in electrical iBs between the m-limit voltage on the writing side and the threshold voltage on the erasing side. Can reduce the time limit of the throttling operation to change the threshold of memory hip cells <? JEBL m total membrane charge of the marginal membrane 1: 〇 The computer system according to the present invention has the above semiconductor non-volatile memory device and central processing device and does not execute the semiconductor non-volatile memory according to the instructions of the central processing device S The above-mentioned rewriting or the above-mentioned re-erasing of the device. According to the above-mentioned computer system 9, the system will not become complicated because the above-mentioned rewriting and the above-mentioned re-erasing of the semi-conducting hip non-volatile memory device are not performed according to the instructions of the central processing unit S. 9 Because the non-volatile semiconductor memory cell can be used to rewrite the limit voltage of the Frau Norden Tunnel Μ m, it is possible to achieve a low m voltage single. Power supply. So use this device Gea's computer system can reduce consumption circuits and improve reliability due to lower voltage. The following describes the present embodiment of the present invention with reference to the drawings. First, refer to the first figure. Figure 4 shows that the semi-conducting non-volatile binding line of this embodiment is compatible with the Chinese National Standard (CNS) Α4 specification (210X297 public f) _ please Read the precautions on the back first, and then fill out this page and print A7 B7 printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the invention (8) Structure of the device • The semiconductor non-volatile memory device of the present invention includes memory crystal Cell array JJL ·, cover_, row address buffer XADB · row address decoder XDCR, detector latch circuit SL and gate array circuit YG shared by the detector amplifier and the grab latch, column address Buffer YADB, column address decoder YDCR, input buffer cyan circuit DIB, output buffer DOB, multiplexer MP, modal control circuit MC, control signal buffer CSB, and internal power supply voltage VS, etc. The memory cell is composed of the E E P R 0M that can be rewritten electrically using the electrical method. Although there are no special restrictions, at the external terminals n, 01 of the control signal buffer c SB, the die start signal is input, the start signal is output, the start signal is written, and the serial clock signal, etc., is generated in conjunction with each signal to generate internal control The monk's timing signal β Ready / Busy signal is input into the modal controller MC from the external terminal R /. In this embodiment, the symbols "I", "I", "I", etc. indicate a complementary signal. Although there is no particular limitation, the internal m-source voltage vs. the m-source voltage V cc is input from the outside to generate the read word line voltage V r, and the word line voltage Vh during the operation of raising the threshold m voltage is checked against the word line voltage. Vhv, the word line voltage V 1 during the action of reducing the threshold voltage, which checks the word line voltage Vlv, reads the bit line "voltage Vrb, reads the reference bit line voltage should be V rr, and increases the threshold value. At the time of the action, the suction terminal "pressure Vh d (please read the note f on the back and then fill in this page)-installed.-* The cost paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) _ 11 _ Printed A7 B7 by the Negative Consumers Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of the invention (9) 'The conversion gate voltage V ht reduces the suction terminal m voltage v 1 d during the action of lowering the threshold current And its conversion gate scan voltage v1 t · the above voltages can also be supplied from the outside · the zigzag line voltage Vr, Vh, Vhv, V1, viv generated from the internal electric sea voltage VS, and the conversion idle voltage Vht · ν lt input Row address decoder XDCR, and bit line voltage Vrb, Vr r, Vwd, Vhd and conversion gate voltage Vh t, VI t input Measuring latch SL · The internal heavy source voltage can also share the cyanide source voltage • For example, it can also share the sink terminal voltage V hd when the threshold voltage is raised and the sink terminal when the enzyme limit voltage is lowered The voltage should be V 1 d, or the common switching gate voltages V ht and V 1 t. Although there is no particular limitation, the row and column address buffers XADB, YADB are activated by the die start selection signal ΓΊΓ inside the device, and the address signals AX, AY are input from the external terminals to form the addresses supplied by the external terminals The internal address signal of the same phase of the signal and the complementary address signal of the opposite phase of the address signal. The row address decoder XD CR forms a memory cell corresponding to the complementary address signal of the row address buffer XADB The selection signal of the group word line W, and the column address decoder YD CR form the selection line number of the bit line B of the memory sickle cell group corresponding to the complementary address signal of the column address buffer YADB. Each of the above selection signals selects any word line W and bit line B in the memory mat (Mat), and selects the desired memory cell. Although there are no special restrictions, the memory cell array I'I in the memory is generous (please fill in this page before ΜΪ # -the back side of the matter), -installation, va line book paper scale applies to Chinese national standards (〇 Yang) 八 4 specifications (2 丨 0 侂 297mm) -12__ ό ^ 〇432 Α7 Β7 V. Description of invention (1 (1) The hip unit cell is composed of, for example, row address decoder XDCR and column address decoder YDCR 8-bit or 16-bit units are selected * and written and read out. Suppose there are m memory cells in a data block in the word line direction (row direction) and in the bit line direction (row Direction) When there are η, 8 or 16 constitute mx η memories "Cling block of the unit cell group * As mentioned above • Memory« Unit cell array and the structure of the memory cell in the ϋ and EP The memory cell of ROM is similar, and the well-known memory cell structure with control gate and floating gate, or the well-known memory cell structure with control gate and floating gate, and selective gate are used • The structure of a memory cell with a control gate and a floating gate is described below with reference to circle 4. The non-volatile memory shown in Figure 4 The structure of the unit cell is the same as the transistor of the memory cell unit of the flash memory in the International. Electron Devices Meeting Tech. Dig. Pp. 560-563 published in 1987. Although there are no special restrictions, the record is 100 million. The mon cell is formed on a semiconducting substrate made of single-crystal P-type silicon. Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs | (please read the precautions on the back before filling this page) The non-volatile memory hip The unit cell consists of the control gate 1, the sink 2, the source 3, the floating gate 5, the interlayer insulating film 4, the tunnel insulating film 6, the P-type substrate 7, the high impurity in the field of the sink and the source. The transistor elements of the N-type diffusion layers 8, 9, the low-impurity N-type diffusion layer 10 on the sink side, and the P-type diffusion layer 11 with low impurity concentration on the source side constitute a flash erase EEPROM Unit Cells The above-mentioned memory cell units are, for example, NOR type, DI NOR type, AND type, HI CR type, or paper size as shown in Figures 7 to 11 in accordance with the Chinese National Standard (CNS) A4 specification ( 210X297mm) _ 13-Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs ________ Β7_ V. Description of the invention (11) NAND type connection, etc. to form the memory cell array unit 1 and the stop_. The following refers to the cross-sectional mode ring and terminals of the memory cell in figures 5a, 5b, 6a, and 6b. The application of the pressure of hyena will remember the selective increase and decrease of the threshold voltage of the generous sickle cell, which is to rewrite the action. Figures 5a and 5b show the selective decrease of the memory cell in the segment. Action of threshold voltage • Apply a negative pressure of approximately −10 V on the zigzag line connected to the segment, and apply a voltage of −10 V to the control gates of all memory cells in the segment. _ As shown in the figure, if you want to lower the threshold voltage of the Kang body cell, that is, the selected terminal of the Kang skull cell is selectively applied with a voltage of about 5 V, you can float A voltage difference is generated between the gate electrode and the sink electrode, and the electrons in the floating gate electrode are attracted to the side of the sink electrode by using the phenomenon of Fro Nord. In addition, as shown in Figure 5b, applying Ο V to the sink terminal of the non-selective memory cell can eliminate the potential difference between the floating gate and the sink, preventing electrons from being released from the floating gate. 6a , 6 b_ the action of selectively increasing the sleep limit voltage of the memory cells in the segment. Apply a positive voltage of, for example, about 16 V to the zigzag line connected to the segment and apply a voltage of 16 V to the control gates of all memory cells in the segment. As shown in section 6a_, increase the threshold voltage as desired A voltage of 0 V is selectively applied to the memory cell of the selected memory card, ie the suction terminal of the selected memory card, to generate a voltage difference between the floating gate and the channel. The German tunnel phenomenon attracts «subs in the channel into the floating gate. In addition, as shown in Section 6b, the paper standard of, for example, about 8 V is applied to the non-selective memory «cell sucker terminal, and the Chinese national standard is applied (€ Yang> 6 4 specifications (2 丨 0 father 297 Mm) _14 (please read the note Ϋ on the back before filling in this page)-Pack. Order A7 ____B7 _ 5. Description of the invention (12) Voltage, you can eliminate the potential difference between the floating gate and the channel to prevent electron injection Inside the floating gate · Please read first-back note · Notes and refill the I page to apply a positive voltage to the high voltage applied to the unselected sway line during the action of lowering the sleep limit voltage * "Disturbance (discharge of electrons) caused by pressure" Therefore * During the rewrite operation, the source is opened to prevent the passage of normal current. It can also be used to increase the threshold voltage of the memory cell. The sink voltage, that is, the channel voltage is set to a negative voltage, reduces the voltage of the control gate, that is, the word line voltage. The order is determined from the circle a, 5b, 6a, and 6b. The threshold of the memory hip unit cell in the segment The voltage can be applied to each generous unit cell by setting it The terminal is rewritten selectively by the pressure value. In order to set the voltage applied to the sucking terminal of the memory cell in the segment for each memory hip unit cell, it can be set at each one as described later The flip-flop in the detection latch circuit SL of the bit line has voltage information applied to the sink terminals of each memory «cell. Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. Refer to Figure 17 below. Description of the detection latch circuit SL · Figure 17 is a circuit diagram of the arrangement of the memory cell array i in the open bit line mode of the first four circles, and the connection to the detection latch circuit SL · Page 1 In Fig. 7, only the bit line B u 1 provided in the memory cell array part _ and the bit line B d 1 in the memory cell liner _ in the memory shim contain positive and negative The symbol SL 1 is attached to the detection latch circuit of the device, and the same (equivalent) detection latch circuit is also connected to the other bit lines B u η and B d η. The control signal of the detection latch circuit SL According to the even / odd separation of bit lines ", the reason is to prevent the use of electrical paper between parasitic lines of bit lines. China National Standards (CNS > Α4 specification (210X297mm) _-310432 Μ Β7 Printed by the Central Standard Falcon Bureau Beigong Consumer Cooperative of the Ministry of Economy V. Invention description (13) Capacity has an adverse effect on detection actions When connected to an even bit line (Bu2, Bu4 or Bd2, Bd4), when the generous cell is detecting, set the potential of the odd bit line (Bui, Bu3 or Bd 1, Bd3) to Vs s and Set the capacitance between the parasitic lines to a certain value, and read out the memory skull cell connected to the even bit line side • Memory "Odd-numbered bit line Bun (n = l • 3) in the cell array section JL_ is connected to With the gate signal BD eu as input, the MOS transistor Ml which discharges the potential of the bit line into the ground voltage Vs s, and the MOS transistor M2 which pre-potentials the potential of the cell line with the gate signal RC eu as input, The connection of the MOS transistor M3 with the precharge signal PCeu as the gate input signal * and the connection of the MOS transistors M4 · M3 and M4 with the information of the flip-flop as the gate input signal is not limited to the method shown in Figure 17, It can also be M3 for the power supply voltage Vcc side, and M4 for odd bit line BuN on the bit line Bun side Connect to the wiring Bunf, and the wiring B unf is connected to the MOS transistor M5 with the gate signal TR eu as an input. The wiring B u 1 f on the flip-flop side is connected to discharge the potential of the flip-flop to ground. The gate monk number RSL eu of V ss is the input MO S transistor M6, and the MO S transistor Μ 7 in the flip-flop is generated with the row gate signal Y add of the row address as input, And the MOS transistor M8 with the information in the flip-flop as the gate input signal. The MOS transistor M8 connected to the odd-numbered wiring B unf has the sink connected to the common signal AL eu. The source is connected to the ground voltage V ss to form a multi-segment input NOR circuit connection. That is, the MO S transistor «Μ8 series The standard paper size is based on the Chinese National Falcon (CNS > A4 specification (210 ~ 297mm > _ _ (please read the precautions on the back and then fill out this page) -installation. Industrial and Consumer Cooperatives A7 ____B7 _ V. Description of Invention (14) Whether the information of all flip-flops connected to the odd-numbered wiring B unf will become a grounded electric house vss mo sm crystal skeleton And even bit lines within Bun (n = 2, 4) and odd cell line arrays within the odd-numbered bit lines Bdn (η = 1, 3) and even bit lines Bdn (η = 2 , 4) The circuit with the same structure is also connected. The above describes the structure of the semiconductor non-volatile billion memory device of this embodiment. The following describes the rewriting operation procedure of the electrical limit value of the special emblem of this embodiment with reference to FIGS. 1 and 2 • About the writing operation procedure of this embodiment • It is the same as the above-mentioned conventional writing operation procedure The same. That is, the semiconductor non-volatile memory device receives the instruction to write from the CPU, the address of the memory cell group in the segment to be written, and write data (steps S 1-S 3). Then, Set the writing paste in the flip-flop in the detection latch circuit SL provided for each bit line, and cooperate with the writing data to selectively write the generous hip cells in the segment (step S4). Then * the entire batch of the threshold voltage check (step S 5) * rewrite the data in the flip-flop, so that only the inadequate writing of the generous unit cell successor write operation (step S6) ). Then repeat the writing operation, checking, and data rewriting operation until the threshold of all the writing objects of the generous unit cell reaches a certain threshold voltage (step 7). The following description 2-Circle erasing action program "The semi-conducting non-volatile memory device receives instructions to erase from the CPU, and the generous" address of the unit cell group (steps S11 and S12) in the segment where erasure is performed. Then, in The detection latch paper button set for each bit line Zhongjiapi (CNS) Α4 specifications (2 丨 GX297 male S) _ 17 _ " ~~~ -------- ΙΊinstallation -------- 丨 order ----- Η line (please Read the precautions on the back first and then fill out this page) Yinli A7, Beigong Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs __ 5. Invention Description (15) Set certain data on the flip-flop in the lock circuit SL (step [S 1 3), perform a batch erasing action on the generous body cells in the clip (step S1 4). Then, check the entire threshold limit in the unit of the block (step 15), and rewrite the flip-flop Data (step S16) in order to erase only the incomplete erasure "cell successor." Then, repeat the erasing operation, check, and data rewriting operation * until the sleep limit voltage of all memory cells written to the object reaches a certain limit value of mold pressure *, which is the rewriting operation program of this embodiment because After the verification action and the judging of the limit voltage and the entire batch of determination actions, the data modification action must be carried out, so it is possible to perform high-precision control on each cell of the cell. 1 3 a _ indicates the distribution of the memory cell threshold voltage when the rewrite operation program of this embodiment is executed * As can be seen from the circle 13 (a), execution of the rewrite operation program of this embodiment can make the high threshold The distribution range of the value voltage V t hH is consistent with the distribution of the low threshold V th L. The rewriting operation procedure of this embodiment assumes that the cell has a high threshold voltage and a low threshold voltage , That is, with dual-valued information, but the memory cell has multi-valued information can also be executed in this embodiment of the rewriting action procedure. The following refers to the first 13 (b) circle to illustrate the memory sickle cell with 4-valued information Embodiment • According to the erasing operation of this embodiment, the threshold voltage t h4 (or V th 1) of the memory cell of each bit is controlled so that the threshold voltage distribution becomes neat, and every three Other threshold voltages Vthl (or Vth4), Vth2, Vth3 execute the write operation program of this embodiment, you can make the distribution of the four threshold voltages consistent as shown in circle 1 3b. Applicable to the national standard (CNS) A4 specifications (_2 丨 0X297mm) — (Please read the precautions on the back of Jing Jing first and then fill out this page) -Binder A7 ___ B7 printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs V. Description of the invention (16) After executing the rewriting action program of this embodiment, each limit The non-uniformity of the value voltage to the non-volatile semiconductor memory device is less than 1V. The non-uniformity of the threshold voltage depends on the change of the memory cell's target limit voltage due to a write or erase operation. The value Δν th * and the value of the back bias effect set by the number of billions of unit cells passing through the cell current during the checking operation. In order to further suppress the unequal sentence of the threshold voltage, the most effective method is to reduce the threshold voltage change setting Δν t h when writing or erasing, and improve the resistance value on the source side. Figures 15 and 16 show the data of the flip-flops detected in the latch circuit SL when the operation program for rewriting the threshold voltage of the memory cell is executed in segment units. Figures 15 and 16 show The flipper of the flip-flop defines the limit value electric house of the memory hip unit connected to the flip-flop as the threshold voltage of the high-voltage state, and the electric charge of the flipper of the flip-flop is the ground voltage V ss · The data of the positive and negative device '1 # defines the threshold voltage of the Kang Kang unit cell as the threshold voltage of the low voltage state. The data of the positive and negative device is, for example, the external power supply m voltage V cc, which becomes The voltage of the sink terminal of the internal boost potential V hd, V 1 d. First, refer to the first 15 Η to explain the operation procedure of reducing the sleep limit voltage of the memory cell • If the action of reducing the threshold voltage of the memory skull cell is a write operation *, the input will be connected to the high retention limit The flip-flop in the detection latch circuit of the memory hip unit cell of the help (erased state) is set to '0', and the flip-flop connected to the memory cell unit rewritten to a low aiming voltage is set to The material of '1 # · If the memory paper threshold voltage of the memory cell is reduced, the standard of the paper is applicable to the Chinese National Standard (CNS) Λ4 specification < 210 X 297 ^ #) _ jg _ (please read the precautions on the back of the Jiao before filling this page)-installed · D. -'β A7 ___B7_ printed by the Consumer Labor Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Explanation (17) When the action is an erasing action, set all the flippers of the pros and cons to '1 # • Then, connect to the edge of the suction pole shown in circles 5a and 5b. Phenomenon and set the memory of the flip-flop of '1 # * The cell rewrites the action • That is, the power of the selected word line connected to the clipped segment should be 5 V, so that the connected to the set flip-flop The «pressure of the bit line becomes V ss, and only the electrons in its floating gate are drawn out to the memory cell connected to the flip-flop set to '1'. During the verification, the voltage of the selected Zen word line is set to, for example, 1.5V, and only the bit line connected to the flip-flop set to it is pre-charged voluntarily "• When the threshold value of the rewriting threshold is reached and checked The word line electric hall heard the value of 1. 5V. In the generous unit cell, the * unit cell current passed through and became a path, and the potential of the bit line was put into "· Therefore, the data of the flip-flop was rewritten into the target limit The voltage does not reach 1. 5V. There is no unit cell in the body unit cell. The current passes through and becomes the eye path. The bit line's hyena maintains the voltage during pre-charging and keeps the pros and cons of the reverse device as' 1 #. After the verification, the material of the positive and negative devices is used as the rewriting data. * Repeat the rewriting and verification actions. * When all the data of the positive and negative devices become '0 #, the action of reducing the threshold "pressure" Automatically in the unit cell < * The following describes the operation procedure for raising the threshold voltage of the generous unit cell with reference to circle 16. If the action of raising the limit voltage of the memory cell is a write action, input the positive and negative of the detection latching circuit connected to the memory cell that maintains the low threshold voltage (erased state) It becomes the data that the positive and negative devices connected to the memory unit cell rewritten into a high pressure limit m pressure • If the memory unit cell's limit value is increased, the paper standard is applicable to the country of China揂 准 (CNS) 8 4 specifications (210X297 public daughter) _ 2〇_ -------- 丨 — (please read the precautions on the back and then fill in this page) Order 7 Printed by the industrial and consumer cooperatives A 7 __ B7 V. Description of the invention (18) When erasing, all the materials of the pros and cons are set as * 〇〃 The memory cell of the pros and cons of II # is set to rewrite by La Nord's indolent phenomenon. Also set the voltage of the selected word line connected to the selected segment to 16V, set the voltage of the bit line connected to the flip-flop set to Vs s, and connect to the flip-flop set to '1 · The voltage of the bit line is set to 8 V, and only electrons are injected into the floating gate of the memory cell connected to the flip-flop. During verification, the voltage of the selected word line is set to, for example, 4. Ο V . Pre-charge all the bit lines. Therefore, it is rewritten that the threshold voltage does not reach 40V which is the same as the voltage of the checked word line. The cell current in the body cell is broken by the cell current, and the potential of the bit line is changed. Discharge • Therefore, the data of the flip-flop is maintained * On the other hand, the threshold voltage reaches 4. 0 V. «No cell current flows in the body cell, so it becomes conductive * The potential of the bit line remains precharged The voltage is rewritten into the data of the flip-flop '1 #. Then, the rewritten data of the positive and negative devices after verification is used as the rewrite data, and the rewriting and verification operations are repeated. When all the data of the positive and negative devices become, the action of lowering the threshold voltage is completed, the whole batch of judgment It is carried out automatically in the grain
第18，19圖表示第17圓所示偵測閂鎖電路SL 之時序波形匪。 第1 8，1 9圓中之時序圓係選擇記慷體晶胞陣列部 _y_側之片段之波形_ •實線所示之波形爲記憶髏晶胞陣列 部jlJ®I之信號.，虛線所示之波形爲記慷體晶胞陣列I側之 本紙張尺度適用中國國家標準（€阳）八4規格（2丨0'乂297公釐）_21_ (請先閲後背面之>ΐ·意事項再填寫本頁) •裝· 訂 線 ____ B7 五、發明説明（19 ) 信猇•將構成記億體晶胞陣列_u_，止_之記镰體晶胞之連接 做爲第9_所示AND型之連接記憶體晶胞。 第1 8圖表示在降低記憶II晶胞之睡限值電壓之動作 中之偵測閂鎖鬣路S L之時序波形圈· 然後，在到達t 2之前確定正反器之資料*在t 2至 t 6之間進行降低路限值氰壓之動作，在t 6至t 1 〇之 間核對連接至於第偶數條位元線之記慵體晶胞（以後稱偶 數側），在t1〇至t11之間核對連接於第奇數條位元 線之記憶體晶胞群（以後稱奇數側），在til至t 13 之間判定記憶髏晶胞臨限值電壓之全位元終了· 若降低路限值電壓之動作爲抹消動作時，在t 1至 t2之間選擇非選擇側之RSLed，RSLod而使正 反器之電源電壓VSPe/o，VSNe/o活化而將正 反器之資料設定爲全選揮。若降低睡限值竃壓之動作爲寫 入動作時，在t 1之前將寫入賫訊輪入構成偵測閂鏔電路 SL之正反器中，眺過t 1至t 2之間，成爲從t 2開始 之時序波形* 經濟部中央標率局貝工消费合作社印裂 (請先閲讀背面之注意事項再填寫本頁) 在t2至t3之間選擇PCeu，PCou而將正反 器之資料選揮性的從位元線B 1傅送至Β η。然後，在 t 3至t 5之間選揮TReu，TRou而供給改寫吸極 Μ壓·在選擇TReu，TRou之前選擇PCeu * PCou之理由爲，若選擇TReu *TRou時*因爲 從位元線B u 1至B u η之電容量大於從正反器側Figures 18 and 19 show the timing waveform NM of the detection latch circuit SL shown in circle 17. The timing circle in the 18th, 19th circle is selected to record the waveform of the fragment of the cell array part _y_ side of the generous body. The waveform shown by the solid line is the signal of the jlJ®I of the memory cell array part., The waveform shown by the dotted line is the original paper size on the I side of the cell array. The Chinese national standard (€ yang) 84 specifications (2 丨 0 '297 mm) _21_ (please read the back page first) · Please fill out this page if you want to pay attention.) • Installation · Stranding ____ B7 Fifth, the description of the invention (19) Xin Xun • Make the connection of the memory cell unit of _u_, stop_ the sickle body cell as the first 9_ shows the AND type connected memory cell. Figure 18 shows the timing waveform of the detection latch hysteresis SL during the action of lowering the sleep limit voltage of the memory II cell. Then, before reaching t 2, determine the data of the flip-flop * from t 2 to Perform the action of lowering the cyanogen pressure of the road limit between t 6 and check the unit cell connected to the even-numbered bit line (hereinafter referred to as the even-numbered side) between t 6 and t 1 〇, from t 10 to t 11 Check the memory cell group connected to the odd-numbered bit line (hereinafter referred to as the odd-numbered side), and determine that the full-bit of the memory skull cell threshold voltage is ended between til and t 13 When the operation of the value voltage is the erasing operation, select the non-selected side RSLed and RSLod between t 1 and t2 to activate the power supply voltage VSPe / o and VSNe / o of the flip-flop and set the data of the flip-flop to all Choose to swing. If the action of lowering the sleep limit pressure is a write action, the write information is put into the flip-flop that constitutes the detection latch metal circuit SL before t 1 and overlooks between t 1 and t 2 to become Timing waveform starting from t 2 * Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards and Economics of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page). Select PCeu and PCou between t2 and t3 Selectively sent from bit line B 1 to B η. Then, select TReu and TRou between t 3 and t 5 and supply the rewriting suction pressure. · The reason for choosing PCeu * PCou before choosing TReu and TRou is that if you choose TReu * TRou * because from bit line B The capacitance of u 1 to B u η is greater than that from the positive and negative sides
Bui f至Bun f之電容量，可能破壞正反器之黉料。 本紙張尺度適用中國國家標準（CNS > A4規格（210X297公釐）_ & _ A7 B7 經濟部中央標準局貝工消费合作社印褽 五 、發明说明 (2〇 ) 1 | 將 T R e U ♦ T R 0 U 及 S G 1 a / b 之 m 位 設 定 爲 6 V 1 1 之 理 由 爲 轉 換 降 低 臨 限 值 電壓 之 動 作 時 之 吸 極 端 子 電 應 5 1 1 V ( V S P e 及 V S P 0 )° 若 需 要 昇 高 吸 極 電 壓 時 » 考 1 I 請 1 I 慮 T R e U Τ R 0 U 及 閘極 信 號 S G 1 U / b 之 吸 極 側 先 Μ 1 I 讀 選 擇 閘 極 1 之 Μ 0 S 電 m 晶 體之 臨 限 值 電 壓 而 設 定 丁 R e U 背 1 1 9 T R 0 U 及 S G 1 U / b之 m 極 電 位 〇 之 ί 1 I 將 選 擇 字 袖 電 壓 W U 之電 位 下 降 ( t 3 ) 後 選 擇 事 項 再 1 S G 1 U / b ( t 4 ) 之 理由 爲 字 線 之 延 遲 時 間 大 於 吸 極 填 寫 本 1 裝 側 之 選 擇 閘 極 1 〇 資 際 上 之改 寫 時 間 爲 從 t 4 至 t 5 之 間 頁 1 1 1 將 字 線設定 爲 負 竃 壓 一 10 V 使 位 元 線 電 壓 選 擇性 的 1 1 成 爲 5 V 即 可 在 所 m 之 記慷 K 晶 胞 之 漂 浮 閘 極 上 產 生 電 I 場 而 放 出 電 子 〇 訂 I 在 t 5 t 6 之 期 間 內， 磁 了 將 位 元 線 B U 1 至 1 1 1 B U η 之 错 位 及 副 位 元 線 Sub Bi t Li ne 副 源 極 線 Sub 1 1 I Source L ine之電位放電成爲接地電壓V s s而選揮 1 B D e U / d B D 0 U / d 及 吸 極 側 選 擇 閘 極 1 之 閘 極 線 1 信 號 s G 1 U / b 源 Jfler 極 側選 揮 閘 極 2 之 m 極 信 號 1 1 S G 2 U / b 〇 1 I 在 t 6 至 t 7 之 期 間 內， 摄 了 以 正 反 ran 器 之 賫 料 選 備 择 性 1 I 的 對 位 元 線 進 行 預 充 電 及將 基 準 « 位 供 給 於 非 選 揮 側 記 I 1 憶 體 墊 片 Memory Matd側之位元線而選擇P C ( Ϊ 1 1及 1 1 P C e d 〇 此 時 若 考 慮 Μ 0 S 晶 髖 之 睡 限 值 電 壓 假 1 1 設 預 充 電 電 位 爲 1 • 0 V 時， P C e U 之 m 位 變 成 2 0 1 1 V 而 在 基 準 電 位 0 5 V時 1 R C e d 之 « 位 變 成 1 1 本紙張尺度逋用中國國家標準（CNS ) A4規格（210X 297公釐）„ 23 - 經濟部中央標準扃貝工消費合作社印製 A7 ____B7_ 五、發明説明（21 ) 1 . 5 V。 在到達t 7之前，爲了保持正反器之賫料而將內部竃 源幫壓VSPe/o，VSNe / 〇活化*在到達t 6至 t 1 1之間，選擇字線電位成爲核對電壓1 . 5V。 偶數側核對時之記憶體晶胞之放《時間係從t 7時選 擇源極側選擇閘極2之閘極僧號S G 2 u開始至t 8時之 吸極側選擇閘極1之閘極僧號SG1u成爲非活化爲止之 時間•在此期間內，偶數側之正反器由於R S L e u/d 信號之活化而被復置· 然後，在t8至t9之期圈內選擇TReu/e，再 度將偶數側之正反器之電源電壓VSPe，VSNe活化 ，即可將核對後之記憶髏晶胞之資訊输入偶數側之正反器 中·亦即根據記慷體晶胞之資訊之臨限值電壓低或高，將 位元線之電位保持於放電狀態或預充電《壓•在t 9至 t 1 0之間，將偶數側核對時之位元線B u η — 1之電位 及副位元線Sub Bit Line，及副源極線Sub Source Line 之電位放«成爲接地電壓Vs s » 然後，與偶數側核對時相同的，在t10至t11之 間進行奇數側核對動作•然後，在t11至t13之間判 定記憶體晶胞路限值電壓之全部位元線終了。若全部記憶 體晶胞之臨限值電壓之下降•則正反器之資料之電位成爲 接地out!壓Vs s而判定該Vs s ·將ALe u及 ALou活化（從t 1 1至t 1 2)後’檢測其竈位’若 成爲接地氰壓V s s時•則重回至t 2 ’繼績進行降低臨 本紙張尺度適用中國國家標準（<：奶）八4規格（210><297公*)-24- --------(1 裝------—-ΐτ-----Η線 (請先閲讀背面之>i*意事項再填寫本I) Α7 ____ Β7 五、發明说明（22 ) 限值電壓之動作•若AL e u，AL 〇 u成爲高位準時， 則終止降低臨限值電躔之動作》 (請先閲讀背面之注意事項再填寫本頁) 第1 9圔表示昇高記億體晶胞之臨限值電壓之動作時 之偵測閂鎖《路S L之時序波形圈· 在到達t 2之前確定正反器之資料，在t 2至t 6之 間進行昇高臨限值電壓之動作β在t 6至t 1 2之間核對 偶數側，在t12至t13之間核對奇數側，在t13至 t 1 5之間判定記慷體晶胞臨限值電壓之全部位元終了 * 若昇高睡限值m壓之動作爲抹消動作時，在t 1至 t2之間選擇骸選擇墊片側之RSLed *RSLod而 使正反器之睡限值電壓V S P e / ο，V S N e / 〇活化 ，將正反器之資料設定爲全選擇》若昇高籙限值電壓之動 作爲寫入動作時，在達到t 1之前將寫入賫訊输入構成偵 測放大器SL之正反器中，跳過t 1至t 2之間，成爲從 t 2開始之時序波形· 經濟部中央標準局貝工消费合作社印裝 在t 2至t 3之間，使PCou活化而將正反器之資 料傳送至位元線•然後，在達到t 6之期間內’與降低臨 限值電壓之動作相同的活化信號線，即可執行昇高臨限值 電壓之動作。然而，進行此時之改寫之對象字線之電位係 施加字線電壓Vh之16V之高電壓’正反器之氰源電壓 VS P e/o爲非選揮通通及吸極《壓Vh d之霉壓8V ，又將轉換吸極電壓之MO S電晶體之閘極信號TR e u /d，TRou/d及SGI u/b之鼇位設定爲9V之 重新選擇轉換閘極《壓Vh t » 本紙張尺度適用令躅國家標準（〇奶）六4规格（2丨0';<297公1)-25- 經濟部中央標準局負工消费合作社印製 A7 _B7_ 五、發明説明（23 ) 在t 6至t 7之間，爲了在選擇之全位元線上供應預 充電電位，在非選擇側記憶《蟄片之位元線上供應基準電 位而施加2V之RCeu之電壓，及1· 5V之RCed 之電壓•核對偶數側時之記憶體晶胞之放僱時間係從t 7 之選擇源極側選揮閘極2之閘極信號SG 2 u開始至t 8 之吸極側選擇閘極1之閘極信號SG1u之非活化爲止。 在t8至t9之間選擇PCeu/d，將正反器之資 料傅送至位元線•然後，在t 9至t 10之間進行正反器 之復置動作，在t 1 〇至t 1 1之間選揮TRe u/d， 再度使偶數側之正反器之臨限值電壓VS. Pe，VSNe 活化，即可將核對後之記憶镰晶胞之賫訊輸入偶數側之正 反器中· 然後，與偶數側核對時相同的在t 1 2至t 1 3之期 間內進行奇數側之核對動作*然後，在t13至t15之 間進行判定•若需要昇髙臨限值電壓之記憶體晶胞之臨限 值電應高於核對字線電壓時*正反器之資料之電位變成電 源竃壓VSP e/o之電位而判定該高電位狀態。因此， 將非選擇側之AL e d及AL 〇 d活化而進行檢測•若爲 接地電壓V s s時，則成爲從t 2開始昇高臨限值電壓之 動作，而在高位準時完成動作β 由以上說明及圓式可知，可將本發明目的之對應於半 導髖非揮發性記憶裝置之資訊之記憶體晶胞之臨限值電壓 如第1 3圓所示的與對應於各資訊之路限值電壓成爲一致 。爲了與雙值以上之資訊成爲對應，例如使最低之臨限值 本紙張尺度適用t國國家標準（CNS > Α4規格（2丨0X297公釐）_ 26 _ (請先閱讀背面之>i*意事項再填寫本頁) 訂The capacitance of Bui f to Bun f may damage the material of the flip-flop. This paper scale is applicable to the Chinese National Standard (CNS > A4 specification (210X297mm) _ & _ A7 B7 Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, Invention Instructions (2〇) 1 | TR e U ♦ The reason why the m bit of TR 0 U and SG 1 a / b is set to 6 V 1 1 is that the sink terminal current during the conversion to lower the threshold voltage should be 5 1 1 V (VSP e and VSP 0) ° if necessary When increasing the sink voltage »Test 1 I Please 1 I Consider TR e U Τ R 0 U and the gate side of the gate signal SG 1 U / b Μ 1 I read the MOS of the gate 1 select the crystal The threshold voltage is set to R e U back 1 1 9 TR 0 U and m SG 1 U / b of the m pole potential 〇 ί 1 I will select the word sleeve voltage WU potential drop (t 3) 1 The reason for SG 1 U / b (t 4) is that the delay time of the word line is greater than the filling of the suction electrode. 1 The selection gate of the installation side 1 〇 Rewriting in the field The time is between t 4 and t 5 Page 1 1 1 Set the word line to a negative voltage of 10 V to make the bit line voltage selectivity 1 1 to 5 V. An electric I field is generated on the floating gate and electrons are emitted. During the period of t 5 t 6, the misalignment of the bit lines BU 1 to 1 1 1 BU η and the sub bit line Sub Bi t Line ne The potential discharge of the electrode line Sub 1 1 I Source L ine becomes the ground voltage V ss, and the signal s G 1 U / is selected as 1 BD e U / d BD 0 U / d and the gate line 1 of the selection gate 1 on the suction side b Source Jfler pole side selection swing gate 2 m-pole signal 1 1 SG 2 U / b 〇1 I During the period from t 6 to t 7, the optional material 1 I Precharge the bit line and supply the reference «bit to the bit line on the side of the non-selective side mark I 1 memory mat and select PC (Ϊ 1 1 and 1 1 PC ed 〇 this If you consider the sleep limit voltage of Μ 0 S crystal hip voltage false 1 1 Set the precharge potential to 1 • 0 V, the m bit of PC e U becomes 2 0 1 1 V and 1 RC ed at the reference potential 0 5 V The «position becomes 1 1 The paper standard adopts the Chinese National Standard (CNS) A4 specification (210X 297 mm)„ 23-Printed A7 ____B7_ V. Invention description (21) 1 by the Central Standard of the Ministry of Economic Affairs. 5 V. Before reaching t 7, in order to maintain the flippers of the flip-flop, the internal source is pressed against VSPe / o, and VSNe / O is activated * Between t 6 and t 1 1, the word line potential is selected as the check voltage 1. 5V. The release of the memory cell at the time of the even-numbered check "The time is from t 7 to select the source side to select the gate 2 gate monk number SG 2 u to t 8 from the sink side to select the gate 1 gate The time until the monk number SG1u becomes inactive • During this period, the flip-flop on the even side is reset due to the activation of the RSL eu / d signal. Then, select TReu / e in the period of t8 to t9 and try again Activate the power supply voltages VSPe and VSNe of the flip-flop on the even side to input the information of the checked memory cell into the flip-flop on the even side. That is, according to the threshold of the information on the cell of the generous body When the voltage is low or high, keep the potential of the bit line in a discharged state or precharge "voltage between t 9 and t 1 0, and check the even side of the bit line B u η-1 potential and sub bit The potential of the sub-bit line Sub Bit Line and the sub-source line Sub Source Line «becomes the ground voltage Vs s» Then, the same as the even-numbered side is checked, the odd-numbered side is checked between t10 and t11. Then, at t11 All the bit lines that determine the limit voltage of the memory cell circuit between t13 are terminated. If the threshold voltage of all memory cells drops • the potential of the data of the flip-flop becomes grounded out! Press Vs s to determine the Vs s. • Activate ALe u and ALou (from t 1 1 to t 1 2 ) After the 'detection of its stove position' becomes the grounded cyanide pressure V ss, then return to t 2 'Continue the performance and reduce the size of the paper. The Chinese National Standard (<: Milk) 84 specification (210 > < 297 public *)-24- -------- (1 pack -------- lτ ----- Η line (please read the "i" on the back first and then fill in this I ) Α7 ____ Β7 5. Description of invention (22) Action of limit voltage • If AL eu and AL 〇u become high level, the action of lowering the threshold limit will be terminated "(please read the notes on the back before filling in this Page) Page 19 shows the detection latch during the action of raising the threshold voltage of the body cell. "The timing waveform circle of the road SL." Determine the data of the flip-flop before reaching t 2, at t 2 To increase the threshold voltage between t 6 and β, check the even side between t 6 and t 1 2, check the odd side between t 12 and t 13, and judge the generosity between t 13 and t 1 5 Unit cell threshold voltage If the action of raising the sleep limit m pressure is the erasing action, select RSLed * RSLod on the side of the skeletal choice between t 1 and t2 to make the sleep limit voltage VSP e / ο , VSN e / 〇 activation, set the data of the flip-flop to full selection. "If the action of increasing the voltage of the threshold is the write action, the input of the write signal will form the detection amplifier SL before t 1 is reached. In the flip-flop, skip t 1 to t 2 and become a timing waveform starting from t 2 · The Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs prints between t 2 and t 3 to activate PCou The data of the inverter is transmitted to the bit line. Then, within the period of reaching t 6 'the activation signal line with the same action as lowering the threshold voltage can perform the action of raising the threshold voltage. However, perform this The potential of the word line to be rewritten at the time is a high voltage of 16V applied to the word line voltage Vh. The cyanide source voltage VS P e / o of the flip-flop is an unselected swing pass and the suction electrode "pressure Vh d is 8V, The gate signals TR eu / d, TRou / d and SGI u / b of the MO S transistor that converts the suction voltage are set to 9V's reselection switch gate "Press Vh t» This paper scale is applicable to the national standard (〇 奶) 6 4 specifications (2 丨 0 '; < 297 public 1) -25-Unemployment consumption of the Central Standards Bureau of the Ministry of Economic Affairs Printed by the cooperative A7 _B7_ V. Description of the invention (23) Between t 6 and t 7, in order to supply the precharge potential on the selected full bit line, the non-selected side memorizes "The reference potential is supplied on the bit line of the dormant bit. Apply a voltage of 2V RCeu and a voltage of 1.5V RCed • The firing time of the memory cell when checking the even-numbered side is to select the gate signal SG 2 u of gate 2 from the selection source side of t 7 It starts until the gate signal SG1u of the selection gate 1 on the sink side of t 8 is deactivated. Select PCeu / d between t8 and t9, send the data of the flip-flop to the bit line • Then, perform the reset operation of the flip-flop between t 9 and t 10, and t 1 〇 to t 1 Select TRe u / d between 1 and activate the threshold voltages VS. Pe and VSNe of the flip-flop on the even-numbered side again. Medium • Then, perform the check operation on the odd side during the period from t 1 2 to t 1 3 as same as the check on the even side * Then, determine between t13 and t15 • If you need to remember the memory of the threshold voltage The threshold value of the body cell should be higher than the voltage of the check word line. * The potential of the data of the flip-flop becomes the potential of the power supply voltage VSP e / o to determine the high potential state. Therefore, AL ed and AL 〇d on the non-selected side are activated and detected. In the case of the ground voltage V ss, the threshold voltage is increased from t 2, and the action is completed at the high level. It can be seen from the description and the circle type that the threshold voltage of the memory cell corresponding to the information of the semiconducting hip non-volatile memory device, which is the object of the present invention, can be as shown in circle 13 and the limit corresponding to each information The value voltage becomes consistent. In order to correspond to the information of more than two values, for example, the minimum threshold value of this paper scale is applicable to the national standard of t country (CNS > Α4 specification (2 丨 0X297mm) _ 26 _ (please read the back of > i * If you want to fill out this page again)
T 線 經濟部中央標準局貝工消费合作杜印製 A7 B7 五、發明説明（24 ) 電應成爲抹消狀態，在毎一位元擁制使其醮限值電壓成爲 一致，输入毎一次動作後昇高睡限值《懕之動作之寫入賫 料，在每一位元予以控制而使隳限值m懕成爲一致•亦可 使最高之路限值電壓成爲抹消狀態，在寫入動作時資現低 臨限值電壓· 以上說明本發明之具體實施例·但本發明不受上述實 施例之限制，可在不超過其要旨之範鼷內變更實施》 例如在以上說明中係說明將本發明之半導體非揮發性 記慷裝置應用於快閃記憶臁（EEPROM)之例•但本 發明亦可應用於利用電氣方式改寫之E E P ROM， E P ROM等其他非揮發性記慷晶胞· 本發明之裝置不但以快閃記慷β使用於記憶裝置單位 ，又可做爲《腦系統·數位靜止攝影機系統•汽車系統等 各種系統之記億裝置廣泛的使用•以下參照第2 4鼸說明 將本發明應用於《腦系統之實施例*T-line Ministry of Economic Affairs, Central Standards Bureau, Beigong Consumer Co., Ltd. Du Printed A7 B7 V. Description of the invention (24) The electricity should be in the erasing state, after each one-member system makes its limit voltage consistent, enter each action Raise the sleep limit "Write the material of the action of 懕, control it at each bit to make the limit value of 雕 consistent. • You can also make the highest road limit voltage to be erased. The current low threshold voltage is described above. The above describes specific embodiments of the present invention. However, the present invention is not limited by the above embodiments, and can be changed and implemented within a range not exceeding the gist. For example, in the above description, this Invented example of semiconductor non-volatile memory device applied to flash memory (EEPROM) • However, the invention can also be applied to EEP ROM, EP ROM and other non-volatile memory cells rewritten by electrical methods. The device is not only used as a flash memory generous β in the memory device unit, but also as a "brain system · digital still camera system · car system and other systems to record billions of devices in a wide range of use • The following refer to No. 2 4 Luo said The present invention is applied to "an embodiment of the Brain *
第2 0圈中之電腦系統中包括做爲賫訊機器之中央處 理裝置CPU，設在資訊處理系統內之I/O匯流排，匯 流單元，存取主記憶體或擴充記憶讎等高速記憶體之記憶 體控制單元Memoyr Control Unit，做爲主記慷II之 DRAM，傭存基本控制程式之ROM，及前端連接於鍵 盤之鍵盤控制器K B D C等•顯示轉接器Display Adapter連接於I / 〇匯流排，而該顯示轉接器之前鳙連 接於顯示器。該I/O匯流排連接於並聯埠I/F，滑鼠 等串聯埠I/F，軟碟鼸動器FDD，及蠻換成來自賅I 本紙張尺度適用中國國家樣準（CMS > A4规格（210X29·?公着）_ 27 - 裝 訂 I ^線 (請先聞讀背面之注意事項再填寫本頁) A 7 B? 經濟部中央標準局貝工消費合作社印製 五 、發明説明 (25 ) / 0 匯 流 排 之 Η D D I / F 之 緩 衝 控 制 器 Η D D 緩 衝 器 0 此 外 t 又 連 接 於 來 白 該 記 憶 體 控 制 置 元 Memory Con t r 〇1 Un it之 BBS 匯 流 排 » 而 逋 接 於 擴 充 R A Μ 及 wtt 做 xS& Μ 主 記 憶 髏 之 D R A Μ 0 以 下 說 明 該 電 腦 系 統 之 動 作 0 溢 通 電 源 而 開 始 動 作 後 * 首 先 C Ρ U am 級 由 該 I / 0 匯 流 排 存 取 賅 R 0 Μ 進 行 初 期 診 斷 及 初 期 orb 定 0 然 後 將 系 m 程 式 從 诚 fffi 助 iQ 慷 裝 管 中 裝載 於 做 爲 主 記憶 體 之 D R A Μ 0 C Ρ U 經 由 該 I / 0 匯 流 排 存 取 Η D D 控 制 器 之 Η D D ο 系 統 處 式 之裝 載 完 成 後 根 據使 用 者 之 處 理 要 求 進 行 處 理 P 使 用 者 利 用 骸 I / 0 匯 iejbt 概 排 上 之 鍵 盤 控 制 器 K B D C 或 顯 示 轉 接 器 進 行 處 理 所 需 之 輸 入 及 輸 出 而 同 時 進 行 處 理 0 視 冊 要 可 應 用 連 接 於 並 聯 卑 I / / F 串 聯 埠 I / F 之 输 入 输 出 裝 置 〇 若 主 記 憶 容 1: 不 足 時 在 本 臁 上 之 做 J3S Μ 主 記 憶 II 之 D R A Μ 利 用 擴 充 R A Μ 補 償 主 記 憶 〇 若 使 用 者 希 望 讀 寫 播 Ira 案 時 使 用 者 將 該 Η D D 當 做 補助 記 慷裝 置 而 要 求 存 取 補 助 記 憶 裝 置 〇 由 本 發 明 之 快 閃 記 憶 體構 成 之 快 閃 棺 案 系 統 接 受 其 指 令 而 存 取 檐 案 資 料 〇 如 上 所述 本 發 明 之 快 閃 記 憶 體 等 半 導 體 非 揮 發 性 記 憶 裝 置 可 做 爲 電 腦 系 統 之 快 閃 檐 案 系 統 廣 泛 的 應 用 〇 在 筆 記 型 個 人 電 腦 攜 帶 用 資 訊終 端 等 電 腦 系 統 中 9 使 用 可 插 裝 於 系 統 上 之 個 人 幫 腦 ( Ρ C ) 卡 〇 如 第 2 1 圈 所 示 該 Ρ C 卡 中 包 括 具 有 R 0 Μ 及 R A Μ 之 C P U 連 訂 •線 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 請 閲 讀 背 之 注*" 意 事 項 再一 %裝 本各 頁 28 - 經濟部中央標準局貝工消费合作社印製 A7 _ B7 五、發明説明（26 ) 接於該P C U以便互相授受資料之快閃記慵體陣列（ FLASH-ARRAY)，控制器（Controller)，可 發射資料之控制邏轎電路Control Logic，緩衝器，及介 面《路等· 該P C卡中，可在快閃記憶體，控制邐_電路，緩衡 器，與介面電路之間授受賫料，而P C卡在插入系統本« 上時，可經由介面電路連接於系統匯流排》 例如C P U以8位元之資料形成進行全部管理，執行 介面控制，改寫及讀出動作控制，及運算處理等·快閃記 憶髖陣列係例如由3 2M位元之快閃記憶體裝置陣列所構 成。例如1個片段係由5 1 2信息組之賫料區域及1 6信 息組之公用區域所構成•而8 1 9 2片段成爲1個裝置。 控制器係由晶胞基tt (Cell Base)或分立I C等所 構成，而設有由D RAM或S RAM所構成之片段表格。 控制邏輯電路產生時序侰號，控制價號，而緩衝器係用來 暫時傭存改寫時之資料* 如上所述，快閃記億髖等記憶體裝置又可使用於P C 卡，而該非揮發性半導體記憶裝置可應用於需要利用電氣 方式改II資料之各種系統中· 上述實施例可產生如下之效果。 (1 )在改寫動作（寫入動作及抹消動作）程序中， 在改寫動作後之核對之後改寫賫料，以該資料進行再改寫 動作而抑制記憶«晶胞之臨限值電壓分佈，故可減小寫入 與抹消時之臨限值電壓之差，可大幅度的提高改寫次數· 本紙張尺度適用中國國家標準（CNS ) i\4規格（2丨0X297公釐）_ 29 - (請先閲讀背面之注意事項再填寫本頁) -裝. .νά, 旅 A7 B7 3^〇432 五、發明説明（27 ) (請先閲讀背面之注意事項再填寫本頁) (2 )抑制對應於資訊之各記慷體晶胞之臨限值電壓 分佈，故可降低在具有多值資訊之半導髏非揮發性記憶裝 置之改寫動作時之最大電壓*可提高寄生電晶髋等之耐壓 (3 )尤其在可利用電氣方式改寫之半導臁非揮發性 記憶裝置中，利用佛拉•諾德茵醮道現象進行改寫動作， 故可實現低電壓之單一電源化，又因爲提高改寫次數，故 在使用本發明裝置之電腦系統中*可因低電壓化而減少系 統之消耗功率，可提高可靠性。 圖式： 第1圖爲本發明一實施例之半導體非揮發性記憶裝置 之寫入動作之流程圓ί 第2圚爲本發明一實施例之半導镰非揮發性記慷裝置 之抹消動作之流程圓； 第3園爲習用例之抹消動作之流程麵； 經濟部中央標隼局員工消費合作社印裝 第4圓爲本發明一實施例之半導體非揮發性記億鶄晶 胞之電晶體之斷面圚； 第5a ，5b園爲本發明一實施例之將半導髗非揮發 性記憶髄晶胞之電晶體之臨限值電壓選擇性的降低之動作 時之電壓施加例之斷面圓； 第6 a ，6b圓爲本發明一實施例之將半導體非揮發 性記憶體晶胞之電晶镰之臨限值電壓選擇性的昇降之動作 時之電壓施加例之断面圖： 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X297公釐）_ 3〇 _~~ 經 濟 部 中 央 標 準 員 工 消 費 合 作 社 印 製 A7 B7 五 、發明説明 丨（28 ) 1 I 第 7 園 爲 構 成 1 個 記 憶 體 m m 胞 m r*t* 列 部 之 記 H-l·» H 髗 晶 胞 之 1 1 連 接 例 ( N 0 R ) 之 « 路 圖 * 1 1 第 8 圓 爲 構 成 1 個 記 憶 髖 晶 胞 陣 列 部 之 記 憶 體 晶 胞 之 1 I 請 1 1 連 接 例 ( D I N 0 R ) 之 電 路 圈 先 Μ 1 I 讀 1 第 9 _ 爲 構 成 1 個 記慷 髖 晶 胞 陣 列部 之 記 憶 讎 晶 胞 之 背 1 之 ! 連 接 例 ( A N D ) 之 m 路 圓 注 查 1 忍 事 1 第 1 0 圈 爲 構 成 1 個 記慷 镰 晶 胞 陣 列 部 之 記 憶镰 晶 胞 項 再 之 連 接 例 ( Η I C R ) 之 電 路 圖 填 寫 本 1 裝 第 1 1 圓 两 構 成 1 個 記 憶 髗 晶 胞 陣 列 部 之 記 憶 體 晶 胞 頁 1 1 之 連 接例 ( Ν A N D ) 之 路 圖 1 1 第 1 2 a 1 2 b 圖 利 用 習 用 例 之 改 寫 動 作 時 之 記 | 憶 體 晶 胞 m Ron 限 值 « 壓 分 佈 之 _ 訂 1 第 1 3 a 1 3 b 躕 爲利 用 本 發 明 實 施 例 之改 寫 動 作 1 1 1 時 之 記 憶 體 晶 胞 臨 限 值 電 壓 之 分 佈 圓 1 1 1 第 1 4 圓 爲 本 發 明 __· 實 施例 之 半 導 flft 非 揮 發 性 記 憶裝 1 置 之 功 能 方 塊 圖 線 1 第 1 5 圖 爲 本 發 明 · 實 施例 之 降 低 記 慷 髏 晶 胞 臨 限 值 1 1 電 壓 之 動 作 時 之 偵 測 放 大 器 內 之 正 反 器 之 資 料 之 rwi 圃 1 | 第 1 6 圖 irqf 本 發 明 — 實 施 例 之 昇髙 記 m 體 晶 胞 臨 mQ 限 值 I 電 壓 之 動 作 時 之 偵 測 放 大 器 之 正 反 tua 挪 之 賫 料 之 Η 1 .! 第 1 7 圓 磁 m 本 發 明 —. 實 施 例 之 偵 測 閂 鎖 電 路 之 詳 細 電 1 1 路 圓 * 1 1 第 1 8 圖 爲 本 發 明 一 實 施 例 之 降 低 臨 限 值 電 應 之 動 作 1 1 時 之 動 作 時 序波 形 η 1 1 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 31 - A? _B7 五、發明説明（29 ) 第1 9圖爲本發明一實施例之昇高臨限值電壓之動作 時之動作時序波形圚； 第2 0園爲本發明一實施例之利用半導體非揮發性記 憶裝置之電腦系統之方塊圖； 第2 1圖爲本發明一實施例之利用半導髓非揮發性記 憶裝置之個人電腦卡之方塊圈· (請先閱瘆背％之注意事項再填寫本頁) -裝· 訂 線 經濟部中央標準局貝工消費合作社印製 本紙張尺度逋用中國國家標準（CNS ) A4規格（210X297公f ) __ π -The computer system in the 20th circle includes the CPU as the central processing unit of the Xun machine, the I / O bus, the bus unit, and the high-speed memory such as the main memory or the expanded memory. The memory control unit Memoyr Control Unit is used as the DRAM of the main memory Kang II, the ROM that stores the basic control program, and the keyboard controller KBDC, etc. connected to the front end. The display adapter is connected to the I / O bus Row, and the display adapter was previously connected to the monitor. The I / O bus is connected to the parallel port I / F, mouse and other serial port I / F, floppy disk FDD FDD, and it is replaced by 赅 I. This paper size is applicable to the Chinese national standard (CMS > A4 Specifications (210X29 ·? Public) _ 27-Binding I ^ Line (please read the precautions on the back before filling this page) A 7 B? Printed by the Ministry of Economic Affairs Central Standards Bureau Beigong Consumer Cooperative V. Invention Instructions (25 ) / 0 buffer controller Η DDI / F of the bus Η DD buffer 0 In addition t is connected to the BBS bus of the memory control device Memory Con tr 〇1 Un it »and connected to the expansion RA Μ and wtt do xS & Μ DRAM of the main memory skeleton Μ 0 The following describes the operation of the computer system 0 After the power supply is turned on and the operation is started * First, the CP U am level is performed by the I / 0 bus access R 0 Μ Initial diagnosis and initial orb set to 0, and then load the m program from Cheng fffi and iQ generous tube into DRA Μ 0 C Ρ U as main memory Access the Η DD controller's Η DD from the I / 0 bus ο After the system loading is completed, it will be processed according to the user's processing requirements. P The user uses the keyboard controller KBDC on the skeletal I / 0 bus iejbt Or display adapter to process the required input and output and process at the same time. 0 The booklet can be applied to the input and output device connected to the parallel port I / / F serial port I / F. If the main memory capacity is 1: insufficient The DRA M of J3S M Main Memory II is used to compensate the main memory by using the extended RA M. If the user wants to read and write the Ira case, the user uses the H DD as a subsidy memory device and requests access to the sub memory device. The flash coffin case system composed of the flash memory of the present invention accepts its commands and accesses eaves case data. As described above, the flash memory of the present invention is half The conductor non-volatile memory device can be used as a flash system for computer systems. It is widely used in computer systems such as portable personal computers and information terminals. 9 Use a personal computer that can be plugged into the system (Ρ C) Card 〇 As shown in circle 21, the PC card includes a CPU with R 0 Μ and RA Μ continuous order. The size of the line paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). Please read the back note * " Items of interest will be reloaded on each page 28-Printed by the Central Standards Bureau of the Ministry of Economic Affairs Beigong Consumer Cooperative A7 _ B7 V. Invention description (26) A flash memory array connected to the PCU for mutual exchange of data ( FLASH-ARRAY), the controller (Controller), the control logic that can transmit data Control Logic, buffer, and interface "Road, etc." This PC card can be used in flash memory to control the _ circuit, balancer , And accept the feed between the interface circuit, and the PC card can be connected to the system via the interface circuit when it is inserted into the system book « "Bus" For example, the CPU uses 8-bit data to perform all management, execute interface control, rewrite and read action control, and arithmetic processing, etc. · Flash memory hip array is a flash memory device such as 3 2M bits Array composed. For example, a clip is composed of a 5 1 2 information group's feed area and a 16 information group's common area, and an 8 1 9 2 clip becomes a device. The controller is composed of TT (Cell Base) or discrete IC, etc., and is provided with a fragment table composed of D RAM or S RAM. The control logic circuit generates timing numbers and control price numbers, and the buffer is used to temporarily store the data at the time of rewriting * As mentioned above, flash memory devices such as 100 million hips can also be used for PC cards, and the non-volatile semiconductor The memory device can be applied to various systems that require the use of electrical methods to modify II data. The above-mentioned embodiment can produce the following effects. (1) In the program of rewriting operation (writing operation and erasing operation), after checking the rewriting operation, rewrite the material, and perform rewriting operation with the data to suppress the threshold voltage distribution of the memory «cell, so it is possible Reducing the difference between the threshold voltages during writing and erasing can greatly increase the number of rewrites. This paper standard is applicable to the Chinese National Standard (CNS) i \ 4 specifications (2 丨 0X297mm) _ 29-(please first Read the precautions on the back and then fill out this page)-Installed ... νά, Travel A7 B7 3 ^ 〇432 5. Description of the invention (27) (Please read the precautions on the back before filling out this page) (2) Suppress corresponding to the information The threshold voltage distribution of each cell of the generous body can reduce the maximum voltage during the rewriting operation of the semi-conductive skeleton non-volatile memory device with multi-value information * and can increase the withstand voltage of parasitic electric crystal hips ( 3) Especially in the semi-conducting non-volatile memory device that can be rewritten by electrical method, the rewrite operation is carried out by the Frauen Norden phenomenon, so the single power supply of low voltage can be realized, and because the number of rewrites is increased, Therefore, the electricity of the device of the invention is used * System may be reduced due to a low voltage of the power consumption of the system, reliability can be improved. Figure 1 is the flow chart of the writing operation of the semiconductor non-volatile memory device according to an embodiment of the present invention. The second diagram is the erasing operation of the semi-conductive sickle non-volatile memory device according to an embodiment of the present invention. Process circle; The third garden is the flow surface of the erasing action of the custom case; The fourth round is printed by the Employee Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs. The fourth circle is the transistor of the non-volatile semiconductor memory cell of one embodiment of the present invention. Sectional circles; Sections 5a and 5b are the section circles of the voltage application example during the action of selectively lowering the threshold voltage of the transistors of the semi-conducting non-volatile memory cell according to an embodiment of the present invention. 6a and 6b are cross-sectional diagrams of an example of voltage application during the selective raising and lowering of the threshold voltage of the electric crystal sickle of the semiconductor non-volatile memory cell according to an embodiment of the present invention: This paper size Applicable to China National Standard Falcon (CNS) A4 specification (210X297mm) _ 3〇_ ~~ Printed by the Ministry of Economic Affairs Central Standards Staff Consumer Cooperative A7 B7 V. Description of invention 丨 (28) 1 I The 7th park is composed 1 Memory mm cell mr * t * column record Hl · »H 1 1 connection example (N 0 R)« Roadmap * 1 1 The 8th circle is the part that constitutes a memory hip cell array 1 I of the memory cell Please connect the circuit circle of the 1 1 connection example (DIN 0 R) first Μ 1 I read 1 9th _ is the back of the memory cell that constitutes a generous hip cell array part 1! The connection example (AND) of the m road circle note 1 Ninja 1 The 10th circle is the circuit diagram of the connection example (H ICR) of the memory sickle cell item that constitutes a memory sickle cell array section. Fill in this 1 pack The first 1 1 circle two constitutes a memory cell page of the memory cell array section 1 1 Connection example (Ν AND) Road 1 1 1 2 a 1 2 b Figure when using the rewriting action of the conventional example Mind | memory body crystal Cell m Ron limit «Pressure distribution _ set 1 The first 1 3 a 1 3 b is the memory cell threshold voltage distribution circle when using the rewriting operation 1 1 1 of the embodiment of the present invention 1 1 1 1 4 is the functional block diagram of the semi-conducting flft non-volatile memory device 1 of the embodiment of the invention __ · Line 1 Page 1 5 The picture shows the reduction threshold of the generative unit cell of the invention · the embodiment 1 1 voltage The data of the flip-flop in the detection amplifier at the time of the operation of the rwi garden 1 | No. 1 6 Figure irqf The present invention-the embodiment of the rise of the body m cell unit mQ limit I voltage detection of the operation of the amplifier The positive and negative tua the Η 1 of the moving material.! The 1st 7th round magnetic m of the present invention-. The embodiment of the detailed detection circuit of the latch circuit 1 1 circle * 1 1 The first 18 Figure 1 shows the implementation of the invention Example of the action of lowering the threshold response 1 1 hour Action timing waveform η 1 1 This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 31-A? _B7 5. Description of the invention (29) Figure 19 is the rising threshold of an embodiment of the invention Time sequence waveforms during the operation of the value voltage; Section 20 is a block diagram of a computer system using a semiconductor non-volatile memory device according to an embodiment of the invention; Figure 21 is a diagram using a semiconducting device according to an embodiment of the invention The square circle of the personal computer card of the non-volatile memory device (please read the notes on the back page first and then fill out this page) -installed China National Standard (CNS) A4 specification (210X297 gf) __ π-