4 I 38pi f.doc/0 08 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（丨） 發明領域 本發明是有關於一種積體電路記憶體元件，且特別是 有關於一種用以儲存多位元資料並能於位元線預充電期間 防止位元線被過度預充電的積體電路記憶體元件，本發明 也是有關於一種讀取儲存在積體電路記憶體元件中之儲存 資料的方法。 發明背景 一種記憶胞陣列，例如唯讀記憶體（以下簡稱“ROM”）， 包括有多個排列成多個列與多個行的記憶胞。多條字元線 沿著記憶胞的列方向延伸，而多條位元線沿著記憶胞的行 方向延伸。每一記憶胞的閘極連接至一對應的字元線，源 極接地，而汲極連接至一對應的位元線。爲了自一定址的 (或選到的）記憶胞中讀取資料，連接此定址的記憶胞之位 元線是設定在一預定的電壓，而連接此定址的記憶胞之字 元線是設定在一字元線電壓。 通常，儲存1位元資料的記憶胞具有一電晶體（或一胞 電晶體），此電晶體的臨限電壓是設定在一高或低位準，以 使記憶胞儲存1位元資料。但是，記憶胞一次只能儲存1 位元資料。爲了儲存大量的資料，記憶胞陣列就必須具有 正比於資料儲存量的記憶胞數目，由是導致晶片尺寸無可 避免地變大。 爲了製造一種不增加晶片尺寸而又能儲存大量資料積 體電路記憶體元件，近來提出一種一記憶胞可儲存2位元 資料的記憶體元件，此種記憶胞稱爲“多階記憶體”或“多位 元記憶體”。各種多位元記憶體被提了出來，其中一種是改 (請先閱讀背面之注意事項再填寫本頁) -------参 【衣--- 丁___尸_____ 、一=° 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） A7 A7 4 138pif.doc/0 0 8 經濟部中央標準局員工消費合作社印製 B7 五、發明説明（〉） 變每一記憶胞之電晶體的閘極長度或寬度，使得當記憶胞 被選到時，其電流可以爲不同的値。另一種是改變每一記 憶胞之MOS電晶體中的離子植入劑量，使得MOS電晶體 的臨限電壓可以是不同的値。於是，多位元記憶體元件的 每一記憶胞便能儲存2個或多個位元的資料以表示2個或 多個狀態。因此，多位元記憶體元件增大了儲存容量。 圖1繪示一種一記憶胞只儲存2位元資料之記憶體， 其對應於多位元資料狀態之字元線電壓與臨限電壓間的關 係。以多位元ROM爲例，每一記憶胞具有4種不同臨限 電壓VthO到Vth3中的一種臨限電壓，且臨限電壓VthO-Vth3具有如下的關係：VthO<Vthl<Vth2<Vth3。任何具有 臨限電壓VthO的記憶胞定義爲記憶胞M00,任何具有臨限 電壓Vthl的記憶胞定義爲記憶胞M01，任何具有臨限電壓 Vth2的記憶胞定義爲記憶胞M10，且任何具有臨限電壓 Vth3的記憶胞定義爲記憶胞Mil。假設記憶胞M00、M01、 M10 與 Mil 分別儲存資料“00”、“01”、“10”與“11”。 圖2繪示資料讀取操作期間施加在字元線上的電壓變 化，請參照圖1與2，儲存2位元資料之記憶胞的資料讀 取操作將於下描述。 首先，連接至儲存2位元資料的被選到（或定址）之記憶 胞的字元線，係被驅動至一介於VthO與Vthl間的第一字 元線電壓Vwu)，然後感測電路（180，請參照圖5)會偵測是 否有電流（或胞電流）流經被選到的記憶胞。接著，在高於 第一字元線電壓VWt。的第二字元線電壓Vwu施加在此字 元線後，也會偵測是否有胞電流流經被選到的記憶胞。最 (請先閱讀背面之注意事項再填寫本頁)4 I 38pi f.doc / 0 08 A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the Invention (丨) FIELD OF THE INVENTION The present invention relates to an integrated circuit memory element, and more particularly to an application An integrated circuit memory device for storing multi-bit data and capable of preventing bit lines from being over-precharged during bit line precharging. The present invention also relates to a storage device for reading and storing in an integrated circuit memory device Information method. BACKGROUND OF THE INVENTION A memory cell array, such as a read-only memory (hereinafter referred to as "ROM"), includes a plurality of memory cells arranged in a plurality of columns and a plurality of rows. Multiple word lines extend along the column direction of the memory cell, and multiple bit lines extend along the row direction of the memory cell. The gate of each memory cell is connected to a corresponding word line, the source is grounded, and the drain is connected to a corresponding bit line. In order to read data from a certain (or selected) memory cell, the bit line connected to the addressed memory cell is set at a predetermined voltage, and the word line connected to the addressed memory cell is set at One word line voltage. Generally, a memory cell that stores 1-bit data has a transistor (or a cell transistor). The threshold voltage of the transistor is set at a high or low level so that the memory cell stores 1-bit data. However, memory cells can only store 1-bit data at a time. In order to store a large amount of data, the memory cell array must have a number of memory cells that is proportional to the data storage amount, which causes the chip size to inevitably increase. In order to manufacture a memory device that can store a large amount of data integrated circuits without increasing the size of the chip, a memory cell that can store 2-bit data is recently proposed. This memory cell is called "multilevel memory" or "Multi-bit memory." Various multi-bit memories have been introduced, one of which is to change (please read the precautions on the back before filling out this page) ------- see [yi --- ding _ corpse _____ 、 1 = ° This paper size applies Chinese National Standards (CNS) A4 specifications (210X 297 mm) A7 A7 4 138pif.doc / 0 0 8 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs B7 V. Description of the invention (>) The gate length or width of the transistor of a memory cell, so that when the memory cell is selected, its current can be different. The other is to change the ion implantation dose in the MOS transistor of each memory cell, so that the threshold voltage of the MOS transistor can be different. Thus, each memory cell of a multi-bit memory element can store 2 or more bits of data to represent 2 or more states. Therefore, the multi-bit memory element increases the storage capacity. FIG. 1 illustrates a memory in which a memory cell stores only 2 bits of data, which corresponds to the relationship between the word line voltage and the threshold voltage in a multi-bit data state. Taking a multi-bit ROM as an example, each memory cell has one of four different threshold voltages VthO to Vth3, and the threshold voltages VthO-Vth3 have the following relationship: VthO < Vthl < Vth2 < Vth3. Any memory cell with a threshold voltage VthO is defined as a memory cell M00, any memory cell with a threshold voltage Vthl is defined as a memory cell M01, any memory cell with a threshold voltage Vth2 is defined as a memory cell M10, and any memory cell with a threshold The memory cell of voltage Vth3 is defined as the memory cell Mil. Assume that memory cells M00, M01, M10, and Mil store data "00", "01", "10", and "11", respectively. Figure 2 shows the voltage change applied to the word line during the data read operation. Please refer to Figures 1 and 2. The data read operation of the memory cell that stores the 2-bit data will be described below. First, the word line connected to the selected (or addressed) memory cell storing 2 bits of data is driven to a first word line voltage Vwu between VthO and Vthl), and then the circuit ( 180, please refer to FIG. 5) It will detect whether a current (or cell current) flows through the selected memory cell. Then, the voltage is higher than the first word line voltage VWt. After the second word line voltage Vwu is applied to this word line, it will also detect whether a cell current flows through the selected memory cell. Most (Please read the notes on the back before filling this page)
本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） A7 B7 經濟部中央標準局員工消費合作社印製 [I 3 8pi f. doc/0 08 五、發明説明（z ) 後，將高於第一與第二字元線電壓vWM與vwu的第三字 元線電壓VWi2施加在此字元線上，然後偵測是否有胞電流 流經被選到的記憶胞。如上所述，假設被選到的記憶胞儲 存2位元資料（也就是，“〇〇”、“01”、“10”與“11”其中之一）， 則依次利用不同的字元線電壓VWU)、Vwu與Vg2執行3 種感測操作(或3種讀取操作），可邏輯性地得到感測結果。 利用上述的一組步驟，就可完成資料讀取操作。 圖3是一電路圖，繪示積體電路記憶體元件10中之習 知一種與多位元記憶胞連接的感測結構。圖3的感測結構 係揭露在美國第5,761,132號，名爲“INTEGRATED CIRCUIT MEMORY DEVICES WITH LATCH-FREE PAGE BUFFERS THEREIN FOR PREVENTING READ FAILURES” 的專利中，故相關的描述在此予以省略。圖4是一時序圖， 用以描述習知之資料讀取操作。積體電路記憶體元件10之 資料讀取操作將伴隨圖3與4描述之。 如上所述，資料讀取操作係藉由依序執行3種讀出操 作而完成之，每一讀出操作是根據一組位元線預充電、感 測與放電時間週期執行之。在執行第一讀出操作前，位元 線預充電與放電訊號Pbpre與Pbdis係保持在高位準(也就 是，電源供給電壓Vcc位準），且偏壓Vbiasi是在介於Vcc 與〇V間的預定電壓位準。這使得位元線BL與節點Ns(以 下簡稱“感測節點”)被放電成地電壓。 在第一讀出操作的位元線預充電期間，訊號Pbpre由 高位準變成低位準（也就是，地電位），且偏壓Vbiasi保持 在預定電壓位準’如此使得位元線接通電晶體（pass (請先閱讀背面之注意事項再填寫本頁)This paper size applies to China National Standard (CNS) A4 (210X 297 mm) A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs [I 3 8pi f. Doc / 0 08 V. After the description of the invention (z), A third word line voltage VWi2 that is higher than the first and second word line voltages vWM and vwu is applied to this word line, and then it is detected whether a cell current flows through the selected memory cell. As described above, assuming that the selected memory cell stores 2-bit data (that is, one of "〇〇", "01", "10", and "11"), different word line voltages are sequentially used VWU), Vwu and Vg2 perform 3 kinds of sensing operations (or 3 kinds of reading operations), and the sensing results can be obtained logically. With the above set of steps, the data reading operation can be completed. FIG. 3 is a circuit diagram showing a conventional sensing structure in the integrated circuit memory element 10 connected to a multi-bit memory cell. The sensing structure of FIG. 3 is disclosed in US Patent No. 5,761,132, entitled "INTEGRATED CIRCUIT MEMORY DEVICES WITH LATCH-FREE PAGE BUFFERS THEREIN FOR PREVENTING READ FAILURES", so the related description is omitted here. FIG. 4 is a timing diagram for describing a conventional data reading operation. The data reading operation of the integrated circuit memory element 10 will be described with reference to FIGS. 3 and 4. As described above, the data reading operation is performed by sequentially performing three kinds of reading operations, and each reading operation is performed according to a set of bit line precharge, sensing, and discharging time periods. Before the first read operation is performed, the bit line precharge and discharge signals Pbpre and Pbdis are maintained at a high level (that is, the power supply voltage Vcc level), and the bias voltage Vbiasi is between Vcc and 0V. Predetermined voltage level. This causes the bit line BL and the node Ns (hereinafter referred to as "sensing node") to be discharged to ground voltage. During the bit line pre-charging of the first read operation, the signal Pbpre changes from a high level to a low level (ie, ground potential), and the bias Vbiasi is maintained at a predetermined voltage level, so that the bit line is turned on to the transistor (Pass (Please read the notes on the back before filling this page)
用中國國家標準（CNS ) A4規格（210X297公釐） A7 B7 4138pif.doc/008 五、發明説明（w ) transistor) 12與位元線預充電電晶體14導通，導致來自導 通電晶體I4的電流經由位元線接通電晶體12流至位元線 BL。也就是說，位元線BL被預充電至一需要的電壓（或預 充電電壓）。 在第一讀出操作的位元線感測期間，訊號Pbpre的電 壓位準變成介於高位準與低位準間的暫態，如圖4所示。 來自根據訊號Pbpre而導通之位元線預充電電晶體14的電 流（或感測電流），經由位元線接通電晶體12流至位元線 BL。感測節點Ns的電位係依據記憶胞MC的“ON”/“OFF” 狀態變化，故改變的感測節點Ns之電位（也就是讀出資料) 被PMOS電晶體IS反相，且經由行選擇電路20輸出。 接著，在第一讀出操作的位元線放電期間，訊號Pbpre 與Pbdis變成高位準且偏壓Vbiasi持續保持在先前的電壓 狀態，導致位元線BL與感測節點Ns變成地電位。藉由依 序執行上述的一組步驟，可完成第一讀出操作，因第二與 第三讀出操作的執行方式同第一讀出操作，故其描述予以 省略。 然而，當執行位元線預充電操作時，位元線接通電晶 體12之閘極上的電壓會在位元線預充電操作的起始瞬間 升高超過偏壓Vbiasi，如圖4所示，這是由於位元線接通 電晶體12的閘極是耦接到位元線BL(圖3中之Cb)與感測 節點Ns(圖3中之Cs)之故。因爲偏壓Vbiasi升高超過所需 的電壓，故位元線BL會被預充電而超過所需的電壓。假 使記憶胞MC於某一讀出操作期間是在“ON”狀態，則位元 線BL與感測節點Ns的開展（developed)時間會延長，如圖 本紙張尺度適用中國國家標率（CNS ) A4規格（210x：297公釐） -----------— (請先閱讀背面之注意事項再填寫本頁) 、言 經濟部中央標隼局員工消費合作社印製 A7 B7 4 1 3 8pi l'.doc/008 五、發明説明（6 ) 4所示。結果，積體電路記憶體元件10的感測速度（或資料 讀取速度）變慢，且在最糟的情況下，資料讀取操作會失 效。因此，積體電路記憶體元件10的可靠度變差。 發明綜合說明 因此，本發明的目的之一就是在提供一種於位元線預 充電期間能防止位元線被過度預充電的積體電路記憶體元 件以及其資料讀取方法。 本發明的另一目的是提供一種積體電路記憶體元件， 其能安全地讀取資料，以增強可靠度。 爲達成上述和其他目的，根據其中一特徵，本發明提 出一種積體電路記憶體元件，包括一安排在一字元線與一 位元線的交叉點上之一記憶胞與一響應於一位元線預充 電訊號，用以分別於一資料讀取操作的位元線預充電與感 測區間提供一預定的電流給位元線的位元線預充電電 路。此積體電路記憶體元件更包括一位元線接通電晶體， 其具有一閘極且連接在位元線預充電電路與位元線間，用 以將來自位元線預充電電路的電流轉移至位元線。甚者， 此積體電路記憶體元件包括一偏壓供給電路，用以於資料 讀取操作期間提供一偏壓給位元線接通電晶體的閘極。在 本實施例中，偏壓供給電路於資料讀取操作的一位元線放 電區間使位元線接通電晶體的閘極上之電壓放電而小於 偏壓，使得位元線在位元線預充電區間的起始階段不會升 商超過偏壓。 雖然根據本發明的積體電路記憶體元件是以一儲存多 位元資料的光罩式唯讀記憶體作爲較佳實施例，然吾人應 I--------Q衣丨| (請先閱讀背面之注意事項再填寫本頁)Use Chinese National Standard (CNS) A4 specification (210X297 mm) A7 B7 4138pif.doc / 008 V. Description of the invention (w) transistor 12 Conducts with the bit line pre-charge transistor 14 to cause the current from the conducting crystal I4 The transistor 12 flows to the bit line BL via the bit line. That is, the bit line BL is precharged to a required voltage (or precharge voltage). During the bit line sensing of the first read operation, the voltage level of the signal Pbpre becomes a transient state between the high level and the low level, as shown in FIG. 4. The current (or sensing current) from the bit line precharge transistor 14 that is turned on according to the signal Pbpre, flows through the bit line transistor 12 to the bit line BL. The potential of the sensing node Ns is changed according to the “ON” / “OFF” state of the memory cell MC, so the potential of the changed sensing node Ns (that is, reading data) is inverted by the PMOS transistor IS and selected by the row The circuit 20 outputs. Then, during the bit line discharge of the first read operation, the signals Pbpre and Pbdis become high and the bias voltage Vbiasi is kept at the previous voltage state, which causes the bit line BL and the sensing node Ns to become ground potentials. By performing the above set of steps in sequence, the first read operation can be completed. Since the second and third read operations are performed in the same manner as the first read operation, their descriptions are omitted. However, when the bit line precharge operation is performed, the voltage on the gate of the bit line turning on transistor 12 will rise above the bias voltage Vbiasi at the beginning of the bit line precharge operation, as shown in FIG. 4, This is because the gate of the bit line switching transistor 12 is coupled to the bit line BL (Cb in FIG. 3) and the sensing node Ns (Cs in FIG. 3). Because the bias Vbiasi rises above the required voltage, the bit line BL is precharged to exceed the required voltage. If the memory cell MC is in the "ON" state during a certain read operation, the development time of the bit line BL and the sensing node Ns will be prolonged, as shown in the paper scale of this paper, China National Standards (CNS) A4 specifications (210x: 297 mm) ------------- (Please read the precautions on the back before filling out this page), printed by the Consumers' Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs, A7 B7 4 1 3 8pi l'.doc / 008 V. Description of the invention (6) 4. As a result, the sensing speed (or data reading speed) of the integrated circuit memory element 10 becomes slow, and in the worst case, the data reading operation will fail. Therefore, the reliability of the integrated circuit memory element 10 is deteriorated. SUMMARY OF THE INVENTION Therefore, one of the objects of the present invention is to provide an integrated circuit memory element and a data reading method thereof that can prevent the bit line from being over-precharged during the bit line pre-charging. Another object of the present invention is to provide an integrated circuit memory device that can safely read data to enhance reliability. In order to achieve the above and other objects, according to one of the features, the present invention provides an integrated circuit memory element including a memory cell and a response to a bit arranged at the intersection of a word line and a bit line. The element line precharge signal is used to provide a predetermined current to the bit line precharge circuit of the bit line in a bit line precharge and sensing interval of a data reading operation, respectively. The integrated circuit memory element further includes a bit line connection transistor, which has a gate and is connected between the bit line precharge circuit and the bit line, and is used for transmitting the current from the bit line precharge circuit. Transfer to bit line. Furthermore, the integrated circuit memory device includes a bias supply circuit for providing a bias to the bit line to turn on the gate of the transistor during a data read operation. In this embodiment, the bias supply circuit discharges the voltage across the gate of the transistor during the bit line discharge interval of the data reading operation to be smaller than the bias voltage, so that the bit line is pre-set on the bit line. The initial stage of the charging interval will not increase the quotient beyond the bias. Although the integrated circuit memory element according to the present invention is a photomask type read-only memory that stores multi-bit data as a preferred embodiment, we should I -------- Q clothing 丨 | ( (Please read the notes on the back before filling out this page)
、1T ΦΙ. 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） A7 A7 4 I38pif.doc/0 0 8 經濟部中央標準局員工消費合作社印製 B7 五、發明説明（6 ) 了解本發明的保護範圍不應侷限在光罩式唯讀記憶體。此 種積體電路記憶體元件包括電性可抹除可程式唯讀記憶體 (EEPROM)、快閃EEPROM、EPROM等儲存多位元資料的 記憶體。熟習此藝者應知本發明可應用在儲存單一位元的 記憶體元件中。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式簡單說明 第1圖繪示一種一記憶胞只儲存2位元資料之記憶 體，其對應於多位元資料狀態之字元線電壓與臨限電壓間 的關係； 第2圖繪示資料讀取操作期間施加在字元線上的電壓 變化； 第3圖是一電路圖，繪示積體電路記憶體元件中之習 知一種與多位元記憶胞連接的感測結構； 第4圖是一時序圖，用以描述習知之資料讀取操作； 第5圖是一種根據本發明之積體電路記憶體元件的方 塊圖； 第6圖繪示根據本發明之一較佳實施例的偏壓解碼器 電路之詳細電路圖；以及 第7圖是一時序圖，用以描述根據本發,明之資料讀取 操作。 圖式標號說明 20 ; 200 :行選擇電路 120 :記憶胞陣列 (請先閱讀背面之注意事項再填寫本頁)、 1T ΦΙ. Printed by the Consumers' Cooperative of the Central Bureau of Standards of the Ministry of Economics This paper is printed in accordance with the Chinese National Standard (CNS) A4 (210X297 mm) A7 A7 4 I38pif.doc / 0 0 8 System B7 V. Description of the invention (6) It should be understood that the scope of protection of the present invention should not be limited to photomask-type read-only memory. Such integrated circuit memory components include electrically erasable programmable read-only memory (EEPROM), flash EEPROM, EPROM, and other memories that store multi-bit data. Those skilled in the art will recognize that the present invention can be applied to a single-bit memory device. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are described below in conjunction with the accompanying drawings, and are described in detail as follows: Figure 1 Brief Description A memory cell only stores 2-bit data, which corresponds to the relationship between the word line voltage and the threshold voltage of the multi-bit data state. Figure 2 shows the data applied to the word line during the data reading operation. Voltage change; Figure 3 is a circuit diagram showing a conventional sensing structure connected to a multi-bit memory cell in an integrated circuit memory element; Figure 4 is a timing diagram for describing the reading of conventional data 5 is a block diagram of an integrated circuit memory element according to the present invention; FIG. 6 is a detailed circuit diagram of a bias decoder circuit according to a preferred embodiment of the present invention; and FIG. 7 It is a timing chart for describing the data reading operation according to the present invention. Description of figure numbering 20; 200: row selection circuit 120: memory cell array (please read the precautions on the back before filling this page)
本纸張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） A7 B7 220 :參考電壓產生器 26〇 :偏壓解碼器 4 138pif.doc/008 五、發明説明（ο ) 140 :字元線電壓產生電路160 : 180 :感測電路 240 :偏壓產生器 .300 :偏壓供給電路 較佳眚施例說里· ' 根據本發明之較佳實施例將伴隨所附圖式描述於後。 吾人必須了解偏壓供給電路3 0 〇只在執行每一讀出操 作中之位元線預充電與感測區間時，提供一偏壓Vbias予 感測電路18〇中之每一位元線接通電晶體ι81的閘極。也 就是說，偏壓供給電路300於位元線放電期間並不提供偏 壓給聞極，以防止閘極電壓於其後的讀出操作之位元線預 充電期間的初始時升高超過偏壓Vbias。這會使每一位元線 於位元線預充電期間不被過度預充電，而確保積體電路記 憶體元件中的資料讀取操作。 圖5是一方塊圖’繪示根據本發明之一種積體電路記 憶體元件1〇〇。This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) A7 B7 220: Reference voltage generator 26〇: Bias decoder 4 138pif.doc / 008 V. Description of invention (ο) 140: Word Element line voltage generating circuit 160: 180: Sensing circuit 240: Bias generator. 300: Bias supply circuit is better. In the example, the preferred embodiment of the present invention will be described with the accompanying drawings Rear. We must understand that the bias supply circuit 300 only provides a bias Vbias to each bit line in the sensing circuit 18 when the bit line pre-charging and sensing interval is performed in each read operation. Gate of transistor ι81. That is, the bias supply circuit 300 does not provide a bias voltage to the sense electrode during the bit line discharge, so as to prevent the gate voltage from rising above the bias voltage during the initial charge period of the bit line precharge during subsequent read operations. Press Vbias. This will prevent each bit line from being pre-charged excessively during the bit line pre-charging, and ensure the data read operation in the integrated circuit memory element. Fig. 5 is a block diagram 'showing an integrated circuit memory element 100 according to the present invention.
在積體電路記憶體元件100中，包括有記憶胞陣列 120，記憶胞陣列120雖未於圖式中繪示，但其具有多個字 元線、多個位元線以及多個與字元線和位元線交叉排列的 記憶胞。記憶胞均儲存多位元資料，且分別具有對應於多 位元資料之可能狀態的多個臨限電壓中之一臨限電壓。字 元線電壓產生電路140於資料讀取操作期間，產生一不同 位準的字元線電壓Vwu(i=0，l,2)。電路140的一種例示揭 露在第5,457,650號美國專利中（名爲“APPARATUS AND METHOD FOR READING MULTI-BIT DATA STORED IN A 本紙張尺度適用中國國家標準（CNS ) Μ規格（210Χ29·?公釐） (請先閲讀背面之注意事項再成寫本頁) 、-=β 經濟部中央標隼局員工消費合作社印製 4l38pif.doc/008 A7 B7 五、發明説明（8) SEMICONDUCTOR MEMORY”），故其詳細描述在此予以省 略。 列選擇電路160選擇至少一字元線，且提供字元線電 壓Vwu予被選到的字元線。電路160會迫使未選到的字元 線接地（也就是〇伏）。儲存在被選到之字元線與位元線中 的資料會被感測電路180感測，且感測到的資料經由根據 一輸入/輸出結構之行選擇電路200輸出。 如圖5所示，偏壓供給電路300提供一偏壓 Vbiasi(i=0，l，2,3)，例如約2.3V給感測電路180。偏壓供給 電路300係由一參考電壓產生器220、一偏壓產生器240 與一偏壓解碼器260組成，參考電壓產生器220響應於表 示元件操作與待機狀態的訊號STB，當訊號STB變成代表 激化狀態（activated state)的低位準時’產生一參考電壓 Vref。且，當參考電壓是在所需的電壓位準時，偏壓產生 器240被致能，而產生一約2.3V的偏壓Vbias。 經濟部中央標準局員工消費合作社印製 偏壓解碼器260接收來自偏壓產生器240的偏壓 Vbias，且響應於表示位元線放電區間之位元線放電訊號 Pbdis的互補訊號Pbdis，輸出一選自偏壓Vbiasi(i=0，l,2,3) 的偏壓。也就是說，當互補訊號Pbdis_是在低位準時（當執 行位元線放電操作時），偏壓解碼器260不輸出偏壓。當互 補訊號是在高位準時（當執行位元線預充電與感測操 作時），選到的偏壓Vbiasi被輸出至感測電路180。 在本實施例中，記憶胞陣列120中的位元線是5 1 2條。 512條位元線分割成16個區段（segment) ’每一區段包含4 個單元。也就是說，一單元有8條位元線。這樣的位元線 本紙張尺度適用_中國國家標準（CNS ) Λ4規格（210X 297公釐） A7 B7 4l38pif.doc/008 五、發明説明（1 ) 結構是爲了解決當偏壓同時加在感測電路1 8 〇中以及對應 於512條位元線之位元線接通電晶體（將於下描述）時所感 應的電源問題。根據此種位元線結構，來自偏壓解碼器26〇 的偏壓會施加在對應於某一單元之位元線接通電晶體上， 而不會施加在對應於其他單元之位元線接通電晶體上。在 此情形下，滿足上述需求的本發明之偏壓解碼器260係倂 同一記憶胞與對應於該記憶胞之感測電路180例示在圖6 中。圖6中，感測電路1 8 0中的組成元件係與圖3之習知 技藝者同，故描述部分予以省略。 請參照圖6，偏壓解碼器260係由一非及閘26 1、3個 反相器262 ; 263與264、一 PMOS電晶體265、以及2個 NMOS電晶體266與267組成。非及閘261與反相器262 和263係作爲邏輯電路，而反相器264、PMOS電晶體265 和NMOS電晶體266則係作爲轉移電路以輸出對應於某一 單元的偏壓VbiasO。當互補訊號Pbdis是在高位準時（當執 行位元線預充電與感測操作時），邏輯電路根據選擇訊號 Αχ與Αχ輸出訊號C。當對應於選到的單兀之選擇訊號Αχ 與ϋ致能時，訊號C於位元線預充電與感測區間變成低 位準。這會使來自偏壓產生器24〇的偏壓Vbias，經由轉移 電路（264,265與266)轉移至感測電路180中之位元線接通 電晶體181的閘極。對應於其他單元的組成元件雖然未繪 不於圖6中，但熟習此藝者應知，其係與例示在圖6中者 同。 反之，當互補訊號是在低位準時（當執行位元線 放電操作時），即使選擇訊號Αχ與被致能’訊號C會 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ：297公釐） __________衣__ (請先閲讀背面之注意事項再填寫本頁)The integrated circuit memory element 100 includes a memory cell array 120. Although the memory cell array 120 is not shown in the figure, it has multiple word lines, multiple bit lines, and multiple AND characters. Lines and bit lines cross memory cells. The memory cells each store multi-bit data, and each of them has one of a plurality of threshold voltages corresponding to a possible state of the multi-bit data. The word line voltage generating circuit 140 generates a word line voltage Vwu (i = 0, 1, 2) of a different level during a data reading operation. An example of circuit 140 is disclosed in U.S. Patent No. 5,457,650 (named "APPARATUS AND METHOD FOR READING MULTI-BIT DATA STORED IN A. This paper size applies to the Chinese National Standard (CNS) M specification (210 × 29 ·? Mm) (Please Read the notes on the back before writing this page),-= β Printed by the Consumers' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 4l38pif.doc / 008 A7 B7 V. Invention Description (8) SEMICONDUCTOR MEMORY "), so its detailed description It is omitted here. The column selection circuit 160 selects at least one word line, and provides a word line voltage Vwu to the selected word line. Circuit 160 forces unselected word lines to ground (i.e. 0 volts). The data stored in the selected zigzag line and bit line is sensed by the sensing circuit 180, and the sensed data is output via the line selection circuit 200 according to an input / output structure. As shown in FIG. 5, the bias supply circuit 300 provides a bias voltage Vbiasi (i = 0, 1, 2, 3), for example, about 2.3V to the sensing circuit 180. The bias supply circuit 300 is composed of a reference voltage generator 220, a bias generator 240, and a bias decoder 260. The reference voltage generator 220 responds to the signal STB indicating the operation and standby status of the component. When the signal STB becomes The low-level on-time 'representing the activated state' generates a reference voltage Vref. In addition, when the reference voltage is at a desired voltage level, the bias generator 240 is enabled to generate a bias voltage Vbias of about 2.3V. The printed bias decoder 260 of the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs receives the bias Vbias from the bias generator 240, and responds to the complementary signal Pbdis of the bit line discharge signal Pbdis indicating the bit line discharge interval, and outputs a The bias is selected from the bias Vbiasi (i = 0,1,2,3). That is, when the complementary signal Pbdis_ is at a low level (when a bit line discharge operation is performed), the bias decoder 260 does not output a bias. When the complementary signal is at a high level (when the bit line pre-charging and sensing operation is performed), the selected bias voltage Vbiasi is output to the sensing circuit 180. In this embodiment, the number of bit lines in the memory cell array 120 is 5 1 2. 512 bit lines are divided into 16 segments. Each segment contains 4 cells. That is, a cell has 8 bit lines. This bit line paper size is applicable _ Chinese National Standard (CNS) Λ4 specification (210X 297 mm) A7 B7 4l38pif.doc / 008 V. Description of the invention (1) The structure is to solve the problem when the bias voltage is simultaneously added to the sensing Power problems induced in circuit 180 and when bit lines corresponding to 512 bit lines are turned on transistors (described below). According to this bit line structure, the bias voltage from the bias decoder 26 will be applied to the bit line switch transistor corresponding to a certain cell, but not to the bit line switch corresponding to other cells. Power on the crystal. In this case, the bias decoder 260 of the present invention that satisfies the above requirements is the same memory cell and a sensing circuit 180 corresponding to the memory cell are illustrated in FIG. 6. In FIG. 6, the constituent elements in the sensing circuit 180 are the same as those in the art of FIG. 3, so the descriptions are omitted. Referring to FIG. 6, the bias decoder 260 is composed of a NAND gate 26, three inverters 262; 263 and 264, a PMOS transistor 265, and two NMOS transistors 266 and 267. The NOT gate 261 and the inverters 262 and 263 are used as logic circuits, and the inverter 264, the PMOS transistor 265, and the NMOS transistor 266 are used as transfer circuits to output the bias voltage VbiasO corresponding to a certain cell. When the complementary signal Pbdis is at a high level (when the bit line precharge and sensing operations are performed), the logic circuit outputs a signal C according to the selected signals Αχ and Αχ. When the selection signals Αχ and ϋ corresponding to the selected unit are enabled, the signal C becomes low in the bit line precharge and sensing interval. This causes the bias voltage Vbias from the bias generator 240 to be transferred to the bit line in the sensing circuit 180 via the transfer circuits (264, 265, and 266) to turn on the gate of the transistor 181. Although the constituent elements corresponding to other units are not shown in FIG. 6, those skilled in the art should know that they are the same as those exemplified in FIG. 6. Conversely, when the complementary signal is at a low level (when performing the bit line discharge operation), even if the signal Αχ and the enabled signal are selected, the Chinese paper standard (CNS) Α4 specification (210X: 297 mm) is applied to this paper. ） __________ 衣 __ (Please read the notes on the back before filling this page)
、1T 經濟部中央標準局員工消費合作社印製 4 I 38pif.doc/008 A7 B7 五、發明説明（e) 變成高位準。這會使來自偏壓產生器240的偏壓Vbias，不 會經由轉移電路（264,265與266)轉移至位元線接通電晶體 181的閘極。結果，感測電路180中之位元線接通電晶體 181的閘極經由偏壓解碼器260中之NMOS電晶體267(做 爲放電電晶體）接地。 圖7是時序圖，用以描述根據本發明之資料讀取操 作。積體電路記憶體元件100之資料讀取操作將伴隨所附 圖式於下描述。 如前所述，藉由執行3種讀出操作可完成2位元資料 的讀取，其中每一種讀出操作包含一組位元線預充電區 間、位元線感測區間與位元線放電區間。 首先，當訊號STB由高位準變成低位準時，參考電壓 產生器220產生一參考電壓Vref。然後偏壓產生器240利 用參考電壓Vref產生偏壓Vbias，例如約2.3V。於是，偏 壓Vbias被提供給偏壓解碼器260。然而，如圖7所示，在 第一讀出操作前，位元線放電與預充電訊號Pbdis與Pbpre 仍保持在高位準，使得無偏壓Vbias自偏壓產生器240轉 移至位元線接通電晶體181的閘極。這是因爲低位準的互 補訊號Pbdis是在低位準，故不管選擇訊號Αχ與ϋ的狀 態如何，PMOS與NMOS電晶體265與266組成的轉移電 路是關閉的。此時，位元線接通電晶體181的閘電位將經 由放電電晶體267保持在地電壓（〇V) ’且聯結被選到之記 憶胞MC的位元線BL經由感測電路1 8〇中之位元線放電 電晶體183放電成低位準。 然後，開始執行真正的讀出操作。在第一讀出操作的 (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐） A7 B7 4 1 38pif.doc/008 五、發明説明（；（） 位元線預充電區間，位元線預充電訊號Pbpre自高位準變 成低位準，使得位元線預充電電晶體182導通，且感測節 點Ns開始經由導通的電晶體182充電。同時，因爲位元線 放電訊號Pbdis變成低位準（也就是說互補訊號Pbdis變成 高位準），位元線接通電晶體181的閘電位自低位準上拉至 約2.3V的偏壓VbiasO，如圖7所示（意指位元線接通電晶 體181導通）。因此，聯結被選到之記憶胞MC的位元線 BL經由導通的位元線接通電晶體181預充電。 在本實施例中，位元線預充電區間的初始階段因爲偏 壓Vbias是設定在低位準，故位元線接通電晶體181的閘 電位不會升高超過偏壓VbiasO。換句話說，雖然閘電位因 閘極與位元線BL間以及閘極與感測節點間的耦合之故而 升高，但閘電位不會高過偏壓Vbias位準。 在第一讀出操作的位元線感測區間，位元線預充電訊 號Pbpre位準自低位準變成介於高位準與低位準間的位 準，如圖7所示。來自位元線預充電電晶體182的電流（或 感測電流）因訊號Pbpre之故經由位元線接通電晶體181流 向位元線BL。感測節點Ns的電位因記憶胞MC的 “ON”/“OFF”狀態之故而改變，於是改變的感測節點Ns之 電位(也就是讀出資料）被PMOS電晶體184反相，然後經 由行選擇電路2〇〇輸出。 最後，在第一讀出操作的位元線放電區間，位元線預 充電與放電訊號Pbpre與Pbdis均變成高位準，使得偏壓 VbiasO以如前所述的同樣方式變成低位準，且位元線BL 放電至低位準以供接下來的第二讀出操作之用。第一讀出 (請先閲讀背面之注意事項再填窝本頁) ’ —1 - - *.1 ^^^1 n I—..... - I - - • n T 、-° 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨〇><297公釐） A7 A7 4 1 3 8 p i 1'. d o c / Ο Ο 8 B7 五、發明説明（|> ) 操作已經藉由依序執行如上所述的一組步驟而完成，第二 與第三讀出操作的執行與第一讀出操作同，故不再贅述。 根據本發明，感測電路180中之位元線接通電晶體181 的閘極於每一讀出操作的位元線放電區間均是放電至小於 偏壓Vbias的電壓，也就是地電壓。這使得即使閘極與位 元線BL耦合（Cb，參照圖3)以及與感測節點耦合（Cs,參照圖 3)，在每一讀出操作的起始階段，閘電位也不會高過偏壓 Vbias。因此，可以防止當位元線接通電晶體181的閘電位 升高超過偏壓Vbias時感應的位元線過度預充電之現象。 結果，可以避免積體電路記憶體元件1〇〇之感測速度（或資 料讀取速度）降低，且增進了積體電路記憶體元件之可靠 度。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閲讀背面之注意事項再填寫本頁) 丁___Γ 、τ 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ 297公釐）, 1T Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 4 I 38pif.doc / 008 A7 B7 V. Description of Invention (e) Become high. This will prevent the bias voltage Vbias from the bias generator 240 from being transferred to the gate of the bit line transistor 181 via the transfer circuits (264, 265, and 266). As a result, the gate of the bit line switching transistor 181 in the sensing circuit 180 is grounded via the NMOS transistor 267 (as a discharge transistor) in the bias decoder 260. Fig. 7 is a timing chart for describing a data reading operation according to the present invention. The data reading operation of the integrated circuit memory device 100 will be described below with the accompanying drawings. As mentioned before, reading of 2-bit data can be accomplished by performing three types of readout operations, each of which includes a set of bitline precharge intervals, bitline sensing interval, and bitline discharge Interval. First, when the signal STB changes from a high level to a low level, the reference voltage generator 220 generates a reference voltage Vref. The bias generator 240 then uses the reference voltage Vref to generate a bias Vbias, such as about 2.3V. Then, the bias voltage Vbias is supplied to the bias decoder 260. However, as shown in FIG. 7, before the first read operation, the bit line discharge and precharge signals Pbdis and Pbpre remain at a high level, so that the unbiased Vbias self-bias generator 240 is transferred to the bit line connection. The gate of the crystal 181 is energized. This is because the low-level complementary signal Pbdis is at a low level, so the transfer circuit composed of PMOS and NMOS transistors 265 and 266 is closed regardless of the state of the selected signals Αχ and ϋ. At this time, the gate potential of the bit line turn-on transistor 181 will be maintained at the ground voltage (0V) 'via the discharge transistor 267 and the bit line BL connecting the selected memory cell MC will pass through the sensing circuit 1 8. The middle bit line discharge transistor 183 is discharged to a low level. Then, the actual read operation starts. In the first reading operation (please read the precautions on the back before filling out this page) Order printed by the Central Consumers Bureau of the Ministry of Economic Affairs, printed by the Consumer Cooperatives. The paper size is applicable to the Chinese National Standard (CNS) Α4 size (210X 297 mm) A7 B7 4 1 38pif.doc / 008 V. Description of the invention (; () Bit line precharge interval, the bit line precharge signal Pbpre changes from a high level to a low level, so that the bit line precharge transistor 182 is turned on and senses The test node Ns starts to be charged through the transistor 182 that is turned on. At the same time, because the bit line discharge signal Pbdis becomes low (that is, the complementary signal Pbdis becomes high), the bit line turns on the transistor 181's gate potential from the low level. Pull up to a bias voltage VbiasO of about 2.3V, as shown in FIG. 7 (meaning that the bit line is turned on by transistor 181). Therefore, the bit line BL of the selected memory cell MC is connected via the turned-on bit The line-on transistor 181 is pre-charged. In this embodiment, because the bias voltage Vbias is set to a low level in the initial stage of the bit-line pre-charge interval, the gate potential of the bit-line-on transistor 181 does not increase Exceeded bias VbiasO In other words, although the gate potential increases due to the coupling between the gate and the bit line BL and between the gate and the sensing node, the gate potential does not exceed the bias Vbias level. During the first read operation In the bit line sensing interval, the bit line precharge signal Pbpre level changes from a low level to a level between a high level and a low level, as shown in Figure 7. Current from the bit line precharge transistor 182 (Or sensing current) The signal Pbpre is connected to the transistor 181 and flows to the bit line BL via the bit line. The potential of the sensing node Ns is changed by the “ON” / “OFF” state of the memory cell MC, so The potential of the changed sensing node Ns (that is, read data) is inverted by the PMOS transistor 184, and then output through the row selection circuit 2000. Finally, during the bit line discharge interval of the first read operation, the bit The line precharge and discharge signals Pbpre and Pbdis both become high, so that the bias VbiasO becomes low in the same way as described above, and the bit line BL is discharged to a low level for the next second read operation. Use. First read (Please read the notes on the back first Refill this page) '—1--* .1 ^^^ 1 n I —.....-I--• n T,-° Printed on paper scales applicable to employees' cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs China National Standard (CNS) A4 specification (2 丨 〇 < 297 mm) A7 A7 4 1 3 8 pi 1 '. Doc / Ο Ο 8 B7 V. Description of the invention (| >) The operation has been carried out in order It is completed by performing a set of steps as described above, and the execution of the second and third readout operations is the same as the first readout operation, and therefore will not be described again. According to the present invention, the bit line discharge transistor 181 in the sensing circuit 180 discharges the bit line in each readout operation in a discharge interval to a voltage less than the bias voltage Vbias, that is, the ground voltage. This makes the gate potential not higher than the gate potential at the beginning of each readout operation even if the gate is coupled to the bit line BL (Cb, see FIG. 3) and to the sensing node (Cs, see FIG. 3). Bias Vbias. Therefore, it is possible to prevent the phenomenon that the bit line is induced to be precharged excessively when the gate potential of the bit line turn-on transistor 181 rises above the bias voltage Vbias. As a result, the decrease in the sensing speed (or data reading speed) of the integrated circuit memory device 100 can be avoided, and the reliability of the integrated circuit memory device can be improved. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the notes on the back before filling in this page) Ding ___ Γ, τ Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs This paper size is applicable to the Chinese National Standard (CNS) Α4 specification (210 × 297 mm)