JP2003187588A - Nonvolatile semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress a control circuit area except a memory cell from being increased in an EEPROM which can store multi-level data. <P>SOLUTION: A nonvolatile semiconductor memory is an EEPROM provided with a memory cell having electric charges accumulating section which can store ternary data and a data circuit storing temporarily write data, the data circuit is constituted of three NOR logic circuits having two input terminals. Also, the device has a sense circuit reading out data stored in the memory cell, the sense circuit is constituted of switch circuits of (n-1) pieces turned on and off in accordance with a value of read-out data. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable non-volatile semiconductor memory device (EEPROM), and more particularly to an EEPROM which performs multi-valued storage for storing information of more than 1 bit in one memory cell.

[0002]

2. Description of the Related Art As one of EEPROM memory cells, one having a MOSFET structure in which a charge storage layer and a control gate are laminated on a semiconductor substrate is known.
Usually, data "0" or "1" is stored according to the amount of charge stored in the charge storage layer, and 1-bit data is stored in one cell. In contrast, higher density EEPR
In order to realize the OM, a multi-value storage system in which data for multiple bits is stored in one cell is also known. Eg 4
In the value storage system, data “0”, “1”, “2”,
In order to store "3" in one cell, four charge amounts corresponding to the data are stored in the charge storage layer.

An example of a data storage state will be described by taking a four-value system as an example. A state in which the charge amount of the charge storage layer is 0 is a neutral state, and a state in which more positive charges are stored than the neutral state is an erased state. Also, the erased state is made to correspond to the data “0”. For example, a high voltage (~ 20V) is applied to the substrate and the control gate is set to 0V to perform erasing. The state in which a negative charge is stored compared to the neutral state is defined as the state of data “1”. The state of data "2" is also a state in which more negative charges are stored than the neutral state, but the amount of negative charges is made larger than the amount of negative charges in the state of data "1". In the state of data “3”, the negative charge amount is further increased. For example, the substrate, the source, and the drain are set to 0 V, and the control gate is set to a high voltage (up to 20 V), so that negative charges are stored in the charge storage layer.

Generally, the data holding of the EEPROM is 1
Guaranteed for 0 years. The electric charge stored in the electric charge storage layer leaks although it is very small. In order to prevent the data “0”, “1”, “2”, and “3” from being indistinguishable due to this leak, the charge amount corresponding to each data is normally set discretely. Further, the difference in the charge amount is called a charge amount margin.

However, if the charge amount margin is too small, it cannot be guaranteed for 10 years. On the other hand, as the charge amount margin is increased, the charge amount corresponding to, for example, the data “3” must be increased. Therefore, the writing time becomes long and the writing voltage becomes high. Further, since the leak charge amount increases as the stored charge amount increases, there is a problem that the data guarantee time does not increase as the charge amount margin increases.

Further, as one of the EEPROMs, one in which data for a plurality of bytes is written at once is known. This is to shorten the writing time, and is provided with a data circuit for temporarily storing a plurality of bytes of data. In case of multi-value storage with such an EEPROM, the data circuit must also be capable of multi-value storage. Therefore, there is a problem that the circuit area of the data circuit becomes large.

[0007]

As described above, the multi-value storage method is an effective means for increasing the density, but it has a problem that the reliability of data guarantee is lowered. Further, there is a problem that a control circuit such as a data circuit other than the memory cell becomes large.

The present invention has been made in consideration of the above circumstances, and an object thereof is a multi-value storage system EE capable of suppressing an increase in the area of a control circuit other than a memory cell.
It is to provide a PROM.

[0009]

(Structure) In order to solve the above problems, the present invention adopts the following structure.

That is, according to the present invention (Claim 1), multi-valued (n
(≧ 3) value) A non-volatile semiconductor memory device capable of storing data, comprising a memory cell having a charge storage section and a data circuit for temporarily storing write data, wherein the data circuit has n−1 input terminals. It is characterized by being constituted by n logic circuits having Further, in the n logic circuits having the n-1 input terminals, each output terminal is connected to one of the n-1 input terminals of the other n-1 logic circuits. It is characterized in that they are connected to each other to form a data circuit.

The present invention (Claim 2) provides a multi-valued (n
(≧ 3) value In a non-volatile semiconductor memory device capable of storing data, a memory cell having a charge storage portion, a sense circuit for reading data stored in the memory cell, and a data read by the sense circuit are A data circuit for temporarily storing is provided, the sense circuit is composed of n-1 switch circuits that are turned on / off according to the value of read data, and the data circuit has n-1 input terminals. It is characterized by being composed of individual logic circuits. Further, the n-1 switch circuits form a sense circuit by serially connecting a first MOS transistor to which a different sense signal is input and a second MOS transistor to which the read data is input, The n logic circuits having the n-1 input terminals have their output terminals mutually connected to one input terminal of the n-1 input terminals of the other n-1 logic circuits. It is characterized in that they are connected to form a data circuit.

The present invention (Claim 5) provides a multi-valued (n
(≧ 3) value In a nonvolatile semiconductor memory device capable of storing data, a memory cell array including a plurality of memory cells having a charge storage portion, a plurality of bit lines, a plurality of word lines, and a plurality of program controls A plurality of program control circuits, each of which includes 1) holding write control data that determines a write voltage applied to the corresponding memory cell; and 2) corresponding memory according to the held write control data. The write voltage is applied to the cells at the same time, 3) the write state of the memory cell is detected, and 4) the write voltage is applied so that only the insufficiently written memory cells are brought into a predetermined write state. According to a predetermined logical relationship from the write state of the memory cell and the write control data. Te, the write control data retained selectively changed, each of said program control circuit comprises a data circuit for holding said write control data, characterized in that.

Further, the following are preferred embodiments of the present invention.

(1) The data circuit is composed of n logic circuits having n-1 input terminals.

(2) An n logic circuit having n-1 input terminals has one output terminal of n-1 input terminals of the other n-1 logic circuits. The data circuit is formed by being connected to input terminals.

(3) Each program control circuit includes a sense circuit for changing the write control data held in the data circuit according to the signal on the bit line.

(4) Each program control circuit includes n-1 sense circuits for changing the data held in the data circuit according to the signal on the bit line.

(5) The sense circuit is composed of n-1 switch circuits which are turned on / off according to the signal on the bit line.

Further, according to the present invention (claim 9), multi-valued (n
(≧ 3) value In a nonvolatile semiconductor memory device capable of storing data, a memory cell array including a plurality of memory cells having a charge storage portion, a plurality of bit lines, a plurality of word lines, and a plurality of program controls A circuit and a plurality of data circuits, the plurality of program control circuits,
1) select the memory cell, 2) apply a write voltage to the selected memory cell, and the plurality of data circuits are applied to the corresponding memory cells selected by the program control circuit. The write control data of the first, second, ..., N logical levels for controlling the write control voltage is held, 2) the write control voltage is applied to the corresponding memory cells, and 3) the logic other than the first logic is applied. Selectively detecting only the write state of the memory cell corresponding to the data circuit holding the write control data of a level, and 4) the data circuit corresponding to the memory cell having reached a predetermined write state. 5) A memory cell in which the logic level of the write control data is changed to the first logic level and 5) a predetermined write state is not reached. Holds the logic level of the write control data of the corresponding data circuit, 6) the first
The write control data of the data circuit which holds the write control data of the logical level is held at the first logic level.

Further, the following are preferred embodiments of the present invention.

(1) Each data circuit comprises a data holding circuit composed of n logic circuits having n-1 input terminals.

(2) For n logic circuits having n-1 input terminals, each output terminal is one input of the n-1 input terminals of the other n-1 logic circuits. The terminals are connected to each other to form a data holding circuit.

(3) Each data circuit includes a sense circuit for changing the logic level of the write control data held in the data circuit according to the signal on the bit line.

(4) Each data circuit has n-1 sense circuits for changing the logic level of the data held in the data circuit according to the signal on the bit line.

(5) The sense circuit is composed of n-1 switch circuits which are turned on / off according to the signal on the bit line.

Further, according to the present invention, a memory cell array composed of a plurality of memory cells having a charge storage portion capable of storing multi-valued (n (≧ 3) values) data, a plurality of bit lines, and a plurality of word lines. , A plurality of program control circuits, each of which has 1) holding write control data that determines a write voltage applied to the corresponding memory cell, and 2) according to the held write control data. The write voltage is simultaneously applied to the respective corresponding memory cells, 3) the write state of the memory cell is detected, and 4) the write voltage is set so that only the insufficiently written memory cells are brought into a predetermined write state. Is applied to a predetermined logical relationship from the write state of the memory cell and the write control data. Thus, each of the program control circuits selectively changes the held write control data, and each program control circuit includes a data circuit for holding the write control data. A non-volatile semiconductor memory device comprising a sense circuit for changing the write control data held in the data circuit according to a signal.

Further, according to the present invention, a memory cell array composed of a plurality of memory cells having a charge storage portion capable of storing multi-valued (n (≧ 3) values) data, a plurality of bit lines, and
Equipped with multiple word lines and multiple program control circuits,
The plurality of program control circuits 1) hold write control data that determines a write voltage applied to the corresponding memory cell, and 2) write the corresponding memory cell in accordance with the held write control data. Voltage is applied simultaneously, 3) the write state of the memory cell is detected, and 4) the write voltage is applied so that only the memory cell in which writing is insufficient is brought into a predetermined write state. A data circuit for selectively changing the held write control data according to a predetermined logical relationship from the write state of the cell and the write control data, and each of the program control circuits holding the write control data. Each of the program control circuits further includes a signal of the bit line. The nonvolatile semiconductor memory device, characterized in that it comprises (n-1) sense circuit for changing the data held in the data circuit I.

Here, the data circuit is composed of n logic circuits having n-1 input terminals. Further, in the n logic circuits having the n-1 input terminals, each output terminal is connected to one of the n-1 input terminals of the other n-1 logic circuits. The data circuits are connected to each other to form the data circuit.

Further, according to the present invention, a memory cell array composed of a plurality of memory cells having a charge storage portion capable of storing multi-valued (n (≧ 3) values) data, a plurality of bit lines, and a plurality of word lines. , A plurality of program control circuits and a plurality of data circuits, the plurality of program control circuits,
1) select the memory cell, 2) apply a write voltage to the selected memory cell, and the plurality of data circuits are applied to the corresponding memory cells selected by the program control circuit. The write control data of the first, second, ..., N logical levels for controlling the write control voltage is held, 2) the write control voltage is applied to the corresponding memory cells, and 3) the logic other than the first logic is applied. Selectively detecting only the write state of the memory cell corresponding to the data circuit holding the write control data of a level, and 4) the data circuit corresponding to the memory cell having reached a predetermined write state. 5) A memory cell in which the logic level of the write control data is changed to the first logic level and 5) a predetermined write state is not reached. Holds the logic level of the write control data of the corresponding data circuit, 6) the first
Holding the logic level of the write control data of the data circuit holding the logic level of the write control data at the first logic level, and each of the data circuits further stores in the data circuit according to the signal of the bit line. A nonvolatile semiconductor memory device, comprising: a sense circuit for changing a logic level of the held write control data.

Further, according to the present invention, a memory cell array composed of a plurality of memory cells having a charge storage portion capable of storing multi-valued (n (≧ 3) values) data, a plurality of bit lines, and
A plurality of word lines, a plurality of program control circuits, and a plurality of data circuits are provided, and the plurality of program control circuits 1) select the memory cells and 2) apply a write voltage to the selected memory cells. , The plurality of data circuits: 1) write control data of a first, second, ..., Nth logic level for controlling a write control voltage applied to the corresponding memory cell selected by the program control circuit. Hold, 2) the write control voltage is applied to the corresponding memory cell, and 3) the write state of the memory cell corresponding to the data circuit holding the write control data of a logic level other than the first level. 4) selectively write only, and 4) write control data of the data circuit corresponding to a memory cell that has reached a predetermined write state. Changing the logic level of the data to the first logic level, 5) holding the logic level of the write control data of the data circuit corresponding to a memory cell which has not reached a predetermined write state, 6) the The write control data of the data circuit holding the write control data of the first logic level is held at the first logic level, and each of the data circuits further stores the data according to the signal of the bit line. A non-volatile semiconductor memory device comprising n-1 sense circuits for changing a logic level of data held in the circuit.

Here, each of the data circuits is n-1.
It is characterized by comprising a data holding circuit composed of n logic circuits having a number of input terminals. Further, the n logic circuits having the n-1 input terminals have the output terminals n-1 of the other n-1 logic circuits.
The data holding circuit is configured by being connected to one of the input terminals of the input terminals.

(Operation) Multi-valued (n (≧ 3) according to the present invention
An EEPROM capable of storing (value) data stores n-valued data in association with the n charge amounts stored in the charge storage layer of the memory cell. Then, by configuring an n-value storage data circuit for temporarily storing n-value write data with n logic circuits having n-1 input terminals,
The control circuit area can be reduced.

Further, the n charge amounts are set discretely, and the charge amount margin, which is the difference between the charge amounts, is set larger as the charge amount increases. As a result, the maximum charge amount can be reduced by reducing the charge amount margin for the data corresponding to the relatively small charge amount while ensuring the reliability of the data corresponding to the relatively large charge amount. Therefore,
It is possible to realize a highly reliable EEPROM while suppressing an increase in writing time and writing voltage.

[0034]

DETAILED DESCRIPTION OF THE INVENTION The details of the present invention will be described below with reference to the illustrated embodiments.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
2 shows the structure of the memory cell M in the embodiment of FIG.
A floating gate (charge storage layer) 4 is formed on a p-type semiconductor substrate (or p-type well) 1 via a tunnel insulating film 3.
A control gate 6 is formed on this via a gate insulating film 5. The n-type diffusion layer 2 is formed on the surface of the substrate 1 as a source.
Formed as a drain. Data is stored in the memory cell M by controlling the amount of charge accumulated in the floating gate 4.

For example, data storage is performed as follows. When the substrate voltage Vsub, the source voltage Vs, and the drain voltage Vd are set to a high voltage Vpp (for example, 20V) and the control gate voltage VCG is set to 0V, charges move through the insulating film 3,
Positive charges are accumulated in the floating gate 4. This state is made to correspond to the state of data "0". From the state of data “0”, the control gate voltage VCG is set to the high voltage Vpp (for example, 20
V), the substrate voltage Vsub, the source voltage Vs, and the drain voltage Vd are set to 0V, negative charges are accumulated in the floating gate 4. Data "1", "2", and "3" are stored by controlling the negative charge amount in three regions. The threshold value Vt of the memory cell changes depending on the charge amount of the floating gate 4, and data is actually read by detecting the value of this Vt.

The charges stored in the floating gate 4 leak over a long period of time. FIG. 2 shows an example of changes over time in the threshold Vt of the memory cell M. The threshold (neutral threshold) when the charge amount of the floating gate 4 is 0 is V
Let be e. The more negative charges there are, the higher the threshold Vt becomes, and three values V1, V2, and V3 (V1 <V2 <V3) are shown as initial values of the threshold Vt of the memory cell.
Leakage of charges accumulated in the floating gate 4 is 0
Will stop. Therefore, V1, V2, and V3 gradually approach Ve as time goes by. Further, the higher the threshold value, the faster the speed dV / dt approaching Ve. This is because the larger the charge amount, the larger the leak amount. For example, the change amount of the threshold value after leaving for 10 years is ΔV1 <ΔV2 <ΔV3
Becomes

FIG. 3 shows the relationship between the threshold value of the memory cell and the data. EEPR having a plurality of memory cells
In OM, it is difficult to control the threshold values of all the memory cells to the same value, so that the threshold value corresponding to certain data generally has a certain threshold distribution width. In FIG. 3, the threshold value corresponding to the data "0" is set to Vr1 or less. Here, it is set to the neutral threshold Ve or less,
This is the case when the charge amount of the floating gate is positive. The threshold value corresponding to the data "1" is set to Vr1 or more and Vr2 or less. The threshold value corresponding to the data "2" is set to Vr2 or more and Vr3 or less, and the threshold value corresponding to the data "3" is set to Vr3 or more. Here, Ve <Vr1 is set, which corresponds to data “3”, “2”, and “1” in order of increasing negative charge amount of the floating gate. The voltages Vr1, Vr2, Vr3 are called reference voltages.
Data is read based on the magnitude relation between the threshold voltage of the memory cell and these reference voltages.

A margin of ΔV is provided between the minimum value of the threshold value corresponding to the data "1" and Vr1. This is because when the threshold value corresponding to the data “1” approaches Ve with time to stand and becomes Vr1 or less, the data “1” is transformed into the data “0”, so that the data retention period of the memory cell is lengthened. Similarly, a margin of ΔV is provided between the minimum threshold value corresponding to the data “2” or “3” and Vr2 or Vr3.

As described with reference to FIG. 2, the more the charge of the floating gate is, the more the threshold changes with time. Therefore, in the example shown in FIG. 3, until the data “1” becomes “0”. The time until the data “2” is transformed into “1” is shorter than the time of, and the time until the data “3” is transformed into “2” is shorter. This is because the threshold margin ΔV for holding each data is constant.

FIG. 4 shows the relationship between the threshold value of the memory cell and the data in the present invention. A margin of ΔV1 is provided between the minimum value of the threshold value corresponding to the data “1” and Vr1. A margin of ΔV2 is provided between the minimum value of the threshold value corresponding to the data “2” and Vr2.
A margin of ΔV3 is provided between the minimum threshold value corresponding to the data “3” and Vr3. Where ΔV1 <
ΔV2 <ΔV3. Ideally, it takes the same time for the data to be transformed from "1" to "0", "2" to "1", and "3" to "2". By setting ΔV1 <ΔV2 <ΔV3, it is not necessary to provide an extra threshold value margin ΔV1 for holding data “1”, for example.

As described above, the threshold value corresponding to each data can be lowered by reducing the threshold value margin for the data whose corresponding threshold value changes little with time. Therefore, the amount of charge stored in the floating gate can be reduced, and the writing time can be shortened or the writing voltage can be reduced.

In FIG. 4, the neutral threshold value Ve is the reference voltage V.
Although it is less than r1, for example, consider a case where Ve is located between Vr1 and Vr2. When ΔV2 <ΔV3 is set, the time taken to change the data “2” to the data “1” and the time taken to change the data “3” to the data “2” can be made substantially equal. The data “1” cannot be garbled. Therefore, ΔV1 <ΔV2 <ΔV3 is set.

As a method of detecting the threshold value of the memory cell and reading the data, there is a method of applying a reference voltage to the control gate to sense whether or not a current flows between the drain and the source. In this case, the voltage stress is applied to the memory cell by applying the reference voltage to the control gate. Data may be corrupted by this stress.

In FIG. 4, when Vr1 <Vr2 <Vr3 <0V, a negative voltage is applied to the control gate at the time of reading, and if the substrate, source and drain are 0V or a positive potential, the threshold value is It changes in the negative direction due to stress. The threshold value of the memory cell becomes a neutral threshold value V along with the standing time.
When the speed of threshold change due to this voltage stress is more prominent than the speed of asymptotically approaching e, not only when Ve is Vr1 or less, but also when Ve is larger than Vr3, ΔV1 <ΔV2
<ΔV3 is set. If Ve> Vr3, data “1”
The threshold value corresponding to is lower than the threshold value corresponding to the data “2”, and the positive charge stored in the floating gate is large. Therefore, regarding the voltage stress as described above, the changing speed of the threshold value corresponding to the data “1” is slower than the changing speed of the threshold value corresponding to the data “2”. Similarly, the changing speed of the threshold value corresponding to the data “2” is slower than the changing speed of the threshold value corresponding to the data “3”.

A large threshold margin means that
This means that the charge amount margin is also large. In an actual memory device, in addition to the threshold value of the memory cell, a current flowing through the memory cell (hereinafter referred to as a cell current) may be used for correspondence. For example, a certain voltage is applied to the control gate and the cell current flowing from the drain to the source is detected. In an n-channel type memory cell, the cell current decreases as the threshold value increases.

FIG. 5 shows the relationship between cell current and data in a memory cell. The neutral cell current when the amount of charge stored in the floating gate is 0 is Ie. A margin of ΔI1 is provided between the maximum value of the cell current corresponding to the data “1” and the reference current Ir1. Data “2”
Between the maximum value of the cell current and the reference current Ir2 corresponding to
A margin of ΔI2 is provided. Between the maximum value of the cell current corresponding to the data “3” and the reference current Ir3, ΔI3
Margin is provided. ΔI1 <ΔI2 <ΔI3. Ideally, it takes the same time for the data to be transformed from "1" to "0", "2" to "1", and "3" to "2". ΔI1 <Δ
By setting I2 <ΔI3, it is not necessary to provide an extra cell current margin ΔI1 for holding data “1”, for example.

As described above, the cell current corresponding to each data can be increased by reducing the cell current margin for the data whose corresponding cell current changes little with time. Therefore, the amount of charge stored in the floating gate can be reduced, and the writing time can be shortened or the writing voltage can be reduced.

FIG. 6 shows the change over time in the threshold value when positive charges are stored in the floating gate. The larger the amount of positive charges, the lower the threshold and the larger the rate of change over time. Figure 7
Contrary to FIG. 4, the data “0”,
They are "1", "2", and "3". Therefore, ΔV1 <
Let ΔV2 <ΔV3. In contrast to FIG. 5, FIG. 8 corresponds to FIG. 7, in which data “0”,
They are "1", "2", and "3". Therefore, ΔI1 <
Let ΔI2 <ΔI3.

As described with reference to FIGS. 2, 4 and 5 and FIGS. 6, 7 and 8, the charge amount margin accumulated in the floating gate in order to prevent the data from being changed and the stored information being destroyed due to various causes, Alternatively, the amount of charge stored in the floating gate can be reduced by setting the threshold margin or the cell current margin for each data. Therefore, the writing time is shortened or the writing voltage is lowered. Whether the margin is secured by the charge amount, the threshold value, or the cell current depends on the control circuit of the memory device.

Although an n-channel type memory cell has been described here as an example, a p-channel type memory cell can also be used.

FIG. 9 shows the basic structure of a multi-value storage type EEPROM which is constructed by using the memory cell M shown in FIG. Here, a three-value storage type is shown as an example. For the memory cell array 7 configured by arranging the memory cells M in a matrix, a word line selecting / driving circuit 11 for selecting a memory cell and applying a write voltage and a read voltage to the control gate is provided. The word line selection / drive circuit 11 is connected to the address buffer 10 and receives an address signal. The data circuit 8 is a circuit for temporarily holding write data and reading data in a memory cell. The data circuit 8 is connected to the data input / output buffer 9 and receives an address signal from the address buffer 10.

The data input / output buffer 9 is an EEPROM
It controls the data input / output with the outside. The memory cell array 7 is formed on the p-type well 15 in the n-type well 14 formed on the p-type substrate 13 as seen in FIG. Then, the n-type well 14 and the p-type well 1
A cell well control circuit 12 for controlling the voltage of 5 is provided.

FIG. 11 shows a specific structure of the memory cell array 7 and a data circuit 8 connected to it. The memory cells M1 to M4 are connected in series to form a NAND cell. Both ends thereof have selection transistors S1 and S2.
To the bit line BL and the source line Vs, respectively. The memory cell group sharing the control gate CG is
A unit called "page" is formed, and writing and
It is read. In addition, four control gates CG1 to CG
A block is formed by the memory cell group connected to 4. The “page” and “block” are selected by the word line selection / drive circuit 11. Data circuits 8-0 to 8-m are connected to the bit lines BL0 to BLm to temporarily store write data to corresponding memory cells.

FIG. 12 shows a specific structure of the data circuit 8 shown in FIGS. NAND logic circuit G
1, G2 and G3 form a multi-valued data latch circuit.
Only one of the nodes N1, N2 and N3 is at "L" level and the other two are at "H" level. The ternary data is latched depending on which of the three nodes is at the "L" level.

By using four 3-input NAND logic circuits and inputting their outputs to the other three NAND logic circuits and connecting them to each other, 4-level data can be latched. In general, n-valued data can be latched by using n (n-1) input NAND logic circuits and inputting their outputs to other (n-1) NAND logic circuits and connecting them. Other than the NAND logic circuit, NO as shown in FIG.
It can also be configured by using a circuit such as an R logic circuit. In FIG. 16, only one of the three nodes N4, N5, N6 is at "H" level.

FIG. 17 shows a conventional data latch circuit for latching ternary data with two 1-bit data latch circuits composed of inverters I2 and I3 and 1-bit data latch circuits composed of I4 and I5. Shows. FIG. 17
18 shows the configuration of the data latch circuit of FIG. 18 and FIG. 19 shows the configuration of the multi-valued data latch circuit including the NAND logic circuits G1, G2 and G3. The number of wirings from the p-channel MOS region to the n-channel MOS region is four in the data latch circuit of FIG. 17, but is three in the multi-valued data latch circuit composed of the NAND logic circuits G1, G2 and G3. It is a book. The advantage of the multi-valued data latch circuit composed of the NAND logic circuits G1, G2, G3 is that the circuit area can be reduced by such a small number of wirings.

In FIG. 12, the data input / output line IO
A, IOB and the multi-valued data latch circuit are n-channel MO
It is connected through S transistors Qn11 and Qn12. The data input / output lines IOA and IOB are also connected to the data input / output buffer 9 in FIG. The gates of the n-channel MOS transistors Qn11 and Qn12 have the NAND logic circuit G4.
And an inverter I1 connected to the output of the column address decoder. n-channel MOS transistor Q
In the circuit composed of n1, Qn2, or Qn3, Qn4, the activation signal SEN1 or SEN2 becomes "H", and the bit line voltage is sensed to change the data of the multi-valued data latch circuit.

N-channel MOS transistors Qn5, Qn
In the circuit composed of 6, Qn7, Qn8 and the p-channel MOS transistor Qp1, the signal BLC2 becomes "H", and the bit line voltage at the time of writing is controlled according to the data of the multi-valued data latch circuit. In the n-channel MOS transistor Qn9, the signal BLC1 becomes "H", and the data circuit 8 and the bit line BL are connected. In the n-channel MOS transistor Qn10, the signal PRE becomes "H" to set the bit line BL to the voltage VBLP. High breakdown voltage n-channel MOS
The transistor Hn33 is for preventing the high voltage applied to the bit line BL from being applied to the data circuit at the time of erasing, and the signal ERSB is "H" except at the time of erasing.

Next, the EEPROM configured as described above
The operation will be described with reference to FIGS. Figure 1
Reference numeral 3 shows a read timing, FIG. 14 shows a write timing, and FIG. 15 shows a write verify timing.

The read operation will be described with reference to FIG. First, the voltage VBLP is the power supply voltage Vcc (for example, 5V).
Then, the bit line becomes "H" level. At the same time, the voltage VSR also becomes Vcc, and the signals SEN1 and SEN2 are "H".
Then, the nodes N1 and N3 are reset to "H" and the node N2 is reset to "L". The signal PRE becomes "L", and the bit line becomes in a floating state. Subsequently, the selected control gate CG2 of the block selected by the word line selection / drive circuit 11 is 0V, the non-selected control gates CG1, CG3, CG4 and the selection gates SG1, SG2.
Is brought to Vcc.

When the threshold value of the selected memory cell is 0 V or less, the bit line voltage becomes "L". If the threshold value of the selected memory cell is 0 V or higher, the bit line voltage remains "H". After that, the signal SEN1 becomes "H". If the bit line is "L", the n-channel MOS transistor Qn1 is "OFF" and the node N1 remains "H". If the bit line is "H", n channel M
The OS transistor Qn1 is "ON" and the node N1 is 0V.
Is set to "L" by the voltage VSR.

Next, the selected control gate is set to 2V. If the threshold of the selected memory cell is 2V or less,
The bit line voltage becomes "L". If the threshold value of the selected memory cell is 2 V or higher, the bit line voltage remains "H". After that, the signal SEN2 becomes "H". if,
If the bit line is "L", n-channel MOS transistor Q
n3 is "OFF" and the node N3 remains "H".
If the bit line is "H", the n-channel MOS transistor Qn3 is "ON" and the node N3 is "L" by the voltage VSR of 0V.

Finally, when the column activation signal CENB input to the column address decoder becomes "H", the data held in the data circuit selected by the address signal is output to the data input / output lines IOA and IOB. ,
It is output to the outside of the EEPROM via the data input / output buffer 9.

The relationship between the data stored in the memory cell, the threshold value, and the nodes N1, N2, and N3 after reading is as follows:
It is as shown in the following (Table 1).

[0066]

[Table 1]

Two memory cells adjacent to each other can have nine storage states. Of these, eight states are used to store 3-bit data. The signals output to the data input / output lines IOA and IOB are converted into 3-bit data by the data input / output buffer 9 based on the ternary information of adjacent even and odd two columns and output. For example, the following (Table 2) is used.

[0068]

[Table 2]

FIG. 14 shows the write operation. Before the write operation, the input 3-bit data is
As shown in (Table 2), it is converted into two ternary data by the data input / output buffer 9 and input to the data circuits of the adjacent even and odd columns. 3-level data and data input / output line IO
The relationship between A, IOB, and nodes N1, N2, N3 is as shown in (Table 3) below.

[0070]

[Table 3]

The converted ternary data is transferred to the data circuit at the column address designated by the address signal when the column activation signal CENB is "H".

In the write operation, first, the signal PRE is "L".
And the bit line is floated.

Next, the signal BLC2 is "H" and the voltage VLH.
Is 2.5 V and VLL is 0 V. As a result, Vcc from the data circuit holding the data “0”, VLH from the data circuit holding the data “1”,
From the data circuit holding the data "2", VLL
Is output to the bit line. n-channel MOS transistors Qn8, Qn9, high breakdown voltage n-channel MOS transistor H
When the voltage drop corresponding to the threshold value of n33 becomes a problem, the signals BLC1, BLC2 and ERSB may be boosted.

The selection gate SG1 and control gate CG of the block selected by the word line selection / drive circuit 11 are selected.
1 to CG4 become Vcc. The select gate SG2 is 0V. Next, the selected control gate CG2 is set to the high voltage Vpp.
(For example, 20 V), non-selection control gates CG1, CG3,
CG4 and the selection gate SG1 become VM (for example, 10V).

In the memory cell corresponding to the data circuit in which the data "2" is held, electrons are injected into the floating gate due to the potential difference between the channel potential of 0 V and Vpp of the control gate, and the threshold value rises. In the memory cell corresponding to the data circuit in which the data “1” is held, electrons are injected into the floating gate due to the potential difference between the channel potential of 2.5 V and Vpp of the control gate, and the threshold value rises. The channel potential is set to 2.5V because the electron injection amount may be smaller than that in writing "2" data. In the memory cell corresponding to the data circuit holding the data "0", the potential difference between the channel potential and Vpp of the control gate is small, so that electrons are not effectively injected into the floating gate. Therefore, the threshold value of the memory cell does not change.

After the write operation, the threshold value of the memory cell is detected (write verify). If the desired threshold value is reached, the data in the data circuit is changed to "0". If the desired threshold value has not been reached, the data in the data circuit is held and the write operation is performed again. The write operation and write verify are repeated until all the selected memory cells reach the desired threshold value.

This write verify operation will be described with reference to FIG. First, the voltage VBLP is the power supply voltage Vcc
(For example, 5V), the bit line becomes "H" level. The signal PRE becomes "L", and the bit line becomes in a floating state. Then, the voltage VLH is Vcc, and the voltage V
When LL is set to 0V and the signal BLC2 is set to "H", only the bit line BL corresponding to the data circuit in which the data circuit holds "2" data is set to 0V.

Next, the selected control gate CG2 of the block selected by the word line selection / drive circuit 11 is set to 0.5V, and the non-selected control gates CG1, CG3, CG4 and the selection gates SG1, SG2 are set to Vcc. . If the threshold value of the selected memory cell is 0.5 V or less, the bit line voltage becomes "L". If the threshold value of the selected memory cell is 0.5 V or higher, the bit line voltage remains "H". After that, the signal SEN1 becomes "H". If the bit line is "L", the n-channel MOS transistor Qn1 is "OFF" and the node N1 remains unchanged. If the bit line is "H", the n-channel MOS transistor Qn1 is "ON" and the node N1 is "L" by the voltage VSR of 0V. That is, when the data in the data circuit corresponding to the memory cell in which the "1" write is successful in the "1" data verify operation up to this point is "1",
It is changed to "0". Other data is unchanged.

Then, the voltage VBLP becomes the power supply voltage Vcc (for example, 5V), and the bit line becomes "H" level.
Next, the selected control gate CG2 of the block selected by the word line selection / drive circuit 11 is 3V, the non-selected control gates CG1, CG3, CG4, and the selection gate SG.
1, SG2 are set to Vcc. If the threshold voltage of the selected memory cell is 3 V or less, the bit line voltage becomes "L".
If the threshold value of the selected memory cell is 3 V or higher, the bit line voltage remains "H". After this, the signal SEN1
Becomes "H". If the bit line is "L", the n-channel MOS transistor Qn1 is "OFF" and the node N1
Does not change. If the bit line is "H", the n-channel MOS transistor Qn1 is "ON" and the node N1 is 0.
It is set to "L" by the voltage VSR of V. That is, in the "2" data verify operation up to this point, if the data of the data circuit corresponding to the memory cell in which the "2" write is successful is "2", it is changed to "0". Other data is unchanged.

When all the memory cells reach the desired threshold value, the nodes N1 of all the data circuits become "L". Therefore, when the level of the node N1 of all the data circuits becomes "L". Writing to the cell is terminated. The data conversion rule of the data circuit at the time of write-verify is as follows (Table 4).

[0081]

[Table 4]

As described with reference to FIGS. 14 and 15, by performing writing while verifying, the threshold value of the memory cell corresponding to “1” data is 0.
The threshold value of the memory cell corresponding to "2" data is controlled to be 5 V or more and 2 V or less, and Vcc or less to 3 V or more of the verify reference voltage. As described with reference to FIG. 13, since the reference voltages at the time of reading are 0 V and 2 V, the threshold margin of “1” data is 0.5 V and the threshold margin of “2” data is 1.0 V. To be done. The threshold value corresponding to "0" data is 0 V or less, which is the same as the erased state. For erasing, a high voltage Vpp (for example, 20 V) is applied to the cell well.
Then, the control gate CG is set to 0V. Electrons are emitted from the floating gate and the threshold value becomes 0 V or less.

FIG. 20 shows the cell well control circuit 1 shown in FIG.
2 shows a specific configuration of No. 2. High breakdown voltage n-channel MO
The S transistors Hn17 to Hn28 form a booster circuit. When the pump activation signal PMP is “H” and the oscillating signal Φ is input, the output Vqq becomes a high voltage of Vcc or more. The voltage Vqq is limited by the voltage limiter 16. When the booster circuit reset signal RSTB becomes "L",
Vqq is reset to Vcc. Device standby signal STN
When BY goes to "H", power supply to the booster circuit is cut off. This is because if the threshold of the high breakdown voltage n-channel MOS transistor Hn is lowered in order to increase the voltage transfer efficiency,
This is because the standby power consumption is large due to the leakage current during standby. When the signal CWPMPB becomes "L", the boosted Vqq becomes a high breakdown voltage n-channel MOS transistor Hn10,
It is applied to the cell well via Hn11.

Referring to FIG. 21, cell well control circuit 12
The operation of will be described. During standby, the signal STNBY is "H". The signals RSTB and CWPMPB are also “H”, and PMP and Φ are “L”. Therefore, the cell well is at 0V.

In the non-standby mode, except when erasing, the signal STNB
"L" for Y, RSTB, PMP, "H" for CWPMPB
Is. The signal Φ vibrates. The voltage Vqq is Vcc and the cell well is 0V.

At the time of erasing, the signals RSTB and PMP become "H" and the voltage Vqq is boosted to Vpp. continue,
When the signal CWPMPB becomes "L", the cell well becomes Vpp. CWPMPB becomes “H” and cell well becomes 0V
Are reset, the signals RSTB and PMP become "L", and Vqq is reset to Vcc.

(Second Embodiment) FIG. 22 is a plan view of FIGS.
FIG. 9 is a specific configuration diagram showing another embodiment of the data circuit 8 seen in FIG. It is configured by taking ternary storage as an example. FIG. 22
As shown in (a), the clock synchronous inverter CI
Write / read data is latched in two flip-flops FF1 and FF2, which are respectively configured by 1, CI2 and CI3, CI4. Moreover, these also operate as sense amplifiers. The specific configuration of the clock synchronous inverter CI is shown in FIG. The circuit threshold of the clock synchronous inverter CI is, for example, half of the power supply voltage Vcc (for example, 5V).

The flip-flop FF1 "whether to write" 0 "or write" 1 "or" 2 """
Is latched as read data information, and "whether the memory cell holds" 0 "information or" 1 "or" 2 "information" is sensed and latched as read data information. The flip-flop FF2 is
"Write" 2 "or write" 1 "or" 0 "" is latched as write data information, and the memory cell holds "2" information, "1" or "0". "Have information?" Is sensed and latched as read data information.

The data input / output lines IOA and IOB and the flip-flop FF1 are connected to the n-channel MOS transistor Q.
It is connected via n101 and Qn102. Data input / output line IO
C, IOD and flip-flop FF2 are connected via n-channel MOS transistors Qn103, Qn104. Data input / output lines IOA, IOB, IOC, IOD
Is also connected to the data input / output buffer 9 in FIG.
n-channel MOS transistors Qn101, Qn102, Qn10
The gates of 3 and Qn104 are connected to the output of a column address decoder composed of a NAND logic circuit G101 and an inverter I101. n-channel MOS transistor Q
n105 and Qn109 control the connection between the flip-flops FF1 and FF2 and the MOS capacitor Qd101. The circuit composed of the n-channel MOS transistors Qn106, Qn107, Qn108 and the p-channel MOS transistors Qp102, Qp103 responds to the data of the flip-flops FF1 and FF2 by the activation signal VRFYB or PRO.
The gate voltage of the S capacitor Qd101 is changed. The MOS capacitor Qd101 is a depletion type n-channel MO.
It is composed of an S transistor and is sufficiently smaller than the bit line capacitance. The p-channel MOS transistor Qp105 charges the MOS capacitor Qd101 by the signal PREC. A p-channel MOS transistor for detecting the data of the flip-flop FF1 in order to output to the detection signal PEND whether or not the write data of all the data circuits 8-0, 8-1, ... Qp101 is provided.

N-channel MOS transistor Qn110, p
The channel MOS transistor Qp104 has a signal BLCN,
The connection between the data circuit 8 and the bit line BL is controlled by BLCP. The n-channel MOS transistor Qn111 is
The signal PRE becomes "H", and the bit line BL is set to the voltage VBL.
Set to P. High breakdown voltage n-channel MOS transistor Hn101
Is to prevent the high voltage applied to the bit line during erase from being applied to the data circuit.
ERSB is “H”.

Next, the EEPROM configured as described above
The operation of will be described with reference to FIGS. Figure 2
Reference numeral 3 shows a read timing, FIG. 24 shows a write timing, and FIG. 25 shows a write verify timing.

The read operation will be described with reference to FIG. First, the voltage VBLP is the power supply voltage Vcc (for example, 5V).
Then, the bit line becomes "H" level. At the same time, the signal BLCN becomes "L" and BLCP becomes "H", and the bit line and the MOS capacitor Qd101 are disconnected. Signal P
When RE becomes "L", the bit line is in a floating state. Then, the selected control gate CG2 of the block selected by the word line selection / drive circuit 11 is set to 0.
V, the non-selection control gates CG1, CG3, CG4 and the selection gates SG1, SG2 are set to Vcc. The signal PREC becomes "L" and the MOS capacitor Qd101 is charged to Vcc.

When the threshold value of the selected memory cell is 0 V or less, the bit line voltage becomes "L". If the threshold value of the selected memory cell is 0 V or higher, the bit line voltage remains "H". After that, the signal BLCN is, for example, V
It is set to 1.5V below cc. When the threshold value of the n-channel MOS transistor Qn110 is 1V and if the bit line is 0.5V or less, the n-channel MOS transistor Qn110
Is "ON", the voltage of the node N101 becomes 0.5 V or less.
If the bit line is 0.5 V or more, the n-channel MOS transistor Qn110 is "OFF" and the node N101 is V
kept at cc.

The signal BLCN becomes "L" again, and the bit line BL and the MOS capacitor Qd101 are disconnected.
After the signals LAT1 and SEN1 become "L" and the flip-flop FF1 is deactivated, the signal SAC1 becomes "H". The signal SEN1 becomes “H” again, and then the signal LAT1 becomes “H”.
Is sensed and latched. Thus, whether or not the data in the memory cell is "0" is sensed by the flip-flop FF1 and the information is latched.

Next, the selected control gate is set to 2V. If the threshold of the selected memory cell is 2V or less,
The bit line voltage becomes "L". If the threshold value of the selected memory cell is 2 V or higher, the bit line voltage remains "H". After that, the signal BLCN is set to 1.
It is set to 5V. If the threshold value of the n-channel MOS transistor Qn110 is 1V and the bit line is 0.5V or less, the n-channel MOS transistor Qn110 is "ON",
The node N101 becomes 0.5V or less. If the bit line is more than 0.5V, n-channel MOS transistor Qn1
10 is "OFF" and the node N101 is kept at Vcc.

The signal BLCN becomes "L" again and the bit line BL and the MOS capacitor Qd101 are disconnected.
After the signals LAT2 and SEN2 become "L" and the flip-flop FF2 is deactivated, the signal SAC2 becomes "H". The signal SEN2 becomes “H” again, and the signal LAT2 becomes “H” again.
Is sensed and latched. Thus, the flip-flop FF2 senses whether the data in the memory cell is "2" and the information is latched.

During reading, the signal ERSB is "H", VRFY.
B is "H" and PRO is "L". In addition, the voltage VBL
M and Vs are 0V.

When the column activation signal CENB input to the column address decoder becomes "H", the data held in the data circuit selected by the address signal is output to the data input / output lines IOA, IOB, IOC, IOD. Via the data input / output buffer 9 to the EEPROM
It is output to the outside.

Data stored in memory cells, threshold values, data input / output lines IOA, IOB, IOC, IOD
The relationship between the level output after the reading and the level is as shown in (Table 5) below.

[0100]

[Table 5]

Two memory cells adjacent to each other can have nine storage states. Of these, eight states are used to store 3-bit data. Data input / output lines IOA, IOB, I
The signals output to OC and IOD are converted into 3-bit data by the data input / output buffer 9 based on the ternary information of adjacent even and odd two columns and output. For example,
Correspond as described above (Table 2).

FIG. 24 shows a write operation. Before the write operation, the input 3-bit data is stored in the data 3 in the data input / output buffer 9 as shown in (Table 2) above.
It is converted into value data and input to the data circuits 8 of adjacent even and odd columns. The relationship between the ternary data and the data input / output lines IOA, IOB, IOC, IOD is as shown in (Table 6) below.

[0103]

[Table 6]

The converted ternary data is transferred to the data circuit of the column address designated by the address signal when the column activation signal CENB is "H".

In the write operation, first, the signal PRE is "L".
And the bit line is floated.

Next, the signal VRFYB is "L" and the signal PR is
O is "H" and the voltage VBLM is 2.5V. As a result, Vcc is output to the bit line from the data circuit holding the data "0", and 2.5 V is output to the bit line from the data circuit holding the data "1". When the signal SAC2 is set to 1.5V, 0V is output to the bit line from the data circuit holding the data "2". Assuming that the threshold value of the n-channel MOS transistor Q109 is 1 V, the n-channel MOS transistor is written at the time of writing "0" or "1".
The transistor Qn109 is "OFF", and is "ON" when writing "2". When the voltage drop corresponding to the threshold value of the high breakdown voltage n-channel MOS transistor Hn101 becomes a problem, the signal ERSB may be boosted.

The selection gate SG1 and control gate CG of the block selected by the word line selection / drive circuit 11 are selected.
1 to CG4 become Vcc. The select gate SG2 is 0V. Next, the selected control gate CG2 is set to the high voltage Vpp.
(For example, 20 V), non-selection control gates CG1, CG3,
CG4 becomes VM (for example, 10V). In the memory cell corresponding to the data circuit holding the data “2”,
Due to the potential difference between the channel potential of 0 V and Vpp of the control gate, electrons are injected into the floating gate and the threshold value rises.
In the memory cell corresponding to the data circuit in which the data “1” is held, electrons are injected into the floating gate due to the potential difference between the channel potential of 2.5 V and Vpp of the control gate, and the threshold value rises. The channel potential is set to 2.5V because the electron injection amount may be smaller than that in writing "2" data.

In the memory cell corresponding to the data circuit holding the data "0", the potential difference between the channel potential and Vpp of the control gate is small, so that electrons are not effectively injected into the floating gate. Therefore, the threshold value of the memory cell does not change. During writing, signals SEN1, LAT1, S
EN2 and LAT2 are "H", signal SAC1 is "L", signal PREC is "H", signals BLCN and BLCP are "H" and "L", respectively, and signal ERSB is "H".

After the write operation, the threshold value of the memory cell is detected (write verify). If the desired threshold value is reached, the data in the data circuit is changed to "0". If the desired threshold value has not been reached, the data in the data circuit is held and the write operation is performed again. The write operation and write verify are repeated until all the selected memory cells reach the desired threshold value.

This write verify operation will be described with reference to FIG. First, the voltage VBLP is the power supply voltage Vcc
(For example, 5V), the bit line becomes "H" level. At the same time, the signal BLCN is "L" and BLCP is "H".
Then, the bit line and the MOS capacitor Qd101 are separated. The signal PRE becomes "L", and the bit line becomes in a floating state. Subsequently, the selected control gate CG2 of the block selected by the word line selection / drive circuit 11 is 0.5 V, and the non-selected control gates CG1 and CG are
3, CG4 and select gates SG1 and SG2 are set to Vcc. Signal PREC becomes "L" and MOS capacitor Q
d101 is charged to Vcc.

The threshold value of the selected memory cell is 0.5
If it is V or less, the bit line voltage becomes "L". If the threshold value of the selected memory cell is 0.5 V or higher, the bit line voltage remains "H". After that, the signal BLCN is set to 1.5 V which is lower than Vcc, for example. If the threshold value of the n-channel MOS transistor Qn110 is 1V, and if the bit line is 0.5V or less, the n-channel MOS transistor Qn
n110 is “ON”, and the voltage of the node N101 is 0.5 V or less. If the bit line is over 0.5V, n channel MO
The S transistor Qn110 is "OFF", and the node N101
Is kept at Vcc.

The signal BLCN becomes "L" again and the bit line BL and the MOS capacitor Qd101 are disconnected.
When the signal VRFYB becomes “L”, only the data circuit holding the “0” write data is p-channel MOS.
Since the transistor Qp103 is "ON", the node N101
Becomes Vcc. When the signal SAC2 becomes 1.5V,
The node N101 is set to 0V only in the data circuit holding the "2" write data. In the data circuit holding the "1" write data, the voltage of the node N101 of 0.5 V or higher does not change. The voltage of the node N1 of 0.5V or less is charged up to 0.5V. Signal LA
T1 and SEN1 become "L" and flip-flop F
After F1 is deactivated, the signal SAC1 becomes "H". The signal SEN1 becomes “H” again and the signal LA continues.
When T1 becomes "H", the voltage of the node N101 is sensed and latched.

With this, only in the data circuit holding the "1" write data, it is detected whether or not the data of the corresponding memory cell is sufficiently in the "1" write state. If the data in the memory cell is "1", the write data is changed to "0" by sensing and latching the voltage of the node N101 by the flip-flop FF1. If the data in the memory cell is not "1", flip-flop FF
The write data is held at "1" by sensing and latching the voltage of the node N101 at 1. The write data of the data circuit holding the "0" or "2" write data is not changed.

Next, the selected control gate is set to 3V. If the threshold of the selected memory cell is 3V or less,
The bit line voltage becomes "L". If the threshold value of the selected memory cell is 3 V or higher, the bit line voltage remains "H". After that, the signal BLCN is set to 1.
It is set to 5V. If the threshold value of the n-channel MOS transistor Qn110 is 1V and the bit line is 0.5V or less, the n-channel MOS transistor Qn110 is "ON",
The node N101 becomes 0.5V or less. If the bit line is more than 0.5V, n-channel MOS transistor Qn1
10 is "OFF" and the node N101 is kept at Vcc.

The signal BLCN becomes "L" again and the bit line BL and the MOS capacitor Qd101 are disconnected.
When the signal VRFYB becomes “L”, only the data circuit holding the “0” write data is p-channel MOS.
Since the transistor Qp103 is "ON", the node N101
Becomes Vcc. After the signals LAT1 and SEN1 become "L" and the flip-flop FF1 is deactivated, the signal SAC1 becomes "H". Again, the signal SEN1 is "H"
Then, the signal LAT1 becomes "H", and the voltage of the node N101 is sensed and latched.

Then, the signal PRO is "H" and the voltage VBL is
M becomes Vcc. Only the data circuit holding the "1" write data changes its node N101 to "H". After the signals LAT2 and SEN2 become "L" and the flip-flop FF2 is deactivated, the signal SAC
2 becomes "H". The signal SEN2 becomes "H" again and the signal LAT2 becomes "H" again, so that the node N1
The voltage 01 is sensed and latched.

Thus, only the data circuit holding the "2" write data detects whether or not the data of the corresponding memory cell is sufficiently in the "2" write state. If the data in the memory cell is "2", the write data is changed to "0" by sensing and latching the voltage of the node N101 by the flip-flops FF1 and FF2. If the data in the memory cell is not "2", the write data is held at "2" by sensing and latching the voltage of the node N101 by the flip-flops FF1 and FF2. The write data of the data circuit holding the "0" or "1" write data is not changed.

During the write verify, the signal ERSB is "H" and the voltage Vs is 0V.

Whether or not all the selected memory cells have reached the desired threshold value can be determined by detecting the signal PEND. If all the selected memory cells have reached the desired threshold value, the write data becomes all “0”, and the data detection p of each data circuit 8-0, 8-1, ..., 8-m.
The channel MOS transistors Qp101 are all "OFF". When it is detected whether the signal line PEND is disconnected from the power supply voltage Vcc, it is possible to know whether all the selected memory cells have reached the desired threshold value. The data conversion rule of the data circuit at the time of write verify is as described above (Table 4).

As described with reference to FIGS. 24 and 25, by performing writing while verifying, the threshold value of the memory cell corresponding to "1" data is 0.
The threshold value of the memory cell corresponding to "2" data is controlled to be 5 V or more and 2 V or less, and Vcc or less to 3 V or more of the verify reference voltage. As described with reference to FIG. 23, since the reference voltages at the time of reading are 0 V and 2 V, the threshold margin of "1" data is 0.5 V and the threshold margin of "2" data is 1.0 V. To be done. The threshold value corresponding to "0" data is 0 V or less. This is the same as the erased state.

(Modification) The present invention is not limited to the above embodiments. In the embodiment, EEPR
Although the OM has been described as an example, the present invention can be similarly implemented in the EPROM. Further, although the NAND type memory cell is used for the description, various kinds of memory cells can be similarly implemented.

In the description using the NAND type memory cell,
By controlling the reference potential at the time of reading and the reference potential at the time of writing verification, the threshold margin was secured. The cell current margin can be secured by controlling the read reference current and the reference current during verification. Further, in the embodiment, the three-value or four-value storage is described as an example, but any value can be similarly implemented. In addition, various modifications can be made without departing from the scope of the present invention.

[0123]

As described above in detail, according to the present invention, in a memory cell capable of multi-value storage, n for temporary storage is provided.
By configuring the value storage data circuit with n logic circuits having n-1 input terminals, an increase in the area of the control circuit other than the memory cells can be suppressed. In addition to this, by setting the charge amount margin to be larger as the charge amount is larger, it is possible to realize a highly reliable EEPROM while suppressing an increase in the write time and the write voltage.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a configuration of a memory cell according to a first embodiment.

FIG. 2 is a diagram showing a data retention characteristic of a memory cell according to the first embodiment.

FIG. 3 is a diagram showing a threshold distribution of a conventional memory cell.

FIG. 4 is a diagram showing a threshold distribution of memory cells according to the first embodiment.

FIG. 5 is a diagram showing a cell current distribution of a memory cell according to the first embodiment.

FIG. 6 is a diagram showing a data retention characteristic of a memory cell according to the first embodiment.

FIG. 7 is a diagram showing a threshold distribution of memory cells according to the first embodiment.

FIG. 8 is a diagram showing a cell current distribution of a memory cell according to the first embodiment.

FIG. 9 is a block diagram showing the configuration of the EEPROM according to the first embodiment.

FIG. 10 is a cross-sectional view showing the structure of the EEPROM according to the first embodiment.

FIG. 11 is a diagram showing a circuit configuration of a memory cell array in the first embodiment.

FIG. 12 is a diagram showing a specific configuration of a data circuit according to the first embodiment.

FIG. 13 is a timing chart showing a data read operation according to the first embodiment.

FIG. 14 is a timing chart showing a data write operation according to the first embodiment.

FIG. 15 is a timing chart showing a write verify operation according to the first embodiment.

FIG. 16 is a diagram showing a modified example of the multi-valued storage data latch circuit in the first embodiment.

FIG. 17 is a diagram showing a conventional data latch circuit.

FIG. 18 is a diagram showing a configuration of a conventional data latch circuit.

FIG. 19 is a diagram showing a configuration of a multi-value storage data latch circuit according to the first embodiment.

FIG. 20 is a diagram showing a specific configuration of a cell well control circuit according to the first embodiment.

FIG. 21 is a timing chart showing the operation of the cell well control circuit according to the first embodiment.

FIG. 22 is a diagram showing a specific configuration of a data circuit according to the second embodiment.

FIG. 23 is a timing chart showing a data read operation according to the second embodiment.

FIG. 24 is a timing chart showing a data write operation according to the second embodiment.

FIG. 25 is a timing chart showing a write verify operation according to the second embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... P-type semiconductor substrate 2 ... N-type diffusion layer 3 ... Insulating film 4 ... Floating gate (charge storage layer) 5 ... Gate insulating film 6 ... Control gate 7 ... Memory cell array 8 ... Data circuit 9 ... Data input / output buffer 10 ... Address buffer 11 ... Word line selection / drive circuit 12 ... Cell well control circuit 13 ... P-type semiconductor substrate 14 ... N-well 15 ... P-well 16 ... Voltage limiter M ... Memory cell SG ... Select gate CG ... Control gate BL ... Bit Line Qn ... n channel MOS transistor Qp ... p channel MOS transistor Hn ... high breakdown voltage n channel MOS transistor Qd ... depletion type n channel MOS transistor CI ... clock synchronous inverter FF ... flip flop

Claims (12)

[Claims] 1. A memory cell having a charge storage portion capable of storing multi-valued (n (≧ 3) value) data, and a data circuit for temporarily storing write data, wherein the data circuit is n−.
A non-volatile semiconductor memory device comprising n logic circuits each having one input terminal. 2. The n logic circuits having n-1 input terminals each have one output terminal out of n-1 input terminals of each of the other n-1 logic circuits. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the two input terminals are connected to each other to form a data circuit. 3. A memory cell having a charge storage portion capable of storing multi-valued (n (≧ 3) value) data, a sense circuit for reading data stored in the memory cell, and a read circuit by the sense circuit. A data circuit for temporarily storing data is provided, and the sense circuit is composed of n-1 switch circuits that are turned on / off according to the value of read data, and the data circuit has n-1 input terminals. A non-volatile semiconductor memory device comprising n logic circuits included therein. 4. The n-1 switch circuits are connected in series with a first MOS transistor to which a different sense signal is input and a second MOS transistor to which the read data is input, to form a sense circuit. And n
-N logic circuits having -1 input terminals have their output terminals connected to one input terminal of the n-1 input terminals of the other n-1 respective logic circuits. 4. The non-volatile semiconductor memory device according to claim 3, wherein the data circuit is configured as a data circuit. 5. A memory cell array composed of a plurality of memory cells having a charge storage section capable of storing multi-valued (n (≧ 3) values) data, a plurality of bit lines, a plurality of word lines, and a plurality of word lines. A program control circuit, wherein each of the plurality of program control circuits holds write control data that determines a write voltage to be applied to the corresponding memory cell, and the memory cell corresponding to each of the stored memory cells according to the held write control data. The write voltage is simultaneously applied to the memory cells, the write state of the memory cells is detected, and the write voltage is applied so that only the memory cells incompletely written have a predetermined write state. According to a predetermined logical relationship from the write state of the write control data and the write control data, Each program control circuit selectively changes write control data, and each program control circuit includes a data circuit for holding the write control data, and the data circuit has n-1 logic circuits having n-1 input terminals. A non-volatile semiconductor memory device comprising: 6. The n logic circuits having the n-1 input terminals have one output terminal out of the n-1 input terminals of each of the other n-1 logic circuits. 6. The non-volatile semiconductor memory device according to claim 5, wherein the data circuit is configured by being connected to one input terminal with each other. 7. The nonvolatile memory according to claim 6, wherein the program control circuit includes a sense circuit for changing the write control data held in the data circuit according to a signal of the bit line. Semiconductor memory device. 8. The program control circuit comprises n-1 switch circuits which are turned on / off according to the signal of the bit line in order to change the data held in the data circuit according to the signal of the bit line. 7. The switch circuits each include a first switch element to which a different sense signal is input and a second switch element to which a signal of the bit line is input, connected in series. Nonvolatile semiconductor memory device. 9. A memory cell array composed of a plurality of memory cells having a charge storage section capable of storing multi-valued (n (≧ 3) values) data, a plurality of bit lines, a plurality of word lines, and a plurality of word lines. A program control circuit and a plurality of data circuits, wherein the plurality of program control circuits select the memory cell and apply a write voltage to the selected memory cell, and the plurality of data circuits are the program control circuits. The memory which holds write control data of the first, second, ..., Nth logic levels for controlling the write control voltages applied to the respective corresponding memory cells selected by the circuit, and which corresponds to the respective write control voltages. Writing to the memory cell corresponding to the data circuit that holds write control data of a logic level other than the first level applied to the cell Only the state is selectively detected, and the logic level of the write control data of the data circuit corresponding to the memory cell that has reached the predetermined write state is changed to the first logic level to determine the predetermined write state. Hold the logic level of the write control data of the data circuit corresponding to the memory cell that has not yet reached the level of the write control data of the data circuit holding the write control data of the first logic level. The first
, And each data circuit has n-1 input terminals.
A non-volatile semiconductor memory device comprising a data holding circuit composed of individual logic circuits. 10. The n logic circuits having the n-1 input terminals each have one output terminal out of n-1 input terminals of the other n-1 logic circuits. 10. The nonvolatile semiconductor memory device according to claim 9, wherein the data holding circuit is configured by being connected to one input terminal with each other. 11. The data circuit further comprises a sense circuit for changing a logic level of the write control data held in the data holding circuit according to a signal of the bit line. The nonvolatile semiconductor memory device described. 12. The data circuit comprises n-1 switch circuits which are turned on / off according to the signal of the bit line in order to change the data held in the data holding circuit according to the signal of the bit line. 2. Each switch circuit is configured by serially connecting a first switch element to which a different sense signal is input and a second switch element to which a signal of the bit line is input.
The nonvolatile semiconductor memory device according to 0.