JPH09246404A - Non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide DINOR type flash memory cutting down the gate length without decreasing the implanting efficiency in floating gate. SOLUTION: Within the title non-volatile semiconductor memory, a gate length shorter than the marginal gate length in the drain withstand voltage length characteristics is adopted while setting up the relation formula of IdsR<leak> <ids<read> /Nbit/M to be satisfied. In said formula, Ids<read> represents the reading out current running between the source drain of a selective memory cell MC 22 in the data reading-out time, IdsR<leak> represents the reading out leakage current between the source drain of the MC23-MC25, Nbit represents the numbers of MC11-MC15 or 1MC21-MC25, M represents the previously specified margin factor exceeding 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly to DINOR (divided
bit line NOR) type flash memory.

[0002]

2. Description of the Related Art In recent years, a flash memory, which is a type of non-volatile semiconductor memory device, can be manufactured at a lower cost than a dynamic random access memory (DRAM), and is therefore expected as a memory device for the next generation.

In order to unify the power supply of this flash memory, an n-channel memory cell has already been used, and an F region is formed in the overlapping region of the n-type drain region and the floating gate.
A DINOR type flash memory that writes data by injecting N current into a floating gate is "IEEE JOURNAL OF SOLID-STATE CIRCUIT, VOL.29, No.
4, APRIL 1994 ", pages 454-460.

On the other hand, the present applicant has filed Japanese Patent Application No. 7-148.
No. 969 proposes a DINOR type flash memory using a p-channel memory cell in order to miniaturize the memory cell and prevent the punch-through phenomenon from occurring easily. Although this prior application has not yet been published at the time of filing of the present application, the present invention mainly aims to improve the DINOR type flash memory using the p-channel memory cell according to the above prior application. , A DINOR type flash memory using p-channel memory cells will be briefly described.

FIG. 8 is a sectional view showing the structure of a p-channel memory cell in a DINOR type flash memory. Referring to FIG. 8, the memory cell 80 includes an n-type well 81, ap ⁺ type source 82 and a drain 83 formed on the surface of the well 81, a tunnel oxide film 84 formed on the well 81. The floating gate 85 formed on the tunnel oxide film 84, the interlayer insulating film 86 formed on the floating gate 85, and the interlayer insulating film 8
6 and the control gate 87 formed on the upper surface of the control unit 6.
A memory cell having such a configuration is generally called a stack gate type.

When writing data to the memory cell 80, a positive potential is applied to the control gate 87, a negative potential is applied to the drain 83, and the well 81 is grounded.
The source 82 is opened. As a result, electron-hole pairs (electron-hole pairs) 88 and 89 are generated in a region where the drain 83 is overlapped with the floating gate 85 by a band-band tunneling phenomenon (hereinafter referred to as BTBT). Of these, the electrons 88 are accelerated by an electric field parallel to the substrate surface, and become hot electrons having high energy. Therefore, by injecting the hot electrons into the floating gate 85, the memory cell 80
The data will be written in.

FIG. 9 shows a drain current Id-drain potential Vd characteristic and a gate current Ig-drain potential Vd when the floating gate 85 of the memory cell 80 is connected to the control gate 87 and a gate potential Vg of 6V is applied. Show the characteristics. FIG.
Shows the injection efficiency Ig / Id which is the ratio of the gate current Ig to the drain current Id shown in FIG. As is clear from FIG. 10, in the vicinity of Vd = −6V, 10 ⁻²
High injection efficiency is obtained. Here, Vd = 0
The increase in injection efficiency at V to -6V is due to the increase in electron-hole pairs due to BTBT. Also, Vd = -6V
The decrease in the injection efficiency at -7V is caused by the avalanche breakdown that occurs near the junction with the well 81 in the drain 83. Since avalanche breakdown is a rapid increase in electrons due to impact ionization, the drain current Id increases even though the gate current Ig hardly increases at this time, so that the injection efficiency Ig is increased.
/ Id decreases as shown in FIG.

Generally, as shown in FIG. 11, an n ⁺ type punch-through stopper 1 is provided below the channel in the well 81.
10 are formed. This is to suppress the punch-through current that increases with the shortening of the gate length. BTB mentioned above
The electron-hole pair due to T penetrates under the floating gate 85 and the BTBT generation region 11 in the drain 83.
It is generated within 1. On the other hand, the avalanche current due to the impact ionization described above is generated by the punch-through stopper 11
0 is mainly generated in the impact ionization generation region 112 in the vicinity where 0 contacts the drain 83.

Since the DINOR type flash memory operates with a single external power source (for example, 3.3V), the drain potential Vd at the time of data writing or data erasing is externally supplied by a charge pump circuit inside the chip. It is generated by reducing the voltage. In general, the charge pump circuit has almost no current supply capability, and thus the load current accompanying the data write operation or data erase operation must be suppressed as much as possible. If the load current cannot be suppressed, the area and the number of stages of the charge pump circuit will be increased, which will increase the chip area and eventually the manufacturing cost. Drain current I due to avalanche breakdown described above
Since the rapid increase in d increases the load current of the charge pump circuit, the increase in drain current Id due to the avalanche breakdown must be suppressed as much as possible.

[0010]

By the way, miniaturization and high integration of memory cells are performed by shortening the gate length thereof. However, there is a problem that the punch-through current between the source / drain increases as the gate length is shortened.

As one of the techniques for suppressing such an increase in punch through current, the punch through stopper 11 is used.
There is a method of setting a high density of 0. In the memory cell having the p ⁻ type buried diffusion layer 120 as shown in FIG. 12, the well 8 between the source and the drain is formed.
A valley of potential is formed deep inside 1. The distribution of equipotential lines 121 is shown in FIG. The punch-through described above is due to the leak 122 flowing in the valley of the potential.

Well 81 and punch-through stopper 1
When the concentration of 10 is constant, the potential spread between the source / drain tends to increase as the gate length decreases. Therefore, it is necessary to set the concentration of the well 81 and the punch-through stopper 110 to be high in order to suppress the potential increase due to the shortening of the gate length.

However, if the concentration of the punch-through stopper 110 is increased as the gate length is shortened, the drain breakdown voltage BVds is lowered. Here, increasing the concentration of the punch-through stopper 110 causes the drain breakdown voltage BVds to decrease. The higher the concentration of the punch-through stopper 110, the wider the width of the depletion layer between the punch-through stopper 110 and the drain 83 or the source 82. It becomes narrower and the electric field in this region becomes larger.

FIG. 2 is a characteristic diagram showing the relationship between the drain breakdown voltage BVds and the gate length L. This drain breakdown voltage-
The gate length characteristic is, for example, when the control gate 87, the well 81, and the source 82 are grounded, and the drain current Id observed when the potential applied to the drain 83 is increased, is a certain threshold value (for example, 1 μA or more). ) Is obtained for each different gate length L. The flat characteristic in the region where the gate length L is relatively long is determined by the avalanche breakdown that occurs in the impact ionization generation region 112 shown in FIG. In addition, the reduction characteristic of the drain breakdown voltage BVds with the reduction of the gate length L is the source 82.
-Determined by punch through occurring between drains 83. In the drain breakdown voltage-gate length characteristics, the gate length at which the drain breakdown voltage BVds starts to decrease as the gate length L is shortened will be described below as the critical gate length L.
It is called min (Lmin ¹ or Lmin ² ). As is clear from FIG. 2, the higher the concentration of the punch through stopper 110, the shorter the critical gate length Lmin. That is, the critical gate length Lmin ² when the concentration of the punchthrough stopper 110 is relatively high is shorter than the critical gate length Lmin ¹ when the concentration of the punchthrough stopper 110 is relatively low.

In the memory cell of the flash memory, a bias near the drain breakdown voltage BVds is applied when writing or erasing data. Therefore, the critical gate length L
In the memory cell using the gate length Luse shorter than min, when the drain voltage Vd is set near the drain breakdown voltage BVds as shown in FIG. 13, the leak current due to the subthreshold increases. That is,
Originally should be cut off Vg (gate potential) = 0V
Also in this case, a minute leak current flows between the source and the drain.

Therefore, the gate length Luse shorter than the critical gate length Lmin is not used, and in general, the gate length Luse longer than the critical gate length Lmin is used in consideration of the margin of the critical gate length Lmin.

As described above, the factor that determines the critical gate length Lmin is the spread of the potential between the source and the drain. Therefore, in order to shorten the gate length, the spread of the potential between the source and the drain is suppressed. It is necessary to increase the density of the punch through stopper 110. That is, as the concentration of the punch through stopper 110 is increased, the critical gate length Lmin is shortened, so that the gate length Luse used for the memory cell can be shortened.

However, if the density of the punch-through stopper 110 is increased to shorten the gate length L,
The impact ionization (II) current in the impact ionization generation region 112 shown in FIG. 11 increases,
Drain breakdown voltage BV determined by avalanche breakdown
ds decreases. This decrease in drain breakdown voltage BVds causes a decrease in injection efficiency Ig / Id shown in FIG. That is, in FIG. 10, the injection efficiency is lowered at Vd = −6V to −7V, but if the concentration of the punch-through stopper 110 is increased as the gate length is shortened, the region where the injection efficiency is lowered becomes the drain voltage Vd. Shift to the side where the absolute value becomes smaller (left side in FIG. 10). Such a decrease in injection efficiency increases the load on the charge pump circuit, which in turn leads to an increase in chip size.

As described above, the concentration of the punch-through stopper 110 cannot be lowered in order to shorten the gate length, but as a method for suppressing the decrease in implantation efficiency due to impact ionization, the source 82 is used in a general memory cell.
And LDD (Lightly
There is a method called Doped Drain). However,
This method cannot be used in a DINOR type flash memory using p-channel memory cells. This is because the concentration of the BTBT generation region 111 shown in FIG. 11 is 10 ¹⁹ in order to generate a sufficient current by BTBT.
This is because about cm ^-3 is necessary. If the concentration of the source 82 and the drain 83 is reduced as in a general memory cell, the current generated by the BTBT is reduced, and as a result, the injection efficiency is reduced.

FIG. 14 and FIG. 15 show the outline of the reduction of the injection efficiency due to the reduction of the gate length described above. As shown in FIG. 14, in order to achieve the purpose of reducing the gate length, it was thought that the necessity of ensuring the critical gate length Lmin cannot be avoided. As a method for securing the critical gate length Lmin, a technique of increasing the concentration of the punch through stopper 110 can be considered, but as shown in FIG. 15, the leak current due to impact ionization increases, and as a result, BTBT.
The injection efficiency of the hot electrons induced by this is reduced. As another method for securing the critical gate length Lmin, a method in which the source 82 and the drain 83 have an LDD structure can be considered.
BT does not generate a sufficient amount of electrons, and as a result, the injection efficiency of hot electrons is also reduced.

As described above, in the DINOR type flash memory using the p-channel memory cell, in order to shorten the gate length, it is unavoidable that the injection efficiency of hot electrons induced by BTBT cannot be reduced. there were.

It is an object of the present invention to shorten the gate length to achieve higher integration of flash memory.

Another object of the present invention is to shorten the gate length without lowering the injection efficiency of hot electrons induced by BTBT.

[0024]

A nonvolatile semiconductor memory device according to the present invention comprises a plurality of stack gate type memory cells, a plurality of word lines, a main bit line, a sub bit line, a select gate and a source. Including lines and. The plurality of word lines are provided corresponding to the plurality of stack gate type memory cells, and each word line is connected to the control gate of the corresponding stack gate type memory cell. The sub bit line is commonly connected to the drains of the plurality of stack gate type memory cells. The select gate is connected between the main bit line and the sub bit line. The source line is commonly connected to the sources of the plurality of stack gate type memory cells. The gate length of the stack gate type memory cell is set shorter than the critical gate length. Here, the critical gate length means the gate length when the drain breakdown voltage starts to decrease as the gate length is shortened in the drain breakdown voltage-gate length characteristic, which represents the relationship between the drain breakdown voltage and the gate length. Further, the read current flowing between the source / drain of the stacked gate type memory cell selected by the word line at the time of data reading is defined as Ids ^read, and is not selected by the word line at the time of data reading and the data is programmed. ^Let Ids ^{Rleak be the} read leak current flowing between the source and drain of the stack gate type memory cell, ^Nbit be the number of stack gate type memory cells, and M be a predetermined margin factor of 1 or more. The memory device is set so as to satisfy the relational expression Ids ^Rleak <Ids ^read / ^Nbit / M.

In the above nonvolatile semiconductor memory device, the margin factor is preferably set to about 10.

The non-volatile semiconductor memory device preferably further includes opening means for opening the source line when writing data to the stack gate type memory cell.

The nonvolatile semiconductor memory device preferably further includes first back gate applying means for applying a predetermined potential to the source line when writing data to the stack gate type memory cell.

The nonvolatile semiconductor memory device preferably further includes second back gate applying means for applying a predetermined potential to the source line during data reading.

[0029]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.

[First Embodiment] FIG. 1 is a circuit diagram showing a partial configuration of a memory cell array in a DINOR type flash memory according to a first embodiment of the present invention. Referring to FIG. 1, the DINOR type flash memory includes a plurality of stack gate type memory cells MC11 to MC15,
MC21 to MC25 and a plurality of word lines WL1 to WL5
, The main bit line MBL, the sub bit line SBL1,
SBL2, select gates 11 and 12, source line S
L and. The plurality of word lines WL1 to WL5 are provided corresponding to the plurality of stack gate type memory cells MC11 to MC15 or MC21 to MC25. Word line W
Each of L1 to WL5 is connected to the control gate of the corresponding stack gate type memory cell. For example, word line WL1 is commonly connected to the control gates of stack gate type memory cells MC11 and MC21. The sub bit line SBL1 is commonly connected to the drains of the stack gate type memory cells MC11 to MC15.
The sub bit line SBL2 is a stack gate type memory cell M
It is commonly connected to the drains of C21 to MC25. Select gate 11 is connected between main bit line MBL and sub bit line SBL1. Select gate 12 is connected between main bit line MBL and sub bit line SBL2. The source line SL is commonly connected to the sources of the stack gate type memory cells MC11 to MC15 and MC21 to MC25. Although not shown, the memory cell array of the DINOR type flash memory is provided with a plurality of configurations as shown in FIG.

The flash memory further has a source control circuit 13 which opens the source line SL in response to the write enable signal PROG and applies a potential of 0 V to the source line SL in response to the read enable signal READ. Equipped with. The write enable signal PROG is activated when data is written to the memory cells MC11 to MC15 and MC21 to MC25, and the read enable signal READ is activated when data is read from the memory cells MC11 to MC15 and MC21 to MC25.

FIG. 2 is a characteristic diagram showing the relationship between the drain breakdown voltage BVds and the gate length L. As described above, if the concentration of the punch through stopper is increased, a short critical gate length Lmin can be secured, but the injection efficiency of hot electrons induced by BTBT is reduced.
Therefore, the density of the punch through stopper is not set high in the first embodiment.

Memory cells MC11 to MC commonly connected to one sub-bit line SBL1 or SBL2.
A write drain potential Vd ^prog is applied to 15 or MC21 to MC25 during data writing, and a read drain potential Vd ^read is applied during data reading. In general, the absolute value | Vd ^prog | of the write drain potential is larger than the absolute value | Vd ^read | of the read drain potential. Therefore,
The drain breakdown voltage BVds is the write drain potential | Vd ^prog |
Must be larger than

In the first embodiment, the gate length of memory cells MC11 to MC15 and MC21 to MC25 is shorter than the critical gate length Lmin ¹ . Here, in the drain breakdown voltage-gate length characteristic shown in FIG. 2, the drain breakdown voltage BVds starts to decrease as the gate length is shortened.
Is the critical gate length Lmin
^Is one.

FIG. 3 is a characteristic diagram showing the relationship between the drain current (-Id) and the gate potential (-Vg). A gate length longer than the critical gate length is used for this characteristic diagram (L
A conventional characteristic curve (use> Lmin) and a characteristic curve of the first embodiment using a gate length shorter than the critical gate length (Luse <Lmin) are shown. Also,
This characteristic diagram shows the floating gate potential of a memory cell in which data is programmed during data read and the floating gate potential of a memory cell in which data is erased during data read. Has been done. Here, the potential Vfg of the floating gate is expressed by the following equation (1).

Vfg = -α_cg(Vcg + ΔVth) + α_dVd (1) Here, ΔVth is a normal threshold voltage of the memory cell.
Vth, if there is no charge on the floating gate
The threshold voltage of the memory cell in the case of Vth UV
Is expressed by the following equation (2).

ΔVth = Vth−Vth UV (2) Further, α _cg represents the value of the coupling capacitance between the control gate and the floating gate, and α _d represents the value of the coupling capacitance between the drain and the floating gate.

As is apparent from the characteristic curve when a gate length longer than the critical gate length shown in FIG. 3 is used (Luse> Lmin), the data read (Vd) is performed in this case.
= Vread), a read current indicated by A flows in the selected memory cell as a drain current, and a read leak current indicated by A ′ flows in the non-selected memory cell as a drain current. The read leak current indicated by A ′ is sufficiently smaller than the read current indicated by A. In this case, at the time of writing data (Vd = Vpro
The characteristic curve of g) is almost equal to the characteristic curve at the time of data reading (Vd = Vread).

On the other hand, in the first embodiment, as described above, the gate length Lu is shorter than the critical gate length Lmin.
Since se is used, the subthreshold current flowing in the memory cell increases. Therefore, if a gate length shorter than the critical gate length is used (Luse <L
As is clear from the characteristic curve at the time of data reading (Vd = Vread) at (min), the read current Ids ^read flowing in the selected memory cell indicated by B flows in the non-selected memory cell indicated by B ′. Read leak current I
There is a risk that ds ^Rleak will increase to a ^level that cannot be ignored.

When a gate length shorter than the critical gate length is used (Luse <Lmin), data is written (Vd = Vprog) and data is read (Vd = Vprog).
A relatively large amount of leak current flows as compared with Vread). This leak current is not a channel current but a punch-through current flowing inside the substrate (well). On the other hand, when a gate length shorter than the critical gate length is used (Lus
When data is read when e <Lmin (Vd = Vrea)
In d), since the drain potential Vd is lower than that during data writing, extension of the depletion layer from the drain is suppressed, and as a result, a channel current controllable by the gate potential flows between the source and drain.

At the time of writing data in this flash memory, as shown in FIG. 4, the source control circuit 1 in FIG.
3, the source line SL is opened, the main bit line MBL is provided with a drain potential Vd of, for example, −6V, the selected word line WL2 is provided with, for example, + 8V as a control gate potential, and the unselected word line W is selected.
For example, 0V is applied as a control gate potential to L1 and WL3 to WL5. Here, since the select signal SG1 of L (logical low) level is given to the select gate 11 and the select signal SG2 of H (logical high) level is given to the select gate 12, the potential of the main bit line MBL (- 6V) is the sub bit line S
It is given only to BL2 and not to sub-bit line SBL1. Therefore, only the memory cells MC21 to MC25 connected to the sub bit line SBL2 are in the writable state. However, here, + 8V is applied to the word line WL2, and 0 is applied to the other word lines WL1 and WL3 to WL5.
Since V is given, only the memory cell MC22 is selected and the other memory cells MC21, MC23 to MC25 are selected.
Is not selected.

Therefore, data is written only in the selected memory cell MC22, but since the density of the punch-through stopper is not particularly high in the first embodiment, BT is set.
The injection efficiency of hot electrons induced by BT does not decrease. However, the gate length Lus
Since e is set shorter than the critical gate length Lmin, a relatively large write leak current Ids1 due to punch-through occurs in the non-selected memory cells MC21, MC23 to MC25.
^Pleak , Ids3 ^{Pleak to} Ids5 ^Pleak flow. However, since the source line SL is opened in the first embodiment, the potential of the source line SL decreases, for example, 0V → −0.5V. for that reason,
The source potentials of the non-selected memory cells MC21, MC23 to MC25 decrease, and as a result, the leak current between the source and the drain is cut off due to the back gate effect. Therefore, these write leakage currents Ids1 ^Pleak , I
ds3 ^{Pleak to} Ids5 ^Pleak only temporarily flow at the beginning of the write operation. Therefore, the first embodiment
Even if the gate length Luse is shorter than the critical gate length Lmin as described above, the write leak current does not pose a problem.

On the other hand, at the time of reading data from this flash memory, as shown in FIG. 5, source control circuit 13 in FIG. 1 gives source line SL a source potential of, for example, 0 V, and main bit line MBL. For example, -1V is applied as the drain potential. Also here, as in FIG. 4, the potential of the main bit line MBL (-1 V).
Are applied only to the sub-bit line SBL2, and the memory cell M
Only C21 to MC25 can be read.
However, for example, -3V is applied to the word line WL2 as a control gate potential, and the other word lines WL1 and W
For example, 0V is applied to L3 to WL5 as the control gate potential, so that the memory cell MC
22 is selected and the other memory cells MC21 and MC2 are selected.
3 to MC25 are not selected.

Therefore, the read current Ids2 ^read flows in the selected memory cell MC22 and the other memory cell MC2.
1, a read leak current Ids1 is included in MC23 to MC25.
^{Rlea k} , Ids3 ^{Rleak to} Ids5 ^Rleak flow. However, since the source line SL is fixed to 0V at the time of data reading, these read leak currents Ids1 ^Rleak , Ids3 ^Rleak .
The Ids5 ^Rleak is never cut off.

Therefore, the first embodiment is set so as to satisfy the following expression (3).

[0046]

[Equation 1] That is, the sum of the read leak current Idsi ^Rleak flowing in the non-selected memory cell at the time of data reading is set to be sufficiently smaller than the read current Ids ^read flowing in the selected memory cell. The read leak current flowing in the non-selected memory cell in which the data is programmed is larger than the read leak current flowing in the non-selected memory cell in the state in which the data is erased. Considering the worst case where the total sum of the currents is maximum, the read leak current Idsi ^Rleak here flows in the unselected memory cells in the programmed state.

Generally, the read current flowing between the source and the drain at the time of reading data from the selected memory cell is Ids ^read.
The read leak current flowing between the source and drain of the non-selected memory cell in the programmed state at the time of data reading is Id.
s ^Rleak , the number of memory cells connected to one sub-bit line is N bit, and the margin factor is M
Then, this flash memory is set so as to satisfy the following relational expression (4) obtained by modifying the above expression (3).

Ids ^Rleak <Ids ^read / ^Nbit / M (4) Here, the margin factor M is a predetermined value of 1 or more, preferably 10.

Generally, the drain potential (-1 V, for example) during data reading is the drain potential (-6 V) during data writing.
Is lower (absolute value is smaller), the read leak current is smaller than the write leak current. Therefore, it is sufficiently possible to set so as to satisfy the above relational expression (4).

As described above, according to the first embodiment,
Since the gate length is shorter than the critical gate length, the integration degree of the flash memory can be further increased. Further, since the relational expression (4) is set, the read leak current due to punch-through that flows in the non-selected memory cell at the time of data reading despite the gate length being shorter than the critical gate length. Is sufficiently suppressed, and a stable read operation can be performed. Further, since the write leak current due to punch through flowing in the non-selected memory cell at the time of data writing is cut off by the back gate effect, a stable writing operation can be performed. Furthermore, since the concentration of the punch through stopper is not particularly high, the injection efficiency of hot electrons induced by BTBT does not decrease.

[Second Embodiment] FIG. 6 is a circuit diagram showing a partial structure of a flash memory according to a second embodiment of the present invention. Referring to FIG. 6, this flash memory differs from the first embodiment in that the write enable signal PROG is used.
And a back gate application circuit 60 that applies a predetermined potential (for example, -0.5 V) to the source line SL.

In such a flash memory,
Since a predetermined potential (for example, -0.5 V) is applied to the source line SL during data writing, the memory cells MC21 to M21.
This means that a substantially negative potential is applied to the back gate (well) of C25. Therefore, it is possible to reduce the write leak current due to punch-through that flows in the non-selected memory cells at the time of data writing due to the back gate effect.

[Third Embodiment] FIG. 7 is a circuit diagram showing a partial structure of a flash memory according to a third embodiment of the present invention. Referring to FIG. 7, this flash memory differs from the first embodiment in that read enable signal READ
In response to the above, a back gate application circuit 70 for applying a predetermined potential (for example, -0.5 V) to the source line SL is provided.
At this time, in order to set the source-drain voltage to 1 V as in the first embodiment, the drain potential is −1.
It is desirable to apply 5V.

In such a flash memory,
As in the second embodiment, the read gate leakage current due to punch-through can be reduced by the back gate effect.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a partial configuration of a memory cell array in a DINOR flash memory according to a first embodiment of the present invention.

FIG. 2 is a diagram showing drain withstand voltage BVds-gate length characteristics in a memory cell of a flash memory.

FIG. 3 is a diagram showing drain current-gate potential characteristics in a memory cell of a flash memory.

FIG. 4 is a circuit diagram showing an operation at the time of writing data in the flash memory shown in FIG.

5 is a circuit diagram showing an operation at the time of reading data from the flash memory shown in FIG. 1. FIG.

FIG. 6 is a circuit diagram showing a partial configuration of a memory cell array in a DINOR type flash memory according to a second embodiment of the present invention.

FIG. 7 is a circuit diagram showing a partial configuration of a memory cell array in a DINOR type flash memory according to a third embodiment of the present invention.

FIG. 8 is a cross-sectional view showing the structure of a p-channel stack gate type memory cell in a DINOR type flash memory.

9 is a diagram showing drain current-drain potential and gate current-drain potential characteristics in the memory cell shown in FIG.

10 is a diagram showing the relationship between the drain potential and the injection efficiency, which is the ratio of the gate current to the drain current shown in FIG.

FIG. 11 is a sectional view showing the structure of a p-channel stack gate type memory cell having a punch-through stopper.

FIG. 12 is a cross-sectional view for explaining punch-through current flowing in a p-channel stack gate type memory cell.

FIG. 13 is a diagram showing drain current-gate potential characteristics in a stack gate type memory cell.

FIG. 14 is a diagram for explaining a problem associated with reduction in gate length.

FIG. 15 is a diagram showing a relationship between injection efficiency and drain potential for explaining the same problem as in FIG.

[Explanation of reference numerals] MC11 to MC15, MC21 to MC25 Stack gate type memory cells, WL1 to WL5 word lines, MBL
Main bit line, SBL1 and SBL2 sub-bit lines, 11 and 12 select gate, SL source line, critical gate lengths Lmin ¹ , Lmin ² and Ids
1 ^Rleak , Ids3 ^{Rleak to} Ids5 ^Rleak read leak current, Ids2 ^read read current, 60, 70 back gate applying circuit.

Claims (5)

[Claims] 1. A plurality of stack gate type memory cells, provided corresponding to the stack gate type memory cells,
A plurality of word lines each connected to the control gate of the corresponding stack gate type memory cell; a main bit line; a sub bit line commonly connected to the drains of the plurality of stack gate type memory cells; the main bit line and the above A select gate connected between the sub-bit line and a source line commonly connected to the sources of the plurality of stack gate type memory cells, and the gate length of the stack gate type memory cell is a drain breakdown voltage and a gate length. In the drain withstand voltage-gate length characteristic that represents the relationship with, the drain withstand voltage is shorter than the critical gate length when the drain withstand voltage starts to decrease as the gate length is shortened, and the relational expression Ids ^Rleak <Ids ^read / ^Nbit / M (where Ids ^read the data from the stack gate type memory cell selected by the word line A source in the read - shows the read current flowing between the drain, Ids
^Rleak represents a read leak current flowing between the source and drain of the stack gate type memory cell which is not selected by the word line at the time of reading the data and has data programmed therein, and ^Nbit is the number of the stack gate type memory cell. And M is set to satisfy a predetermined margin factor of 1 or more). 2. The nonvolatile semiconductor memory device according to claim 1, wherein the margin factor is set to about 10. 3. The nonvolatile semiconductor memory device according to claim 1, further comprising an opening means for opening said source line when writing data to said stack gate type memory cell. 4. The non-volatile semiconductor according to claim 1, further comprising a first back gate applying unit that applies a predetermined potential to the source line when writing data to the stack gate memory cell. Storage device. 5. The non-volatile semiconductor memory device according to claim 1, further comprising a second back gate applying unit that applies a predetermined potential to the source line when reading the data.