JP4550206B2 - Driving method of nonvolatile semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device having a two-layer gate electrode of a floating gate and a control gate, and a driving method, an operating method, and a manufacturing method thereof.
[0002]
[Prior art]
FIG. 26 is a circuit configuration diagram showing a memory cell array in a conventional nonvolatile semiconductor memory device such as a flash memory, and shows an example of a NOR type flash memory, where WLm−1 to WLm + 1 are word lines, BLn-1 to BLn + 1 are bit lines, and SL is a source line.
[0003]
First, the over-erased state of the flash memory will be described.
A memory cell (hereinafter referred to as a cell) having an array configuration called NOR type or DINOR type has a cell whose threshold Vth (hereinafter referred to as Vth) is in a depletion state (Vth <0) on the same bit line. Then, there is a problem that it becomes impossible to measure Vth of all the cells on the bit line. For example, when the Vth of the BLn / WLm cell corresponding to the circle A in FIG. 26 is in the depletion state, the influence of the BLn / WLm cell is affected even if the Vth of other cells on BLn is in the enhanced state (Vth> 0). Vth cannot be measured (all become 0 V or less).
[0004]
Therefore, when the Vth distribution in the array configuration is examined, cells proportional to the number of cells on the same bit line are determined as Vth <0 as shown in the Vth distribution diagram of over-erasure failure in FIG. Such a depletion state cell can be generated when electrons are accidentally excessively extracted when electrons are extracted from the floating gate in the flash memory.
[0005]
This phenomenon is erroneously described in Yamada et al. In “Self-convergence erasing method for NOR type flash EEPROM using avalanche hot carrier injection” (Reference 1: IEEE Trans. Electron Devices, vol. 43, p. 1937, 1996). It is described as an erasure cell (erotic over erase).
[0006]
Next, the Vth write-back of the overerased cell will be described. Here, returning Vth of the overerased cell to the enhanced state is referred to as write back. Several methods have already been reported for this writeback.
[0007]
First, a method using CHE (Channel Hot Electron) as a method of injecting electrons into a cell in a flash memory is known. Here, writing by CHE refers to a method of injecting high energy electrons, which are accelerated above the barrier height of the oxide film, into the floating gate among channel electrons accelerated by a steep electric field near the drain of the memory cell. .
[0008]
Next, overerased bit write-back using CHE will be described using the cell structure of a conventional NOR flash memory. FIG. 28 is a schematic cross-sectional view of a flash memory cell for explaining a conventional CHE overerase bit write-back, in which 11 is a P-type semiconductor substrate, 12a and 12b are N-channel source and drain regions, respectively. 14 is a floating gate made of polycrystalline silicon or the like, 15 is an insulating film called ONO having a three-layer structure of an oxide film, a nitride film, and an oxide film as a countermeasure against leakage, 16 is a control gate made of polycrystalline silicon or the like, Vs Is a source voltage, Vd is a drain voltage, Vcg is a control voltage, and Vsub is a substrate voltage.
The control voltage Vcg is usually set higher than the drain voltage Vd.
[0009]
In the flash memory using the CHE method, in order to increase the CHE efficiency, a high P + substrate concentration (˜10−10) is provided in the vicinity of the drain. ¹⁸ cm ^-3 Degree) and a dense N + diffusion layer (-10 ²⁰ cm ^-3 Degree). For example, FIG. 29 is a graph showing the distribution of impurities on the channel surface in the vicinity of the drain end in the conventional cell structure. According to this, there is a change in the impurity concentration at the surface layer position P0 where the value of logN falls all at once. In this conventional cell structure, the depletion layer suppresses the expansion only in the P channel substrate region and achieves CHE efficiency. Also in the previous literature 1, the drain injection is As = 5 × 10. ¹⁵ cm ^-2 Under these implantation conditions, the N + diffusion layer concentration after heat treatment is 10 ²⁰ cm ^-3 That's it.
[0010]
Next, the operation will be described.
Writing into the cell is performed by injecting high energy electrons, that is, CHE accelerated above the barrier height of the first gate oxide film 13 among channel electrons accelerated by a steep electric field near the drain into the floating gate. On the other hand, writing back to the cell is possible by setting Vth to the enhanced state for the over-erased cell by using the above CHE method.
[0011]
However, this method has the following problems.
(1) Since it is necessary to select an overerased cell, the circuit configuration becomes complicated.
(2) Since the Vth variation width to be written is different from that of the conventional writing, it is necessary to set a desired voltage for the drain and the gate. In other words, this voltage generally requires a potential arrangement different from the potential arrangement that puts the cell in the write state.
(3) It is necessary to drive the channel current when writing back. (Id to several 10 μA / cell)
[0012]
On the other hand, drain avalanche hot electron (hereinafter abbreviated as DAHE), drain avalanche hot hole (drain avalanche hot hole); A writing back method using a gate current according to DAHH has been reported (refer to Document 1).
[0013]
A cell structure using this write-back method will be described below.
FIG. 30 is a schematic cross-sectional view of a flash memory cell for explaining the conventional overwriting of overerased bits by DAHE / DAHH. In FIG. 30, the device configuration is almost the same as that of the above-mentioned CHE memory cell, but the description thereof is omitted. There is a difference in how to apply an applied voltage to the electrode, and a GND level is applied to Vcg and GND or a negative bias is applied to Vsub.
[0014]
As shown in FIG. 31, the gate current Ig such as DAHH, DAHE, and CHE is observed from the low gate voltage side in the gate voltage region where the channel current flows as shown in FIG. It is known that This state is also described in Document 1 and other documents (for example, Document 2: IEEE Electron Devices Letter, EDL-7, p.561, 1986, Y. Nissan-Cohen, and Document 3: US Patent). No. 5,546,340, Chung-Yu Hu et al.). Here, the DAHE / DAHH gate current refers to a current flowing through the channel, and out of the electron / hole pairs generated in the high electric field region near the drain, the electrons or holes accelerated to the high energy state by the electric field. Can be explained as having been injected into the floating gate.
[0015]
If this DAHH / DAHE is used, the over-erased cell can be written back in a self-convergent manner. The DAHH / DAHE gate current is based on the current flowing through the channel as a seed. Among the electron-hole pairs generated in the high electric field region near the drain, electrons or holes accelerated to a high energy state by the electric field are generated. It is assumed that it has been injected into the floating gate.
[0016]
Hereinafter, evaluation by this write-back method will be described.
As the cell structure, a cell structure having a cross-sectional configuration shown in FIG. FIG. 34 is a graph showing the result of evaluating the write-back by this method in a single cell.
If a cell in which Vth is over-erased to about 0V is left under the conditions of drain voltage Vd = 5V and control gate voltage Vcg = 0V (source voltage Vs = Vsub = GND), the convergence Vth is about 1.75V after about 0.1 sec. Has been written back. That is, in this write-back method, there is no need to select a bit which was a problem in the CHE method. A drain voltage may be applied to the bit lines of the entire array, and the gate voltage may be set to 0 V and left.
[0017]
Further, what is characteristic of this method is that a state having a Vth higher than the convergence Vth also changes to the convergence Vth. That is, as shown in the graph of the gate current characteristic when using the self-convergence method in FIG. 31, DAHE injection (electron injection) occurs in the cell below the convergence Vth, and the floating potential reaches Vg * in the figure. Go down. As a result, the cell Vth is written back to the convergence Vth. On the other hand, DAHH injection (hole injection) occurs in the cell having the convergence Vth or higher, and the floating potential rises to Vg * in the figure. As a result, the cell Vth falls to the convergence Vth. That is, at the convergence Vth, the electron injection by DAHE and the hole injection by DAHH are balanced (both electrons and holes are continuously injected).
[0018]
FIG. 35 is a graph showing the dependency of the drain voltage Vd on the write-back method using the self-convergence method. As the drain voltage decreases from Vd = 6V to 4V, the time required for write-back increases. I understand.
[0019]
FIG. 36 is a graph showing a gate voltage Vg-drain current Id characteristic in a cell that has reached the convergence point, that is, the convergence Vth in the write back method by the self-convergence method. In this figure, even when Vg = 0V. It can be seen that current flows in the rewritten cell. This measurement is performed at Vd = 1V, and a current of several μA / bit flows at the time of actual writing back (when Vd is applied to ˜5V). In addition, referring to FIG. 39, the write-back operation time is 10 ¹ -10 ² In the range of sec, the drain current Id is stably 20 μA (= 2 × 10 ^-Five A) It can be seen that this is flowing, and this clearly shows that current flows at the convergence Vth at the time of writing back.
[0020]
Furthermore, when the entire array is selected instead of selecting the bit line, it is assumed that the array block size is 256 bits (BL) × 2048 bits (WL) = 512 kbits, and the cell current at the convergence Vth is assumed to be 1 μA / bit. However, in this writing back method, a current of about 500 mA flows. In other words, this method has a problem that the drive current during the write-back operation is large.
[0021]
Furthermore, it has also been reported that the channel conductance deteriorates by writing back with a DAHE / DAHH gate current (Reference 3: IEDM '94, p.291). This is because both the electrons and holes continue to be injected through the gate oxide film at the convergence Vth, so that the gate oxide film deteriorates.
[0022]
Moreover, the following prior art is mention | raise | lifted as a reference example.
FIG. 37 is a cross-sectional view of a semiconductor memory device described in Japanese Patent Laid-Open No. 10-144809. In the figure, since the structure where the N ++ region 12bb and the dense P + region 2b are in contact with the gate, electrons and holes generated in a portion surrounded by a circle in the figure are injected into the gate, and FIG. As shown in FIG. 4, the drain disturb characteristic is deteriorated. Here, the drain disturb characteristic refers to a problem that Vth decreases when a drain voltage at the time of CHE writing is applied to a cell in a high Vth state for a long time.
[0023]
As an example of the case where the channel region has no electric field relaxation layer, there is a semiconductor memory device described in JP-A-4-21178. According to this, Vth converges where the DAHE / DAHH gate current is balanced. FIG. 39 is a graph showing current convergence characteristics during the write-back operation corresponding to this. In FIG. 39, the horizontal axis represents time, and the vertical axis represents the amount of current flowing through the channel during the write-back operation, which converges to a convergence value of about 10 μA in about 10 seconds. This is a state in which the DAHE / DAHH gate current is balanced. Show. Furthermore, the gate oxide film was destroyed in about 100 seconds. This is because both electrons and holes are injected into the gate oxide film at the same time, resulting in deterioration of the oxide film and destruction.
[0024]
Next, an erase sequence will be described as an operation method of the nonvolatile semiconductor memory device.
FIG. 33 is a flowchart showing an erase sequence of a conventional NOR flash memory. In the figure, ST11 is a command input step, ST12 is a pre-erase write step, ST13 is an erase step, and ST14 is an erase confirmation step.
[0025]
Next, the operation will be described.
When the command is input in step ST11, all the cells of the block that has been selected for erasure are written in the pre-erase write step ST12 in order to suppress the occurrence of overerased cells. Conventionally, in this erasing sequence, it takes a long time to write before erasing, and it is difficult to shorten the erasing time.
[0026]
For example, it is assumed that a 512 kbit block is configured with 256 bits on the same bit line and 2048 bits on the same word line in a NOR type cell array that performs writing by the CHE method. Assume that writing is performed by selecting 32 bits at a time in writing before erasure. Even if the write time for one time is ˜20 μsec, 2048/32 × 256 × 20 μs = 0.328 sec is required.
[0027]
Therefore, for example, if a chip having a capacity of 1 Mbits is configured in the above-described block configuration, it takes 0.328 sec × 2 = 0.65 sec only after the erase command input after the erase command is input. Regarding the actual erasing time (operation to bring the cell to the low Vth state), although the FN tunnel electric field applied to the oxide film at the time of erasing can be increased to about 0.1 sec, it is excessive. Only writing before erasing to suppress the generation of erasing cells would take nearly six times that time.
[0028]
In the above description, the conventional NOR type flash memory has been described as an example, but the DINOR type flash memory will also be described supplementarily.
FIG. 40 is a schematic cross-sectional view showing a cell structure of a conventional DINOR type flash memory. In FIG. 40, except that 17 is a low concentration N type drain region, that is, an N-drain region, Since it is the same as that of FIG. 28, the same code | symbol shows the same component or an equivalent part, and the description is abbreviate | omitted.
[0029]
Unlike the NOR type using CHE writing, the DINOR type cell structure has the following characteristics.
(1) The DINOR type array configuration may be the same as the NOR type flash memory (see FIG. 26).
(2) Writing is performed in a low Vth state and erasing is performed in a high Vth state.
(3) In the write operation, a positive bias is applied to Vd and a negative bias is applied to Vcg, and electrons are extracted from the floating gate to the drain junction region by an FN tunnel.
(4) In the erase operation, Vcg is positively biased and Vsub is biased, and electrons are injected into the floating gate by the FN tunnel over the entire channel surface.
[0030]
FIG. 42 collectively shows operating voltages in the DINOR type flash memory.
Next, a write sequence will be described as an operation method of the nonvolatile semiconductor memory device. 41 shows a write sequence in the conventional DINOR type flash memory. In the figure, ST21 is a write step, ST22 is a write confirmation step, ST23 is a step for determining whether all bits are completed, and ST24 is a write back step.
As for the operation, since confirmation (verification) is performed for each bit in the DINOR type (ST22), the cell Vth is in a depletion state compared to the NOR type (the NOR type is an overerased state, but the DINOR type is an overwritten state) ) There are few things.
[0031]
[Problems to be solved by the invention]
Since the conventional nonvolatile semiconductor memory device such as a flash memory and the driving method thereof are configured as described above, in the write-back using the normal CHE method in which the gate voltage Vg is higher than the drain voltage Vd, There are problems such as generation of a potential different from that at the time of writing operation, bit selection of over-erased cells, and a large driving current at the time of writing back in order to actively flow channel current.
[0032]
On the other hand, in the write-back using the self-convergence method using the DAHE / DAHH gate current, since the write-back can be performed in a self-convergent manner, there is an advantage that the bit selection is unnecessary and the potential generation can be set almost the same as that in the write. When a voltage drop occurs, the time until convergence is increased (typically, it extends from ~ 0.1 sec to 1 sec), and the drive current at the time of writing back is large because the convergence current flows in the entire array. In addition, there is a problem that the channel conductance of the cell deteriorates.
[0033]
In addition, since the operation method of the conventional nonvolatile semiconductor memory device is configured as described above, it is difficult to shorten the erase time because it takes a long time to write before erasure in order to suppress the occurrence of overerased cells. There were problems such as accidental increase in writing speed and overwriting.
[0034]
The present invention has been made to solve the above-described problems, and can reduce overcurrent and write-back operation time, and can write overerased cells in a self-convergent manner while preventing deterioration of channel conductance. It is an object of the present invention to obtain a nonvolatile semiconductor memory device that can be returned or erased from overwritten cells, and a driving method, operating method, and manufacturing method thereof.
[0035]
[Means for Solving the Problems]
A method of driving a nonvolatile semiconductor memory device according to the present invention includes first and second diffusion layers of a second conductivity type opposed to each other via a first conductivity type channel region on a semiconductor substrate, and a first conductivity type. A transistor having a two-layer gate electrode composed of a floating gate and a control gate formed via a gate insulating film is disposed on the channel region of the first conductivity type, Setting one of the two diffusion layers to the first voltage level, setting the other of the first and second diffusion layers to the second voltage level, and setting the control gate to the first or third voltage level. The step of setting the level, and the potential difference between the first voltage level and the second voltage level being set larger in absolute value than the potential difference between the first voltage level and the third voltage level. Ri, in which a part of the charge flowing through the channel region with respect to the transistor channel current flows and a step of injecting into the floating gate.
[0036]
According to the driving method of the nonvolatile semiconductor memory device according to the present invention, the transistor is arranged, the step of setting the channel region of the first conductivity type to the first voltage level, and one of the first and second diffusion layers To the second voltage level, to set the other of the first and second diffusion layers to the third voltage level, and to set the control gate to the first, second or fourth voltage level And the potential difference between the first voltage level and the second voltage level is determined by the potential difference between the first voltage level and the third voltage level and the potential difference between the first voltage level and the fourth voltage level. Is set to be large in absolute value, so that a transistor in which a channel current flows has a step of injecting a part of the charge flowing in the channel region into the floating gate. .
[0037]
The method of driving a nonvolatile semiconductor memory device according to the present invention is applied to a NOR type or DINOR type flash memory.
[0038]
The nonvolatile semiconductor memory device according to the present invention includes first and second diffusion layers of a second conductivity type facing a surface layer portion of a semiconductor substrate via a channel region of the first conductivity type, and a channel of the first conductivity type Formed between the channel region and at least one of the first and second diffusion layers and the two-layer gate electrode composed of the floating gate and the control gate formed on the region via the gate insulating film A transistor having a second conductivity type electric field relaxation layer is provided, and a diffusion layer adjacent to the electric field relaxation layer does not overlap with the two-layer gate electrode.
[0039]
The nonvolatile semiconductor memory device according to the present invention is formed in a surface layer portion of a first conductivity type semiconductor substrate, and has a first conductivity type region having a higher concentration than the semiconductor substrate, and a first conductivity type in the first conductivity type region. The first and second diffusion layers of the second conductivity type facing each other through the channel region of the mold, and the floating gate and the control gate formed on the channel region of the first conductivity through the gate insulating film And a second conductivity type electric field relaxation layer formed in the first conductivity type region between at least one of the first and second diffusion layers and the channel region. The diffusion layer adjacent to the electric field relaxation layer does not overlap with the two-layer gate electrode.
[0040]
The non-volatile semiconductor memory device according to the present invention is formed in a surface layer portion of a first conductivity type semiconductor substrate and is opposed to the second conductivity type first and second diffusion layers via the first conductivity type channel region. A two-layer gate electrode composed of a floating gate and a control gate formed on the first conductivity type channel region via a gate insulating film, at least one of the first and second diffusion layers, and a channel The second conductivity type electric field relaxation layer formed in the first conductivity type region, the electric field relaxation layer and the diffusion layer adjacent thereto are formed between the region and the first conductivity type region. A transistor having one conductivity type region is provided, and the diffusion layer adjacent to the electric field relaxation layer does not overlap with the two-layer gate electrode.
[0041]
In the nonvolatile semiconductor memory device according to the present invention, the second conductivity type concentration of the electric field relaxation layer is lower than that of the diffusion layer adjacent thereto.
[0042]
In the nonvolatile semiconductor memory device according to the present invention, the transistor is applied to a NOR type or DINOR type flash memory.
[0043]
The method for manufacturing a nonvolatile semiconductor memory device according to the present invention includes a step of forming a first conductivity type region at a predetermined depth at a higher concentration than the substrate in a surface layer portion of a first conductivity type semiconductor substrate, A step of forming a two-layer gate electrode composed of a control gate and a floating gate on the conductive type region through a gate insulating film, and implanting impurities using the two-layer gate electrode as a mask to form a second conductive type in the surface layer portion Forming a diffusion layer, forming an insulating film on the entire surface, then performing anisotropic etching to form a sidewall on the side surface of the two-layer gate electrode, and using the two-layer gate electrode and the sidewall as a mask Forming a part of the diffusion layer in the electric field relaxation layer by performing impurity implantation and forming the first and second diffusion layers of the second conductivity type within a predetermined depth range; Those were example.
[0044]
The method for manufacturing a nonvolatile semiconductor memory device according to the present invention includes a step of forming a two-layer gate electrode composed of a control gate and a floating gate on a first conductivity type semiconductor substrate via a gate insulating film, Impurity implantation using the layer gate electrode as a mask to form a diffusion layer of the second conductivity type in the surface layer portion of the substrate, and an impurity implantation at a predetermined depth higher than the substrate so as to include at least the diffusion layer Forming a first conductivity type region, forming an insulating film on the entire surface, performing anisotropic etching to form a sidewall on the side surface of the two-layer gate electrode, and forming the two-layer gate electrode and the sidewall Impurity implantation is performed using the mask, and the first and second diffusion layers of the second conductivity type are formed within a predetermined depth, so that part of the diffusion layer is an electric field relaxation layer. It is obtained by a step of forming.
[0045]
In the method for manufacturing a nonvolatile semiconductor memory device according to the present invention, the step of forming the first conductivity type region is performed by setting the impurity implantation angle within 30 degrees with respect to the substrate normal.
[0046]
According to an operation method of a nonvolatile semiconductor memory device according to the present invention, first and second diffusion layers of a second conductivity type facing a surface layer portion of a semiconductor substrate through a channel region of the first conductivity type, and a first conductivity A two-layer gate electrode composed of a floating gate and a control gate formed on the channel region of the mold via a gate insulating film, and between the channel region and at least one of the first and second diffusion layers A transistor having a second conductivity type electric field relaxation layer formed; and a diffusion layer adjacent to the electric field relaxation layer does not overlap with the two-layer gate electrode. In the following, a step of confirming that erase or writing has been performed, and a step of setting one of the channel region of the first conductivity type and the first and second diffusion layers to the first voltage level. Setting the other of the first and second diffusion layers to the second voltage level, setting the control gate to the first or third voltage level, the first voltage level and the second voltage level Since the potential difference with the voltage level is set larger in absolute value than the potential difference between the first voltage level and the third voltage level, a part of the charge flowing through the channel region is floated with respect to the transistor through which the channel current flows. Injecting into the gate.
[0047]
According to an operation method of a nonvolatile semiconductor memory device according to the present invention, first and second diffusion layers of a second conductivity type facing a surface layer portion of a semiconductor substrate through a channel region of the first conductivity type, and a first conductivity A two-layer gate electrode composed of a floating gate and a control gate formed on the channel region of the mold via a gate insulating film, and between the channel region and at least one of the first and second diffusion layers A transistor having a second conductivity type electric field relaxation layer formed; and a diffusion layer adjacent to the electric field relaxation layer does not overlap with the two-layer gate electrode. A step of confirming that the channel has been erased or written, a step of setting the channel region of the first conductivity type to the first voltage level, and one of the first and second diffusion layers; Setting the second voltage level; setting the other of the first and second diffusion layers to the third voltage level; and setting the control gate to the first, second or fourth voltage level. The potential difference between the step and the first voltage level and the second voltage level is greater than the potential difference between the first voltage level and the third voltage level and the potential difference between the first voltage level and the fourth voltage level. Since the absolute value is set to be large, a step of injecting a part of the electric charge flowing through the channel region into the floating gate for the transistor through which the channel current flows is provided.
[0048]
The operation method of the nonvolatile semiconductor memory device according to the present invention includes a step of writing in the transistor in order to suppress the occurrence of the overerased transistor prior to the step of checking.
[0049]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described below.
Embodiment 1 FIG.
FIG. 1 is a schematic cross-sectional view showing a cell structure of a nonvolatile semiconductor memory device according to Embodiment 1 of the present invention, and shows an example applied to a NOR type flash memory. FIG. 2 is a partially enlarged view of the circle X in FIG. 1 and shows the impurity profile in the cell structure near the drain of the cell transistor. This flash memory is arranged in a NOR type array configuration and corresponds to that of FIG. 3A to 3D are process diagrams showing a manufacturing procedure of the flash memory of FIG.
[0050]
In the figure, 1 is a P-type semiconductor substrate (semiconductor substrate), 1a is a high-concentration P-type region, that is, a P + region (first conductivity type region), 2b is a high-concentration N-type drain region, that is, an N + drain region, and 2b ' The N + drain region, 2aa, 2bb as the electric field relaxation layer are respectively higher-concentration N-type source, drain region, that is, N ++ source, drain region (first and second diffusion layers), and 3 is the first gate insulating film (gate Insulating film) 4 is a floating gate composed of polycrystalline silicon or the like, 5 is a second gate insulating film which is abbreviated as ONO and has a three-layer structure of an oxide film, a nitride film and an oxide film to prevent leakage , 6 are control gates made of polycrystalline silicon, 7a and 7b are side walls which are insulating films on the source side and the drain side, respectively, and 8 is a resist. These floating gate 4, second gate insulating film 5 and control gate 6 constitute a two-layer gate electrode.
[0051]
A method for manufacturing a flash memory according to Embodiment 1 of the present invention will be described below with reference to FIG.
First, in order to create the structure of the channel region, that is, the P + region 1a, the P concentration in the surface layer of the P-type semiconductor substrate 1 is 1 × 10 5 as shown in FIG. ¹⁸ cm ^-3 Channel doping is performed by ion implantation of boron B or the like. For example, although depending on the conditions of the heat treatment after doping, the implanted boron spreads as a result of the heat treatment to a depth of about 0.4 μm from the surface of the P-type semiconductor substrate 1, and a P + region 1a can be formed. Specifically, boron is 4 × 10. ¹³ cm ^-2 If the above implantation is performed, the P concentration in the P + region 1a is 4 × 10. ¹³ /0.4 μm = 1 × 10 ¹⁸ cm ^-3 It becomes.
[0052]
Next, as shown in FIG. 3B, the floating gate 4 is formed on the P-type semiconductor substrate 1 via the first gate insulating film 3, and the control gate 6 is further interposed via the second gate insulating film 5. To complete a two-layer electrode. Subsequently, in order to form the cell drain structure, as shown in the figure, the resist 8 is patterned, and arsenic As or the like is ion-implanted only on one side of the two-layer electrode to form the N + drain region 2b and heat treatment. In this case, the N + drain region 2b extends to a depth of about 0.2 μm from the surface layer. For example, before forming the sidewalls 7a and 7b in the next process (see FIG. 3B), arsenic As or the like is added 1 × 10 6. ¹⁵ cm ^-2 If injected below, about 5 × 10 ¹⁹ cm ^-3 An N + drain region 2b having a moderate concentration is obtained.
[0053]
Although not shown, only the source side is opened with a resist pattern in the same manner as in the drain side N + implantation step to form the source side N + structure 2a.
Next, as shown in FIG. 3C, an insulating film having a predetermined thickness is formed on these upper surfaces, and when this oxide film is anisotropically etched, side walls 7a and 7b are formed on the side surfaces of the gate electrode. Is done. With respect to this surface structure, as shown in FIG. 3 (d), if high concentration As or the like is ion-implanted, the two-layer electrode and the sidewall serve as a mask to further increase the concentration of N ++ source and drain regions 2aa, 2bb is obtained, and an N + drain region 2b 'as an electric field relaxation layer is obtained adjacent thereto.
[0054]
Thereafter, although not shown, an interlayer insulating film is formed on the entire surface, a part of the interlayer insulating film is opened so as to reach the P-type semiconductor substrate 1 where the N ++ source region 2aa and the drain region 2bb are present, and contact holes are formed. Form. Further, if the source electrode Vs and the drain electrode Vd are formed by depositing a metal film such as aluminum by vapor deposition, sputtering, chemical vapor deposition or the like and patterning with a resist or the like, the flash memory cell according to the present invention is used. The structure is complete.
[0055]
A characteristic part in the cell structure of the flash memory will be described.
1 and 2, it is generally known that an LDD (Lightly Doped Drain) structure may be used in order to suppress hot carrier deterioration (generation of drain avalanche current) of a transistor. . Therefore, in the first embodiment, in a memory cell (hereinafter simply referred to as a cell) of a flash memory in which electronic writing is performed by CHE, the concentration of the N + diffusion layer is near the lower portion of the sidewall of the N + drain region 2b in contact with the P + region 1a. The N + drain region 2b ′ having a decreased value is generated to suppress the generation of drain avalanche, and the concentration of the P + region 1a adjacent to the N + drain region 2b ′ is increased to increase the CHE efficiency.
[0056]
For example, FIG. 5 is a graph showing the impurity distribution on the channel surface in the vicinity of the drain end of the cell structure according to Embodiment 1 of the present invention, and is shown in comparison with the conventional cell structure. In the figure, a is a curve of the conventional cell structure, b is a curve of the cell structure of the present invention, and the surface layer positions P1 to P2 correspond to the lower part of the sidewall 7b (SW region). Here, as the formation of the N + drain region 2b, the arsenic As concentration is set to As <1 × 10. ¹⁵ cm ^-2 The injection amount was suppressed to the extent. As a result, the concentration of the N + drain region 2b under the side wall 7b is 1 × 10. ¹⁹ cm ^-3 The above has been secured, but the conventional 1 × 10 ²⁰ cm ^-3 The setting is low compared to.
[0057]
Further, for the problem that the N + concentration in the N + drain region 2b is lowered, the electric field in the vicinity of the drain is relaxed and the CHE efficiency is lowered, the concentration in the P + region 1a is reduced to the conventional 1 × 10. ¹⁸ cm ^-3 Darker than the following (1 × 10 ¹⁸ cm ^-3 This is avoided.
[0058]
Further, as the cell structure of the NOR flash memory, the concentration of the P + region 1a adjacent in the vicinity of the drain is 1 × 10. ¹⁸ cm ^-3 The concentration of the N + drain region 2b in contact with the P + region 1a is 1 × 10 ²⁰ cm ^-3 It set so that it might become the following. As a result, a feature that the channel current is cut off at the convergence Vth was obtained.
[0059]
Next, the operation of the cell structure of the above invention will be described.
The cell is written by the CHE method, and among the channel electrons accelerated by a steep electric field in the vicinity of the drain, high energy electrons accelerated beyond the barrier height of the first gate insulating film 3 are transferred to the floating gate 4. By injecting into On the other hand, in writing back to the cell, the same drain voltage Vd as that at the time of writing is applied to the bit lines of the entire array, and the gate potential Vcg is held at, for example, the GND level (0 V) (Vs = Vsub = GND). Do.
[0060]
As a result, overerased cells can be written back in a self-convergent manner so that the channel current at the time of convergence is cut off. Further, the back gate potential (negative bias) can be applied to the substrate to increase the CHE writing efficiency (Vs = GND, Vsub <0 V).
[0061]
As described above, since the nonvolatile semiconductor memory device such as the flash memory according to the first embodiment of the present invention has the above-described cell structure, a potential is applied to the entire bit line of the conventional cell array, and all the control gates are provided. The Vth of the cell below the convergence Vth can be selectively written back to the convergence Vth at high speed without having to go through the step of selecting an overerased cell while maintaining the GND level. In addition, since the cell current is cut off in the convergence Vth state, current consumption can be suppressed as Vth converges.
[0062]
Next, a method for erasing the nonvolatile semiconductor memory device according to the first embodiment of the present invention will be described.
FIG. 4 is a flowchart showing an erase sequence by the flash memory. In the figure, ST1 is a command input step, ST2 is an erase step, ST3 is an erase confirmation (verify) step, and ST4 is a write back step.
[0063]
Next, the operation will be described.
When an erase sequence is started and an erase command is input in step ST1, programming before erase is not performed, but erase confirmation step ST3 is entered. After confirming that all bits are erased to a certain Vth or less, write back step ST4 is performed. The erase sequence ends.
[0064]
Here, it should be noted that the cell characteristics are not deteriorated in the write-back step ST4 unlike the conventional write-back using the DAHE / DAHH gate current. In addition, the time required for the write-back step ST4 is about 10 msec. As a result, even if the pre-erase write step ST12, which takes the longest time in the conventional erase operation time, is omitted, the generation of overerased cells is suppressed and the erase time is 0.1 sec (erase) +0.01 msec (write back). ) = 0.11 sec. The effect of shortening the erasing time appears more remarkably as the degree of integration increases (that is, as the number of bits / number of blocks increases), and thus contributes to the improvement of the access speed of the entire apparatus.
Note that it is needless to say that the same erasure time reduction effect as described above can be obtained in the flowchart of FIG. 6 including the pre-erase write step ST12 as shown in FIG.
[0065]
Hereinafter, it will be described with reference to the graph that the cell write-back in the flash memory according to the first embodiment of the present invention is performed only by CHE.
FIG. 7 is a graph showing convergence characteristics and write-back characteristics in the cells of the flash memory according to the first embodiment. In the measurement according to this figure, Vd = 4.5V, Vcg = 0V, Vs = Vsub = GND and the same potential arrangement as the write back by DAHE / DAHH gate current. From this figure, it can be seen that the Vth of the cell in the depletion state is written back to Vth> 2.0 V in about 1 msec.
[0066]
FIG. 8 is a graph showing the result of the write-back measurement with a shorter write-back time than FIG. It can be seen that the write-back time, which took about 0.1 sec in the conventional write-back using the DAHE / DAHH gate current, is reduced to about 0.1 msec, which is about three digits.
[0067]
Furthermore, in the cell write-back according to the first embodiment, unlike the conventional write-back by the DAHE / DAHH gate current, a potential is applied only to the drain, and the gate is held at 0V, unlike the conventional case. The Vth of a cell that is above the convergence Vth does not drop (see FIG. 7). This is because the drain avalanche generation is suppressed and the CHE efficiency is increased in the cell structure according to the first embodiment.
[0068]
FIG. 9 shows the drain voltage dependency in the write-back of this method. Compared with the prior art, high-speed write-back is performed even when Vd = 4V.
FIG. 10 shows an example of writing back when Vd is a low voltage (2 to 4 V).
FIG. 11 is a graph showing the Vg-Vth measurement result in the cell in the write-back convergence state. According to this, it is understood that the channel current is cut off in the converged cell, unlike the case of writing back by the conventional DAHE / DAHH gate current. That is, in the conventional write back by DAHE / DAHH gate current, a current of about 500 mA continues to flow in the 512 kbits array during the write back of about 0.1 sec. However, according to the present invention, the current is cut off as it converges. Is done. As a result, the current consumption is significantly reduced as compared with the conventional case.
[0069]
FIG. 12 is a graph of gate current characteristics when using the above convergence method. Here, Ig represents the gate current in the new cell structure, and Ig ′ represents the gate current in the conventional cell structure. The curve on the gate current Ig side according to the present invention gradually converges after logId / Ig steeply rises from the point Vg ** as the gate voltage Vg increases, and matches the curve of the drain current Id. However, the curve on the side of the gate current Ig ′ in the conventional structure shows that logId / Ig falls to 0 while increasing from the Vg ** point to the Vg * point as the gate voltage Vg increases, and then rises and then decreases slightly. There are mountains and valleys.
[0070]
From this examination result, it is considered that the DAHH / DAHE gate current was suppressed and the CHE efficiency was increased to several stages thanks to the adoption of the cell drain structure. That is, if this structure is used, the energy accelerated component of the subthreshold leakage current flowing in the channel region is injected into the floating gate as the gate current. As a result, the potential of the floating gate is lowered, and the cell Vth converges to a state where the channel is cut off. That is, rewriting is performed with CHE of the subthreshold leakage current.
[0071]
FIG. 13 shows an example of writing back in a 256 kbits array using the cell structure according to the first embodiment. It can be seen that the Vth distribution that caused overerasure after erasure is written back to Vth> 2V or more. That is, the phenomenon in a single cell was also demonstrated in the cell array.
[0072]
As described above, according to the first embodiment, in the cell drain structure, the N + diffusion layer serving as the electric field relaxation layer having a concentration lower than that of the drain N ++ diffusion layer in contact with the high concentration P region is provided. Since the P region includes the N ++ diffusion layer and the N + diffusion layer, the generation of drain avalanche holes and electrons can be suppressed and the CHE efficiency can be improved. As a result, in a nonvolatile semiconductor memory device such as a flash memory having an array configuration, the Vth of cells below the convergence Vth can be selectively written back to the convergence Vth at high speed without having to select overerased cells. The access time of the apparatus is improved.
[0073]
Further, since the cell current is cut off in the convergence Vth state, the current consumption can be suppressed as the Vth converges, so that the power consumption of the entire apparatus can be reduced.
Furthermore, in the above configuration, instead of omitting the pre-erase write step, the write step can be used to speed up the erase sequence, and the avalanche hole / electron can be connected to the control gate via the first insulating film. Therefore, the channel conductance can be prevented from being deteriorated.
Furthermore, since the dielectric breakdown of the tunnel oxide film such as the first insulating film can be prevented, there is an effect that the device life can be improved.
[0074]
Embodiment 2. FIG.
FIG. 14 is a schematic sectional view showing a non-volatile semiconductor memory device according to the second embodiment of the present invention, which is applied to a NOR type flash memory as in the first embodiment. FIG. 15 is a partially enlarged view of the circle Y in FIG. 14 and shows the impurity profile in the cell structure near the drain of the cell transistor. 16A to 16C are process diagrams showing the manufacturing procedure of the flash memory shown in FIG.
In the figure, 1b is a P + pocket region (first conductivity type region) having a high P concentration, and the other components are the same as those in the first embodiment, so the same components are denoted by the same reference numerals and the description thereof is omitted. To do.
[0075]
Hereinafter, a flash memory manufacturing method according to the second embodiment of the present invention will be described with reference to FIGS.
First, as shown in FIG. 16A, the floating gate 4 is formed on the P-type semiconductor substrate 1 through the first gate insulating film 3, and the control gate 6 is further formed through the second gate insulating film 5. Form a two-layer electrode.
Subsequently, in order to form the cell drain structure, as shown in FIG. 16B, the resist 8 is patterned and ions of arsenic As or the like are ion-implanted only on one side of the two-layer electrode to form the N + drain region 2b. Subsequently, boron or the like is ion-implanted to form the P + pocket region 1b.
Furthermore, although not shown, the source side N + structure 2a is formed by opening only the source side region as in the case of forming the drain side N +.
Next, as shown in FIG. 16C, an oxide film having a predetermined thickness is formed on these upper surfaces, and when this oxide film is anisotropically etched, side walls 7a and 7b are formed on the side surfaces of the gate. The When higher concentration As or the like is ion-implanted into this surface structure, the N-layer source and drain regions 2aa and 2bb can be obtained with the two-layer electrode and the sidewalls 7a and 7b as masks, and the electric field can be relaxed. An N + drain region 2b 'as a layer is obtained adjacent to this.
[0076]
Thereafter, as in the case of the first embodiment, contact holes are formed in the formed interlayer insulating film to form the source electrode Vs and the drain electrode Vd, whereby the cell structure of the flash memory according to the present invention is completed. The operation of this cell structure and the contents of the erase sequence of the fresh memory using the same are the same as those in the first embodiment, so that the description thereof is omitted.
[0077]
The feature of the cell structure of this flash memory is almost the same as that of the first embodiment, except that the P + region 1a is formed on the entire surface layer portion of the P-type semiconductor substrate 1 with a high concentration P + region 1a. In contrast, the P + pocket region 1b is generated by selectively increasing the P concentration only in the vicinity of the cell drain. Thereby, the effect of the first embodiment can be obtained without increasing the cell Vth more than necessary.
[0078]
As described above, according to the second embodiment, in addition to the effects of the first embodiment, there is an effect that the apparatus can be stably operated as it is without increasing the cell Vth more than necessary. It is done.
[0079]
Embodiment 3 FIG.
FIG. 17 is a schematic cross-sectional view showing a cell structure of a nonvolatile semiconductor memory device according to Embodiment 3 of the present invention. As an example, this is applied to a DINOR type flash memory. A feature of this structure is that a P + pocket region 1b as shown in the cell structure of the second embodiment is provided on the source side instead of the drain side, and an N + drain region 2b which is an electric field relaxation layer is provided therein. In the point. Therefore, the reference numerals of the drawings and the manufacturing method are omitted. FIG. 18 collectively shows operating voltages in the DINOR type flash memory according to the third embodiment of the present invention.
[0080]
Conventionally, for example, writing back is performed by applying 7 V to the drain Vd and 8 V to the gate Vcd. However, if the cell structure of the present invention is applied, the conventional DINOR type flash memory referred to FIG. In the write sequence, when the cell is over-programmed, that is, in a depletion state, a potential different from the DINOR write / erase is generated in the cell, and the so-called bit selection is not required to write back by CHE. The write-back based on the voltage setting can selectively restore the overwritten cell, that is, return Vth to the enhanced state, by merely applying a potential of about 5 to 6 V to the source for about 10 msec.
[0081]
As described above, according to the third embodiment, only a predetermined voltage is applied to the source of a depletion state cell, that is, an overwritten state cell, in the DINOR type flash memory. There is an effect that can be rescued.
[0082]
Hereinafter, characteristics of the flash memory according to the first to third embodiments of the present invention and those of the conventional example will be compared.
19, 20, 22 and 24 are graphs showing characteristics when a single cell in a conventional flash memory is written back by DAHE / DAHH. FIG. 19 shows Vd = 5V, and FIGS. Vd = 8V, FIG. 22 shows the case where Vd = 6V. On the other hand, FIG. 21, FIG. 23 and FIG. 25 are graphs showing characteristics when CHE applied to a subthreshold leakage current is used for a single cell in the flash memory of the present invention.
[0083]
19 and 20, it can be seen that a potential difference of 6 V or more is necessary to relieve the overerased bit in about 10 msec, and that the state of convergence Vth or more is shifted because the convergence point of DAHE / DAHH is used. . On the other hand, in the case of using the CHE as in the present invention, as shown in FIG. 21, compared to the DAHE / DAHH system, the overerased bit can be relieved at a low voltage (Vd> 4 V) and at a high speed (about 10 msec). It can be seen that, since only electrons are injected, the state above the convergence Vth does not shift.
Next, when FIG. 22 is compared with FIG. 23, it can be seen that the channel conductance deteriorates in the former when it is left in the write-back state, but does not deteriorate in the latter.
Further, comparing FIG. 24 and FIG. 25, it can be seen that in the convergence state, a channel current of about 100 μA level flows in the former, but the channel current is cut off in the latter.
[0084]
【The invention's effect】
As described above, according to the present invention, the method for driving the nonvolatile semiconductor memory device includes the first and second diffusions of the second conductivity type opposed to each other through the first conductivity type channel region on the semiconductor substrate. For the device in which a transistor comprising a layer and a two-layer gate electrode composed of a floating gate and a control gate formed on a channel region of the first conductivity type via a gate insulating film is disposed, Setting one of the conductivity type channel region and the first and second diffusion layers to a first voltage level; setting the other of the first and second diffusion layers to a second voltage level; The step of setting the control gate to the first or third voltage level, and the potential difference between the first voltage level and the second voltage level is more absolute than the potential difference between the first voltage level and the third voltage level; Since the step of injecting part of the charge flowing through the channel region into the floating gate is applied to the transistor through which the channel current flows, the generation of avalanche hot holes and electrons is suppressed. In addition, the channel hot electron (CHE) efficiency can be improved.
[0085]
In addition, since the cell current is cut off in the convergence threshold Vth state, the current consumption can be suppressed as the transistor threshold Vth converges, and the power consumption of the entire device can be reduced.
Further, since avalanche hot holes / electrons are not injected into the control gate through the first insulating film, there is an effect that deterioration of channel conductance can be prevented.
Furthermore, since the dielectric breakdown of the tunnel oxide film such as the gate insulating film can be prevented, the device life can be improved.
[0086]
According to the present invention, for the above-described nonvolatile semiconductor device, the step of setting the channel region of the first conductivity type to the first voltage level, and setting one of the first and second diffusion layers to the second voltage level. A level setting step, a step of setting the other of the first and second diffusion layers to the third voltage level, a step of setting the control gate to the first, second or fourth voltage level; The potential difference between the first voltage level and the second voltage level is determined by the potential difference between the first voltage level and the third voltage level and the potential difference between the first voltage level and the fourth voltage level. Since the absolute value is set to be large, the step of injecting a part of the charge flowing through the channel region into the floating gate is applied to the transistor through which the channel current flows. Since the, in addition to the above effects, there is an effect that can increase the write efficiency of the channel hot electrons.
[0087]
According to the present invention, the driving method of the nonvolatile semiconductor memory device is configured such that the transistor is applied to the NOR type or DINOR type flash memory. Therefore, in the NOR type array configuration, the over-erased transistor cell is selected. Since it is possible to selectively write back the Vth of the transistor cell below the convergence Vth to the convergence Vth at high speed without necessity, or to selectively erase the overwritten transistor cell even in the DINOR type array configuration. The access time of the apparatus is improved.
[0088]
According to the present invention, in the nonvolatile semiconductor memory device, the second conductivity type electric field relaxation layer is formed between at least one of the first and second diffusion layers and the channel region, and the floating gate and the control Since the two-layer gate electrode composed of the gate and the diffusion layer adjacent to the electric field relaxation layer are configured as transistors that do not overlap in the surface layer portion, the impurity concentration of the adjacent diffusion layer is set higher than that of the electric field relaxation layer Thus, even if the write-back potential arrangement by the gate current due to the normal avalanche hot electrons / holes is used, the Vth of the transistor that is higher than the convergence Vth does not decrease, and high-speed write-back can be performed. Since the current is cut off, the power consumption of the device is reduced and the access time is improved. A.
[0089]
According to the present invention, in the nonvolatile semiconductor memory device, the first conductivity type electric field relaxation layer and the first and second diffusion layers are formed in the high concentration first conductivity type region. Is formed between the channel region and the two-layer gate electrode composed of the floating gate and the control gate and the diffusion layer adjacent to the electric field relaxation layer are configured as transistors that do not overlap in the surface layer portion. In addition to the effect, there is an effect of improving the efficiency of writing electrons into the transistor by the electric field relaxation layer.
[0090]
According to the present invention, in the nonvolatile semiconductor memory device, the first conductivity type electric field relaxation layer and at least one of the first and second diffusion layers are formed in the high concentration first conductivity type region. Since the electric field relaxation layer is formed between the channel region and the two-layer gate electrode and the diffusion layer adjacent to the electric field relaxation layer are configured as transistors that do not overlap in the surface layer portion, a part of the channel region is formed. Since only the first conductivity type region can be used, in addition to the above effect, there is an effect that the Vth of the transistor can be reduced to the substrate level.
[0091]
According to the present invention, the nonvolatile semiconductor memory device is configured such that the second conductivity type concentration of the electric field relaxation layer is lower than that of the diffusion layer adjacent to the electric field relaxation layer, thereby suppressing the generation of avalanche hot electrons and holes. In addition, there is an effect of improving the injection efficiency of channel hot electrons into the floating gate.
[0092]
According to the present invention, the non-volatile semiconductor memory device is configured so that the transistor is applied to a NOR type or DINOR type flash memory. Therefore, in the former case, the generation of drain avalanche hot electrons / holes is caused at the time of write back. In addition, the latter has the effect of improving channel hot electron injection efficiency. In the latter case, the overwritten transistor can be selectively erased.
[0093]
According to the present invention, a method for manufacturing a nonvolatile semiconductor memory device includes a step of forming a two-layer gate electrode on a first conductivity type region of a semiconductor substrate, and an impurity implantation using the two-layer gate electrode as a mask. A step of forming a diffusion layer of the second conductivity type in the surface layer portion in one conductive region, a step of forming a sidewall on the side surface of the two-layer gate electrode, and impurity implantation for this, Forming the electric field relaxation layer by separating a part of the diffusion layer by forming the first and second diffusion layers of the second conductivity type in the range, so that the adjacent diffusion described above By setting the impurity concentration of the layer higher than that of the electric field relaxation layer, the Vth of the transistor that is above the convergence Vth can be lowered even in the write-back potential arrangement by the gate current due to normal avalanche hot electrons and holes. You are possible to write back fast not Rukoto, transistor convergence state since the channel current is cut off, the effect of device for improving the reducing power consumption of the device access time can be obtained.
[0094]
According to the present invention, a method for manufacturing a nonvolatile semiconductor memory device includes the steps of forming a two-layer gate electrode on a semiconductor substrate, and implanting impurities using the two-layer gate electrode as a mask, A step of forming a diffusion layer of two conductivity type, a step of implanting impurities at a higher concentration than the substrate so as to include at least this diffusion layer, and forming a first conductivity type region at a predetermined depth; and a two-layer gate A step of forming a side wall on the side surface of the electrode, and an impurity implantation for the step are performed to form the first and second diffusion layers of the second conductivity type within a predetermined depth, whereby the diffusion layer becomes an electric field. In addition to the above effects, there is an effect that the Vth of the transistor can be reduced.
[0095]
According to the present invention, the method of manufacturing the nonvolatile semiconductor memory device is configured such that the step of forming the first conductivity type region is performed with the impurity implantation angle being within 30 degrees with respect to the substrate normal. There is an effect that a device structure in which the expansion of the electric field relaxation layer in the channel region direction is suppressed can be obtained.
[0096]
According to the present invention, the operation method of the non-volatile semiconductor memory device includes the second conductivity type first and second diffusion layers facing each other through the first conductivity type channel region, and the first conductivity type channel region. A transistor comprising a two-layer gate electrode formed thereon, and a second conductivity type electric field relaxation layer formed between at least one of the first and second diffusion layers and a channel region. A step of confirming that the transistor has been erased or written below a predetermined threshold in a device configuration in which the diffusion layer adjacent to the electric field relaxation layer does not overlap with the two-layer gate electrode; and Setting one of the channel region and the first and second diffusion layers to a first voltage level; setting the other of the first and second diffusion layers to a second voltage level; First Or the step of setting the third voltage level, and the potential difference between the first voltage level and the second voltage level is larger in absolute value than the potential difference between the first voltage level and the third voltage level. And the step of injecting a part of the electric charge flowing through the channel region into the floating gate with respect to the transistor through which the channel current flows. In addition to the fact that no deterioration is observed, when the confirmation step is performed for the erase, the pre-erase write step, which has been necessary in the past, becomes unnecessary, so that the erase time can be shortened accordingly. Access speed, while if the step to confirm is done for written, it is Star there is an effect that can be self-focusing to relief even in the depletion state. Moreover, these effects increase as the degree of integration of the device increases.
[0097]
According to the present invention, a method of operating a nonvolatile semiconductor memory device includes: a first conductivity type first diffusion layer, a second diffusion layer facing a surface layer portion of a semiconductor substrate via a channel region of the first conductivity type; A two-layer gate electrode comprising a floating gate and a control gate formed on a channel region of one conductivity type via a gate insulating film, at least one of the first and second diffusion layers, and the channel region; In the device configuration in which the diffusion layer adjacent to the electric field relaxation layer does not overlap with the two-layer gate electrode. A step of confirming that erasing or writing is performed below a threshold value, a step of setting a channel region of the first conductivity type to a first voltage level, a first and a second Setting one of the diffusion layers to the second voltage level, setting the other of the first and second diffusion layers to the third voltage level, and setting the control gate to the first, second, or fourth level. The step of setting to the voltage level and the potential difference between the first voltage level and the second voltage level are the potential difference between the first voltage level and the third voltage level, and the first voltage level and the fourth voltage level. And the step of injecting a part of the electric charge flowing through the channel region to the floating gate for the transistor through which the channel current flows. In addition to the above effect, a negative bias can be applied to the channel region of the first conductivity type, which has the effect of improving the channel hot electron writing efficiency.
[0098]
According to the present invention, the operation method of the nonvolatile semiconductor memory device is configured to include the step of writing in the transistor in order to suppress the occurrence of the over-erased transistor prior to the step of checking, so that the access speed is improved. Although it does not contribute to the above, there is an effect that the occurrence of the overerased transistor can be suppressed more reliably.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view showing a NOR type cell structure of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.
2 is an enlarged view showing the vicinity of the drain of a circle X in FIG. 1. FIG.
FIG. 3 is a process diagram showing a manufacturing procedure of the nonvolatile semiconductor memory device according to the first embodiment of the invention.
FIG. 4 is a flowchart showing an erase sequence of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.
FIG. 5 is a graph showing the impurity distribution on the channel surface in the vicinity of the drain of the nonvolatile semiconductor memory device according to the first embodiment of the present invention;
FIG. 6 is a flowchart showing another erase sequence of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.
FIG. 7 is a graph showing convergence characteristics / write-back characteristics of the nonvolatile semiconductor memory device according to Embodiment 1 of the present invention;
FIG. 8 is a graph showing convergence characteristics / write-back characteristics of the nonvolatile semiconductor memory device according to Embodiment 1 of the present invention;
FIG. 9 is a graph showing the write-back characteristics of the nonvolatile semiconductor memory device according to the first embodiment of the invention.
FIG. 10 is a graph showing the write-back characteristics of the nonvolatile semiconductor memory device according to the first embodiment of the invention.
FIG. 11 is a graph showing a convergence Vg-Vth characteristic in the driving method of the nonvolatile semiconductor memory device according to the first embodiment of the present invention;
FIG. 12 is a graph showing gate current characteristics at the time of convergence in the method for driving a nonvolatile semiconductor memory device according to the first embodiment of the present invention;
FIG. 13 is a graph showing an example of writing back in the method for driving the nonvolatile semiconductor memory device according to the first embodiment of the present invention;
FIG. 14 is a schematic sectional view showing a NOR type cell structure of a nonvolatile semiconductor memory device according to a second embodiment of the present invention.
15 is an enlarged view showing the vicinity of the drain of a circle Y in FIG. 14. FIG.
FIG. 16 is a process diagram illustrating a manufacturing procedure of the nonvolatile semiconductor memory device according to the second embodiment of the present invention;
FIG. 17 is a schematic cross-sectional view showing a DINOR type cell structure of a nonvolatile semiconductor memory device according to a third embodiment of the present invention.
18 is a table showing operating voltage settings of the nonvolatile semiconductor memory device in FIG.
FIG. 19 is a graph showing DAHE / DAHH write-back characteristic evaluation in a conventional nonvolatile semiconductor memory device.
FIG. 20 is a graph showing DAHE / DAHH write-back characteristics in a conventional nonvolatile semiconductor memory device.
FIG. 21 is a graph showing the write-back characteristics of the nonvolatile semiconductor memory device according to the first to third embodiments of the present invention.
FIG. 22 is a graph showing Vg-Id characteristics in a conventional nonvolatile semiconductor memory device.
FIG. 23 is a graph showing a convergence Vg-Id characteristic in the nonvolatile semiconductor memory device according to the first to third embodiments of the present invention;
FIG. 24 is a graph showing Vg-Id characteristics in a conventional nonvolatile semiconductor memory device.
FIG. 25 is a graph showing Id / Is characteristics in the nonvolatile semiconductor memory device according to the first to third embodiments of the present invention.
FIG. 26 is a cell array configuration diagram of a NOR type flash memory.
FIG. 27 is a graph showing a Vth distribution of overerase failure by a conventional nonvolatile semiconductor memory device.
FIG. 28 is a schematic cross-sectional view shown for explaining overerased bit write-back by CHE of a conventional nonvolatile semiconductor memory device.
FIG. 29 is a graph showing the impurity distribution on the channel surface in the vicinity of the drain end in the cell structure of the conventional nonvolatile semiconductor memory device.
FIG. 30 is a schematic cross-sectional view shown for explaining overerased bit write-back by DAHE / DAHH of a conventional nonvolatile semiconductor memory device.
FIG. 31 is a graph showing gate current characteristics when the self-convergence method is used in a conventional nonvolatile semiconductor memory device.
FIG. 32 is a schematic cross-sectional view of a conventional nonvolatile semiconductor memory device.
FIG. 33 is a flowchart showing a NOR-type erase sequence of a conventional nonvolatile semiconductor memory device.
FIG. 34 is a graph showing the write-back by the self-convergence method by the conventional nonvolatile semiconductor memory device.
FIG. 35 is a graph showing the write-back by the self-convergence method by the conventional nonvolatile semiconductor memory device.
FIG. 36 is a graph showing the write-back by the self-convergence method by the conventional nonvolatile semiconductor memory device.
FIG. 37 is an explanatory diagram showing generation of DAHE / DAHH by a conventional nonvolatile semiconductor memory device.
FIG. 38 is a graph showing drain disturb characteristics of a conventional nonvolatile semiconductor memory device.
FIG. 39 is a graph showing current convergence characteristics during a write-back operation by a conventional nonvolatile semiconductor memory device.
FIG. 40 is a schematic cross-sectional view showing a DINOR type cell structure of a conventional nonvolatile semiconductor device.
FIG. 41 is a flowchart showing a DINOR type write sequence of a conventional nonvolatile semiconductor device.
FIG. 42 is a table showing DINOR type operating voltage setting of a conventional nonvolatile semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 P type semiconductor substrate (semiconductor substrate), 1a P + area | region (1st conductivity type area | region), 1b P + pocket area | region (1st conductivity type area | region), 2b, 2b 'N + drain area | region (electric field relaxation layer), 2aa, 2bb N ++ Source and drain regions (first and second diffusion layers), 3 first gate insulating film (gate insulating film), 4 floating gate, 6 control gate, 7a, 7b sidewalls.

Claims (9)

A method for driving a nonvolatile semiconductor memory device, comprising:
The nonvolatile semiconductor memory device includes a transistor,
The transistor
First and second diffusion layers of the second conductivity type opposed to the surface layer portion of the semiconductor substrate via the channel region of the first conductivity type;
A two-layer gate electrode composed of a floating gate and a control gate formed on the channel region via a gate insulating film;
An electric field relaxation layer formed between the second diffusion layer and the channel region and having a second conductivity type concentration lower than that of the adjacent second diffusion layer;
Extracting the charge accumulated in the floating gate;
A channel hot that is part of the charge flowing through the channel region from the first diffusion layer toward the second diffusion layer to return to the enhancement state when the transistor is in a depletion state in the extracting step. Injecting carriers into the floating gate,
In the step of injecting, the magnitude of the gate current due to channel hot carriers injected into the floating gate changes according to the magnitude of the channel current due to the charge flowing through the channel region,
In the injecting step, the magnitude of the channel current decreases exponentially as the floating gate voltage between the floating gate and the semiconductor substrate decreases. Method. The injecting step includes
Setting the channel region of the first conductivity type and the first diffusion layer to a first voltage level;
Setting the second diffusion layer to a second voltage level different from the first voltage level;
Setting the control gate to a third voltage level different from the first voltage level;
The potential difference between the first voltage level and the second voltage level is set larger in absolute value than the potential difference between the first voltage level and the third voltage level. A method for driving a nonvolatile semiconductor memory device. The injecting step includes
Setting the channel region of the first conductivity type and the first diffusion layer to a first voltage level;
Setting the second diffusion layer to a second voltage level different from the first voltage level;
The method for driving a nonvolatile semiconductor memory device according to claim 1, further comprising: setting the control gate to the first voltage level. The injecting step includes
Setting the channel region of the first conductivity type to a first voltage level;
Setting the first diffusion layer to a second voltage level different from the first voltage level;
Setting the second diffusion layer to a third voltage level different from any of the first and second voltage levels;
Setting the control gate to a fourth voltage level different from any of the first and second voltage levels;
The potential difference between the first voltage level and the third voltage level is set larger in absolute value than the potential difference between the first voltage level and the fourth voltage level. A method for driving a nonvolatile semiconductor memory device. The injecting step includes
Setting the channel region of the first conductivity type to a first voltage level;
Setting the first diffusion layer to a second voltage level different from the first voltage level;
Setting the second diffusion layer to a third voltage level different from any of the first and second voltage levels;
The method for driving a nonvolatile semiconductor memory device according to claim 1, further comprising: setting the control gate to the second voltage level. 6. The method for driving a nonvolatile semiconductor memory device according to claim 1 , wherein the transistor is applied to a NOR flash memory. 6. The method for driving a nonvolatile semiconductor memory device according to claim 1 , wherein the transistor is applied to a DINOR type flash memory. After withdrawing above and, prior to the step of the injection, the threshold value of the transistor further comprises a step of confirming that is below a predetermined threshold value, any one of the preceding claims A driving method of the nonvolatile semiconductor memory device according to the above. 9. The method of driving a nonvolatile semiconductor memory device according to claim 8 , further comprising a step of injecting charges into the floating gate in order to suppress generation of a depletion state transistor before the extracting step.

Images