JPH09102198A - Semiconductor memory device and control method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a reverse operation which has a high speed as a whole and suppresses memory cell off-leakage current by changing an operation unit to perform a reverse operation. SOLUTION: By setting both batch reverse control gates RVG 00 and RVG 01 to a logic voltage 'H', the memory cells of all bit lines of memory cell array block BLKn are connected with a reverse voltage supply circuit DVS 00, and an entire batch reverse operation is performed. When either of the batch reverse control gate RVG 00 and RVG 01 is made to a logic voltage 'H', the memory cell in the even number of memory cell array blocks BLKn or the pit line of the odd number is connected with the reverse voltage supply circuit DVS 00, and a partial batch reverse operation is performed. Further, when one of column selection gates CG 0-CG 63 is made to a logic voltage 'H', the selected bit line is connected with the reverse voltage supply circuit DVS 01, and a line reverse operation is performed on the memory cell connected with the bit line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a flash memory.

[0002]

2. Description of the Related Art A flash memory is a memory in which information can be rewritten by electrically erasing and writing. The memory cell can be configured with one transistor, and all or blocks of the memory cell can be electrically erased collectively. In the flash memory, the batch erasing function can shorten the data rewriting time.

13 to 16 show sectional structures of the flash memory cell in each operating state. Here, a field effect transistor having a two-layer gate structure formed on a P-type silicon substrate SUB as a flash memory cell is shown. This field effect transistor comprises a floating gate FG, a control gate CG, a source S and a drain D.

Writing to the memory cell is performed by injecting hot electrons generated near the drain into the floating gate FG to raise the threshold value, as shown in FIG. At this time, for example, the potential of the control gate CG is 6V, the potential of the drain D is 5V, and the potentials of the source S and the substrate SUB are 0V. As shown in FIG. 14, erasing of memory cells is performed by FN (Fowler Nordheid).
n) The tunnel current is used to extract charges from the floating gate FG to the source S to lower the threshold value. At this time, for example, the control gate CG and the substrate SUB are at ground potential 0V, the drain D is open, and the source S potential is 12V. If this erasing operation is performed for a long time, it will be in an over-erased state, and the memory cell transistor will remain on even if the potential of the control gate CG is set to 0V.

The reverse described below eliminates this over-erased state. As shown in FIG. 15, the memory cell is reversed by injecting hot electrons generated in the vicinity of the drain into the floating gate FG to raise the threshold value, as in writing. At this time, for example, the potential of the control gate CG is 0 V and the drain D is
Is 5V, the potential of the source S and the substrate SUB is 0V
It is.

At the beginning, since the memory cell is in the over-erased state, current flows in the ON state even when the control gate CG is 0V. When hot electrons generated near the drain D are injected into the floating gate FG, the threshold value gradually approaches 0 V from a negative voltage. And the threshold is 0
At about V, no current will flow through the memory cell and hot electrons will not be generated.
It does not rise above V and the over-erased state is resolved.

As shown in FIG. 16, the reading of the memory cell is performed by setting the control gate CG to 5V, the source S and the substrate SUB to ground potential 0V, and the drain D potential to 1V, for example. It is determined whether the data is 0 or 1 depending on whether or not the current flows from the drain to the memory cell. When negative charges are accumulated in the floating gate FG, no current flows in the memory cell. The data at this time is set to 0. On the other hand, when negative charges are not stored in the floating gate FG, current flows in the memory cell. The data at this time is 1.

In the conventional example shown here, the over-erase state is eliminated by reversing the memory cell, and in the read state, the on-current flowing in the memory cell in the erased state and the off-leakage current flowing in the memory cell in the written state. It is possible to increase the current difference between

FIG. 17 shows the threshold value of the memory cell transistor according to the above operation. Further, FIG. 18 shows the relationship between the reverse time and the memory cell off-leakage current in the reverse operation. It can be seen from FIG. 18 that when the reverse time is lengthened, the memory cell off-leakage current is reduced but is saturated at a certain value.

FIG. 19 shows a memory cell array block BL.
The circuit block diagram of Kn is shown. FIG. 20 shows a circuit configuration diagram of the entire memory device in which four memory cell array blocks of FIG. 19 are arranged. FIG. 21 shows the control signal timing of the reverse operation of the entire circuit of FIG.

This conventional memory device is composed of four memory cell array blocks BLK0 to BLK3, and a reverse operation is sequentially performed on each block. The circuit of FIG. 17 will be briefly described. WL0 to WL255 are word lines, BL0 to BL63 are bit lines, CG0 to CG6
3 is a column select gate, DL is a data line, RVG00 is a collective reverse control gate, SC00 is a source control gate, SOU00 is a common source node, VSS is a ground voltage, SA is a sense amplifier circuit, DVS00 is a reverse voltage supply circuit, and Qn is N-channel type MOS transistor,
Qm is a memory cell transistor.

The drains of memory cells on different word lines are connected to one bit line, and the sources of memory cells on the same word line are connected to one common source node SOU00. The common source node SOU00 is connected to the ground voltage VSS via the N-channel MOS transistor Qn whose gate is the source control gate SC00. Each bit line is connected to a reverse voltage supply circuit DVS00 via an N-channel MOS transistor Qn which is a collective reverse control gate RVG00 having a common gate.

Each bit line has an N-channel type M whose gates are column selection gates CG0 to CG63, respectively.
It is connected to the data line DL via the OS transistor Qn, and the data line DL is further connected to the sense amplifier circuit SA. In the reverse operation, the collective reverse control gate RVG00 is set to the logical voltage “H”, and the bit lines BL0 to BL0
This is performed by supplying a reverse voltage from the reverse voltage supply circuit DVS00 to BL63.

As shown in FIG. 21, the collective reverse control gates RVG00 to RVG30 are sequentially set to the logic voltage "H", whereby the memory cell array block BL of FIG.
Reverse operation is performed for K0 to BLK3. By setting the collective reverse control gates RVG00 to RVG30 to the logic voltage "H" at the same time, the reverse operation may be simultaneously performed on the entire device.

[0015]

The inventor has found that the following problems occur when all the flash memory cells or all of a certain memory cell array block are reversed at once. That is, a current flows from the drain to the source collectively in all the memory cells, and a large current flows as a whole, so that the resistance component forming the source node causes a voltage drop and the source potential rises. As the potential of the source rises, the voltage difference between the drain and the source of the memory cell becomes smaller, and it becomes more difficult for current to flow than when the potential of the source does not rise. When the current does not flow easily, the generation of hot electrons is reduced and the reverse operation becomes inefficient. That is, the reverse operation time for suppressing the memory cell off-leakage current becomes long, or the memory cell off-leakage current cannot be suppressed sufficiently.

An object of the present invention is to provide a semiconductor memory device (flash memory) capable of solving the above problems and a control method thereof.

[0017]

A semiconductor memory device according to the present invention includes a memory cell array in which a plurality of flash memory cells sharing a source are arranged in a matrix, and a reverse voltage for applying a voltage to the drain of the flash memory cells. Applying means, dividing means for dividing the plurality of drains of the flash memory cell into a plurality of groups, and selecting some groups from the plurality of groups and connecting the reverse voltage applying means to the groups at the same time. And a selecting means for performing the selection.

In the method for controlling the semiconductor memory device according to the present invention, the reverse operation is performed in a plurality of times, and the number of groups selected by the selection means is sequentially decreased. That is, initially, the reverse operation is performed on many groups at the same time, and the number of selected groups is sequentially decreased. For example, the memory cell off-leakage current can be sufficiently suppressed in a short time by three reverse operations including a full batch reverse operation, a partial batch reverse operation, and a line reverse operation.

A semiconductor memory device according to another structure of the present invention includes a plurality of memory cell arrays in which a plurality of flash memory cells sharing a source are arranged in a matrix. A reverse voltage applying means for applying a voltage to the drain of the flash memory cell in each memory cell array; a dividing means for dividing the plurality of drains of the flash memory cell into a plurality of groups;
A selecting circuit for selecting some of the plurality of groups and connecting the reverse voltage applying circuit to the groups at the same time; and a control circuit for simultaneously selecting the selecting circuits of the plurality of memory cell arrays. I have it.

In this way, the respective groups of the plurality of memory cell arrays are simultaneously selected and the reverse operation is performed. By performing the reverse operation in parallel with respect to each memory cell array block, the memory cell off-leakage current can be sufficiently suppressed without increasing the reverse operation time as a whole even if the number of memory cell array blocks increases.

Further, it is preferable that the group division in the memory cell array is performed so that the rise of the source potential is minimized regardless of which group is selected. Also,
If the source node is used as the ground voltage source of the word line drive means for controlling the gate of the flash memory cell, the potential of the word line also rises in accordance with the amount of increase in the potential of the source.
As a result, the reverse operation is facilitated by the hot electrons generated. Therefore, the reverse operation can be performed at a higher speed, and the memory cell off-leakage current can be sufficiently suppressed.

In a semiconductor memory device according to another structure of the present invention, a word line connected to a gate of a flash memory cell and a bit line connected to a drain of the flash memory cell are shared in the word line direction. And a source voltage source, the source of the flash memory cell is arranged in a matrix, and the source and the source voltage source are shared in the word line direction and select the word line. Connected selectively by signal. By selectively connecting the source and the source voltage source shared in the word line direction with a signal for selecting the word line, it is possible to reduce the influence of the off-leak current of the memory cell of the non-selected word line.

Preferably, by configuring the shared source to be selected by a plurality of word lines,
It is possible to reduce the influence of the off-leakage current of the memory cell of the non-selected word line with a small layout area. Also,
It is preferable that the word line is composed of a first wiring layer that constitutes the gate of the flash memory cell and another second wiring layer, and the shared source is connected by the second wiring layer. For example, by delaying the word line signal and lowering the resistance of the source signal line with the second wiring layer having a low resistance, it is possible to reduce the reverse operation time and the influence of the off leak current of the memory cell.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 shows a memory cell array block BLK.
It is a circuit block diagram of n. FIG. 2 is a control signal timing diagram for the reverse operation of the circuit of FIG. FIG. 3 is a relationship diagram between the reverse time and the memory cell off-leakage current in the reverse operation.

The circuit diagram of FIG. 1 will be briefly described. W
L0 to WL255 are word lines, BL0 to BL63 are bit lines, CG0 to CG63 are column selection gates, DL is a data line, RVG00 to RVG01 are collective reverse control gates, SC00 is a source control gate, SOU00 is a common source node, and VSS is Ground voltage, SA is a sense amplifier circuit, DVS00 and DVS01 are reverse voltage supply circuits, Qn is an N-channel MOS transistor, and Qm is a memory cell transistor.

The drains of memory cells on different word lines are connected to one bit line, and the sources of memory cells on the same word line are connected to one common source node SOU00. The common source node SOU00 is connected to the ground voltage VSS through the N-channel MOS transistor Qn whose gate is the source control gate SC00.
Each bit line has an N-channel MOS transistor Qn whose gate is a common batch control gate RVG00.
Or collective reverse control gate RVG0 with common gate
It is connected to the reverse voltage supply circuit DVS00 via the N-channel type MOS transistor Qn which is 1.

Each bit line has an N-channel type M whose gates are column selection gates CG0 to CG63, respectively.
The data line DL is connected via the OS transistor Qn, and the data line DL is further connected to the sense amplifier circuit SA and the reverse voltage supply circuit DVS01. The reverse operation of this embodiment includes the following three reverse operations.

Collective reverse control gates RVG00 and RV
By setting both G01 to the logical voltage "H", the memory cells of all the bit lines of this memory cell array block BLKn are connected to the reverse voltage supply circuit DVS00 and the all-at-all reverse operation is performed. Further, by setting only one of the collective reverse control gates RVG00 and RVG01 to the logic voltage "H", the memory cells of the even or odd bit lines in this memory cell array block BLKn are connected to the reverse voltage supply circuit DVS00. Then, the partial batch reverse operation is performed. Further, by selecting one of the column selection gates CG0 to CG63 and setting it to the logic voltage "H", the selected bit line is connected to the reverse voltage supply circuit DVS01 and the memory cell connected to the bit line is connected. A line reverse operation is performed.

FIG. 2 shows a timing chart when the above-described three reverse operations, that is, the full batch reverse operation, the partial batch reverse operation, and the line reverse operation are performed in this order. The memory cell off-leakage current cannot be sufficiently suppressed by only the all-at-all reverse operation as described as the problem of the conventional technique (see the curve 31 in FIG. 3). On the other hand, in the line reverse operation, the memory cell off-leakage current can be sufficiently suppressed as shown by the curve 32 in FIG. Instead, since the reverse operation is performed for each bit line, it takes a long time to sufficiently suppress the initial memory cell off-leakage current.

Therefore, in the present embodiment, by using the above three reverse operations, the initial memory cell off-leakage current is performed at high speed by the full batch reverse operation, then by the partial batch reverse operation, and finally by the line reverse operation. By performing a series of reverse operations of sufficiently suppressing the memory cell off-leakage current, it is possible to realize high speed and sufficiently suppress the memory cell off-leakage current as shown by a curve 33 in FIG.

Although the present embodiment is an example using three reverse operations, the reverse operation region and the like can be changed according to the reverse characteristics of the device, the memory cell array block size, and the source resistance.

(Second Embodiment) FIG. 4 shows an overall circuit configuration in which four memory cell array blocks BLK0 to BLK3 shown in FIG. 1 are arranged. FIG. 5 shows the timing of control signals in the reverse operation of the entire circuit of FIG. CG0 to CG
Reference numeral 255 is a column selection gate, and RVG00 to RVG31 are collective reverse control gates.

The operation of the second embodiment is the same as the operation of one memory cell array block shown in the first embodiment, but four memory cell array blocks BLK0 to BLK3.
Are performed in parallel with respect to. Similar to the first embodiment, the reverse operation has the following three reverse operations.
Collective reverse control gates RVG00, RVG01, RV
G10, RVG11, RVG20, RVG21, RVG
30 and RVG31 are all set to the logic voltage "H", so that the memory cell array blocks BLK0 to BLK3
The memory cells of all the bit lines can be collectively reverse-operated.

The collective reverse control gate RVG0
0, RVG10, RVG20 and RVG30, or RVG01, RVG11, RVG21 and RVG
By setting the four collective reverse control gates of one of the groups 31 to the logical voltage “H”, the memory cells of the even or odd bit lines of the memory cell array blocks BLK0 to BLK3 can be collectively reversed.

The column selection gates CG0 to CG6 are also provided.
3, CG64 to CG127, CG128 to CG191,
By selecting each one of CG192 to CG255 and setting it to the logic voltage "H", the memory cell of the selected bit line can be subjected to the line reverse operation.

In the second embodiment, the reverse operation is performed in parallel for each memory cell array block, and even if the number of memory cell array blocks increases, the memory cell off-leak current is sufficiently increased without increasing the reverse operation time as a whole. The suppressing operation can be realized.

(Third Embodiment) FIG. 6 shows a circuit configuration of the memory cell array block BLKn. 7 shows the control signal timing of the reverse operation of the circuit of FIG. 6 of FIG.

The circuit diagram of FIG. 6 will be briefly described. W
L0 to WL255 are word lines, BL0 to BL63 are bit lines, CG0 to CG63 are column selection gates, DL is a data line, RVG00 to RVG03 are partial batch reverse control gates, SC00 is a source control gate, SOU00 is a common source node, and VSS. Is a ground voltage, SA is a sense amplifier circuit, DVS00 is a reverse voltage supply circuit, Qn is an N-channel MOS transistor, and Qm is a memory cell transistor.

The drains of memory cells on different word lines are connected to one bit line, and the sources of memory cells on the same word line are connected to one common source node SOU00. The common source node SOU00 is connected to the ground voltage VSS at two points via the N-channel MOS transistor Qn whose gate is the source control gate SC00. Every other four bit lines, the partial batch reverse control gates RVG00 to RV have a common gate.
It is connected to the reverse voltage supply circuit DVS00 through the N-channel type MOS transistor Qn which is G03. Further, each bit line is connected to the data line DL via the N-channel MOS transistor Qn whose gates are the column selection gates CG0 to CG63, and the data line DL is connected to the sense amplifier circuit SA.

The reverse operation of this embodiment is similar to the first embodiment in that the partial batch reverse control gate RVG00 is used.
This is performed by setting all of RVG03 to logic voltage "H". The memory cells of all the bit lines of the memory cell array block BLKn have the reverse voltage supply circuit DVS00.
Is connected to and all reverse operations are performed. Also, by selectively setting a part of the partial batch reverse control gates RVG00 to RVG03 to the logic voltage "H", the bit line of 1/4 or 1/2 or 3/4 of the memory cell array block BLKn. The memory cell of is connected to the reverse voltage supply circuit DVS00 and the partial batch reverse operation is performed.

The timing of the partial batch reverse operation is shown in FIG.
Is shown in Partial batch reverse control gate RVG0
0 to RVG03 are sequentially set to the logical voltage "H", and the memory cell array block BLKn is reversely operated by 1/4.

Here, the feature of the third embodiment resides in that every four bit lines controlled by the same control gate are equally formed. For example, when only the partial batch reverse control gate RVG00 is set to the logic voltage "H", since the common source node SOU00 has a parasitic resistance, the ground voltage VSS is supplied through the common source node SOU00.
Electric current flows to the part. As a result, the potential rises as the source of the memory cell farther from the ground voltage VSS and the parasitic resistance of the common source node SOU00 is larger. That is, the source of the memory cell on the bit line BL32 has the largest potential rise.

This increase in the potential of the source hinders the high speed of the reverse operation and the sufficient suppression of the off leak current of the memory cell. Therefore, no matter which partial batch reverse control gates RVG00 to RVG03 are selected, the bit lines on which the reverse operation is performed are evenly arranged so that the maximum value of the source potential rise is almost the same. The arrangement of the bit lines so that the maximum value of the source potential rise is almost the same is not limited to the arrangement of this embodiment. Further, like the first embodiment, it is also possible to connect the reverse voltage supply circuit to the data line DL and use it in combination with the line reverse operation for selecting the column selection gates CG0 to CG63.

With the arrangement of the bit lines of the third embodiment, the partial batch reverse operation can be performed at a higher speed, and the memory cell off-leakage current can be sufficiently suppressed. (Fourth Embodiment) FIG. 8 shows a memory cell array block BLK.
The circuit structure of n is shown. The figure shows the relationship between the reverse time and the memory cell off-leakage current in the reverse operation. FIG.
0 shows the relationship between the reverse time and the source voltage in the reverse operation.

The circuit diagram of FIG. 8 will be briefly described. W
L0 to WL255 are word lines, BL0 to BL63 are bit lines, CG0 to CG63 are column select gates, DL is a data line, RVG00 is a collective reverse control gate, and SC0.
0 is a source control gate, SOU00 is a common source node, VSS is a ground voltage, SA is a sense amplifier circuit, DV
S00 and DVS01 are reverse voltage supply circuits, Qn
Is an N-channel MOS transistor, and Qm is a memory cell transistor.

The drains of memory cells on different word lines are connected to one bit line, and the sources of memory cells on the same word line are connected to one common source node SOU00. The common source node SOU00 is connected to the ground voltage VSS via the N-channel MOS transistor Qn whose gate is the source control gate SC00. Each bit line has an N-channel MOS transistor Qn whose gate is a common reverse control gate RVG00 or a common reverse control gate RV whose gate is common.
It is connected to the reverse voltage supply circuit DVS00 through the N-channel type MOS transistor Qn which is G01.

Further, each bit line is an N-channel type M whose gates are column selection gates CG0 to CG63, respectively.
It is connected to the data line DL via the OS transistor Qn, and the data line DL is further connected to the sense amplifier circuit SA. Further, the word line drive circuit 81 is an N-channel type MOS whose gate signals are the control signals WC0 to 255.
Transistor Qn and P-channel MOS transistor Q
p. The source of the N-channel type MOS transistor Qn is connected to the common source node SOU00 as a ground voltage source. Reverse operation is first
The same operation as in the above embodiment is performed.

The feature of the fourth embodiment is that the ground voltage source of the word line drive circuit 81 is connected to the common source node SOU00. According to this configuration, when the potential of the source is increased by the reverse operation, the potential of the word line is also increased according to the amount of increase in the potential of the source, and the current easily flows through the memory cell. Reverse operation becomes easier.

As the reverse operation progresses, it becomes difficult for current to flow in the memory cell, the rise in the potential of the source is reduced, and the potential of the word line becomes the ground voltage. That is, the reverse operation can be performed at a higher speed, and the memory cell off-leak current can be sufficiently suppressed. FIG. 9 shows the relationship between the reverse time and the memory cell off-leakage current in comparison between this embodiment and the conventional example. FIG. 10 shows the relationship between the reverse time and the source voltage similarly compared.

(Embodiment 5) The entire circuit configuration shown in FIG. 11 is almost the same as that of the first embodiment. The feature of this embodiment is that the source and the source voltage source shared in the word line direction are selectively connected by a signal for selecting the word line. As a result, the influence of the off-leakage current of the memory cells on the non-selected word line can be reduced. Also, by configuring the shared source to be selected by a plurality of word lines, the layout area is reduced,
The word lines and sources are connected by a low resistance wiring layer.

In the circuit diagram of FIG. 11, R0 to R63 are row selection signals, and ΦW0 to ΦW3 are low boost selection signals. In the layout diagram of FIG. 12, 1 is an element isolation region, 2 is a word line forming a control gate of a memory cell transistor, 3 is a first aluminum wiring layer forming a bit line, and 4 is a word line forming a word line. Reference numeral 2 is an aluminum wiring layer, 4B is the same wiring layer as 4 constituting the source line, 5 is a contact to the wiring layer 3 and its lower layer, and 6 is a contact to the wiring layer 4 and its lower layer.

In the fifth embodiment, the sources of the four word lines WL0 to WL3 are shared. For example, when the low level selection signal R0 is selected by the logical voltage “H”,
The shared source line is connected to the ground voltage source VSS. Further, one of the low-level boost selection signals ΦW0 to ΦW3 is selected and boosted, and the word line corresponding thereto is selected. In the layout diagram of FIG. 12, there is a second aluminum wiring 4 as a backing wiring of a word line 2 which constitutes a control gate of a memory cell transistor formed of, for example, polysilicon, and the source line is formed in this same wiring layer. doing. That is, one source line is formed for each of the four word lines forming the control gate of the memory cell transistor. Five second aluminum wirings are formed for the four word lines formed of polysilicon.

With such a structure, the resistance of the signal line can be reduced, and the influence of the off-leak current of the memory cell of the non-selected word line can be reduced with a small layout area. As a result, high speed operation and low voltage operation can be performed.

[0054]

As described above, according to the semiconductor memory device of the present invention, by changing the driving unit of the reverse operation such as the batch reverse operation, the partial batch reverse operation, and the bit line reverse operation, the overall high speed operation can be achieved. In addition, the reverse operation that sufficiently suppresses the memory cell off-leakage current is realized, and the low voltage operation is realized.

[Brief description of the drawings]

FIG. 1 is a memory cell array circuit diagram of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is an operation timing chart of the semiconductor memory device of FIG.

3 is a diagram showing a relationship between a reverse time and a memory cell off-leakage current in a reverse operation of the semiconductor memory device of FIG.

FIG. 4 is a block configuration diagram of a memory cell array of a semiconductor memory device according to a second embodiment of the present invention.

5 is an operation timing diagram of the semiconductor memory device of FIG.

FIG. 6 is a memory cell array circuit diagram of a semiconductor memory device according to a third embodiment of the present invention.

7 is an operation timing chart of the semiconductor memory device of FIG.

FIG. 8 is a memory cell array circuit diagram of a semiconductor memory device according to a fourth embodiment of the present invention.

9 is an operation timing chart of the semiconductor memory device of FIG.

10 is a diagram showing a relationship between a reverse time and a source voltage of a memory cell in a reverse operation of the semiconductor memory device of FIG.

FIG. 11 is a memory cell array circuit diagram of a semiconductor memory device according to a fifth embodiment of the present invention.

12 is a layout diagram of a memory cell array of the semiconductor memory device of FIG.

FIG. 13 is a sectional view for explaining a write operation to a memory cell of a flash memory.

FIG. 14 is a sectional view for explaining an erase operation of a memory cell of a flash memory.

FIG. 15 is a sectional view for explaining a reverse operation of a memory cell of a flash memory.

FIG. 16 is a sectional view for explaining a read operation of a memory cell of a flash memory.

FIG. 17 is a diagram showing threshold values of memory cell transistors in each operation of the flash memory.

FIG. 18 is a diagram showing the relationship between the reverse time and the memory cell off-leakage current in the reverse operation of the conventional flash memory.

FIG. 19 is a memory cell array circuit diagram of a conventional flash memory.

FIG. 20 is a block configuration diagram of a memory cell array of a conventional flash memory.

FIG. 21 is an operation timing chart of a conventional flash memory.

[Explanation of symbols]

1 element isolation region 2 word line constituting control gate of memory cell transistor 3 aluminum wiring layer constituting bit line 4 aluminum wiring layer constituting word line 4B aluminum wiring layer constituting source line 5 aluminum wiring layer 3 and its Connection with lower layer 6 Connection between aluminum wiring layer 4 and its lower layer CG Control gate of memory cell FG Floating gate of memory cell S Source of memory cell D Drain of memory cell SUB substrate WL0 to WL255 Word line BL0 to BL63 Bit Line CG0 to CG63 Column selection gate DL Data line RVG00 to RVG10 Batch reverse control gate SC00 Source control gate SOU00 Common source node VSS Ground voltage SA Sense amplifier circuit DVS00 to DVS01 Reverse voltage supply circuit Qn N channel Type MOS transistor Qp P-channel type MOS transistor Qm memory cell transistor WC0~255 control signal R0~R63 boost selection signal of the low selection signal ΦW0~ΦW3 low

Claims (8)

[Claims] 1. A memory cell array in which a plurality of flash memory cells sharing a source are arranged in a matrix, a reverse voltage applying means for applying a voltage to a drain of the flash memory cell, and a plurality of drains of the flash memory cell. And a selecting means for selecting some of the plurality of groups and connecting the reverse voltage applying means to those groups at the same time. 2. The method of controlling a semiconductor memory device according to claim 1, wherein the reverse operation is performed in a plurality of times, wherein the number of groups selected by the selection means is sequentially reduced. Control method. 3. A plurality of memory cell arrays in which a plurality of flash memory cells sharing a source are arranged in a matrix, reverse voltage applying means for applying a voltage to the drains of the flash memory cells in each memory cell array, and Dividing means for dividing the plurality of drains of the flash memory cell into a plurality of groups, and selecting means for selecting some of the plurality of groups and connecting the reverse voltage applying means to those groups at the same time, A semiconductor memory device comprising: a control circuit that simultaneously selects selection means included in each of a plurality of memory cell arrays. 4. A memory cell array in which a plurality of flash memory cells sharing a source are arranged in a matrix, a reverse voltage applying means for applying a voltage to the drain of the flash memory cell, and a plurality of drains of the flash memory cell. And a dividing means for dividing the semiconductor memory into a plurality of groups, wherein the dividing means is configured to minimize a rise in source potential when a predetermined group of the plurality of groups is selected. apparatus. 5. A memory cell array in which a plurality of flash memory cells sharing a source are arranged in a matrix, a reverse voltage applying means for applying a voltage to a drain of the flash memory cell, and a gate of the flash memory cell is controlled. And a word line driving means for controlling the source voltage of the word line driving means. 6. A plurality of word lines connected to the gates of the flash memory cells, bit lines connected to the drains of the flash memory cells, and sources of the flash memory cells shared in the word line direction are arranged in a matrix. Comprising a arranged memory cell array and a source voltage source,
A semiconductor memory device, wherein a source shared in the word line direction and the source voltage source are selectively connected by a signal selecting the word line. 7. The semiconductor memory device according to claim 6, wherein the shared source is selected by a plurality of word lines. 8. The word line is composed of a first wiring layer forming a gate of the flash memory cell and another second wiring layer, and the shared source is a second wiring layer. 7. The semiconductor memory device according to claim 6, wherein the semiconductor memory devices are connected with each other.