JP2010027154A - Method of writing data to semiconductor device, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of stably verifying write operation even if an electric charge remains on an insulation film when writing data to a memory cell of a flash memory. <P>SOLUTION: A method of writing data to a semiconductor device is disclosed. In the semiconductor device, a source S and a drain D are formed on a semiconductor substrate 10, and a floating gate 13 and a control gate 11 surrounded by an insulation layer 12 are laminated on the semiconductor substrate 10 in an area between the source S and the drain D. In the method, first, a predetermined voltage is applied to the control gate 11, a positive voltage is applied to the drain D, and a ground voltage is applied to the source S to inject the electric charge to the floating gate 13. Next, a voltage of same polarity as the predetermined voltage is applied to the control gate 11, a negative voltage is applied to the drain D, and the ground voltage is applied to the source S to verify the electric charge injected to the floating gate 13. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to data write processing to a nonvolatile semiconductor memory device, and more particularly, to a method and a semiconductor device for performing write confirmation after writing data to a nonvolatile semiconductor memory device.

  Non-volatile semiconductor memory devices are roughly classified into MROM (Mask Read Only Memory), PROM (Programmable Read Only Memory), UV-EPROM (Ultra-Violet Programmable Read Only Memory), and EEPROM (Electrically Erasable and Programmable Read Only Memory). being classified. The EEPROM is roughly classified into a conventional EEPROM capable of electrical erasing and writing for each bit and a flash memory capable of batch electrical erasing and writing. Flash memory includes a NOR type and a NAND type.

  An EEPROM memory cell is a MOS (Metal Oxide Semiconductor) transistor having a double gate structure in which a floating gate is provided between a control gate and a silicon substrate. Logic data “1” or “0” is stored depending on the presence or absence of charge in the floating gate. For example, when there is a charge in the floating gate, when the voltage applied to the control gate exceeds a predetermined value, a channel is formed between the source and the drain, and a current flows. When there is no charge in the floating gate, no channel is formed between the source and drain even when the voltage applied to the control gate reaches a predetermined value. Therefore, no current flows. In other words, the threshold voltage of the memory cell is shifted by the electric charge accumulated in the floating gate, thereby representing “1” or “0” of the logical data. Since the floating gate is surrounded by an insulating film, the charge in the floating gate does not leak from the floating gate even if the power is turned off after the charge is injected into or released from the floating gate. Also, no new entry.

When writing data to the memory cell of the NOR type flash memory, hot electrons generated near the drain of the memory cell are injected into the floating gate. For this purpose, the source is grounded, and a high voltage (for example, 5 V for the drain and 10 V for the gate) is applied to the drain and the control gate. Due to the voltage applied to the drain, hot electrons are generated in the vicinity of the drain that can overcome the energy barrier from the substrate surface to the insulating film. This hot electron is attracted to a high voltage applied to the control gate and injected into the floating gate. After the charge is injected into the floating gate, writing is confirmed. Patent Documents 1 to 3 describe inventions relating to data write processing to a memory cell of a flash memory including such write confirmation.
JP 07-169280 A JP 2007-80338 A JP 2007-257827 A

Although all of the generated hot electrons are ideally injected into the floating gate, a part of the hot electrons actually remains in the insulating film surrounding the floating gate. The charge remaining in the insulating film is unstable and is excited by a small amount of energy. Such unstable charges degrade the gm of the memory cell due to the hot carrier effect. As a result, the threshold voltage of the memory cell shifts, which may adversely affect write confirmation.
The influence of the unstable charge on the write confirmation process becomes larger as the gate length of the memory cell is shorter. This hinders further integration of the flash memory. Therefore, it is important to perform the write confirmation process without being affected by unstable charges remaining in the insulating film.

  In view of the above problems, the present invention provides a technique capable of stably performing a write confirmation process even when charges remain in an insulating film when writing to a semiconductor device such as a memory cell of a flash memory. This is the issue.

  In the method for writing data to a semiconductor device of the present invention that solves the above-described problems, first and second diffusion regions are formed in a semiconductor substrate, and insulation is provided on the semiconductor substrate in a region sandwiched between the two diffusion regions. This is a method of writing data to a semiconductor device in which a charge storage layer surrounded by layers and a control gate are stacked. First, a predetermined voltage is applied to the control gate, a positive voltage is applied to the first diffusion region, a ground voltage is applied to the second diffusion region, and charges are injected into the charge storage layer. Next, a voltage having the same polarity as the predetermined voltage is applied to the control gate, a negative voltage is applied to the first diffusion region, and the ground voltage is applied to the second diffusion region to be injected into the charge storage layer. Confirm the generated charge. Thereby, data writing and writing confirmation are performed.

  In such a data writing method to the semiconductor device of the present invention, the direction of the electric field between the first and second diffusion regions is reversed between data writing and confirmation. When the charge is an electron, hot electrons are generated on the first diffusion region side during writing and injected into the charge storage layer. At the time of writing confirmation, since a negative voltage is applied to the first diffusion region, there is little influence on the channel current due to the charge remaining in the insulating film without being injected into the charge storage layer. Note that the polarity of the voltage applied to the control gate changes depending on the polarity of the charge injected into the charge storage layer. A positive voltage is applied when the charge is an electron, and a negative voltage is applied when the charge is a hole.

  In the step of confirming the charge injected into the charge storage layer, for example, a voltage of 4.5 to 5.0 V is applied to the control gate, and −1.0 V to −0.5 V is applied to the first diffusion region. Apply a voltage of.

  In the semiconductor device of the present invention, first and second diffusion regions are formed in a semiconductor substrate, and a charge storage layer and a control gate surrounded by an insulating layer are formed on the semiconductor substrate in a region sandwiched between the two diffusion regions. Are connected to the NOR type, a word line is connected to the control gate, a bit line is connected to the first diffusion region, and the second diffusion region is grounded. A power supply for applying a negative voltage to the bit line through a resistor and causing a current corresponding to the charge injected into the charge storage layer to flow through the bit line when writing to the semiconductor element is confirmed; and A confirmation sense amplifier that compares the voltage corresponding to the current flowing through the reference voltage with the reference voltage for confirmation and outputs the result as a result of the write confirmation.

The semiconductor device of the present invention applies a negative voltage to the first diffusion region via the bit line when data writing is confirmed. When no charge is injected into the charge storage layer, when a voltage is applied to the control gate, the semiconductor elements of the memory cell array are turned on. As a result, a channel current flows through the bit line. When charge is injected into the charge storage layer, the channel current does not flow because the semiconductor element of the memory cell array is not turned on even when a voltage is applied to the control gate. Whether or not writing is performed can be confirmed by the presence or absence of a channel current.
In this semiconductor device, since a negative voltage is applied to the first diffusion region, it is possible to perform write confirmation as performed by the data writing method to the semiconductor device of the present invention. Therefore, when writing is confirmed, there is little influence on the channel current due to charges remaining in the insulating film without being injected into the charge storage layer.
The resistance of the semiconductor device of the present invention may be any element that acts as a resistance component on the circuit, and may be one using a channel resistance of a transistor in addition to a normal resistance element. It is of course possible to use elements having other resistance components.

The resistor includes, for example, a first resistor connected to the switch, and a second resistor connected between the first resistor and the cathode of the power source. In this case, the voltage between the first resistor and the second resistor is compared with the confirmation reference voltage by the confirmation sense amplifier.
In order to read data from the memory cell array, the semiconductor device of the present invention compares the voltage according to the voltage of the bit line with the reference voltage for reading and reads the result when reading data from the semiconductor element. A read sense amplifier that outputs data, and a switch that connects the read sense amplifier to the bit line when reading data from the semiconductor element, and connects the resistor to the bit line when writing to the semiconductor element is confirmed. , May be further provided.

  According to the present invention as described above, by applying a negative voltage to the first diffusion region at the time of writing confirmation after data writing, stable confirmation processing can be performed even when charges remain in the insulating film. Become.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

1A and 1B are diagrams for explaining a data write process to a memory cell to which the present invention is applied. FIG. 1 a is an explanatory diagram of data writing (charge injection) to the memory cell 1.
The memory cell 1 has, for example, an n-type MOS transistor structure having a floating gate. In the memory cell 1, two n-type diffusion regions are formed in the semiconductor substrate 10. One of the diffusion regions is a source S and the other is a drain D. On the semiconductor substrate 10 in a region sandwiched between the diffusion regions, a floating gate 13 surrounded by a silicon oxide film 12 and a control gate 11 are stacked. The silicon oxide film 12 becomes an insulating film. The floating gate 13 functions as a charge storage layer, and charges are injected when data is written.

  When injecting charges into the memory cell 1, for example, the source S is grounded (source voltage VS = 0V), the control gate 11 is 10V (gate voltage VG = 10V), and the drain D is 5V (drain voltage VD = 5V) is applied. By applying in this way, the channel region 14 is formed between the source S and the drain D. Due to the potential difference between the source voltage VS and the drain voltage VD, charges (in this case, electrons) move from the source S to the drain D and collect in the vicinity of the drain D. The electric charges collected in the vicinity of the drain D are hot electrons that can cross the energy barrier from the semiconductor substrate 10 to the silicon oxide film 12. Hot electrons are injected into the floating gate 13 by an electric field generated by the gate voltage VG applied to the control gate 11. By applying a voltage as described above, charges are injected into the floating gate 13, but charges remain in the silicon oxide film 12 as in the conventional case.

FIG. 1B is an explanatory diagram of a write confirmation process performed on the memory cell 1 after data is written.
When writing is confirmed, the source S is grounded (source voltage VS = 0V), the control gate 11 is 4.5 to 5.0 V (gate voltage VG = 4.5 to 5.0 V), and the drain D is connected. −1.0 to −0.5 V (drain voltage VD = −1.0 to −0.5 V) is applied. By applying in this way, a channel region 15 is formed between the drain D and the source S. The direction of the channel is opposite to that at the time of data writing.
Since the drain voltage VD applied to the drain D is a negative voltage, it is not affected by the charge remaining in the silicon oxide film 12. Therefore, the channel current between the drain D and the source S flows more than before. Since a large amount of channel current flows, the write confirmation can be performed more reliably than before.

FIG. 2 is a configuration diagram of an apparatus for performing data read and write confirmation processing on a NOR type flash memory constituted by such a memory cell 1.
In the memory cell array 20 configured by connecting the memory cells 1 shown in FIGS. 1a and 1b in a NOR type, the word line WLn (n = 0, 1, 2,...) Is connected to the control gate 11, and the source S is grounded. The bit line BL is connected to the drain D. Normally, a plurality of bit lines BL are also provided. However, in order to simplify the description, only one bit line BL will be described here.
An appropriate voltage is applied to the word line WLn according to processing such as writing, reading, writing confirmation, and erasing. The voltage applied to the word line WLn becomes the control gate voltage VG of the memory cell 1. As a device for applying a voltage to the word line WLn, a device having the same configuration as that of the conventional one can be used, and the description thereof is omitted here.

  An appropriate voltage is applied to the bit line BL according to processing such as writing, reading, writing confirmation, and erasing. The voltage applied to the bit line BL becomes the drain voltage VD of the memory cell 1. Note that a device for applying a voltage to the bit line BL at the time of writing and erasing processing can be the same as that of the conventional device, and the description thereof is omitted here.

A switch 21 is connected to the bit line BL. Connected to the switch 21 is a reading device comprising a cascode circuit 22 and a reading sense amplifier 23 and a confirmation device comprising a voltage supply circuit 24 and a confirmation sense amplifier 25. The switch 21 connects the bit line BL to the reading device during the reading process, and connects to the checking device during the checking process.
A reference voltage applied to the read sense amplifier 23 and the confirmation sense amplifier 25 is supplied from a reference voltage generator 26. The read reference voltage applied to the read sense amplifier 23 and the confirmation reference voltage applied to the confirmation sense amplifier 25 may be either the same voltage or different voltages.

The cascode circuit 22 and the read sense amplifier 23 constituting the reading device are used when reading data from the memory cell 1.
The voltage of the drain D of the memory cell 1 at the time of reading differs depending on whether or not charges are injected into the floating gate 13. Therefore, the voltage of the bit line BL is also different. A voltage corresponding to the different voltage is input from the cascode circuit 22 to the read sense amplifier 23. The read sense amplifier 23 compares the voltage input from the cascode circuit 22 with the read reference voltage, and reads the voltage that is the logical data “0” when the charge is injected into the floating gate 13. When data is output and no charge is injected into the floating gate 13, a voltage that is logical data “1” is output as read data.

  The voltage supply circuit 24 and the confirmation sense amplifier 25 constituting the confirmation device apply a negative voltage to the drain D of the memory cell 1 by the voltage supply circuit 24 when confirming writing of the memory cell 1. The voltage supply circuit 24 includes a first resistor 27, a second resistor 28, and a power source 29. In series from the switch 21, the first resistor 27, the second resistor 28, and the cathode of the power source 29 are connected, and the anode of the power source 29 is grounded. A voltage between the first resistor 27 and the second resistor 28 is input to the confirmation sense amplifier 25. The confirmation sense amplifier 25 compares this voltage with the confirmation reference voltage. The comparison result is output as confirmation data. The first resistor 27 and the second resistor 28 may be any element that acts as a resistance component on the circuit, and may be a transistor using a channel resistance of a transistor in addition to a normal resistance element. Moreover, the element which acts as another resistance component may be sufficient.

At the time of writing confirmation, since a negative voltage is applied to the bit line BL, a negative voltage is applied to the drain D of the memory cell 1. A positive voltage is applied to the control gate 11 of the memory cell 1 from the word line WLn.
The current flowing through the bit line BL varies depending on whether or not charges are injected into the floating gate 13. A voltage corresponding to each of the different currents is input from the voltage supply circuit 24 to the confirmation sense amplifier 25. The confirmation sense amplifier 25 compares the voltage input from the voltage supply circuit 24 with the reference voltage for confirmation, and when charge is injected into the floating gate 13, the voltage that becomes the logical data “1” is obtained. When it is output as confirmation data and no charge is injected into the floating gate 13, a voltage that is logical data “0” is output as confirmation data.

For example, when no charge is injected into the floating gate 13, a channel is generated and a current flows from the bit line BL to the voltage supply circuit 24 as shown in FIG. Due to this current, the voltage between the first resistor 27 and the second resistor 28 becomes different from the voltage supplied from the power supply 29.
When charge is injected into the floating gate 13, no channel is generated and no current flows through the bit line BL. Therefore, the voltage between the first resistor 27 and the second resistor 28 is the same as the voltage supplied from the power supply 29.
That is, the voltage between the first resistor 27 and the second resistor 28 when no charge is injected into the floating gate 13 is higher than the voltage when charge is injected. In the confirmation sense amplifier, by comparing this voltage with the confirmation reference voltage, it indicates that charge is injected when outputting logical data “1”, and when outputting logical data “0”. Confirmation data indicating that no charge is injected is output.

As described above, the write confirmation process for each memory cell 1 in the memory cell array 20 is performed. Since the channel current at the time of writing confirmation is not affected by the charge remaining in the silicon oxide film 12, the writing confirmation can be performed more reliably than before. In addition, since a positive voltage is applied to the control gate 11 and a negative voltage is applied to the drain D when writing is confirmed, the influence of charges remaining in the conventional silicon oxide film 12 is reduced. be able to.
In the above description, the memory cell 1 is a semiconductor memory device having an n-type MOS structure, but this may be a semiconductor memory device having a p-type MOS structure. In this case, a negative voltage is applied to the control gate 11 when writing is confirmed. Further, instead of the floating gate 13, a charge storage layer may be formed of a nitride film having an ONO (Oxide-Nitride-Oxide) structure.

FIG. 1 a is an explanatory diagram of data writing (injection of charge) into a memory cell, and is an explanatory diagram of a write confirmation process performed on a memory cell that has been written. 1 is a configuration diagram of an apparatus for performing writing and write confirmation processing on a NOR type flash memory. FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Memory cell, 10 ... Semiconductor substrate, 11 ... Control gate, 12 ... Silicon oxide film, 13 ... Floating gate, 20 ... Memory cell array, 21 ... Switch, 22 ... Cascode circuit, 23 ... Reading sense amplifier, 24 ... Voltage supply circuit 25... Sense amplifier 26. Reference voltage generator 27... First resistor 28... Second resistor 29 .. power source S. source D. drain

Claims (5)

A semiconductor device in which first and second diffusion regions are formed in a semiconductor substrate, and a charge storage layer surrounded by an insulating layer and a control gate are stacked on the semiconductor substrate in a region sandwiched between the two diffusion regions A method of writing data to
Applying a predetermined voltage to the control gate, applying a positive voltage to the first diffusion region, applying a ground voltage to the second diffusion region, and injecting charges into the charge storage layer;
A voltage having the same polarity as the predetermined voltage is applied to the control gate, a negative voltage is applied to the first diffusion region, and the ground voltage is applied to the second diffusion region to be injected into the charge storage layer. A step of confirming the charge,
A method for writing data to a semiconductor device. In the step of confirming the charge injected into the charge storage layer, a voltage of 4.5 to 5.0 V is applied to the control gate, and a voltage of −1.0 V to −0.5 V is applied to the first diffusion region. Apply
A method of writing data to the semiconductor device according to claim 1. A semiconductor element in which first and second diffusion regions are formed in a semiconductor substrate, and a charge storage layer surrounded by an insulating layer and a control gate are stacked on the semiconductor substrate in a region sandwiched between the two diffusion regions A memory cell array that is connected to a NOR type, a word line is connected to the control gate, a bit line is connected to the first diffusion region, and the second diffusion region is grounded;
A power supply for applying a negative voltage to the bit line via a resistor and causing a current corresponding to the electric charge injected into the charge storage layer to flow through the bit line when confirming writing of the semiconductor element;
A confirmation sense amplifier that compares a voltage according to the current flowing through the bit line with a reference voltage for confirmation and outputs the result as a result of write confirmation;
Semiconductor device. The resistor includes a first resistor connected to the switch, and a second resistor connected between the first resistor and a cathode of the power source,
The voltage between the first resistor and the second resistor is compared with the reference voltage for confirmation by the confirmation sense amplifier.
The semiconductor device according to claim 3. A read sense amplifier that compares a voltage corresponding to the voltage of the bit line with a read reference voltage and outputs the result as read data when reading data from the semiconductor element;
A switch that connects the read sense amplifier to the bit line when reading data from the semiconductor element, and connects the resistor to the bit line when writing to the semiconductor element is confirmed.
The semiconductor device according to claim 3 or 4.

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