CN113192549B

CN113192549B - Three-dimensional memory, detection device, three-dimensional memory device and detection method

Info

Publication number: CN113192549B
Application number: CN202110527922.8A
Authority: CN
Inventors: 何雪松
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2021-05-14
Filing date: 2021-05-14
Publication date: 2022-05-20
Anticipated expiration: 2041-05-14
Also published as: CN113192549A

Abstract

The application provides a three-dimensional memory, a detection device, a three-dimensional memory device and a detection method, wherein the three-dimensional memory comprises: a memory plane comprising a plurality of memory bank groups, each of said memory bank groups comprising at least one memory block and at least one sub-source line separating adjacent memory blocks; and the switch unit comprises a plurality of switch subunits respectively corresponding to the plurality of storage block groups, and each switch subunit is arranged between the corresponding storage block group and the common source line so as to control the connection or disconnection between the sub-source line and the common source line in the corresponding storage block group. The three-dimensional memory device provided by the application can be used for disconnecting the connection between the sub-source line corresponding to the electric leakage storage unit and the public source line by arranging the switch unit, so that the large-range electric leakage of the public source line can be avoided, and the yield of devices can be improved.

Description

Three-dimensional memory, detection device, three-dimensional memory device and detection method

Technical Field

The present application relates to the field of semiconductor technology. In particular, the present application relates to the field of three-dimensional memories.

Background

The 3D NAND memory, as a three-dimensional nonvolatile flash memory, overcomes the limitations of two-dimensional (2D) memory devices by increasing the storage density per unit area by stacking multiple layers of memory cells to form an array of memory strings. The memory strings include source select transistors, and the source select transistors of the plurality of memory strings are connected to ground through the same source line (e.g., a common source line).

Existing 3D NAND memory cell architectures are typically vertical channel, lateral gate layer designs. In the manufacturing process of the memory, the sidewall of the channel may be damaged due to defects, manufacturing processes and the like, and then the word line connected to the damaged sidewall leaks current. When the damaged portion is adjacent to the common source line, the common source line may be affected, which may further cause large-area leakage of the memory device, and reduce the yield of the device.

It should be appreciated that this background section is intended in part to provide a useful background for understanding the technology. This background section, however, may also include views, concepts or insights that are part of what is not known or understood by those of ordinary skill in the relevant art prior to the corresponding effective application date of the subject matter disclosed herein.

Disclosure of Invention

In order to solve the above problems, the present application provides a three-dimensional memory to avoid the situation of large-scale electrical leakage of a plane, and effectively improve the yield of chips.

The memory includes:

a memory plane comprising a plurality of memory bank groups, each of said memory bank groups comprising at least one memory block and at least one sub-source line separating adjacent memory blocks;

a switch unit including a plurality of switch sub-units respectively corresponding to the plurality of memory block groups, each of the switch sub-units being disposed between a corresponding memory block group and a common source line to control connection or disconnection between the sub-source line and the common source line in the corresponding memory block group.

According to an embodiment of the application, the three-dimensional memory comprises a plurality of storage planes, all the sub-source lines of each of the storage planes being connected to the same common source line via a respective sub-switch unit.

According to one embodiment of the present application, the switch subunit includes a PMOS transistor or an NMOS transistor.

According to one embodiment of the present application, each of the memory blocks includes: a plurality of memory strings electrically connectable in common to a same source line at one end.

Another aspect of the present application provides a detection apparatus for performing leakage detection on the above three-dimensional memory, where each of the memory blocks of the three-dimensional memory includes a plurality of memory strings, and each of the memory strings includes a plurality of memory cells, the detection apparatus including:

a word line detection module configured to apply a detection voltage to a word line of each of the memory cells and detect a first current flowing through the word line; and

and the control module is configured to control the on-off of the switch subunit according to the first current.

According to an embodiment of the application, the detection device further comprises: and the channel detection module is configured to apply a channel detection voltage to the memory string where the memory cell is located while applying a turn-on voltage to the word line of each memory cell, and detect a second current flowing through the channel.

According to one embodiment of the present application, wherein the plurality of memory cells of each of the memory strings is divided into a first group of memory cells and a second group of memory cells, the word line detection module is configured to:

a first detection voltage is applied to word lines of a first memory cell group and a second detection voltage different from the first detection voltage is applied to word lines of a second memory cell group to form a first current flowing through an adjacent word line.

According to one embodiment of the application, the value of the applied first detection voltage is higher than the value of the applied second detection voltage.

According to one embodiment of the application, the value of the second detection voltage applied is zero.

According to one embodiment of the present application, even memory cells of the plurality of memory cells constitute the first memory cell group, and odd memory cells constitute the second memory cell group.

According to one embodiment of the application, the control module is configured to:

and comparing the detected value of the first current with a first reference value aiming at each memory block group, and controlling the corresponding switch subunit to be switched off when the value of the first current is greater than the first reference value.

According to an embodiment of the application, the control module is further configured to:

and comparing the detected value of the second current with a second reference value aiming at each memory block group, and controlling the corresponding switch subunit to be switched off when the value of the second current is greater than the second reference value.

Based on the same inventive concept, the present application further provides a three-dimensional memory device, which includes the three-dimensional memory and the detection device.

The present application further provides a detection method for performing leakage detection on the three-dimensional memory, where each memory block of the three-dimensional memory includes a plurality of memory strings, and each memory string includes a plurality of memory cells, the detection method includes:

applying a detection voltage to a word line of each of the memory cells and detecting a first current flowing through the word line; and controlling the on-off of the switch subunit according to the first current.

According to an embodiment of the present application, the detection method further comprises: applying a channel detection voltage to a memory string where the memory cell is located while applying a turn-on voltage to a word line of each of the memory cells, and detecting a second current flowing through the channel.

According to one embodiment of the present application, wherein the plurality of memory cells of each of the memory strings are divided into a first memory cell group and a second memory cell group, wherein applying a detection voltage to a word line of each of the memory cells comprises:

According to one embodiment of the application, the first detection voltage is applied at a value higher than the second detection voltage.

According to one embodiment of the application, the value of the applied second detection voltage is zero.

According to an embodiment of the present application, controlling the switching of the switch subunit according to the first current comprises:

According to an embodiment of the present application, the detection method further comprises:

According to the three-dimensional memory, the plurality of sub-source electrode lines corresponding to the defective storage block group of the storage unit are controlled to be disconnected with the common source electrode line in the storage plane through the sub-switch units, so that large-area electric leakage of the three-dimensional memory is avoided, and the yield of devices is improved.

Drawings

Other features, objects, and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, with reference to the accompanying drawings. In the drawings:

fig. 1 is a schematic top view of a three-dimensional memory according to an embodiment of the present application.

Fig. 2 is a schematic top view of a region of a storage plane of a three-dimensional memory according to an embodiment of the present application.

Fig. 3 is a schematic top view of a region of a memory block of a three-dimensional memory according to an embodiment of the present application.

Fig. 4 is a schematic sectional view taken along line a-a of fig. 3.

Fig. 5 is a schematic view of a detection device according to an embodiment of the present application.

Fig. 6 is a flowchart of a detection method according to an embodiment of the present application.

Detailed Description

While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the relevant art will recognize that other configurations and arrangements can be used without parting from the spirit and scope of the disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used in a variety of other applications.

Note that references in the specification to "one embodiment," "an example embodiment," "some embodiments," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the relevant art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

In general, terms may be understood at least in part from the context of their use. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular or may be used to describe a combination of features, structures, or characteristics in the plural, depending, at least in part, on the context. Similarly, terms such as "a" or "the" may also be understood to convey a singular use or to convey a plural use, depending, at least in part, on the context. Moreover, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors not necessarily explicitly described, again depending at least in part on the context.

It should be readily understood that the meaning of "on," "above," and "over" in this disclosure should be interpreted in the broadest manner, such that "on" means not only "directly on" but also includes the meaning of "on" and having intervening features or layers therebetween, and "above" or "over" means not only the meaning of "above" or "over" but may also include the meaning of "above" or "over" and having no intervening features or layers therebetween (i.e., directly on something).

Furthermore, spatially relative terms such as "under," "below," "lower," "above," "upper," and the like may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The layer may extend over the entire upper or lower layer structure or may have a smaller extent than the lower or upper layer structure. Furthermore, the layer may be a region of a continuous structure, uniform or non-uniform, having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any pair of lateral faces at the top and bottom surfaces of the continuous structure. The layers may extend laterally, vertically, and/or along the tapered surface. The substrate may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, above, and/or below. The layer may comprise a plurality of layers.

In the drawings, the thickness, size, and shape of the components have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. For example, as used herein, the terms "approximately", "about" and the like are used as table-approximating terms and not as table-wise terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art.

It will be further understood that the terms "comprises," "comprising," "has," "having," "includes" and/or "including," when used in this specification, specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Moreover, when a statement such as "at least one of" appears after a list of listed features, the entirety of the listed features is modified rather than modifying individual elements in the list. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.

Three-dimensional (3D) memory refers to a semiconductor memory having vertically oriented strings of memory cell transistors (referred to herein as "memory strings") on a laterally oriented substrate such that the memory strings extend in a vertical direction relative to the substrate.

Unless otherwise defined, all terms (including engineering and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

In addition, the embodiments and features of the embodiments in the present application may be combined with each other without conflict. In addition, unless explicitly defined or contradicted by context, the specific steps included in the methods described herein are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Fig. 1 shows a schematic top view of a three-dimensional memory according to an embodiment of the present application, which provides a three-dimensional memory 10 that may include one or more memory planes 11, each having its own set of read/write circuits, such that multiple memory planes can operate in parallel. Each memory plane 11 may comprise a plurality of memory block sets 12, each memory block set 12 comprising at least one memory block 13 and at least one sub-source line for separating adjacent memory blocks 13 (see fig. 2). The directions of the word lines "WL" and the bit lines "BL" are labeled in fig. 1, and the bit lines and word lines may be arranged vertically (e.g., in rows and columns, respectively). The exemplary three-dimensional memory 10 in fig. 1 includes six memory planes 11, each memory plane 11 includes two memory block groups 12 arranged in the BL direction, and each memory block group 12 includes three memory blocks 13 distributed in the BL direction. In one memory plane, there is only one memory block group 12 and one memory block 13 in the WL direction, where the memory block 13 does not refer to the erasable minimum unit, and only the memory plane needs to be divided into a plurality of memory stripes distributed along the BL direction according to the design of the present invention, and the plurality of memory stripes are grouped to form a plurality of memory block groups 12. It should be understood that the number of memory blocks 12 and the number of memory blocks 13 within a memory block group per memory plane may be any other positive integer without departing from the teachings of the present invention.

Fig. 2 shows a part-region within one memory plane 11 comprising a plurality of memory block sets 12, each memory block set comprising a plurality of memory blocks 13, each adjacent memory block being separated by a sub-source line 30, the sub-source line 30 being parallel to the WL direction. Each memory block comprises a plurality of memory strings 20, one end of the plurality of memory strings 20 being commonly electrically connected to the same source line 30. The three-dimensional memory according to the embodiment of the present application further includes a switch unit 50, where the switch unit 50 includes a plurality of switch sub-units respectively corresponding to the plurality of memory block groups 12, and the switch sub-units may be PMOS transistors or NMOS transistors. Each switch subunit is disposed between a corresponding memory block group 12 and the common source line 60 to control connection or disconnection between the sub-source line 30 in the corresponding memory block group and the common source line 60. The sub-source lines 30 within all memory block groups within a memory plane 11 for separating adjacent memory blocks 13 are connected to the same common source line 60 via respective switch subunits, the common source line 60 may be parallel to BL. When a certain sub-source polar line in a certain storage block group is detected to possibly face short circuit, the sub-source polar line and the public source polar line can be controlled to be disconnected by turning off the switch subunit corresponding to the storage block group, the integral leakage of the storage plane caused by the leakage of the individual sub-source polar line through the public source polar line is avoided, the large-area leakage of a device is effectively avoided, and the yield of the device is improved.

Fig. 2 exemplarily shows 2 switching subunits 501 and 502 included in the switching unit 50, where the switching subunits 501 and 502 correspond to the memory block group 121 and the memory block group 122, respectively. Memory block group 121 includes n memory blocks 13_k0-13_kn-1(n is an integer of 1 or more), adjacent memory blocks are formed by the sub source lines 30 apart. In the memory block group 121, all the sub-source lines 30 for separating adjacent memory blocks are connected to or disconnected from the common source line through the switch subunit 501, and the memory block group 122 includes n memory blocks 13_kn-13_2n-1Likewise, all of the sub-source lines 30 within a bank 122 that are used to separate adjacent memory blocks are connected or disconnected from a common source line by a switch subunit 502. It should be understood that the number of memory blocks included in different memory block groups may be the same, or may be different according to actual needs.

When n is equal to 1, the memory block group 121 and the memory block group 122 respectively include only one memory block, and when the schematic plan view of the three-dimensional memory according to the embodiment of the present application is shown in fig. 3 (fig. 3 does not show the memory block on the other side of the sub-source line 302), the switching unit 50 includes 2

switching sub-units

503 and 504 respectively connected to the two

sub-source lines

301 and 302, that is, the sub-switching units are corresponding to each memory block and the corresponding sub-source line.

According to the embodiment of the application, the memory blocks are grouped to form the plurality of memory block groups, and the sub-switch unit is arranged between each memory block group and the common source line, so that the use of the switch sub-units can be effectively reduced, the cost is saved, and the improvement of the integration level of the memory device is facilitated.

Fig. 4 is a schematic cross-sectional view taken along line a-a of fig. 3, the memory block 13 including a substrate 130, an insulating layer 131 on the substrate 130, a row of Bottom Select Gates (BSGs) 132 on the insulating layer 131, and dielectric layers 134 and Gate layers 133 stacked on top of the BSGs alternating in a vertical direction, the Gate layers 133 leading out word lines for connection with external circuits. The substrate 130 may be any suitable semiconductor substrate having any suitable conductive material, such as a single crystal, polycrystalline, or single crystal semiconductor, among others. For example, the substrate 130 may include silicon, silicon germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride, silicon carbide, III-V compounds, or any combination thereof. The gate layer 133 is a conductive material such as W, Co, Cu, Al, Ti, Ta, TiN, TaN, Ni, doped silicon, silicide (e.g., NiSix, WSix, CoSix, TiSix), or any combination thereof. The dielectric layer 134 material may comprise a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The memory block also includes a row of Top select gates 135 (TSGs) on alternating Gate layers 133 and dielectric layers 134. The memory string 20 includes a plurality of stacked memory cells, and the memory cells of the plurality of memory strings 20 are addressable by interconnects (e.g., bit lines and word lines). (20 a, 20b, 20c as shown in fig. 4), the channels of the memory cells constituting the same memory string 20 are physically connected along the vertical direction. The "rows" described herein are substantially the same height. It will be understood by those skilled in the art that the number of the memory cells shown in fig. 4 is only exemplary for the purpose of illustration, and the specific number thereof can be set according to actual needs.

The memory string 20 also includes at least one field effect transistor at the top and bottom, controlled by the BSG and TSG, respectively. And the two corresponding transistors are referred to as a top select transistor and a bottom select transistor. The drain terminal of the top select transistor may be connected to a bit line, and the source terminal of the bottom select transistor (also referred to as "source select transistor") may be connected to a doped source line region 136, from which the sub-source line 30 may be formed. The source lines may be shared by the memory strings 20 throughout the memory block. As described herein, the "top" is farther from the substrate 130 in the vertical direction, and the "bottom" is closer to the substrate 130 in the vertical direction.

Another embodiment of the present application provides a detection apparatus for performing leakage detection on the three-dimensional memory. As shown in fig. 5, the detection device 101 may include: the control circuit 600 controls the burn-in module 100, the word line detection module 200, the channel detection module 300, the control module 400 and the sub-source line detection module 500 to apply required voltages and output required detection currents respectively through the control circuit 600. It will be appreciated by those skilled in the art that the detection apparatus 101 shown in fig. 5 is merely exemplary, and the detection apparatus may include only a portion of the above modules, or include other modules in addition to the above modules.

Therein, the aging module 100 may be configured to apply an aging voltage to the word line of each memory cell. According to an exemplary embodiment, the plurality of memory cells of each memory string is divided into a first memory cell group and a second memory cell group, and applying the aging voltage to the word line of each memory cell may include: a first aging voltage is applied to each word line of the first group of memory cells, and a second aging voltage different from the first aging voltage is applied to each word line of the second group of memory cells. According to one example, even memory cells of the plurality of memory cells constitute the first memory cell group, odd memory cells constitute the second memory cell group, and an aging high voltage may be applied to each word line of the odd memory cells and an aging low voltage may be applied to each word line of the even memory cells. For example, the memory cell at the bottom of the memory string 20 is 20_k020 even memory cells_k0One memory cell of above is 20_k1And so on, as odd memory cells. The applied aging high voltage value is greater than the applied aging low voltage value, the aging high voltage can be 10V-50V, the aging low voltage can be 0V-10V, and the applied aging low voltage is 0V, which represents grounding. Wherein the memory cells connected to the same word line may be configured to have the aging high voltage or the aging low voltage applied thereto by the same word line. Therefore, aging current is formed between word lines of adjacent memory cells in the same memory string, aging of the word lines is accelerated, and the defective word lines are directly aged and burnt out, so that the defective memory cells are screened out. At the same time, the dielectric layer between the gate layers 133 (i.e., word lines) may be damaged, causing the conductive material (e.g., tungsten) of the gate layers 133 to diffuse into the dielectric layer 134 causing a short. When a defective word line of a memory cell is adjacent to a sub-source line 30, the above-mentioned aging process is very likely to cause the damage extent to diffuse to the adjacent sub-source line 30, so that the conductor material of the gate layer 133 diffuses to the sub-source line. As shown in fig. 2, the damaged region 40 is analyzed by an Energy Dispersive Spectrometer (EDS) to clearly detect the diffusion of the conductive material of the gate layer to the dielectric layer and the adjacent sub-source lines 30, resulting in further damaged shorts of the sub-source lines. In the drain of source linesDuring electrical detection, the source line detects the leakage current of the high bit.

The word line detection module 200 may be configured to: a detection voltage is applied to a word line of each memory cell, and a first current flowing through the word line is detected. The word line detection module 200 may perform the detection after the burn-in module 100 completes the burn-in. According to an exemplary embodiment, the manner of applying the sensing voltage to the word lines of the memory cells may refer to the manner of applying the aging voltage described above, and exemplarily, a first sensing voltage is applied to the word lines of the even memory cell groups and a second sensing voltage different from the first sensing voltage is applied to the word lines of the odd memory cell groups to form a first current (which may also be referred to as "word line leakage current") flowing through the adjacent word lines. Wherein a sensing low voltage is applied to each word line of the even group of memory cells and a sensing high voltage is applied to each word line of the odd group of memory cells. The applied detection high voltage value is larger than the applied detection low voltage value, and the applied detection low voltage is 0V, which represents grounding. The memory cells connected to the same word line may be configured to apply a high detection voltage or a low detection voltage to the same word line so as to detect a word line leakage current formed between two word lines of adjacent memory cells. The value range of the detection high voltage is 5V-25V, the value range of the detection low voltage is 0V-5V, and the detection low voltage is 0V and represents grounding.

The channel detection module 300 may be configured to: a channel sensing voltage is applied to the memory string 20 in which each memory cell is located while a turn-on voltage is applied to the word line of the memory cell to form a second current (which may also be referred to as a "channel current") flowing through the channel. Channel current exceeding the normal threshold generally indicates that the memory string has channel sidewall damage. Damage to the channel sidewall also easily causes short circuit of adjacent sub-source lines, and often damage to the memory cell basically indicates that the channel sidewall at this point is damaged, so in an actual detection process, only the word line detection module 200 is usually configured to perform word line leakage current detection, and the channel detection module 300 is generally configured to be used as an auxiliary module of the word line detection module 200.

The control module 400 may be configured to: and controlling the on-off of the switch subunit according to the value of the word line leakage current detected by the word line detection module 200 or the value of the channel current detected by the channel detection module 300. According to an exemplary embodiment, controlling the switching of the switch subcell according to the value of the word line leakage current or the value of the channel current comprises: for each memory block group 12, the detected word line leakage current value is compared with a first reference value or the detected channel current value is compared with a second reference value, and when the word line leakage current value or the channel current value is greater than the corresponding reference value, the memory cell is determined to be leaky, so that the defective memory cell is located. The first reference value and the second reference value may be selected based on empirical values, for example, the first reference value and the second reference value may range from 100nA to 400 nA. If the sub-source polar line corresponding to the storage block where the defective storage unit is located is just adjacent to the storage unit, the sub-source polar line is possibly damaged greatly; if the sub-source line corresponding to the memory block in which the defective memory cell is located is far away from the memory cell, the sub-source line will not be damaged. Generally, to avoid the influence of possible damage of the sub-source lines, when the memory cell is determined to be defective and leaky, it can be considered that the sub-source line corresponding to the memory block where the memory cell is located may face short circuit. And controlling the switch sub-units corresponding to the memory block group in which the memory block is positioned to be disconnected, so that all the sub-source line in the memory block group is disconnected from the common source line, and the other memory block groups without leakage are kept connected with the common source line through the corresponding sub-switch units.

When the switch unit 50 and the sub-switch units thereof are not arranged, since all the sub-source lines 30 corresponding to all the storage blocks in the storage plane 11 are commonly connected to the same common source line 60, in the subsequent implementation of leakage detection of the sub-source lines, the damage and short circuit of a certain sub-source line can cause leakage current of all the sub-source lines in the storage plane 11 to detect high-order bits, which is large-scale leakage, and often only the whole storage plane can be discarded, thereby reducing the yield of the memory.

The sub-source line inspection module 500 may be configured to: and carrying out leakage current detection on the sub-source electrode lines corresponding to the plurality of storage blocks in the storage plane. The sub-source line inspection module 500 may perform the inspection after the control module 400 controls the switch sub-unit corresponding to the memory block group in which the defective memory cell is located to be turned off. According to one exemplary embodiment, the leakage current detection of the sub-source line includes: high voltage is applied to the sub-source lines corresponding to the plurality of memory blocks, word lines corresponding to the memory cells in the plurality of memory blocks are grounded, bit lines connected to the tops of the memory strings 20 in the plurality of memory blocks are grounded, and the high voltage is in the range of 1V-5V. Because the sub-switch unit disconnects the connection between the public source line and the sub-source line which is possibly damaged, when the sub-source line detection is carried out, high-order leakage current (milliampere level) in a large range cannot be detected, the detection qualification rate of the sub-source line in the storage plane is improved, and the yield of devices is synchronously improved.

In another embodiment of the present application, a method for performing leakage detection on the above three-dimensional memory is provided, wherein each of the memory blocks of the three-dimensional memory includes a plurality of memory strings, and each of the memory strings includes a plurality of memory cells. As shown in fig. 6, the detection method may include:

s1, applying a detection voltage to the word line of each memory cell, and detecting a first current flowing through the word line;

and S2, controlling the on-off of the switch subunit according to the first current.

Wherein, the detection method further comprises: performing the step S0 before performing the step S1; the step S0 may include: aging the word line of each memory cell to screen out defective memory cells, according to an exemplary embodiment, the plurality of memory cells of each memory string being divided into a first memory cell group and a second memory cell group, and the applying the aging voltage to the word line of each memory cell in S0 may include: a first aging voltage is applied to each word line of the first group of memory cells, and a second aging voltage different from the first aging voltage is applied to each word line of the second group of memory cells. Illustratively, even memory cells among the plurality of memory cells constitute the first memory cell group, odd memory cells constitute the second memory cell group, an aging high voltage is applied to each word line of the odd memory cells, an aging low voltage is applied to each word line of the even memory cells, a value of the applied aging high voltage is greater than a value of the applied aging low voltage, the aging high voltage may be in a range of 10V to 50V, the aging low voltage may be in a range of 0V to 10V, and ground is indicated when the applied aging low voltage is 0. Wherein the aging high voltage or the aging low voltage is applied by the same word line to the memory cells connected to the same word line. Therefore, an aging current is formed between the word lines of the adjacent memory cells, so that the defective word lines are directly aged and burnt out, and the defective memory cells are screened out.

According to an example embodiment, after applying the aging voltage for a predetermined time, referring to the aging manner of S0, applying the detection voltage to the word line of the memory cell and detecting the first current (which may also be referred to as "word line leakage current") flowing through the word line in S1 may include:

a first detection voltage is applied to word lines of even memory cell groups and a second detection voltage different from the first detection voltage is applied to word lines of odd memory cell groups to form word line leakage currents flowing through adjacent word lines. Wherein a sensing low voltage is applied to each word line of the even group of memory cells and a sensing high voltage is applied to each word line of the odd group of memory cells. The applied detection high voltage value is larger than the applied detection low voltage value, and the applied detection low voltage is 0V, which represents grounding. Wherein the memory cells connected to the same word line may be configured to apply the sensing high voltage or the sensing low voltage by the same word line.

According to an exemplary embodiment, the controlling of the switching of the switch subunit according to the first current in S2 includes: comparing the value of the first current (also called as "word line leakage current") with a first reference value for each memory block group, and when the value of the first current is greater than the first reference value, indicating that the memory cell is defective and leaky, the reference value can be in the range of 100nA-400nA, and then controlling the switch subunit corresponding to the memory block group where the word line is located to be turned off.

If the sub-source line corresponding to the memory block in which the defective memory cell is located is exactly adjacent to the memory cell, the sub-source line is most likely to be damaged. Generally, to avoid the influence of possible damage of the sub-source lines, when the memory cell is determined to be defective and leaky, it can be considered that the sub-source line corresponding to the memory block where the memory cell is located may face short circuit.

According to an exemplary embodiment, the detection method further comprises: referring to the aging mode of S0 after applying the aging voltage for a predetermined time, the detecting method further includes:

s1', a channel sensing voltage is applied to the memory string in which each memory cell is located while a turn-on voltage is applied to the word line of the memory cell to form a second current.

S2', for each stored block group, comparing the detected value of the second current with a second reference value, and controlling the corresponding switch subunit to be turned off when the value of the second current is greater than the second reference value.

When the value of the second current (also referred to as "channel current") is greater than a second reference value, which may range from 100nA to 400nA, indicating that the memory cell is defective and leaky. Damage to the side wall of the channel is also likely to cause damage and short circuit of the adjacent sub-source line, and often damage to the memory cell basically indicates that the side wall of the channel is damaged, so in an actual detection process, only the word line leakage current is usually detected to screen out a defective memory cell, and channel current detection is generally used as an auxiliary means for screening out a defective memory cell.

According to an exemplary embodiment, the detection method further comprises: and after the switch subunits corresponding to the memory block group in which the defective memory cell is located are controlled to be disconnected, performing leakage current detection on the sub-source electrode lines corresponding to the plurality of memory blocks in the memory plane. Illustratively, the detecting the leakage current of the sub source line comprises: high voltage is applied to the sub-source lines corresponding to the plurality of memory blocks, word lines corresponding to the memory cells in the plurality of memory blocks are grounded, bit lines connected to the tops of the memory strings 20 in the plurality of memory blocks are grounded, and the high voltage is in the range of 1V-5V. Since the sub-switch unit disconnects the common source line from the possibly damaged sub-source line, a large-range high-order leakage current (in milliampere) cannot be detected during the detection of the sub-source line.

The voltages applied and currents sensed by the burn-in module 100, the word line inspection module 200, the channel sidewall inspection module 300, the control module 400, and the sub-source line inspection module 500 may be actually inspected by a tester or a test processor mounted probe.

Another embodiment of the present application provides a three-dimensional memory device 102 including the three-dimensional memory 10 and the detection device 101 described above.

According to the three-dimensional memory provided by the embodiment of the application, the sub-switch unit is arranged between the memory block group 13 and the common source line 60, so that the sub-source line in the memory block group and the common source line 60 in the storage plane 11 can be disconnected, and according to the detection device provided by the embodiment of the application, whether the word line of the memory unit leaks electricity is detected to judge whether the corresponding sub-source line 30 is possibly short-circuited with the word line at the position, and then the sub-source line 30 in the corresponding memory block group 13 is disconnected from the common source line 60. Therefore, the leakage of the current at the high position of the individual sub-source line 30 is avoided, the leakage of the whole high position of the storage plane caused by the common source line 60 is avoided, and the yield of the device is improved.

It should be noted that additional steps may be provided before, during, and after the manufacturing method, and that some of the steps described herein may be replaced, deleted, performed in a different order, or performed in parallel for additional embodiments of the manufacturing method.

The above description is only an embodiment of the present application and an illustration of the technical principles applied. It will be appreciated by a person skilled in the art that the scope of protection covered by the present application is not limited to the embodiments with a specific combination of the features described above, but also covers other embodiments with any combination of the features described above or their equivalents without departing from the technical idea. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims

1. A three-dimensional memory, comprising:

a memory plane including a plurality of memory block groups, each of the memory block groups including at least one memory block and at least one sub-source line for separating adjacent memory blocks, wherein each of the memory blocks includes a plurality of memory strings, each of the memory strings including a plurality of memory cells corresponding to a plurality of word lines and connected in series;

a switching unit including a plurality of switching sub-units respectively corresponding to the plurality of memory block groups, each of the switching sub-units being disposed between a corresponding memory block group and a common source line independently of the word line to control connection or disconnection between the sub-source line and the common source line in the corresponding memory block group.

2. The three-dimensional memory according to claim 1, comprising a plurality of memory planes, all of the sub-source lines of each of the memory planes being connected to a same common source line via a respective sub-switch cell.

3. The three-dimensional memory according to claim 1, wherein the switch subunit comprises a PMOS transistor or an NMOS transistor.

4. The three-dimensional memory according to claim 1, wherein one end of each of the plurality of memory strings included in the memory block is commonly electrically connectable to a same sub-source line.

5. A detection device for performing leakage detection on the three-dimensional memory according to any one of claims 1 to 4, the detection device comprising:

6. The detection device according to claim 5, wherein: the detection device further comprises: and the channel detection module is configured to apply a channel detection voltage to the memory string where the memory cell is located while applying a turn-on voltage to the word line of each memory cell, and detect a second current flowing through the channel.

7. The sensing device of claim 5 or 6, wherein the plurality of memory cells of each of the memory strings is divided into a first group of memory cells and a second group of memory cells, wherein the word line sensing module is configured to:

8. The detection device according to claim 7, wherein a value of the applied first detection voltage is higher than a value of the applied second detection voltage.

9. The detection apparatus according to claim 8, wherein the value of the second detection voltage applied is zero.

10. The sensing device of claim 9, wherein even memory cells of the plurality of memory cells comprise the first group of memory cells and odd memory cells comprise the second group of memory cells.

11. The detection apparatus of claim 5, wherein the control module is configured to:

12. The detection apparatus of claim 6, wherein the control module is further configured to:

13. A three-dimensional memory device comprising a three-dimensional memory according to any of claims 1-4 and a detection device according to any of claims 5-12.

14. A detection method for performing leakage detection on the three-dimensional memory according to any one of claims 1 to 4, the detection method comprising:

applying a detection voltage to a word line of each of the memory cells and detecting a first current flowing through the word line; and

and controlling the on-off of the switch subunit according to the first current.

15. The detection method according to claim 14, characterized in that: the detection method further comprises the following steps: applying a channel detection voltage to a memory string where the memory cell is located while applying a turn-on voltage to a word line of each of the memory cells, and detecting a second current flowing through the channel.

16. The method of claim 14 or 15, wherein the plurality of memory cells of each of the memory strings is divided into a first group of memory cells and a second group of memory cells, wherein applying a sensing voltage to a word line of each of the memory cells comprises:

17. The detection method according to claim 16, wherein the first detection voltage is applied at a value higher than that of the second detection voltage.

18. The detection method according to claim 17, wherein the value of the applied second detection voltage is zero.

19. The sensing method according to claim 18, wherein even memory cells of the plurality of memory cells constitute the first memory cell group, and odd memory cells constitute the second memory cell group.

20. The detection method according to claim 14, wherein controlling the switching of the switch subunit according to the first current comprises:

21. The detection method according to claim 15, further comprising: