JP3146528B2 - Nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically erasable PROM (hereinafter referred to as EE) capable of electrically erasing data stored in a memory transistor and writing new data.
Non-volatile semiconductor storage device such as PROM).

[0002]

2. Description of the Related Art Conventionally, various researches and developments have been made on nonvolatile semiconductor memory devices in which written data is not lost even when the power is turned off. In recent years, the development of the EEPROM has rapidly progressed, and various products have been put to practical use. EE
There are various types of PROMs, and recently, a configuration in which memory transistors are connected in series has been proposed.

FIG. 21 is a circuit diagram of an example of such a nonvolatile semiconductor memory device. The code S _ij (i = 1, 2, j =
1 to 4) represent selection transistors with reference symbols Mi _{, j} (i = 1, 2).
2, j = 1 to 6) indicate memory transistors. The control gate electrode of the memory transistor is a word line X for each row.
_i (i = 1 to 6). The gate electrodes of the first selection transistor group (S ₁₁ , S ₂₁ , S ₁₃ , S ₂₃ in the figure) connected to the bit line among the selection transistors are connected to the first selection lines Z ₁ and Z ₃ , respectively. Of the second selection transistors S ₁₂ , S ₂₂ , S ₁₄ and S ₂₄ are connected to _second selection lines Z ₂ and Z ₄ , respectively. Further, the first selection transistor, the three memory transistors, and the second selection transistor form a pair and are connected in series between the bit lines Y ₁ and Y ₂ and the source line S. The bit lines Y ₁ and Y ₂ connect the drain electrodes of the selection transistors for each column. FIG. 18 is a plan view of a transistor group forming a pair from a bit line to a source line of the storage device.
FIG. 22 is a sectional view taken along line AA of FIG.

Here, 21 is a semiconductor substrate, 22a is a drain region of a first selection transistor, 22b is a source region of a second selection transistor, 22c is an impurity diffusion layer region connecting each transistor in series, and 32 is a first and a first. 2 selection transistor gate insulating film, 23 is a first gate insulating film of a memory transistor, 25 is a second gate insulating film of a memory transistor, 24 is a floating gate electrode, 30 is a control gate electrode, and 28 is a select gate electrode. Gate electrode,
29 is an interlayer insulating film, 30 is a contact hole, and 32 is a bit line metal wiring. A structural feature of this device is that the first gate insulating film of the memory transistor is as thin as 9 nm, for example, so that tunneling between the floating gate electrode-substrate and the floating gate electrode-source / drain electrode can easily occur. Also, this device performs electrical writing and erasing using this operation principle.

The principle of operation of this non-volatile semiconductor will be described first with reference to an example of an N-channel transistor as a series transistor group of S ₁₁ , M _1,1 , M _1,2 , M _1,3 and S ₁₂ in FIG. . FIG. 24 shows the potentials of the bit lines, the first and second selection lines, and the word lines in the data erasing, writing, and reading modes in this case. However, the unit of numerical values in the figure is volt (V).

Here, erasing data means a state in which electrons are injected into the floating gate electrode, and writing data means a state in which electrons are emitted from the floating gate electrode. When erasing data, a high voltage (for example, 17 V) is applied by setting the word lines X ₁ , X ₂ and X ₃ to the positive potential side and the bit line Y ₁ and the source line S to the ground potential side. Since 5 V is applied to the first selection line Z ₁ and the second selection line Z ₂ , the potentials of the channel and the source / drain electrodes are fixed to 0 V in this state, and the memory transistors M _1,1,. M
The electric field in the first gate insulating film 23 of _1,2 , M _1,3 becomes strong, and a Fowler-Nordheim tunnel phenomenon (hereinafter, referred to as FN tunnel phenomenon) occurs, and the semiconductor substrate and the impurity diffusion layer 22c. Then, electrons are injected into the floating gate electrode 24 through the first gate insulating film 24. As a result, the threshold voltage of each memory transistor M _1,1 , M _1,2 , M _1,3 increases. This state is the state where the data has been erased. In this erase mode, there is no selectivity of the memory transistor, so that data stored in all memories is erased at the same time. On the other hand, when writing data to the memory transistors M _1,1 , M _1,2 or M _1,3 , the bit line Y ₁ and the memory transistors M _1,1 , M _1,2 to be written, or The word lines X ₁ , X ₁ of the memory transistor connected to the bit line side of M _1,3
2 or X ₃ with a high potential (for example, 20 V),
Memory transistors M _1,1 , M _1,2 , M to be written
The word lines X ₁ , X ₂ , or X ₃ of the memory transistors connected to _{1, 3} and the source line side thereof are set to the ground potential. Then, the electric field in the first gate insulating film 23 of the write memory transistor becomes strong, and electrons are emitted from the floating gate electrode 24 toward the impurity diffusion layer 22c by the FN electron tunneling phenomenon. At this time, the memory transistor in which a high voltage is applied to the control gate electrode 30 and the drain electrode functions only as a transfer transistor. In addition, the electric field of the first gate insulating film 23 of the memory transistor in the bias state becomes small, and the F-
Does not cause N electron tunneling. Further, in a memory transistor connected to the source side of the write memory transistor, the potential of the control gate 27 becomes the ground potential.
Since the drain electrode potential is cut off by the write memory transistor, the potential does not increase. As a result, the electric field in the first gate insulating film decreases, and the FN electron tunnel phenomenon does not occur. Thereby, selective writing to the memory transistor is achieved. If the memory transistor to be subjected to writing of a plurality writes sequentially from the source side of the memory transistor in the manner described above with respect to the plurality of memory transistors connected to one selection transistor S _11. This is to protect already-written data due to electric field stress during writing to the memory transistor, that is, to prevent threshold fluctuation. When writing this data, the second
Second selection line Z ₂ which is connected to the gate electrode of the select transistor is required to be held at 0V. This is because even if the control gate electrode potential of the memory transistor is 0 V, the channel current flows in the case of the already-written memory transistor, so that the channel current is cut off.

When reading data stored in the memory transistor, the bit line Y ₁ is fixed at 1 V, the first selection line Z ₁ and the second selection line Z ₂ are fixed at 5 V, and the memory transistor to be read is selected. Connected word lines X ₁ , X
Only ₂ or X ₃ to connect all other 5V to the ground potential.
Then, when the selected memory transistor is in the erased state, no current flows from the bit line to the source line because the threshold voltage is positive. On the other hand, if the selected memory transistor is in a write state, a current flows because the threshold voltage is negative. All other memory transistors act as transfer gates. Therefore, the threshold value of each memory transistor must be controlled to be equal to or lower than the control gate electrode (for example, 5 V).

Next, from the four transistor groups shown in FIG.
Each of the memory transistors M _1,3 , M _2,3 ,
The bias states of the four transistor groups in the written state will be described using M _1,6 and M _2,6 as representatives. FIG. 25 shows the potentials of the word lines, the first and second selection lines, and the bit lines at this time. M _1,3 and M _2,3 are the same word line X ₃ and M
_1,6 and M _{2, 6} is a control gate electrode potential of the same word line X ₆ are controlled. Therefore, M _1,3 and M _2,3 , M
Selection between _1,6 and M _2,6 is made by bit lines Y ₁ , Y ₂ . For example, when M _1,3 is written and M _2,3 is not written, the bit line Y ₂ is maintained at an intermediate potential of 10 V. As a result, the bias state of M _2,3 is 0 V for the control gate electrode and 10 V for the drain electrode. It is in a state where it is applied. As a result, the first
The electric field applied to the gate insulating film of F is smaller than M _1,3 and F
-N Does not cause electron tunneling. Therefore M
There is no erroneous writing of a _few . At this time, the memory transistors M _2,1 and M _2,2 are in a bias state in which 20 V is applied to the control gate and 10 V is applied to the drain electrode. This state is also smaller than the voltage difference between the control gate and the drain electrode in the erased state described above, so that FN electron tunneling does not occur and erasing of the non-selected memory transistor of the non-written bit line during writing does not occur. M _{1, 6,} the word line for the M _{2, 6} is biased to 0V Moreover drain electrode bit lines by the first selection transistor S _13, S ₂₃ is the gate electrode is fixed at 0V by the first selection line Z ₃ Y _1, Y ₂ from off the voltage stress is erroneous erasing and erroneous writing not applied does not occur because it is made. In order to prevent erroneous writing of a memory transistor sharing a word line and erasure of an unselected memory transistor connected to a digit line to be written, for example,
An intermediate potential such as 0 V is required. In the case where the bit line is controlled only by binary voltages of, for example, 0 V and 20 V without using the intermediate potential, erroneous writing can be prevented by the sequential writing sequence from the source side memory transistor. The erasure of the write bit line non-selected memory transistor cannot be prevented from progressing. Because of this, the problem of over-erasure,
That is, an unintentional increase of the threshold value is caused. This is sometimes remarkable in memory transistors close to the bit line, and becomes a problem because the number of erases during writing increases as the number of memory transistors increases in series. For example, when the threshold value of the non-write transistor becomes higher than the control gate voltage at the time of reading, this problem leads to erroneous reading of data and becomes a fatal defect.

As described above, the conventional nonvolatile semiconductor memory device constructed by connecting the memory transistors in series includes (1) FN electron tunneling for both erasing and writing. (2) Other than the memory transistors, (2) Connect three select transistors in series between the bit line and the source line. (3) High, middle and low bit line potentials to prevent unintentional erasure of unselected transistors during writing And the like.

[0010]

However, as described above, the conventional nonvolatile semiconductor memory device requires three types of bit line potentials for selective writing, and furthermore, the intermediate potential and the high and low potentials are required. It is necessary to control the FN electron tunneling by the potential difference from the above, so that the voltage setting range is narrow. In particular, it is difficult to control the voltage setting of the intermediate potential, especially if the voltage setting is high or low, because it causes a defect.

Further, the problem of over-erasing, that is, the problem that the threshold value of the memory transistor rises above the control gate voltage at the time of reading remains in principle. In order to control this, there is a disadvantage in that the setting and control of the erase voltage is tightly controlled and the method for manufacturing the memory transistor is restricted, which causes a reduction in the manufacturing yield.

Since FN electron tunneling is used for both writing and erasing, a relatively high voltage is required for both writing and erasing, which is a high withstand voltage for both the bit line control transistor and the word line control transistor. The disadvantage is that the transistor and the junction must be used. Since only FN tunneling can be used for both writing and erasing, the first gate insulating film is, for example, 10 n
Only a thin insulating film such as an oxide film having a thickness of m or less can be used. For this reason, it is difficult to control the film thickness and film quality of the insulating film, and the manufacturing yield is low. Further, since writing can be performed only serially from the source line side, erasing and reprogramming of all bits are always necessary, and it is impossible to provide functions such as word erasing and word writing. This means that the time required for reprogramming is long, and even if it is used as a large-capacity nonvolatile memory, it has a drawback that its use is extremely limited.

The present invention has been made in view of such a problem, and does not require an intermediate potential in selective writing.
Enables writing at relatively low voltage, does not cause over-erasing and over-writing problems, has a wide voltage margin for writing / erasing,
It is an object of the present invention to provide a nonvolatile semiconductor memory device that can be manufactured even if the first gate insulating film is thick and can also have word writing / word erasing functions and is suitable for high integration.

[0014]

According to a first aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising a pair of a memory transistor having a floating gate electrode and a control gate electrode and a first selection transistor connected in parallel to one another. At least one second selection transistor is connected in series to an end of at least a plurality of transistors connected in series as a unit to form a memory array constituent unit transistor group, and the memory array constituent unit transistor group is arranged in a matrix. To form a first word line by connecting the control gate electrodes of the memory transistors for each row to form a first word line, and connecting the gate electrodes of the first selection transistors to each row for a second word line. A word line, and connecting the gate electrodes of the second selection transistors in a row to form a selection line; The Lee configuration unit transistor group 2
The drain electrodes of the selection transistors are connected to each other for each column to form a bit line, and the memory transistor at the end of the memory array constituent unit transistor group to which the second selection transistor is not connected and the selection transistor The source electrodes of the memory transistors are commonly connected to form a source line, and the channel portion of the first selection transistor and the channel portion of the memory transistor are provided adjacent to a predetermined region of the semiconductor substrate. Things.

Further, the nonvolatile semiconductor memory device of the second invention of the present application has at least a plurality of pairs each including a memory transistor having a floating gate electrode and a control gate electrode and a first selection transistor connected in parallel as one unit. At least one end is connected to the end of the transistor group connected in series.
A memory array configuration unit transistor group is formed by connecting two second selection transistors in series, and the memory array configuration unit transistor group is arranged in a matrix to form a memory array. Are connected to each row to form a first word line, the gate electrodes of the first selection transistors are connected to each row to form a second word line, and the gate electrodes of the second selection transistors are formed in a row. To the selection line, and the drains of the second selection transistors of the memory array configuration unit transistor group are connected for each column to form bit lines, and the second selection of the memory array configuration unit transistor group is performed. The source electrode of the memory transistor and the source electrode of the selection transistor that are not connected to The memory transistor is a pair of N-type impurity diffusion layers selectively formed on a surface portion of a P-type semiconductor substrate, and the pair of N-type impurity diffusion layers of the P-type semiconductor substrate. A first gate insulating film formed on the surface of the region sandwiched by the layers, a floating gate electrode formed on the first gate insulating film, and a central portion provided on the floating gate electrode so as to cross the central portion. A first inter-gate-electrode insulating film and the first inter-gate-electrode insulating film provided on a portion of the floating gate electrode where the first inter-gate-electrode insulating film is not provided;
A second gate insulating film thinner than the first inter-gate electrode insulating film, and a control gate electrode provided on the second gate insulating film, wherein the second word line is connected to the first inter-gate electrode insulating film. It is provided on the top.

[0016]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of a semiconductor chip showing a first embodiment of the present invention.

FIG. 2 is a sectional view taken along line AA of FIG. 1, and FIG.
FIG. 4 is a sectional view taken along line BB of FIG. 1, FIG.
1 is a sectional view taken along the line DD of FIG. 1, FIG. 6 is a sectional view taken along the line EE of FIG. 1, FIG. 7 is a sectional view taken along the line FF of FIG.
9 is a sectional view taken along line HH of FIG. However, in FIG. 1, metal wiring 15
a and 15b are not shown.

In this embodiment, a pair of a memory transistor M _1,1 ... Having a floating gate electrode and a control gate electrode and a first selection transistor S _1,1 . At least one second selection transistor Q ₁ ,... Is connected in series to an end of the three transistor groups connected in series to form a memory array constituent unit transistor group. The control gate electrodes of the above-mentioned memory transistors are connected to each other for each row to form a first word line X ₁ ,..., And a gate of the above-mentioned first selection transistor is formed. The electrodes are connected on a row-by-row basis to form second word lines Z ₁ ,..., And the gate electrodes of the second selection transistors are connected in rows to form select lines C ₁ ,. The drain electrodes of the second selection transistors of the memory array constituent unit transistor group are connected to each other for each column to form bit lines Y ₁ ,..., And the aforementioned second selection of the memory array constituent unit transistor group is performed. The source electrodes of the memory transistor and the selection transistor on the other end to which the memory transistor is not connected are commonly connected to form a source line S, and the memory transistor is connected to the surface of the P-type silicon substrate 1. A first gate insulating film 3 formed on the surface of a region between the pair of N-type impurity diffusion layers 2c selectively formed and the pair of N-type impurity diffusion layers of the P-type semiconductor substrate 1 described above. A floating gate electrode 4 formed on the first gate insulating film 3, a first inter-gate electrode insulating film 6 provided on the floating gate electrode 4 so as to traverse the central portion, and a first gate electrode 4 on the floating gate electrode 4. The second gate insulating film 5 which is thinner than the first inter-gate electrode insulating film 6 provided in the portion where the inter-gate electrode insulating film 6 is not provided, and the control gate provided on the second gate insulating film 5 The second word lines Z ₁ ,... Are formed of a polysilicon film (8) provided on the first inter-gate-electrode insulating film 6.
It is that.

Reference numeral 1 denotes a P-type semiconductor substrate having a resistivity of, for example, 13 Ωcm; 2a, 2b, and 2c denote N-type impurity diffusion layers formed by selectively introducing impurities such as As; A first gate insulating film of a memory transistor of a silicon film (hereinafter referred to as SiO ₂ film);
Is a floating gate electrode made of a polycrystalline silicon film having a thickness of 200 nm containing impurities such as P,
The second gate insulating film of the memory transistor consisting of SiO ₂ nm, the first gate electrode insulating film 6 is made of SiO ₂ having a thickness of 60nm for example, 7 for example, a thickness of 40n
The gate insulating film 8 of the first selecting transistor made of m ₂ SiO ₂ has a thickness of 300 n containing an impurity such as P, for example.
The gate electrode 9 of the first selection transistor made of a polycrystalline silicon film having a thickness of m is formed on the gate electrode of the first selection transistor made of, for example, SiO _{2 having a} thickness of 60 nm.
Is a control gate electrode of a memory transistor made of a polycrystalline silicon film having a thickness of 400 nm containing impurities such as P, for example.
It is a third inter-gate electrode insulating film made of SiO _{2 of} nm.

Here, the first gate insulating film 3 of the memory transistor covers the channel region of the memory transistor and insulates the floating gate electrode 4 from the P-type silicon substrate 1. The gate insulating film 7 of the first selection transistor covers a channel region of the first selection transistor, and the gate electrode 8 of the first selection transistor and the substrate 1
And insulate it. Further, the first inter-gate-electrode insulating film 6 insulates the floating gate electrode 4 from the gate electrode 8 of the first selecting transistor, and the second inter-gate-electrode insulating film 9 forms the gate electrode of the first selecting transistor. 8 and the control gate electrode 10 of the memory transistor, and the third inter-gate electrode insulating film 11 insulates the control gate electrode 10 of the memory transistor and the impurity diffusion layer 2c. Reference numeral 12 denotes a gate insulating film of a second selection transistor made of, for example, 30 nm thick SiO ₂ , and 13 denotes a gate electrode of a second selection transistor made of a 400 nm thick polycrystalline silicon film containing an impurity such as P. , 14a and 14b are contact holes, 15a and 15b are metal wirings made of a material such as Al, 16 is a field insulating film made of SiO ₂ having a thickness of 400 nm, for example, and 17 is a B film having a thickness of 800 nm and the like
This is an interlayer insulating film made of PSG.

In plan view, a memory transistor having a floating gate electrode and a first selection transistor are provided adjacent to each other in a substrate region whose channel regions are sandwiched between field insulating films 16. In addition, the floating gate electrode 4
Is provided to extend from the field insulating film region to the middle of the substrate region. This is for increasing the coupling capacitance with the control gate electrode 10. In addition, the control gate electrode 10 is connected between the rows to connect the first word line, the gate electrode 8 of the first selection transistor is connected to the row and connects the second word line, and the gate electrode 13 of the second selection transistor is connected. Are connected to each other to form select lines. A bit line contact 14a is opened in the impurity diffusion layer 2a constituting the drain electrode of the second selection transistor, and has a connection with the metal wiring 15a. This metal wiring 15a is not shown in FIG. The metal wiring is provided so as to connect the bit line contacts 14a to each other for each column, and forms a bit line. The source-side impurity diffusion layers 2c are connected in common, and a source line contact 14b is opened thereon to have a connection with the metal wiring 15b. This metal wiring 15b
Constitute a source line. The transistors arranged in series are connected by an impurity diffusion layer 2c. The impurity diffusion layers 2a and 2c and the channel region of the transistor are separated by a field insulating film 16 for each column.

A feature of the present invention is that a first selection transistor paired with a memory transistor connected in series first is provided in parallel with the memory transistor, and a channel region is provided adjacent to the transistor. Second, the gate electrodes of the first selection transistors are connected together in rows and used as second word lines.

The first feature is to reduce the area occupied by the memory cells. That is, since the memory transistor and the first selection transistor are provided without being separated by the field insulating film, the cell occupation area is correspondingly reduced. In connection with this feature, the gate electrode 8 of the first selection transistor, which is the second word line, is arranged across the floating gate electrode 4. But,
As shown in FIG. 1, the width is smaller than the width of the floating gate electrode, and as shown in FIG. 7, since the first inter-gate-electrode insulating film 6 is thick, the potential of the second word line is floating. The effect on the potential of the gate electrode can be ignored for the time being. The control gate electrode of the memory transistor is arranged to cover the gate electrode 8 of the first selection transistor. As a result, capacitive coupling between the control gate electrode 10 and the floating gate electrode 4 occurs in a region where the floating gate electrode 4 and the control gate electrode 10 face each other.

These first and second features provide a stable writing / erasing / reading operation of the device.

Next, the write / erase / read operation of the present invention will be described with reference to FIG. 10 which is a circuit diagram of FIG.

The symbol S _{i, j} (i = 1, 2, j = 1 to 6) is a first selection transistor, and the symbol M _{i, j} (i =
1, 2, j = 1 to 6) are memory transistors. The memory transistor M _{i, j} and the first selection transistor S
_{i, j form} pairs, and these pairs are connected in series in three pairs, for example, M _1,1 , M _1,2 , M _1,3 and S _1,1 , S
_1,2, form one transistor group consisting of S _2. The memory cell array is obtained by arranging a second selection transistor in series at the end of the transistor group as a memory cell array constituent unit transistor group. However, in the plan view of FIG. 1, the layout arrangement is such that the source diffusion layer wiring 2b and the bit line contact 14b are shared by two groups and turned back. The control gate electrode 10 of the memory transistor is connected to the first word line X for each row.
_i (i = 1 to 6) and the second word line Z _i (i = 1 to 6) for each row on the gate electrode 8 of the first selection transistor.
6). The drain electrode 15a of the second selection transistor in the memory cell constituent unit transistor group
Constitutes a bit line Y _i (i = 1, 2) for each column,
On the other hand, the memory transistor at the other end to which the second selection transistor is not connected and the source region 2b of the first selection transistor share a source line S (15
b). The gate electrode 13 of the second selection transistor is connected for each row, and the selection line C _i (i = 1,
Construct 2). FIG. 12 shows an example of the potential of each word line, bit line, and source line when a typical memory transistor is selected during a write operation. The unit of each voltage is volt (V). Note that writing here means increasing the threshold value of the memory transistor by injecting electrons into the floating gate electrode.

The writing in this embodiment utilizes hot electron injection by a channel current. For example, M
When writing to _{1, 1,} 6V through a transistor Q ₁ from the bit line Y ₁ to the drain electrode of the memory transistor is the control gate electrode than the first word line X ₁ 1
0V is supplied. On the other hand this is the first gate electrode of the selection transistor Q _{1, 1} forming the memory transistor and the pair is supplied with 0V by a second word line Z ₁ This transistor is turned off. Therefore, the current path from the drain electrode is only the path passing through the memory transistor M _1,1 .
On the other hand, another series-connected memory transistor M _1,2 , M _1,3 to which the memory transistor M _1,1 belongs.
Are all fixed at 0 V by the first word lines X ₂ and X ₃ . Another first selection transistor S
The second word lines Z ₂ and Z ₂ are connected to the gate electrodes of _1,2 and S _1,3 , respectively.
10V is supplied from ₃ to turn on. Therefore, the source electrode of the selected memory transistor M _1,1 is
Selection transistors S _{1, 2,} is connected to the source line S ₂ of the ground potential via the S _{1, 3.} Electrons are injected into the floating gate electrode hot electrons generated in the channel of M _{1, 1} channel current flows through the source line from the bit line Y ₁ this time. The selected memory transistors M _1,2 , M _1,3 in the same group are not written because the control gate electrode voltage is as low as 0 V and there is only a small potential difference between the source and drain electrodes. Similarly, memory transistors M _1,2
Is written, the gate electrode of the second selection transistor is set to 10 V, the control gate electrode potentials of the other memory transistors in the same group are all set to 0 V, and the gate electrodes of the other first selection transistors are set to 10 V. and a first gate electrode potential of the selection transistor S _{1, 2} it is sufficient to turn off the 0V. That is, the first selection transistor paired with the selected memory transistor blocks a path bypassing the memory transistor, and the other first selection transistors form a path bypassing the unselected memory transistor. , And acts as a transfer gate between the bit line and the source line.

A first word connected to another transistor group for preventing erroneous writing / erase of another memory transistor group connected to the same bit line represented by M _1,5 Lines X _{4 to} X ₆ , second word lines Z ₄ to
Z ₆ and the selection line C ₂ are all fixed at 0V. Therefore, no channel current flows through the memory transistor, and no writing occurs. Selective writing of memory transistors, for example, M _1,1 and M _2,1 connected to the same word line is realized by a bit line voltage. That time of writing of M _2,1 potential difference between the source and drain bit lines Y ₁ is fixed to 0V is not performed is writing to 0V. The even channel current by the bit line Y ₁ in the open state is not a writing not flow out.

Next, an example of erasure will be described. FIG.
FIG. 14 shows an example of the potential of each word line, bit line, and source line during the erase operation.

Here, erasing means reducing the threshold value of the memory transistor by emitting electrons from the floating gate electrode. Erasure in this example is realized as follows. That is, when a high voltage such as 18 V is applied to the source / drain region or one of them, and a low voltage such as 0 V is applied to the control gate electrode, the first gate insulating film in the first gate insulating film from the floating gate electrode to the source or drain region. The electric field becomes stronger. As a result, an FN tunneling phenomenon occurs via the first gate insulating film, and electrons are emitted.
Erasure utilizes the property of FN electron tunneling.

Erasing is possible from both the bit line side and the source line side. First, a case where erasing is performed from the source side will be described with reference to FIG.

In the case of batch erasing, there is no transistor selectivity, all the first word lines X _{1 to} X ₆ are set to 0 V, all the second word lines Z _{1 to} Z ₆ are set to 20 V, and the source lines are set to 20 V.
At V, all the select lines are set to 0V. As a result, the potential of the impurity diffusion layer on the source line side and the drain side of all the memory transistors is maintained at a high voltage, and erasing becomes possible.

When a word line is selected and erased, only the selected first word line is set to 0V, and all other first word lines and all second word lines are set to 20V. The selection line is set to 0 V, and each transistor group is cut off from the bit line. As a result, except for the selected word line, the electric field between the floating gate electrode and the source / drain electrode becomes small, and F
-Erasure is prohibited without tunneling of N electrons. As a result, only the memory transistor connected to the selected first word line is erased.

When erasing from the bit line side, as shown in FIG. 14, the source line S is opened and the bit lines Y ₁ , Y
₂ is the same as the case of erasing from the source line except that 20 V is applied.

FIG. 11A shows a change in the threshold value of the memory transistor in the write / erase mode.
In rise threshold when the write is performed for example, the control gate electrode potential V _G is 0V, no current flows I _D, the threshold if the erasure reversed is performed decreases, the control gate electrode potential V _G is 0V The current flows in.

FIG. 11B shows the variation of the memory transistor threshold with respect to time. Although only the method of electrically erasing data has been described, the erasing method may be, for example, batch erasing using ultraviolet irradiation.

Next, the operation at the time of reading will be described with reference to FIG.

0 V is applied to the control gate electrode of the selected memory transistor, and 0 V is applied to the gate electrode of the first selection transistor paired therewith to turn off the channel of the first selection transistor and turn off the channel of the memory transistor. Current path only for the part. The gate electrodes of the other first selection transistors to which the selected memory transistor belongs are all set to 5 V and turned on to set the current path from the bit line to the drain electrode of the selected memory transistor as a transfer gate transistor. A current path is formed from the selected memory transistor to the source line. As a result, if the selected memory transistor is in the write state and the threshold value is 0 V or more, the current path from the bit line to the source line is cut off by the memory transistor, and no current flows from the bit line to the source line. . Conversely, if the selected memory transistor is in the erased state and the threshold value is 0 V or less, a channel current flows through this memory transistor. This current appears as a current flowing out of the bit line. The "write" or "erase" state of the selected memory transistor corresponds to "absence" or "presence" of the current from the bit line, and this current is detected by a sense amplifier or the like connected to the bit line. Information is stored in association with “1” and “0”. The control gate electrode of the unselected memory transistor is 0
It may be V or 5V. This is because the memory transistor does not need to function as a transfer due to the presence of a pair of selection transistors. In the present invention, the threshold value of the non-selected memory transistor at the time of reading may be any value from the same meaning. In short, if the threshold value of the selection transistor is lower than the second word line voltage, this transistor functions as a transfer and the read function of the present device operates. The first word line, the second word line, and the selection line of the group to which the selected memory transistor does not belong are all fixed to 0V. This blocks the current path from the bit line through this group. Therefore, even if the threshold values of all the memory transistors in the other groups are 0 V or less, the operation is not affected. It is also possible to read memory transistors connected to the same word line in parallel. This is represented, for example, by simultaneously reading out M _1,1 and M _2,1 . That is, the bit line Y ₁
May output data in response to each of the current connected to the bit line Y ₂ in separate sense amplifier and.

The presence of the selection line has the following effects.
First, a parasitic leakage current flowing through the non-selected memory transistor at the time of writing can be cut off by the second selecting transistor, thereby enabling efficient writing. As a result, the threshold fluctuation width between writing and erasing can be widened. Second, since the diffusion layer connected to the bit line can be only the drain diffusion layer of the second selection transistor of each transistor group, the bit line capacitance can be reduced.

FIG. 16 is a plan view of a semiconductor chip showing a second embodiment of the present invention, FIG. 17 is a sectional view taken along line AA of FIG. 16, FIG. 18 is a sectional view taken along line BB of FIG. C- in FIG.
FIG. 20 is a sectional view taken along line C-D of FIG. 16.

In this embodiment, the memory transistor and the first
Only the structure of the paired portion of the selecting transistor of the second embodiment is different from that of the first embodiment. For this reason, only this portion is extracted and shown.

The features of this structure are, first, that the gate electrode 8 of the first selection transistor is on the control gate electrode 10 of the memory transistor, and second, that the channel region of the first selection transistor is used for the memory. It is provided below the opening 18 of the control gate electrode 10 of the transistor, and the gate electrode 8 of the first selection transistor contacts the gate insulating film 7 of the first selection transistor in this region and covers the channel region. It is.

According to this structure, the facing area between the floating gate electrode 4 and the control gate electrode 10 of the memory transistor can be increased, and strong capacitive coupling can be realized. The structure and configuration of the other parts are the same as those of the first embodiment, and the driving method, functions, and the like are not changed at all.

[0045]

As described above, according to the present invention, the first selection transistor is provided in parallel with each of the memory transistors connected in series so that its channel region is adjacent to the memory transistor channel region. A second word line for controlling a gate voltage of the first selection transistor is provided, and a second selection transistor is connected between the bit line and a pair of the memory transistor and the first selection transistor connected in series. The provision of the above has the following effects.

(1) There is no need to set an intermediate potential at the time of selective writing, and binary voltage setting may be used. Therefore, it is easy to design peripheral circuits and control circuits.

(2) The problem of overwriting / overerasing does not occur, that is, there is no upper limit or lower limit on the fluctuation of the threshold value of the memory transistor. For this reason, a large difference in threshold value fluctuation of the memory transistor at the time of writing / erasing can be obtained. Peripheral circuits,
In particular, the design of the write-related control circuit is simple and easy.
In addition, even if a difference in program characteristics occurs due to a variation factor at the time of manufacturing a transistor for a memory, it has an acceptable and high manufacturing yield.

(3) Since hot electron injection can be used for writing, the electric field in the first gate insulating film of the non-selected memory transistor at the time of writing can be reduced as compared with the time of erasing. Therefore, erroneous writing of the non-selected memory transistor connected to the same word line during writing can be easily prevented. In addition, since the control gate voltage at the time of writing can be reduced because the control gate voltage can be set to a low voltage such as 0 V, for example, the threshold after writing can be reduced by using a transistor having a high breakdown voltage drain in the decoder for driving the first word line. , And the design of the decoder becomes easy.

(4) The first gate insulation because the writing need not be performed by FN electron tunneling and the erasing can be performed by avalanche breakdown or ultraviolet irradiation other than by FN tunneling For example, 1
It is also possible to use a relatively thick oxide film such as 2 nm. Therefore, control at the time of manufacturing the insulating film is easy and the manufacturing yield is high.

(5) Since the drain voltage during writing may be low, the electric field between the floating gate electrode and the drain of the memory transistor can be set relatively weak. Therefore, erroneous erasure during writing to already written data is unlikely to occur. Therefore, there is no restriction on the writing order of the memory transistor group connected in series. Therefore, the design of the peripheral circuit is easy.

(6) Word erase / word write is possible. That is, only the information of a specific word line can be rewritten. Therefore, the stored data can be updated without erasing all bits and writing all bits. Therefore, the program time can be significantly reduced. Therefore, it is suitable for use in programs and storage of accumulated data as needed.

(7) Since the channel region of the first selection transistor is provided adjacent to the channel region of each memory transistor, the cell occupation area is small. Further, there is no need to provide any selection transistor on the source side of each transistor group, and the cell array area is small.

As described above, the present invention has many advantages.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor chip showing a first embodiment of the present invention.

FIG. 2 is a sectional view taken along line AA of FIG.

FIG. 3 is a sectional view taken along line BB of FIG. 1;

FIG. 4 is a sectional view taken along line CC of FIG. 1;

FIG. 5 is a sectional view taken along line DD of FIG. 1;

FIG. 6 is a sectional view taken along line EE of FIG. 1;

FIG. 7 is a sectional view taken along line FF of FIG. 1;

FIG. 8 is a sectional view taken along line GG of FIG. 1;

FIG. 9 is a sectional view taken along line HH of FIG. 1;

FIG. 10 is a circuit diagram of a memory array according to the present invention.

FIG. 11 is a diagram showing an I _D -V _G characteristic of the memory transistor in a write state and an erase state (FIG. 11A), and a characteristic diagram showing a temporal change of a threshold voltage during a write operation and an erase operation (FIG. 11); (B)).

FIG. 12 is a diagram used for describing a write operation of the nonvolatile semiconductor memory device of the present invention.

FIG. 13 is a diagram used to explain an erasing operation from a source line of the nonvolatile semiconductor memory device of the present invention.

FIG. 14 is a diagram used to explain an erasing operation from a dot line of the nonvolatile semiconductor memory device of the present invention.

FIG. 15 is a diagram used for describing a read operation of the nonvolatile semiconductor memory device of the present invention.

FIG. 16 is a plan view of a semiconductor chip showing a second embodiment of the present invention.

FIG. 17 is a sectional view taken along line AA of FIG. 16;

FIG. 18 is a sectional view taken along line BB of FIG. 16;

FIG. 19 is a sectional view taken along line CC of FIG. 16;

20 is a sectional view taken along line DD of FIG.

FIG. 21 is a circuit diagram of a conventional nonvolatile semiconductor memory device.

FIG. 22 is a plan view of a semiconductor chip showing a conventional example.

FIG. 23 is a sectional view taken along line AA of FIG. 22;

FIG. 24 is a diagram used for describing a write operation and a read operation of a conventional nonvolatile semiconductor memory device.

FIG. 25 is a diagram used for describing a bias state in a write state of a conventional nonvolatile semiconductor memory device.

[Explanation of symbols]

1,21 P-type silicon substrate 2a-2c, 22a-22c N-type impurity diffusion layer 3,23 First gate insulating film of memory transistor 4,24 Floating gate electrode 5,25 Second gate insulation of memory transistor Film 6 First insulating film between gate electrodes 7 Gate insulating film of first selecting transistor 8 Gate electrode of first selecting transistor 28 Gate electrode of first and second selecting transistors 9 Second insulating film between gate electrodes Film 10, 30 Control gate electrode 11 Third insulating film between gate electrodes 12 Gate insulating film of second selecting transistor 32 Gate insulating film of first and second selecting transistors 13 Gate electrode of second selecting transistor 14a , 14b Contact hole 15a, 15b Metal wiring 16 Field insulating film 17 Interlayer insulating film 29 Interlayer insulating film 31 Transfected hole 32 metal wiring C _1, C ₂ selected line M _{i, j} memory transistors Q _1, Q ₂ second selection transistors S source line S _i1 first selection transistor S _{i, j} first selection transistor S _2j second selection transistor X ₁ to X ₆ first word line Y _1, Y ₂ bit lines Z ₁ to Z ₆ second word line

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-34981 (JP, A) JP-A-4-298079 (JP, A) JP-A-5-36942 (JP, A) JP-A-4-349 351792 (JP, A) JP-A-4-218960 (JP, A) JP-A-4-71269 (JP, A) JP-A-1-235278 (JP, A) JP-A-2-112286 (JP, A) JP-A-3-85770 (JP, A) JP-A-3-296276 (JP, A) JP-A-3-14272 (JP, A) JP-A-60-1697 (JP, A) JP-A-54-110742 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (3)

(57) [Claims] An at least one pair of a memory transistor having a floating gate electrode and a control gate electrode and a first selection transistor connected in parallel as one unit is connected to at least a plurality of series-connected transistors. A memory array configuration unit transistor group is formed by connecting two second selection transistors in series, and the memory array configuration unit transistor group is arranged in a matrix to form a memory array. Are connected to each row to form a first word line, the gate electrodes of the first selection transistors are connected to each row to form a second word line, and the gate electrodes of the second selection transistors are formed in a row. To the selection line, and to drain the second selection transistor of the memory array constituent unit transistor group. The in-electrodes are connected for each column to form a bit line, and the memory transistor and the source electrode of the selection transistor at the end of the memory array constituent unit transistor group that are not connected to the second selection transistor. A non-volatile memory, characterized in that a channel portion of the first selection transistor and a channel portion of the memory transistor are provided adjacent to a predetermined region of a semiconductor substrate, wherein the channel portion is commonly connected to form a source line. Semiconductor memory device. 2. A transistor unit having a floating gate electrode and a control gate electrode, and at least one memory transistor and a first selection transistor connected in parallel as one unit, at least one of which is connected at least to one end of a transistor group connected in series. A memory array configuration unit transistor group is formed by connecting two second selection transistors in series, and the memory array configuration unit transistor group is arranged in a matrix to form a memory array. Are connected to each row to form a first word line, the gate electrodes of the first selection transistors are connected to each row to form a second word line, and the gate electrodes of the second selection transistors are formed in a row. To the selection line, and to drain the second selection transistor of the memory array constituent unit transistor group. The memory cells and the source electrodes of the selection transistors are connected to each other to form a bit line by connecting each of the columns to the other end of the memory array constituent transistor group to which the second selection transistor is not connected. Are commonly connected to form a source line, the memory transistor includes a pair of N-type impurity diffusion layers selectively formed on a surface portion of a P-type semiconductor substrate, and the pair of N-type impurity diffusion layers of the P-type semiconductor substrate. A first gate insulating film formed on a surface of a region sandwiched between the impurity diffusion layers, a floating gate electrode formed on the first gate insulating film, and a central portion on the floating gate electrode. A first inter-gate-electrode insulating film provided on a portion of the floating gate electrode on which the first inter-gate-electrode insulating film is not provided; And a control gate electrode provided on the second gate insulating film, and the second word line is provided on the first inter-gate-electrode insulating film. Nonvolatile semiconductor memory device. 3. The channel portion of the first selection transistor is provided adjacent to the channel portion of the memory transistor, and the floating gate electrode is provided to extend from above the first gate insulating film and extend above the field insulating film. 3. The nonvolatile semiconductor memory device according to claim 2, wherein