JP2582412B2 - Nonvolatile semiconductor memory device - Google Patents

Description

[Contents] Industrial application field Conventional technology (FIGS. 6 and 7) Problems to be Solved by the Invention Means for Solving the Problems Action Embodiment One embodiment of the present invention (FIGS. 1 to 4) Another embodiment of the present invention (FIG. 5) Effects of the Invention [Overview] Regarding a nonvolatile semiconductor memory device, integration in the word line direction can be easily performed.
It is an object of the present invention to provide a nonvolatile semiconductor memory device capable of improving reliability, in which a bit line is connected to a drain diffusion layer through a drain contact hole, and a first select line is connected to the drain diffusion layer. The transistors are arranged in two rows,
The first select transistor is composed of an enhancement type transistor and a depletion type transistor which are connected in series as appropriate, a source line is arranged so as to be orthogonal to the bit line, and a second select transistor is connected to the source line. A plurality of cell transistors each having a floating gate and a control gate are connected in series so as to connect transistors in one row and connect between the first select transistors in two rows and the second select transistors in one row. Configure.

[Industrial applications]

The present invention relates to a nonvolatile semiconductor memory device having a NAND structure, and more particularly, to a nonvolatile semiconductor memory device capable of realizing high integration.

In a nonvolatile semiconductor memory device having an electrically erasable NAND type structure, for example, when writing is performed, writing can be performed by channel hot carriers and hot electrons by avalanche.

[Conventional technology]

6 and 7 are views for explaining a conventional nonvolatile semiconductor memory device. FIGS. 6A and 6B show details of the structure of the conventional example, and FIG. It is a circuit block diagram. 6 (a) is a plan view (a view of the cell array as viewed from above), and FIG. 6 (b) is a cross-sectional view in the XY direction shown in FIG. 6 (a).

In these figures, 31 is a substrate made of, for example, Si, 32
Is a source diffusion layer, which functions as the source line 32a. 33 is a source / drain diffusion layer, 34 is a drain diffusion layer, 35 is an interlayer insulating film made of, for example, SiO ₂ , 36a is a floating gate made of, for example, polysilicon, 36b
Is a gate made of, for example, polysilicon, 37 is a control gate made of, for example, polysilicon, 38 is, for example, PSG
The passivation film 39 made of is a wiring layer made of, for example, Al and functions as the bit line 39a. Four
0 is a cover film made of, for example, PSG, 41 is a drain contact hole, and 42 is a field oxide film made of, for example, SiO ₂ , which functions as an insulating region of a transistor. 43 is a word line, 44a, 44b and 44c are cell transistors, and 45a, 45b and 45c are select transistors.

Note that the word line 43 includes a floating gate 36a and a control gate 37.

In the above-mentioned conventional nonvolatile semiconductor memory device, a select transistor is used in a NAND type structure, and the source line 32a
Select transistors 45a and 45b are provided adjacent to the drain contact hole 41, and cell transistors having a plurality of floating gates 36a and control gates 37 are arranged between the select transistors 45a and 45b. The drain contact hole 41 is located at every other bit of the cell transistor row in the direction of the bit line 39a, and the wiring as the bit line 39a is formed so as to contact the drain diffusion layer 34 via the drain contact hole 41 in this row. Layer 39 is connected.

[Problems to be solved by the invention]

However, in such a conventional nonvolatile semiconductor memory device, as shown in FIG.
In the case of performing integration in 43 directions (arrow W shown in FIG. 6A), the integration adds the pitch of the wiring layer 39 (the width of the wiring layer 39 and the interval between the wiring layers 39 and 39). The wiring layer 39 is determined by reducing the width of the wiring layer 39.
And the wiring layers 39 are short-circuited due to the reduced spacing between the wiring layers 39.

Accordingly, it is an object of the present invention to provide a nonvolatile semiconductor memory device that can easily be integrated in a word line direction and can improve reliability.

[Means for solving the problem]

In order to achieve the above object, in a nonvolatile semiconductor memory device according to the present invention, a bit line is connected to a drain diffusion layer via a drain contact hole, and first select transistors are arranged in two rows so as to be connected to the drain diffusion layer. The first select transistor is appropriately connected in series with an enhancement type transistor and a depletion type transistor, and the second select transistor is arranged so that a source line is orthogonal to the bit line and is connected to the source line. Are arranged in one row, and a plurality of cell transistors having a floating gate and a control gate are connected in series so as to connect between the first select transistor in two rows and the second select transistor in one row. It is configured.

[Action]

According to the present invention, the bit line is connected to the drain diffusion layer through the drain contact hole, the first select transistors are arranged in two rows so as to connect to the drain diffusion layer, and the first select transistor is connected to the enhancement type transistor. Depletion type transistors are connected in series as appropriate, the source lines are arranged so as to be orthogonal to the bit lines, the second select transistors are arranged in one row so as to be connected to the source lines, And a plurality of cell transistors each having a floating gate and a control gate are connected in series so as to connect the select transistor of FIG.

Therefore, in the related art, two bit lines and two drain contact holes are required for two columns of select transistors, but in the present invention, only one bit line and one drain contact hole are required. Thus, the number of bit lines and the number of drain contact holes can be reduced, and integration in the word line direction can be performed without impairing reliability.

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

FIGS. 1 to 5 are diagrams for explaining an embodiment of a nonvolatile semiconductor memory device according to the present invention.
(B) is a diagram showing the details of the structure of one embodiment, FIG. 2 is a circuit block diagram of one embodiment, FIG. 3 is a diagram explaining the operation principle of one embodiment, and FIG. It is a figure explaining a manufacturing method. FIG. 1A is a plan view (a view of the cell array viewed from above), and FIG. 1B is a cross-sectional view in the XY direction shown in FIG. 1A.

In these figures, 1 is a substrate made of, for example, Si, 2
Is a drain diffusion layer, 3 is a source / drain diffusion layer, 4a is a floating gate made of, for example, polysilicon, 4
b and 4c are gates made of, for example, polysilicon, 5 is a control gate made of, for example, polysilicon, 6 is an interlayer insulating film made of, for example, SiO ₂ , 7 is a wiring layer made of, for example, Al, and functions as a bit line 7a. is there. 8 is a cover film made of, for example, PSG, 9 is a field oxide film made of, for example, SiO ₂ , 10 is a drain contact hole, 11
Is an enhancement transistor, 12 is a depletion transistor, 13 is a word line, 14 is a cell transistor, 15 is a gate oxide film made of, for example, SiO ₂ , 16 is a first polysilicon film, and 17 a and 17 b are made of, for example, SiO ₂ A silicon oxide film, 18 a second polysilicon film, 19 a passivation film made of, for example, PSG, 20 a first select transistor, 21 a second select transistor, 22
Is a source line.

The gate 4b is a depletion type transistor 12
The gate 4c is the gate of the enhancement transistor 11.

 Next, the manufacturing method will be described.

First, as shown in FIG. 4A, a transistor region is formed by selectively oxidizing the substrate 1 by, for example, a thermal oxidation method to form a gate oxide film 15. At this time, the field oxide film 9 selectively formed in advance as shown in FIG. 1A becomes an insulating region. Next, after ion implantation for the channel of the cell transistor is performed in the cell transistor region of the substrate 1, polysilicon is deposited on the gate oxide film 15 by, for example, the CVD method, and unnecessary portions of the polysilicon are selected by, for example, the CVD method. Etching to form a first polysilicon film 16.

Next, as shown in FIG. 4 (b), the first polysilicon film 16 is oxidized by, for example, a thermal oxidation method to form a silicon oxide film.
After forming 17a, ion implantation for the channels of the enhancement type transistor and the depletion type transistor is performed on the enhancement type transistor and the depletion type transistor region of the substrate 1, and then polysilicon is deposited so as to cover the entire surface by, for example, a CVD method. Then, a second polysilicon film 18 is formed.

Next, as shown in FIG. 4 (c), after selectively patterning the second polysilicon film 18, the first polysilicon film 16 is patterned by self-alignment. At this time, the first polysilicon film 16 becomes a floating gate of the cell transistor, and the second polysilicon film 18 formed on the first polysilicon film 16 via the silicon oxide film 17a becomes a control gate. Gate oxide film 15
The second polysilicon film 18 formed thereon serves as a gate of the depletion type transistor and the enhancement type transistor.

Next, as shown in FIG. 4D, the first polysilicon film 16 and the second polysilicon film are formed by, for example, a thermal oxidation method.
After oxidizing 18 to form the silicon oxide film 17b, the drain diffusion layer 2 and the source / drain diffusion layer 3 are formed by, for example, an ion implantation method. Next, a passivation film 19 is formed so as to cover the entire surface by, for example, a CVD method.

Next, as shown in FIG.
After selectively forming the drain contact hole 10 by selectively etching the passivation film 19 and the gate oxide film 15, Al is deposited on the entire surface by, for example, a sputtering method, and the drain diffusion layer 2 is formed through the drain contact hole 10. The wiring layer 7 is formed so as to take a contact. And
For example, by forming the cover film 8 so as to cover the entire surface by the CVD method, the nonvolatile semiconductor memory device is completed.

That is, in the above embodiment, as shown in FIGS. 1 to 3, the bit line 7a is connected to the drain diffusion layer 2 through the drain contact hole 10, and the first select line is connected to the drain diffusion film 2. Transistors 20 are arranged in two columns for one bit line 7a, and the first select transistor 20 is connected to the enhancement type transistor 11
And the depletion type transistor 12 are connected in series as appropriate. The source line 22 is arranged so as to be orthogonal to the bit line 7a, and the second line is connected to the source line 22.
Are arranged in one row, and the first
The floating gate 4a is connected to connect the select transistor 20 of the
And a plurality of cell transistors 14 each having the control gate 5 are connected and arranged in series, so that integration in the direction of the word line 13 can be performed and reliability can be improved. Specifically, in the case of the conventional two-row cell transistor 14, two bit lines and two drain contact holes are required, but only one bit line and one contact hole are required. The number of bit lines and the number of drain contact holes can be reduced, and integration in the word line direction can be performed. And bit line 7a
(Wiring layer 7) Disconnection of the bit line 7a due to the reduction of the width and shorting of the bit line 7a and the bit line 7a by reducing the interval between the bit line 7a and the bit line 7a are shorter than those of the conventional one. It is less likely to occur and reliability can be improved.

Next, the operation principle will be described with reference to FIG.

Here, two rows of first select transistors 20 on the side of the drain contact hole 10 are appropriately connected in series by an enhancement type transistor 11 and a depletion type transistor 12, and a plurality of cell transistors in two rows are formed.
14, and bit lines A, B,
It suffices if C and D can be selected as appropriate. That is, the bit line 7a is set to High, and the enhancement type transistor 11 and the depletion type transistor
Only the column A in which 12 is set to High is selected. And, in order, the enhancement type transistor of the line
When 11 and the depression type transistor 12 are set to High, the columns B, C and D are selected in order. Therefore, the two columns of first select transistors 20 are appropriately connected in series by the enhancement type transistor 11 and the depletion type transistor 12, so that the two columns of cell transistors
Although 14 required two bit lines and two drain contact holes in the conventional device, the number of bit lines and the number of drain contact holes were reduced by using only one bit line and one drain contact hole. Can be reduced.

Next, the operation principle will be described more specifically with reference to FIG. Here, the cell transistor 14 in the dotted line section M shown in FIG. 3 is selected, and write (write) and erase (era) are performed.
se) and reading (read). Incidentally, S word line 13 of the second select transistor 21 is the source line 22, S _{1 is, W 1, W 2, W} 3 word lines 13 of the cell transistor _{14, S 2, S 3,} S 4, S 5 Is the word line 13 of the first select transistor 20.

 First, the case where writing is performed will be described.

The conditions bitline 7a of b ₁ is open (OPEN),
b ₂ bit line 7a is 20V, S source line 22 is OV, S
₁ , the word line 13 of S ₂ , S ₄ and S ₅ is Low, the word line 13 of S ₃ is High, the word line 13 of W ₁ and W ₂ is OV, and the word line 13 of W ₃ is 20 V. Specifically, bit line 7 of b ₁
It left open because a is not selected, b ₂ of the bit line 7a
Apply 20V voltage to select only. Then, the cell transistor columns in the cell transistors 14 of the M portions by High word line 13 of the S ₃ is selected. Here, in the case of E ² PROM type writing, the floating gate
Since a case of writing by putting holes 4a, the cell transistor 1 for writing M portions by applying the same voltage 20V and the bit line 7a of b ₂ to the word line 13 of the W ₃
4 is OV. Cell transistor 1 for writing M part
4 OV to gate, 20V to drain, float to source (OV
May be written). And after writing, the depletion type transistor
It becomes 12, and it can be determined that writing is performed because the current flows even when OV is applied.

 Next, a case where reading is performed will be described.

The conditions bitline 7a of b ₁ is opened, the bit line 7a of b ₂ is 5V, the source line 22 of the S is OV, the word line 13 of the S _1, S ₃ is High, the word line 13 of the S ₂ is OV, S ₄ , S ₅
Word line 13 is Low, W ₁ and W ₃ are 5
V, the word line 13 of the W ₂ is OV. More specifically, it is possible to read and read the M transistor by reading OV at the gate, 1-5 V at the drain, and OV at the source of the cell transistor 14 to be read. After reading, it is possible to determine whether the transistor is the enhancement type transistor 11 or the depletion type transistor 12, and it is possible to determine whether data is written or erased.

 Next, the case of performing erasure will be described.

The conditions, the bit line 7a of b ₁ is OV, the bit line 7a of b ₂ is OV, the source line 22 of the S is OV, S _1, S _2, S _3,
The word lines 13 of S ₄ and S ₅ are High, and the word lines 13 of W ₁ , W ₂ and W ₃ are 15V. Specifically, electrons can be erased by putting electrons from the drain into the floating gate 4a. That is, erasing can be performed by setting the gate of the cell transistor 14 to be erased in the M portion to 20 V, the drain to OV, and the source to OV. After the erasure, the enhancement transistor 11 is obtained.

In the above embodiment, as shown in FIGS. 4 (a) to 4 (c), select transistors (enhancement type transistors 11 and depletion type transistors 1 and 2) are used.
The case where the gate of 2) is formed by the second polysilicon film 18 has been described, but the present invention is not limited to this, and as shown in FIGS. 5A and 5B, the select transistor The case where the 20 gates are formed of the first polysilicon film 16 may be adopted. More specifically, as shown in FIGS. 5A and 5B, a gate oxide film is formed on the substrate 1.
15. After a first polysilicon film 16, a silicon oxide film 17a and a second polysilicon film 18 are sequentially formed, the second polysilicon film 18 is patterned. Note that ion implantation for the channels of the select transistor and the cell transistor is performed after the gate oxide film 15 is formed. Next, by patterning the first polysilicon film 16, a gate of the select transistor including the first polysilicon film 16 is formed.

〔effect〕

According to the present invention, there is an effect that integration in the word line direction can be easily performed and reliability can be improved.

[Brief description of the drawings]

1 to 5 are diagrams for explaining an embodiment of a nonvolatile semiconductor memory device according to the present invention. FIG. 1 is a diagram showing details of the structure of one embodiment, and FIG. 2 is an embodiment. FIG. 3 is a diagram illustrating an operation principle of one embodiment, FIG. 4 is a diagram illustrating a manufacturing method of one embodiment, and FIG. 5 is a diagram illustrating a manufacturing method of another embodiment. 6 and 7 are diagrams for explaining a conventional nonvolatile semiconductor memory device, FIG. 6 is a diagram showing details of the structure of the conventional example, and FIG. 7 is a circuit block diagram of the conventional example. DESCRIPTION OF SYMBOLS 1 ... Substrate, 2 ... Drain diffusion film, 3 ... Source / drain diffusion layer, 4a ... Floating gate, 4b, 4c ... Gate, 5 ... Control gate, 6 ... Interlayer insulating film, 7 ... Wiring layer, 7a bit line, 8 cover film, 9 field oxide film, 10 drain contact hole, 11 enhancement transistor, 12 depletion transistor, 13 word line, 14 ... cell transistor, 20 ... first select transistor, 21 ... second select transistor, 22 ... source line.

Claims (1)

(57) [Claims] A bit line is connected to a drain diffusion layer via a drain contact hole, and first select transistors are arranged in two rows so as to be connected to the drain diffusion layer, and the first select transistor is enhanced. A source transistor and a depletion type transistor are connected in series as appropriate, a source line is arranged so as to be orthogonal to the bit line, and a second select transistor is arranged in one row so as to be connected to the source line. A plurality of cell transistors each having a floating gate and a control gate are connected in series so as to connect between two rows of the first select transistors and one row of the second select transistors. Nonvolatile semiconductor memory device.