JPH0228905B2 - - Google Patents

Description

[Detailed Description of the Invention] Semiconductor memories are capable of large-scale integration (hereinafter referred to as LSI) due to the fact that stored information can be retrieved easily and at high speed as electrical signals and the development of integrated circuit (hereinafter referred to as IC) technology. Due to its improved bit density and reliability, it has recently been used as a high-speed memory device for electronic computers.

However, unlike magnetic memories, semiconductor memories have the disadvantage that when the supply of bias electrodes is cut off, the stored contents disappear (hereinafter referred to as volatility). In order to obtain a semiconductor memory that does not have this drawback, research has been carried out on the memory function of semiconductor glasses such as chalcogenide glass, but this has not yet reached a practical stage.

In addition, as a non-volatile semiconductor memory, in the field of silicon semiconductor ICs, MNOS field effect transistors having a structure of metal (M), silicon nitride film (N), silicon oxide film (O), and silicon (S) are used. However, in this case, the silicon oxide film (SiO ₂ ) must be made thin enough to allow carriers on the semiconductor surface to tunnel, so pinholes are likely to occur in the silicon oxide film, and the storage mechanism is likely to be trapped. Because of this, there is a risk that productivity and reproducibility may be degraded due to the position, and for this reason, it has not been put to practical use in electronic computers.

By the way, as a field of semiconductor memory other than these, there is a read-only memory (hereinafter referred to as ROM) which is designed to read fixed storage contents by taking advantage of the high bit density and high speed of semiconductor memory. this
There are two types of ROM configuration methods, one of which is the IC
This is a method of attaching fixed information to the glass mask used for photo-etching when making. The other method is to manufacture ICs uniformly regardless of the content to be stored, and then electrically write information in accordance with the content to be stored.

Three methods of the latter method are known.
That is, the first method is to fuse the wiring with a current pulse, the second method is to use the memory characteristics of alumina traps, and the third method is to use the memory characteristics of alumina when no channel current flows. Due to the avalanche breakdown of the junction between the drain and the semiconductor substrate, a carrier having the same shape as the semiconductor substrate is injected into the oxide film, and this carrier charges the polycrystalline silicon thin film layer in which the oxide film is embedded, so that information can be written. This is the way it was done.

The present invention improves the third method among these three methods and provides a new avalanche writing configuration that can further expand the functionality. First, the conventional method will be explained in more detail with reference to FIG. do. In this case, the first
As shown in FIG. A field effect transistor 7 is formed with a silicon polycrystalline layer 6 embedded in the silicon polycrystalline layer 6. In this field effect transistor 7, as the drain voltage increases, the depletion layer 8 spreads from the drain region 2 into the substrate 1.
In particular, the electric field is concentrated in the lower part 9 of the silicon polycrystalline layer 6 as shown by the arrow, becoming higher than other parts of the depletion layer 8, and finally reaches the critical electric field for avalanche breakdown. At this time, electron-hole pairs of electrons 10 and holes 11 are generated in this portion 9 as shown in FIG. It is accelerated in the direction of the film 4, thereby obtaining high energy and causing the oxide film 4 to
is injected into the. The electrons 10 injected in this manner pass through the oxide film 4 and reach the silicon polycrystalline layer 6, charging it negatively. On the other hand, the holes 11 are transported to the drain region 2 as shown by an arrow 13 by the electric field.

In this way, information can be written by obtaining a charged state of the silicon polycrystalline layer 6, and on the other hand, information once written in this way can be erased in principle by irradiating the field effect transistor 7 with ultraviolet rays or X-rays. Can be done. However, according to the configuration of the present invention, which will be described later, the present invention does not specify whether the information written by avalanche is erased or not, or even if it is erased, which method is used. However, in general, for erasing or rewriting, hot carrier injection, which has been proposed separately by the present applicant, is convenient.

Next, since the present invention is based on a configuration in which the gate electrodes are stacked with first and second layers, this configuration will be described with reference to FIG. 2. 21 is a second gate electrode 2 on an insulating film 27 made of a silicon oxide film.
The field effect transistor 7 has the same structure as the field effect transistor 7 shown in FIG. 1 except that the field effect transistor 3 is provided.

In FIG. 2, 22 is a gate insulating film, 24 is a semiconductor substrate, 25 is a drain region, 26 is a source region, 27 is an insulating film continuous with the gate insulating film 22, and 28 is the gate insulating film 22 and the semiconductor substrate. Insulating film 2
The first gate electrode buried between the electrodes 7 and 29 represents a depletion layer, respectively.

According to the present invention, in order to inject carriers in the substrate 24 into the gate insulating film 22 of the field effect transistor 21, the second gate electrode 23 is kept at the same potential as the substrate 24, and the drain region is 25 is applied with a voltage higher than the breakdown voltage between it and the substrate 24. In this way, an avalanche breakdown occurs between the drain region 25 and the substrate 24, and based on the electric field between the electrode 28 and the breakdown point, charge carriers having a sign opposite to that of the channel carrier charges are accelerated in the direction of the electrode 28. is injected into the insulating film 22, and eventually
Electrode 28 will be charged to the opposite polarity to the channel carrier. At this time, the potential of the gate electrode 23 is changing in the opposite direction to the avalanche potential of the drain, so that the potential of the gate electrode 23 is
It has the effect of making it easier to attract charges of the opposite sign to the drain, and also plays the role of reducing the avalanche potential of the drain. As a specific measurement example is shown in FIG. 7, this effect improves the operating speed of this nonvolatile memory, and in an array configuration, it increases the reliability of writing only to elements at selected addresses. increase.

FIG. 3 shows an embodiment of the present invention, in which the electrodes 33 buried in the insulating films 22 and 27 have a so-called offset configuration in which the electrodes 33 overlap only a portion of the channel region. It is said that According to this configuration, the effect shown in FIG. 2 is obtained, and since an electric field 34 is directly formed between the remaining portion of the channel region and the portion of the gate electrode 23 facing thereto, the remaining portion of the channel region A channel 35 can be induced in the part by the electric field 34, and by controlling the change in the electric field 34, the on/off operation of the field effect transistor 21 can be controlled more reliably and with greater flexibility than in the configuration shown in the second figure. . However, also in FIGS. 2 and 3 mentioned above and FIGS. 4 and 5 described below, the possibility of hot carrier injection from the pinch-off regions 31, 39, and 39' is shown in the drawings. However, as is clear, this is not the gist of the present invention, and merely represents one possibility; in the present invention, the written information is given by avalanche surrender, and in that state, the information content is changed. This provides an element that is not subject to rewriting or modification.

FIG. 4 shows another embodiment of the present invention, in which the electrode 33 is provided with a through hole 36 across its thickness.
Since an electric field 37 is directly formed between the opposing portions of the substrate 24 facing the through hole 36, a channel 38 is induced in the region of the substrate 24 facing the through hole 36 by this electric field 37.

Furthermore, FIG. 5 shows a modification of the configuration of FIG. 3, in which the electrode 34 has an offset structure similar to that shown in FIG. 3 and a through hole 36 similar to that shown in FIG. , and thus has the same effects as described above with respect to FIGS. 3 and 4, respectively.

Note that in the configurations shown in Figures 3 to 5, the source or drain region used to inject carrier charges into the gate electrode 33 by avalanche deposition and the gate electrode 33 over the surface junction between the region and the region 24. It is clear from the spirit of the present invention that the area is a partially covered area.

In order to confirm the effect of the second gate electrode of the present invention, an experiment was conducted using the field effect transistor shown in FIG. 6, and as a result, the relationship shown in FIG. 7 was obtained. In this case, the semiconductor substrate 24 has an impurity concentration of 5×10 ¹³
The source region ²⁶ is made of silicon and is n-type with
The surface impurity concentration near the junction with region 46 is approximately
10 ¹⁶ pieces/cm ³ , thickness of gate insulating film (SiO ₂ ) 22 ι ₁
is about 1000 Å, and the thickness of the insulating film (SiO ₂ ) 27 is about ι ₂
1000 Å, the channel length L is about 10 μ, and the voltage of the buried gate electrode (Si) is “1” with respect to the substrate 24.
Measure the time required to change from 0V to -4V equivalent for writing, and from -4V to 0V equivalent for "0" writing, and send the results to the second gate 23.
(Aι) and the terminal voltage V _GS of the source region 26 (P)
It is expressed as time t for

In FIG. 7, the symbols indicate the values obtained when the drain terminal D and the source terminal s are grounded, the substrate terminal B is given a positive bias, and the reverse current in the junction between the source region 26 and the region 46 is 100 μA. The sign of the curve is when the substrate terminal B is grounded, the drain terminal D is given a negative bias, the source terminal S is given a slight negative bias, and the reverse current at the junction between the substrate 24 and the drain region 25 is 10 μA. The curves obtained are shown respectively.

These measurement results show that by providing a second gate electrode and applying a potential change in the opposite direction to the avalanche potential of the source or drain region, it is possible to significantly speed up the writing time. , is smaller than when the bias is not applied to the second gate electrode, so it can be seen that writing can be performed reliably.

As described above, according to the present invention, it is possible to obtain a semiconductor memory that combines the high speed of readout that semiconductor memory inherently has and the nonvolatile memory that has conventionally been put into practical use only with magnetic memory. When manufacturing such a memory, it is possible to easily manufacture it at high density using conventional silicon gate technology or molybdenum gate technology without requiring any other special technology. Further, it is possible to efficiently inject carriers into the first gate electrode, and furthermore, it is possible to perform on/off control using the second insulated gate regardless of the carrier accumulation state of the first gate electrode.

In the above explanation, the storage content is digital information of "1" and "0", but it is clear that it can also be used to store non-volatile analog information, and it can also be used for digital systems, for example, by applying the transistor of the present invention to memory cells. In this case, the specific static configuration of the circuit of the cell concerned can be achieved by using ordinary circuit technology.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a field effect transistor for explaining a conventional information writing method, and FIG. 2 is a sectional view showing a storage field effect transistor for explaining an example of a nonvolatile memory storage method according to the present invention. , FIG. 3 to FIG. 5 are cross-sectional views showing one embodiment of the present invention, FIG. 6 is a schematic configuration diagram of an example element created to demonstrate the effects of the present invention, and FIG.
It is a figure which shows the experimental result using the illustrated element. In the figure, 21, 45, 70... memory field effect transistor, 22... gate insulating film, 23... second gate electrode, 24... semiconductor substrate, 25...
Drain region, 26... Source region, 27... Insulating film, 28... First gate electrode, 29, 47...
...depletion layer, 30, 35, 38...channel, 3
1, 39, 39'...pinch-off area, 36...
Through hole.

Claims (1)

[Claims] 1 A first semiconductor region, a drain region and a source region formed separately in the first semiconductor region, and a gate insulator attached to the surface of the first semiconductor region at least between the drain region and the source region. a first gate electrode buried between the gate insulating film and the insulating film continuous thereto; and a first gate electrode buried between the gate insulating film and the insulating film continuous thereto, and a region on the first gate electrode and the source region via the insulating film. - a second insulated gate electrode provided on the surface of the first semiconductor region between the drain regions, and the second gate electrode is provided on the surface of the first semiconductor region between the source and drain regions. and an avalanche at a junction between the source region or drain region under the first gate electrode and the first semiconductor region, and having a portion directly opposing each other through an insulating film without intervening the first gate electrode, and an avalanche at a junction between the source region or drain region under the first gate electrode and the first semiconductor region A partially gated nonvolatile memory characterized in that write information is given by surrender.