JP3556491B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an LSI incorporating a nonvolatile memory, and more particularly to a semiconductor memory including a plurality of polysilicon layers such as an EEPROM (Electrically Erasable Programmable ROM), and a peripheral structure and a manufacturing method thereof.
[0002]
[Prior art]
The EEPROM is a nonvolatile memory in which data can be electrically written / erased by a user. In recent years, as a non-volatile memory mixed LSI integrated on the same chip together with a CMOS logic such as an ASIC (Application Specific Integrated Circuit), it is used in a wide range of fields including information devices such as portable devices and IC cards.
[0003]
FIG. 11 is a cross-sectional view showing a structure example of a general EEPROM memory cell in which data can be written / erased bit by bit. Each memory cell is formed with a memory transistor and a selection transistor connected in series with the memory transistor, and a single cell is composed of two transistors.
[0004]
As shown in the figure, the memory transistor has a two-layer polysilicon structure having a floating gate 354 between a control gate 374 of a normal MOSFET and a substrate 310. Although a gate oxide film 330 is formed below the floating gate 354, a thin oxide film 334 of about 100 ° called a “tunnel oxide film” is provided in a part of the region.
[0005]
Under the tunnel oxide film 334, TN⁻An impurity diffusion region 324 is formed, and TN performed through a tunnel oxide film 334 is performed.⁻Data is written to and erased from the memory transistor by injecting or extracting electrons from the impurity diffusion region 324 to the floating gate 354. Since the periphery of the floating gate 354 is insulated by the oxide film, the state of the accumulated charge does not change even when the power is turned off, and data can be stored.
[0006]
The select transistor adjacent to the memory transistor has gate electrodes 352 and 372 of a two-layer polysilicon structure in order to achieve structural and process consistency with the memory transistor. Used in an electrically shorted state. On the substrate surface layer on both sides of the gate electrode 352, the drain region 321 of the cell corresponding to the source / drain region of the selection transistor and N⁻Impurity diffusion regions 322 and 323 are formed. Also, N⁻Impurity diffusion region 323 and TN⁻The impurity diffusion region 324 is formed so as to partially overlap, and both are electrically connected. A source region 326 of the cell is formed in a substrate surface layer beside the memory transistor.
[0007]
In FIG. 11, an insulating film formed between and around the floating gate 354 and the control gate 374, and various wirings are not shown for convenience.
[0008]
For example, when erasing data in a memory cell of an EEPROM, a high voltage of about 20 V is applied to the control gate 374. Then, through the tunnel oxide film 334, TN⁻Electron tunnel injection from the impurity diffusion region 324 to the floating gate 354 occurs, and negative (−) charges are accumulated in the floating gate 354.
[0009]
On the other hand, when writing data, the voltage polarity applied to the control gate 374 is inverted. Electrons flow from the floating gate 354 to the TN⁻It is extracted to the impurity diffusion region 324.
[0010]
[Problems to be solved by the invention]
As described above, data writing / erasing is performed by utilizing the electron tunnel phenomenon that occurs when a high voltage is applied through the thin tunnel oxide film 334 of about 100 °. Therefore, a peripheral circuit such as a booster circuit for supplying a high voltage is required along with the drive circuit around the memory cell.
[0011]
In recent years, there has been an increasing demand for miniaturization of LSIs equipped with EEPROM and simplification of the process burden. To meet these needs, not only the structure of the EEPROM memory cell but also its peripheral circuits have been required. Consideration including this is required.
[0012]
Hereinafter, specific problems regarding a memory cell and those regarding a peripheral circuit will be described.
[0013]
(Issues related to EEPROM memory cells)
FIG. 12A is a plan view schematically showing the structure of an EEPROM memory cell which has been recently proposed by the present applicant and is under development, and FIG. 12B is a sectional view thereof. The basic configuration is the same as that of the conventional general EEPROM memory cell shown in FIG. 11, but differs greatly in that a thin tunnel oxide film 534 is formed over the entire memory transistor. As a result, the required area of the memory transistor follows the general scaling rule of the MOS transistor, and depends on the thickness of the tunnel oxide film.
[0014]
As shown in FIGS. 12A and 12B, in this EEPROM, electrons are injected / extracted into / from the floating gate 554 by a TN formed in a part of the substrate surface layer below the floating gate 554.⁻This is performed between regions where the impurity diffusion region 524 and the floating gate 554 face each other.
[0015]
In this EEPROM memory cell, an opening 580 that penetrates the control gate 574 and the floating gate 554 is provided in the formation region of the two gates.⁻By using a self-alignment process so as to partially overlap the side of the diffusion region 524, N⁻An impurity diffusion region 525 is formed. This N⁻The impurity diffusion region 525 has a floating gate 554 and a TN when writing / erasing data.⁻This has an effect as a hole stopper for preventing a leak current to the substrate called “inter-band tunnel current” generated by the influence of the high electric field applied between the impurity diffusion regions 523.
[0016]
As described above, when only a single cell is operated, by employing the memory cell configuration shown in FIG. 12, it is possible to miniaturize the cell while maintaining good element performance. However, it has been found that the following problem occurs in an EEPROM in which a large number of memory cells are arranged in a matrix on a chip.
[0017]
FIG. 13 is a cross-sectional view simply showing two adjacent cells (S1, S2), which are a part of the memory cells arranged in a matrix, and schematically showing the configuration thereof. As shown in the figure, usually, two cells are arranged so as to be symmetrical on both sides of a common source region 526.
[0018]
At the time of use, first, the data in all the memory cells is erased. That is, the floating gates of all the cells are in a state where negative (-) charges are accumulated. Thereafter, data is written to the designated cell as needed.
[0019]
Therefore, as shown in FIG. 13, when data is written to only one (S1) of the memory cells adjacent to each other while sharing the source region 526, the floating gate 554a of one of the cells is sandwiched by the common source region 526. , And a negative (−) charge is stored in the floating gate 554b of the other cell. In such a case, a leakage current from the common source region 526 to the substrate 510 may occur, or the breakdown voltage characteristics may deteriorate. The occurrence of a leak current or the like may cause the data writing to be shallow, reduce the reliability of data retention, and significantly reduce the number of writable times.
[0020]
In view of the above problems, a first object of the present invention is to provide a semiconductor device having a plurality of EEPROMs arranged in a matrix on a chip and having both miniaturization and high reliability.
[0021]
(Issues on EEPROM Peripheral Circuits: Part 1)
As described above, data writing / erasing in the EEPROM is performed by using a floating gate and a TN through a thin tunnel oxide film of about 100 °.⁻This is performed using the electron tunnel phenomenon that occurs when a high voltage is applied between the impurity diffusion regions.
[0022]
Therefore, a booster circuit for generating a high voltage required for the tunnel phenomenon is required around the EEPROM cell. In addition, since a high voltage may be applied to other driving circuits in the same manner as a memory cell, a transistor having a high breakdown voltage structure (hereinafter, referred to as an HV transistor) needs to be provided as necessary.
[0023]
FIG. 14 is a schematic sectional view showing an example of an HV transistor mounted on the same chip together with the EEPROM. In the figure, the memory cells of the EEPROM are shown on the left side, and the HV transistors are shown on the right side. Here, a P-channel MOS transistor formed in the N well 512 is illustrated.
[0024]
As shown in the figure, this HV transistor has gate electrodes 556 and 576 each having a double-layer polysilicon structure like an EEPROM cell in order to achieve matching in process with the EEPROM. The electrodes are electrically short-circuited. Note that a thick film of about 400 ° is used as the gate oxide film 530 in order to increase the breakdown voltage.
[0025]
In an HV transistor mounted together with the EEPROM, a high electric field is not applied between the source region 582 and the drain region 583. Therefore, generation of hot electrons does not matter so much. The LDD structure in which a thin impurity diffusion region is formed on the side is not adopted.
[0026]
When forming source / drain regions, ion implantation is usually performed using the pattern of the two-layer polysilicon gate electrodes 576 and 556 as a mask. This mask is composed of a two-layer polysilicon film and a thick gate oxide. Since it is composed of a film or the like, the height is considerably large. Therefore, when ion implantation is performed using this as a mask, shadowed portions are likely to be formed, and it is difficult to form the source / drain regions 582 and 583 sufficiently close to both sides of the gate electrode 556. The source / drain regions 582 and 583 need to be high-concentration impurity diffusion regions. However, in the case where high-concentration impurities are ion-implanted, it is difficult to secure a sufficient implantation depth near the mask edge. Insufficiency of injection is likely to occur at the end of.
[0027]
In addition, when performing ion implantation for the purpose of achieving process matching with other circuits, sidewalls are often already formed on the side surfaces of the gate electrode, and therefore, the source / drain regions 582 and 583 are added to the gates. It is difficult to form the electrodes 576 and 556 close to both sides.
[0028]
In this case, as shown by a broken line in the figure, there is a gap between the channel formation region 581 formed below the gate electrode and the source / drain regions 581 and 582, and when the transistor is turned on, a stable channel cannot be formed. , It becomes an offset transistor.
[0029]
In view of the above-described problem, a second object of the present invention is to provide a semiconductor device having a highly reliable EEPROM mounted thereon by preventing an HV transistor mixed with the EEPROM from becoming an offset transistor.
[0030]
(Issues on EEPROM Peripheral Circuits: Part 2)
A booster circuit for obtaining a high voltage necessary for writing / erasing data using a tunnel phenomenon is provided around the EEPROM memory cell. With this booster circuit, for example, the power supply voltage of 5V is boosted to 20V. A capacitor is often used in this booster circuit.
[0031]
A capacitor is composed of a pair of electrodes and a dielectric layer sandwiched between the electrodes. Conventionally, in a semiconductor device equipped with an EEPROM having a two-layer polysilicon structure, a substrate is used as a lower electrode constituting the capacitor. N formed on the surface⁻An impurity diffusion region is used, a thick SiO2 film used as a gate oxide film of an HV transistor is used as a dielectric layer, and a polysilicon film used as a gate electrode is used as an upper electrode.
[0032]
However, when a thick SiO2 film is used as the dielectric layer, the area of the capacitor occupying the chip cannot be ignored, and the area has been a problem in reducing the chip size.
[0033]
In view of the above-described problem, a third object of the present invention is to reduce the size of a capacitor of a booster circuit that is mounted together with an EEPROM without a process load.
[0034]
[Means for Solving the Problems]
The feature of the semiconductor device of the present invention described in claim 1 is thatIn a semiconductor device in which a plurality of EEPROM cells having a selection transistor and a memory transistor are arranged such that memory transistors of adjacent cells have a common source region,The memory transistor includes a tunnel insulating film formed on a semiconductor substrate surface having a first conductivity type, a floating gate formed on the tunnel insulating film, an insulating layer formed on the floating gate, A control gate formed on an insulating layer, a first impurity diffusion region of a second conductivity type formed on a surface layer of the semiconductor substrate corresponding to a partial region immediately below the floating gate, and a surface of the semiconductor substrate beside the floating gate The source region of the second conductivity type formed in the layerWhen,In the substrate surface layer adjacent to the source regionBeen formedA second impurity diffusion region of a second conductivity type having a lower impurity concentration than the source region;An opening penetrating the control gate, the insulating layer, and the floating gate; and a third impurity diffusion layer of a second conductivity type having an impurity concentration lower than that of the first impurity diffusion region in a substrate surface layer corresponding to the opening region. Is to have an area.
[0035]
According to the feature of the first aspect, the presence of the low impurity concentration second impurity diffusion region provided adjacent to the source region can suppress generation of an interband leak current from the source region to the substrate. That is, in the EEPROM cell having the matrix configuration as described above, the memory cells are arranged symmetrically on both sides of the common source region. However, when data is written only in the memory transistor of one of the cells, A negative (-) charge is stored in one of the floating gates adjacent to each other through the region, and a positive (+) charge is stored in the other. A relatively high voltage is applied between the regions. The second impurity diffusion region provided adjacent to the source region substantially reduces the electric field intensity generated by this voltage applied between the source region and the floating gate, suppresses the generation of an interband leakage current, and In addition, a substantial breakdown voltage characteristic of the memory transistor is improved. Note that the tunnel insulating film includes a tunnel oxide film.
[0036]
Further, the memory transistor is:An opening penetrating the control gate, the insulating layer, and the floating gate; and a third impurity diffusion layer of a second conductivity type having an impurity concentration lower than that of the first impurity diffusion region in a substrate surface layer corresponding to the opening region. Region, and the third impurity diffusion region is formed so as to partially overlap the first impurity diffusion region. Therefore, the third impurity diffusion region is formed between the first impurity diffusion region and the substrate. Generation of an interband current can also be suppressed.
[0037]
As described in claim 2,The selection transistor includes a second conductivity type drain region formed in a substrate surface layer beside a gate electrode of the selection transistor, and a second impurity region having a lower impurity concentration than the drain region in a substrate surface layer adjacent to the drain region. If a fourth impurity diffusion region of a conductivity type is provided and the second impurity diffusion region, the third impurity diffusion region, and the fourth impurity diffusion region have substantially the same impurity concentration, The second, third, and fourth impurity diffusion regions can be formed in the same step.
[0038]
The feature of the semiconductor device according to claim 3 is thatA peripheral circuit area of the EEPROM;
In the peripheral circuit area,A channel forming region which is operable under a high voltage required for writing or erasing the data in the EEPROM and which is located on a substrate surface layer at a gate side end of a source region and a drain region, and a channel forming region immediately below a gate electrode; Impurity diffusion regions of the same conductivity type as these so as to partially overlapHigh voltage MOS transistorThat is.
[0039]
According to the features of claim 3,The presence of the impurity diffusion region formed so as to partially overlap the channel region ensures that the channel region is electrically connected to the source region and the drain region when the high breakdown voltage MOS transistor is ON, thereby preventing the occurrence of an offset transistor. it can.
[0041]
The feature of the semiconductor device according to claim 4 is thatFurther, it has a peripheral circuit area of the EEPROM, and in the peripheral circuit area,A booster circuit for supplying a high voltage necessary for writing or erasing data in the EEPROMWhen,The booster circuitinside,An upper electrode, a lower electrode, and a capacitor comprising a dielectric layer sandwiched between these electrodes, wherein the dielectric layer comprises:EEPROMThe same layer as the insulating layerIncludingThat is.
[0042]
According to the features of claim 4When a two-layer polysilicon structure is manufactured in an EEPROM cell, a dielectric layer of a capacitor in a booster circuit can be formed at the same time.
[0043]
A method of manufacturing a semiconductor device according to claim 5, wherein a plurality of EEPROM cells having a selection transistor and a memory transistor are arranged such that memory transistors of adjacent cells have a common source region.Forming a first impurity diffusion region of a second conductivity type on a surface layer of a first conductivity type substrate in a part of a memory transistor formation region; and forming a gate insulating film of a selection transistor on the surface of the substrate. Forming, removing the gate insulating film on the memory transistor formation region, and forming a tunnel insulating film in the removed region; forming a first polysilicon film on the gate insulating film and the tunnel insulating film; Forming a layer and a second polysilicon film sequentially, and etching the first polysilicon film, the insulating layer and the second polysilicon film, respectively, to form a selection transistor andWith openingsForming each gate pattern of the memory transistor, forming a plurality of second-conductivity-type low-concentration impurity diffusion regions in the substrate surface layer by ion implantation using the respective gate patterns as an implantation mask; Form a sidewall on the pattern side wall and use this as an implantation mask by ion implantation.Of the second conductivity typeForming a source / drain region that is a high-concentration impurity diffusion region, wherein the step of forming the low-concentration impurity diffusion region includes a low-concentration impurity diffusion region that partially overlaps the drain region and the first impurity diffusion region. Forming a low concentration impurity diffusion region partially overlapping the source region together with the impurity diffusion region.
[0044]
According to the features of claim 5,In the process of forming the low-concentration impurity diffusion region, since the low-concentration impurity diffusion region is also formed in a region overlapping with the source region, an inter-band leakage from the source region to the substrate can be performed without adding a new burden to the conventional process. The semiconductor device according to claim 1, which includes an EEPROM cell capable of suppressing generation of a current, can be provided.
Note that the gate insulating film includes a gate oxide film.
[0045]
7. A method of manufacturing a semiconductor device according to claim 6, wherein in the step of forming the gate insulating film, a gate insulating film is simultaneously formed in a peripheral circuit region, and the first polysilicon film, the insulating layer, and the second polysilicon film are formed. Forming a first polysilicon film, an insulating layer, and a second polysilicon film sequentially on the gate insulating film in the peripheral circuit region in the step of sequentially forming a silicon film, and forming the respective gate patterns; Simultaneously, the first polysilicon film, the insulating layer and the second polysilicon film are etched in the peripheral circuit region to form a gate pattern of a high breakdown voltage MOS transistor, and the second conductive type low concentration impurity diffusion region is formed. In the forming step, a low concentration impurity diffusion region of the second conductivity type is simultaneously formed using the gate pattern of the peripheral circuit region as an implantation mask. Thereafter, sidewalls are formed on the side walls of the respective gate patterns, and the second conductive patterns are formed on the side surfaces of the substrate in the EEPROM cell formation region and the high breakdown voltage MOS transistor formation region by ion implantation using the sidewalls as implantation masks. Forming a source / drain region which is a high-concentration impurity diffusion region of a mold type.
[0046]
According to the features of claim 6,In the step of forming the low-concentration impurity diffusion region, the low-concentration impurity diffusion region that partially overlaps the source / drain region of the high breakdown voltage transistor is formed. No occurrenceClaim 3The semiconductor device described above can be provided. In the step of forming the source / drain regions, a gate pattern without sidewalls may be used as the implantation mask in the high breakdown voltage MOS transistor formation region.
[0047]
The feature of the method for manufacturing a semiconductor device according to claim 7 is that,In the step of forming the gate insulating film, a step of forming a gate insulating film in a peripheral circuit region at the same time, and in the step of sequentially forming the first polysilicon film, the insulating layer, and the second polysilicon film, simultaneously form the peripheral circuit region. Forming a first polysilicon film, an insulating layer, and a second polysilicon film on the gate insulating film in order, and forming the respective gate patterns in the peripheral circuit region at the same time; Etching the insulating layer and the second polysilicon film to form a capacitor pattern using the first polysilicon film as a lower electrode, the insulating layer as a dielectric layer, and the second polysilicon film as an upper electrode. Is to have.
[0048]
According to the features of claim 7,The first polysilicon film is used as a lower electrode, the insulating layer is used as a dielectric layer, and the second polysilicon film is used as an upper electrode.Claim 4Can be manufactured without imposing a new burden on a conventional process.
[0049]
9. A method of manufacturing a semiconductor device according to claim 8, wherein, in the step of forming the first impurity diffusion region, a first impurity diffusion region is simultaneously formed in a substrate surface layer of the peripheral circuit region, and the gate insulating film is formed. Forming a gate insulating film in the peripheral circuit region at the same time, and forming the first polysilicon film, the insulating layer, and the second polysilicon film sequentially in the step of forming the gate insulating film in the peripheral circuit region at the same time. Forming at least the first polysilicon film thereon and forming the respective gate patterns, simultaneously etching the first polysilicon film and the gate insulating film in the peripheral circuit region to form the first impurity diffusion layer; Forming a capacitor pattern using the region as a lower electrode, the gate insulating film as a dielectric layer, and the first polysilicon film as an upper electrode; It is to have a.
[0050]
the aboveClaim 8According to the feature, an impurity diffusion region formed on the substrate surface layer of the capacitor formation region under the same conditions as the first impurity diffusion region is used as a lower electrode, and the insulating layer or a layer obtained by adding a tunnel insulating film to the insulating layer is formed. The second polysilicon can be used as the dielectric layer, and the upper electrode and the semiconductor device can be manufactured without adding a new burden to the conventional process.
[0054]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described.
[0055]
(First Embodiment)
FIG. 1 is a cell cross-sectional view schematically showing the structure of two memory cells having a common source region among the EEPROM memory cells according to the first embodiment of the present invention.
[0056]
As shown in FIG. 2A, this cross-sectional view is a part of an EEPROM arranged in a matrix on a chip. In FIG. 2A, the thin strips extending vertically are the gate patterns 72a and 72b of the selection transistor, and the slightly thicker and more vertical patterns are the gate patterns 74a and 74b of the memory transistor. The pattern extending in the lateral direction is a formation zone 12 of various impurity diffusion regions including source / drain regions. The vertically adjacent cells are separated by slits 100 formed at the boundaries. The extraction electrode 110 of the source region is formed so as to be common to the four cells.
[0057]
FIG. 2B is a plan view showing two memory cells S1 and S2 which are arranged symmetrically with a common source region, and the cross-sectional view shown in FIG. 1 corresponds to the cross-sectional configuration of these two cells. I do.
[0058]
Returning to FIG. 1, the description will be continued. The EEPROM memory cell according to the first embodiment includes a selection transistor and a memory transistor. The memory transistor and the selection transistor of the two cells have a common source region 26 and are symmetrical on both sides thereof. Are located. Similar to the EEPROM shown in FIG. 13, since the thin tunnel oxide films 32a and 32b are formed over the entire memory transistor formation region, the area of the memory transistor can be kept small. The select transistor is formed of gate electrodes 52a, 52b, 72a, 72b of a two-layer polysilicon structure according to the structure of the adjacent memory transistor, and the upper and lower polysilicon films are used by being electrically short-circuited.
[0059]
The difference between the EEPROM cell in the present embodiment and the conventional EEPROM cell shown in FIG. 13 is that low-density N cells are provided on both sides of a source region 26 common to both memory cells.⁻That is, the impurity diffusion regions 27a and 27b are formed. That is, the source region 26 has a so-called LDD structure.
[0060]
Hereinafter, the effect of the LDD structure formed adjacent to the source region 26 will be described with reference to FIG.
[0061]
Normally, in the initial state of an EEPROM memory cell, all data is erased and negative (-) charges are accumulated in the floating gates of all the memory cells. As shown in FIG. 1, when writing is performed on only the memory cell S1 (selected cell) on one side (left side in the figure) in the cell in this initial state, the gate (50a, 50a, 70a) is applied with the voltage Vpp to turn on the selection transistor. Accordingly, an n-channel is formed in the semiconductor substrate surface layer below the gate electrode 52a.
[0062]
Since a voltage of Vpp is applied to the drain regions 21a and 21b of each memory cell, the drain region 21a⁻N through the impurity diffusion region 22a and an n channel formed under the gate electrode.⁻Conduction with the impurity diffusion region 23a is made, and both regions have the same potential (Vpp). Furthermore, N⁻Impurity diffusion region 23a and TN⁻Since the impurity diffusion region 24a is formed overlapping, the TN⁻The impurity diffusion region 24a also has the same potential (Vpp).
[0063]
On the other hand, since the control gate 74a of the memory transistor is grounded to the ground (G), the control gate 74a and the TN⁻A voltage of Vpp is applied between the impurity diffusion regions 24a. As a result, the floating gate 54a and the TN are connected via the thin tunnel oxide film 32a.⁻A high electric field is applied between the impurity diffusion regions 24a, and the minus (-) charges accumulated in the floating gate 54a are extracted, and the floating gate 55a becomes plus (+) charges.
[0064]
At this time, since the source region 26 is open, a voltage corresponding to the threshold voltage Vth of the memory transistor is applied between the floating gate 54a and the source region 26 via the tunnel oxide film 32a.
[0065]
On the other hand, in the memory cell S2 (non-selected cell) on the right side in the drawing where data is not written, the gates 72b and 52b of the selection transistor and the control gate 74b of the memory transistor are both grounded to the ground (G), and are not selected. In the floating gate 54b of the memory cell S2, a negative (-) charge having the opposite polarity to that of the left memory cell S1 is still stored.
[0066]
As described above, although a voltage corresponding to the threshold voltage Vth is applied between the source region 26 and the floating gate 54a of the left selected memory cell S1, the right floating gate 54b which is an unselected memory cell S2 is applied. Since a negative (-) charge having a different polarity from that of the left floating gate is stored, a high electric field is relatively generated between the source region 26 and the right floating gate 54b via the tunnel oxide film 32b. That would be.
[0067]
At this time, when the common source region 26 does not have the LDD structure as in the conventional EEPROM cell, an electric field is directly applied between the source region 26 on the non-selected memory cell S2 side and the floating gate 54b. It becomes. Along with this, the depletion layer formed around the source region boundary becomes extremely thin on the substrate surface layer, and electrons tunnel from the valence band to the conduction band, leaving holes in the later valence band, and this hole serves as an interband current. Outflows into the substrate. That is, a so-called inter-band leak current occurs.
[0068]
In the case described above, in the conventional EEPROM cell, a high potential difference corresponding to twice the threshold voltage is generated relatively between the unselected cell and the source region. The characteristics are degraded, and Vpp is likely to decrease even under normal use conditions.
[0069]
However, as in the present embodiment, N⁻When the impurity diffusion regions 27a and 27b are provided and the LDD structure is formed, the intensity of the electric field generated between the source region 26 and the floating gate 54b is reduced, thereby suppressing the generation of the inter-band leakage current as described above. can do.
[0070]
Contrary to the case described above, when writing is performed only on the right memory cell S2, a high electric field is applied between the source region 26 and the floating gate 54a of the left memory cell S1. Is the N formed on the side of the source region 26.⁻Due to the presence of the impurity diffusion region 27a, the electric field is alleviated, and generation of a tunnel current can be suppressed. Similarly, the LDD structure formed adjacent to the source region 26 can substantially improve the withstand voltage characteristics on the source region side of the memory cell.
[0071]
FIG. 3 shows the effect of improving the breakdown voltage characteristics of the source region in the EEPROM according to the present embodiment. The horizontal axis shows the source voltage (Vs) and the vertical axis shows the source current (Is). For reference, the graph also shows withstand voltage characteristics data of a conventional EEPROM having no LDD structure.
[0072]
As shown in the graph, in a conventional EEPROM, when writing is performed only on one of a pair of memory cells having a common source region, a relatively high voltage is directly applied between the other cell and the common source region. Therefore, Vpp applied to the drain region may be reduced without the withstand voltage. However, in the EEPROM of the present embodiment, the withstand voltage is improved by about three times, and under the above-described write condition, Also, Vpp will not go down.
[0073]
(Example 1.1)
Hereinafter, an example of a method of manufacturing an EEPROM memory cell according to the first embodiment will be described with reference to FIGS. 4A to 4G illustrating cross sections in respective manufacturing steps of a unit memory cell. It is to be noted that, although it is usually manufactured together with other circuits formed on the same chip, as will be described later, the following description focuses particularly on the manufacturing process for an EEPROM memory cell.
[0074]
First, as shown in FIG. 4 (a), an N type is implanted into a substrate surface layer of a P-type silicon substrate 10 by ion implantation.⁻An impurity diffusion region 24 is formed. The ion implantation conditions at this time are, for example, an acceleration voltage of 70 KeV and a dose of 5.0 × 10 5^ThirteenFinally, a depth of 0.35 μm and an impurity concentration of 3 × 10¹⁷cm^-3Is formed.
[0075]
Next, a gate oxide film (SiO 2 film) 30 of the select transistor is formed on the entire surface of the substrate by using an oxidation method. The thickness of the gate oxide film 30 is made as thick as about 400 to 450 ° in order to secure sufficient withstand voltage. Thereafter, the gate oxide film 30 in the memory transistor formation region is removed by etching.
[0076]
Next, a thin tunnel oxide film 32 having a thickness of about 100 ° is formed on the surface by using an oxidation method. As shown in FIG. 4B, a tunnel oxide film 32 is formed on the exposed surface of the substrate in the memory transistor formation region.
[0077]
As shown in FIG. 4C, on the surface on which the gate oxide film 30 and the tunnel oxide film 32 have been formed, a first polysilicon film 50 having a thickness of about 2000.degree.
[0078]
As shown in FIG. 4D, an insulating layer 60 having a thickness of about 250 ° is formed on the first polysilicon film 50. The insulating layer 60 is formed of a three-layer laminated film in which a Si3N4 film called an "ONO film" is sandwiched between two SiO2 layers. With the three-layer structure, stress is less likely to be generated at the interface with the polysilicon film, the pressure resistance is excellent, and the size of the memory transistor can be reduced.
[0079]
Subsequently, a second polysilicon film 70 having a thickness of about 4000 ° is formed on the insulating layer 60 by using a thermal CVD method.
[0080]
As shown in FIG. 4E, the second polysilicon film 70, the insulating layer 60, and the first polysilicon film 50 are sequentially etched by RIE using a normal photolithography process, so that a selection transistor and a memory transistor are formed. Patterning necessary for formation is performed. At the same time, a pattern of the opening 80 in the memory transistor is formed. By this step, the gate electrodes 52 and 57 of the select transistor and the floating gate 54 and the control gate 74 of the memory transistor are formed.
[0081]
Next, as shown in FIG. 4F, P (phosphorus) is ion-implanted into the substrate surface layer by a self-alignment process using the above-mentioned various gate patterns as an implantation mask.⁻Formed impurity diffusion regions 22, 23, 25 and 27 are formed. That is, the N formed at the side of the source region, which is a feature of this embodiment,⁻The type impurity diffusion region 27 can be formed together with another impurity diffusion region. The ion implantation conditions at this time were as follows: an acceleration voltage of 50 KeV and a dose of 1 × 10^ThirteenFinally, a depth of about 0.3 μm and an impurity concentration of 1 × 10¹⁷cm^-3The following diffusion region is formed.
[0082]
As shown in FIG. 4 (g), a SiO 2 film is formed on the surface, and a suitable etching is performed to form a side wall 90, and ion implantation is performed using the gate electrode and the side wall pattern as an implantation mask to form N 2.⁺A source region 26 and a drain region 21 made of an impurity diffusion region are formed.
[0083]
Thus, the N formed in the previous step is⁻The source region 26 is formed so as to partially overlap the impurity diffusion region 27, and an EEPROM cell having an LDD structure is completed.
[0084]
Although not particularly described, it is assumed that each ion implantation involves an appropriate annealing step (the same applies hereinafter).
[0085]
As described above, the EEPROM cell according to the first embodiment can be easily formed in the conventional low-concentration impurity diffusion region forming step without changing the process by merely changing the ion implantation mask pattern. A source region having an LDD structure can be formed at the same time.
[0086]
(Second embodiment)
FIG. 5 is a sectional view of an apparatus showing a structure of a high breakdown voltage transistor mounted on an EEPROM memory embedded LSI according to a second embodiment of the present invention. The left side of the figure shows the EEPROM memory cell shown in the first embodiment, and the right side shows a high-voltage transistor (HV transistor) mixedly mounted on the same chip.
[0087]
Here, an example of a p-channel HV transistor is shown. The n channel has the same configuration except for the conductivity type. In the case of a p-channel transistor, it is formed in an N-type well 12 formed in an upper layer of a P-type substrate 10. The transistor mounted together with the EEPROM has a gate electrode formed of a double-layer polysilicon structure like the memory transistor of the EEPROM in order to enhance process consistency, but the upper and lower gate electrodes 52 and 72 are electrically short-circuited. Used.
[0088]
In the HV transistor according to the present embodiment, a source region 82 and a drain region 83 formed of a P-type impurity diffusion region are formed in a substrate surface layer, and the source region 82 is formed via a gate oxide film 30 in the same manner as a conventional HV transistor. The gate electrode 52 is formed between the gate electrode 52 and the drain region 83. The gate oxide film 30 is made as thick as about 400 ° like the gate oxide film of the select transistor of the EEPROM in order to maintain the breakdown voltage.
[0089]
The HV transistor according to the present embodiment is different from the conventional HV transistor in that the P-type transistor is adjacent to the inner boundary of the source region 82 and the drain region 83.⁻That is, the type impurity diffusion regions 84 and 85 are formed. That is, the LDD structure is formed in the source region and the drain region.
[0090]
P⁻One end of each of the impurity diffusion regions 84 and 85 is formed so as to partially overlap the source region 82 or the drain region 83, and the other end is formed in a channel formation region 81 formed below the gate electrode 56. Therefore, the occurrence of the offset transistor due to the discontinuity of the channel, which occurs in the conventional configuration, can be suppressed.
[0091]
As described above, the LDD structure does not mainly prevent the generation of hot electrons unlike the LDD structure used in a general MOS transistor, but has a main effect of suppressing generation of an offset transistor.
[0092]
The reason why the implantation layer having a lower impurity concentration than that of the source region 82 and the drain region 83 is formed is that the low-concentration impurity diffusion layer has a sufficient depth to the vicinity of the edges of the gate electrodes 76 and 56 serving as an implantation mask. This is because it is possible to form a diffusion region having an appropriate thickness.
[0093]
(Example 2.1)
FIG. 6 is a process flow chart showing a method for manufacturing an EEPROM and HV transistors according to the second embodiment. Hereinafter, an example of a method for manufacturing an HV transistor according to the present embodiment will be briefly described with reference to this process flow chart and the cross-sectional views of the device in each process shown in FIG.
[0094]
First, a well is formed in a necessary region on the surface of the semiconductor substrate put in the lot (S1) (S2). As shown in FIG. 7A, when the above-described P-channel HV transistor is formed on the P-type semiconductor substrate 10, a heat diffusion method or an ion implantation method and an annealing process are used in advance around the P-channel HV transistor. An N well 12 is formed.
[0095]
Subsequently, an element isolation region (LOCOS) 34 is formed (S3) using a usual method, and an active region of the transistor is defined. Thereafter, the TN is formed by ion implantation into a part of the substrate surface layer in the memory transistor forming region of the EEPROM cell.⁻An impurity diffusion region 24 is formed (S4).
[0096]
Next, in order to adjust the threshold value of the transistor, a P-type impurity is thinly implanted into a region below the gate electrode of the HV transistor, the N-type impurity concentration on the substrate surface is reduced, and the channel formation region 81 is formed. (S5).
[0097]
An SiO 2 film 30 having a thickness of about 400 ° corresponding to the gate oxide film of the HV transistor and the select transistor of the EEPROM cell is formed on the entire surface of the substrate (S6). The SiO2 film 30 in the memory transistor formation region of the EEPROM is removed by etching, and a thin tunnel oxide film (SiO2 film) 32 having a thickness of about 100 degrees is formed here (S7).
[0098]
As shown in FIG. 7B, on the surface on which the gate oxide film 30 and the tunnel oxide film 32 have been formed, a first polysilicon film 50 having a thickness of about 2000 .ANG. Is formed by thermal CVD (S8). .
[0099]
Thereafter, as shown in the process flow chart of FIG. 6, a slit is formed (S9). Although this slit is not shown in FIG. 7, as can be seen from the plan view of FIG. 2A, the tunnel oxide film 32 and the first polysilicon film 50 at the boundary of each EEPROM memory cell are etched. This is a strip-shaped opening pattern formed in this way, and is required for separating each cell.
[0100]
Further, an insulating layer 60 made of an ONO film having a thickness of about 250 ° is formed on the entire surface of the substrate (S10), and a second polysilicon film 70 having a thickness of about 4000 ° is formed on the insulating layer 60 by using a thermal CVD method. (S11).
[0101]
As shown in FIG. 7C, the second polysilicon film 70, the insulating layer 60, and the first polysilicon film 50 are sequentially etched by RIE using a normal photolithography process, and the EEPROM and the HV transistor are formed. (S12). At the same time, a pattern of the opening 80 in the memory transistor is formed. Through this step, the gate electrodes 56 and 76 of the HV transistor are formed together with the gate electrodes 52 and 57 of the selection transistor, the floating gate 54 and the control gate 74 of the memory transistor.
[0102]
Next, as shown in FIG. 7D, P (phosphorus) is ion-implanted into the substrate surface layer by a self-alignment process using the above-mentioned various gate patterns as an implantation mask.⁻Formed impurity diffusion regions 22, 23, 25 and 27 are formed. In the HV transistor forming region, P-type impurity ions, for example, boron (B) are thinly implanted by using the gate electrodes 56 and 76 as an ion implantation mask.⁻An impurity diffusion region is formed (S13). Since the gate electrode has a two-layer polysilicon structure and the gate oxide film is thick, the implantation mask pattern is considerably high.^ThirteenHereinafter, by setting the ion implantation angle to 0 degree and the acceleration voltage to 40 keV, the depth partially overlapping the channel region 84 below the gate electrode 56 is about 0.4 μm, and the impurity concentration is 5 × 10 5.¹⁶cm^-3The following P⁻Type impurity diffusion regions 84 and 85 can be formed.
[0103]
Thereafter, as shown in FIG. 7E, a SiO2 film is formed on the surface, and a suitable etching is performed to form a sidewall 90 (S14). This step is essentially unnecessary for the HV transistor, but in the context of the EEPROM mounted on the same chip and other circuits, unless a separate step is provided to perform a process such as removal. Similarly, the side wall 91 is formed.
[0104]
Subsequently, ion implantation is performed using the sidewall pattern as an implantation mask to form source regions 21 and 82 and drain regions 26 and 83 (S15). Phosphorus (P) or the like is implanted into the EEPROM memory cell, while boron (B) or the like is implanted into the P-channel HV transistor forming region. For example, as an implantation condition for forming a source / drain region of an HV transistor, an acceleration voltage is 50 keV, and a dose is 3.0 × 10 3^FifteenAnd a depth of 0.2 μm and an impurity concentration of 1 × 10¹⁹cm^-3The above diffusion region is formed.
[0105]
Thus, the P formed in the previous step⁻Source regions 82 and 83 are formed so as to partially overlap the impurity diffusion regions 84 and 85, and the HV transistor according to the second embodiment is formed together with the EEPROM cell according to the first embodiment.
[0106]
As described above, in the HV transistor having the double-layer polysilicon structure formed in the LSI on which the EEPROM is embedded, the impurity is formed adjacent to the inner boundary between the source region and the drain region by the same procedure as the process of forming the LDD structure of the normal transistor. By forming the diffusion region, an HV transistor that is unlikely to be an offset transistor can be obtained.
[0107]
When an offset transistor occurs, it is very difficult to find out if there is a defect in the EEPROM memory cell. Therefore, in the conventional configuration, it is necessary to consider an extra write margin (write margin) and a retention margin. However, these are unnecessary in the EEPROM-embedded LSI in the present embodiment, and the reliability is improved.
[0108]
In the second embodiment, the EEPROM according to the first embodiment is exemplified as the EEPROM formed together with the capacitor. However, the EEPROM is not limited to this configuration as long as the EEPROM has a double-layer polysilicon structure. Without the above, the effect of the HV transistor according to the above-described second embodiment can be obtained.
[0109]
(Third embodiment)
The third embodiment of the present invention relates to a capacitor used for a booster circuit mounted on the same chip together with an EEPROM memory.
[0110]
FIGS. 8A to 8C are device cross-sectional views illustrating a configuration example of three types of capacitors according to the third embodiment. The left side of the figure shows an EEPROM mounted on the same chip. The EEPROM shown here has the same configuration as the EEPROM shown in the first embodiment.
[0111]
A feature common to these three types of capacitors is that a so-called ONO film is used as the dielectric layer. The ONO film has a three-layer structure in which an Si3N4 film is sandwiched between upper and lower SiO2 films, and is generally used as an insulating layer formed between a floating gate and a control gate in an EEPROM memory transistor. .
[0112]
In the conventional capacitor, a SiO 2 film of about 400 ° used for the gate oxide film 30 of the control transistor of the EEPROM is used as the dielectric layer. However, if this is replaced with the ONO film as described above, the necessary capacitor area is required. Can be greatly reduced. This is because the dielectric constant of the SiO2 film is 3.9, whereas the dielectric constant of the Si3N4 film is as high as 7.5.
[0113]
When the dielectric layer is composed only of the Si3N4 film, stress is easily generated at the interface between the upper and lower electrodes formed of the polysilicon film and the dielectric layer, and peeling may occur. However, the polysilicon film and the Si3N4 film are formed. When an ONO film having a SiO2 film between them is used, the generation of stress at the interface is small, and problems such as peeling can be suppressed.
[0114]
The first capacitor shown in FIG. 8A has a lower electrode 58 and an upper electrode obtained by patterning a first polysilicon film and a second polysilicon film on a LOCOS film 34 formed on a semiconductor substrate 10. 78 and a dielectric layer 68 obtained by patterning the ONO film.
[0115]
The second capacitor shown in FIG. 8 (b) has a TN⁻When the impurity diffusion region 24 is formed, the TN⁻The impurity diffusion region 24 is used as the lower electrode 29 of the capacitor, the ONO film is patterned to form the dielectric layer 68, and the second polysilicon film is patterned to form the upper electrode 78.
[0116]
Although the third capacitor shown in FIG. 8C is very similar to the second capacitor, the dielectric layer 68 is formed of the tunnel oxide film 32 and the ONO film due to a difference in a process described later. The existence of the tunnel oxide film 32 is only a difference in the thickness of the lower SiO 2 film constituting the ONO film slightly, and the effect of the ONO film does not substantially change.
[0117]
(Example 3.1)
FIGS. 9A to 9D are cross-sectional views of the device in respective steps showing a method for manufacturing the EEPROM according to the third embodiment and the first capacitor shown in FIG. 8A. The left side of each drawing shows an EEPROM mounted on the same chip. A method for manufacturing the first capacitor will be described with reference to these drawings. In this embodiment, each element is manufactured according to the process flow of the EEPROM shown in FIG. However, the formation process of the HV transistor is not described here.
[0118]
As shown in FIG. 9A, in the element isolation region forming step (S3), a LOCOS film 34 is formed on the entire surface of the capacitor formation region. On the other hand, after this, TN is stored in a necessary area in the memory cell of the EEPROM.⁻An impurity diffusion region 24 is formed (S4).
[0119]
Next, as shown in FIG. 9B, after the gate oxide film 30 of the select transistor is formed on the substrate surface (S6), the gate oxide film 30 in the memory transistor formation region is removed by etching. A tunnel oxide film 32 is formed (S7). Subsequently, a first polysilicon film 50 is formed on the substrate surface (S8). In the capacitor formation region, the gate oxide film 30, the tunnel oxide film 32, and the first polysilicon film 50 are stacked on the LOCOS film 34.
[0120]
Thereafter, a slit 100 (see FIG. 2) in which the first polysilicon film and the tunnel oxide film are etched in a strip shape is formed at the cell boundary portion of the memory transistor of the EEPROM (S6) (not shown in FIG. 9). ), But leave the capacitor formation region as it is.
[0121]
As shown in FIG. 9C, an insulating layer 60 made of an ONO film is formed on the first polysilicon film 50. The upper and lower SiO2 films constituting the insulating layer 60 are formed by using an oxidation method. For example, O2 is used as a reaction gas, and a condition of a substrate temperature of 900 ° C. is used. For the Si3N4 film as the intermediate layer, a condition of a substrate temperature of 700 ° C. is used by a CVD method. For example, the upper SiO2 film has a thickness of 60 °, the Si3N4 film has a thickness of 140 °, and the lower SiO2 film has a thickness of 70 °.
[0122]
As shown in FIG. 9D, the second polysilicon film 70, the insulating layer (ONO film) 60, and the first polysilicon film 50 are sequentially etched by RIE using a normal photolithography process. , The necessary gate patterns (52, 72, 54, 74) and openings are formed in the EEPROM formation region (S12), and etching is also performed in the capacitor formation region to form the lower electrode 58, the dielectric layer 68 and the upper electrode 78. Is formed.
[0123]
As described above, by using the ONO film including the Si3N4 film as the dielectric layer of the capacitor, the area can be reduced to about 60% as compared with the conventional capacitor using only the SiO2 film as the dielectric layer 68. It becomes possible.
[0124]
After this, in the EEPROM forming area, the necessary N⁻The impurity diffusion regions 22, 23, 25 and 27 and the source / drain regions 21 and 26 are formed, and the device shown in FIG.
[0125]
(Example 3.2)
FIGS. 10A to 10D are cross-sectional views of the device in respective steps showing a method for manufacturing the EEPROM according to the third embodiment and the second capacitor shown in FIG. 8B. The left side of each drawing shows an EEPROM mounted on the same chip. A method for manufacturing the second capacitor shown in FIG. 8B will be described with reference to these drawings.
[0126]
First, as shown in FIG. 10A, in a device isolation region forming step (S3), a LOCOS film 34 is formed therearound so as to define a capacitor formation region. In the subsequent step, TN is set in a necessary area of the EEPROM memory cell.⁻An impurity diffusion region 24 is formed (S4). At the same time, a TN⁻An impurity diffusion region 29 is formed. This TN⁻The impurity diffusion region 29 forms a lower electrode of the capacitor.
[0127]
Next, a gate oxide film 30 of the select transistor is formed on the substrate surface (S6). Thereafter, the gate oxide film 30 in the memory transistor formation region is removed by etching, and a tunnel oxide film 32 is formed on the substrate surface (S7). . Further, a first polysilicon film 50 is formed on the surface of the substrate. The gate oxide film 30, the tunnel oxide film 32, and the first polysilicon film 50 are also stacked in the capacitor formation region.
[0128]
Thereafter, the first polysilicon film 50 and the tunnel oxide film 32 at the cell boundaries of the memory transistors of the EEPROM are etched into strips to form slits (S9) (not shown in FIG. 9). The first polysilicon film 50, the tunnel oxide film 32 and the gate oxide film 30 in the capacitor formation region are also removed by etching. As shown in FIG. 10 (b), the capacitor forming region is TN⁻Impurity diffusion region 29 is exposed.
[0129]
Next, as shown in FIG. 10C, an insulating layer 60 made of an ONO film is formed on the surface of the substrate. This insulating layer 60 is manufactured under the same conditions as in Example 3.1 described above.
[0130]
As shown in FIG. 10D, the second polysilicon film 70, the insulating layer 60, and the first polysilicon film 50 are sequentially etched by using the RIE method, and gate patterns 52, 72, In addition to forming the openings 54 and 74 and the opening, etching is also performed in the capacitor formation region, and a dielectric layer 68 is formed with the ONO film (insulating layer) 60 and an upper layer electrode 78 is formed with the second polysilicon film 78 to complete the capacitor. I do.
[0131]
In the EEPROM formation area, the necessary N⁻When the impurity diffusion regions 22, 23, 25, 27 and the source / drain regions 21, 26 are formed, the device shown in FIG. 8B is completed.
[0132]
In the capacitor formation region, the gate oxide film 30 may be etched, and the tunnel oxide film 32 may be left without being etched. In this case, as shown in FIG. 8C, a stacked film of the tunnel oxide film 32 and the insulating layer (ONO film) 60 is used as the dielectric layer.
[0133]
As described above, in the capacitor according to the present embodiment, since the layers used in the EEPROM memory cell are used as the upper and lower electrodes and the dielectric layer of the capacitor, no additional process is required in forming the capacitor.
[0134]
Note that, in the third embodiment, the EEPROM according to the first embodiment is illustrated as an EEPROM formed together with the capacitor, but the present invention is not limited to this configuration. For example, in the case of the first capacitor shown in FIG. 8A, an EEPROM having a double-layer polysilicon structure and an ONO film is used to form the first capacitor without burdening the process. it can.
[0135]
In the case of the second and third capacitors, the EEPROM does not necessarily have to have a double-layer polysilicon structure.
[0136]
【The invention's effect】
As described above, the first main feature of the present invention is that in a semiconductor device having a plurality of EEPROM cells arranged in a matrix so that adjacent cells have a common source region, A thin tunnel insulating film is formed over the entire memory transistor formation region of the cell, and a second conductivity type impurity diffusion region having a lower impurity concentration than the source region is provided on the substrate surface layer adjacent to the common source region. .
[0137]
When writing is performed only on one of two adjacent cells with a common source region, the electric field intensity applied between the source region and the floating gate of one cell on which no writing is performed is substantially reduced, and the inter-band leakage current is reduced. And the substantial withstand voltage characteristics of the memory transistor can be improved. Therefore, the reliability of data is high and the number of writable times can be greatly increased while keeping the size of the memory cell small.
[0138]
A second main feature of the semiconductor device of the present invention is that an EEPROM cell having a two-layer polysilicon structure, a high-voltage MOS transistor operable under a high voltage required for writing or erasing data in the EEPROM, and Wherein the high breakdown voltage MOS transistor has an impurity diffusion region formed on the inner substrate surface layer of the source region and the drain region so as to partially overlap each of the regions and the channel formation region immediately below the gate electrode. That is.
[0139]
The presence of the impurity diffusion region formed so as to overlap with the channel formation region can prevent the occurrence of an offset transistor, so that highly reliable operation can be ensured.
[0140]
A third main feature of the semiconductor device of the present invention is that the semiconductor device includes an EEPROM cell having a double-layer polysilicon structure and a booster circuit for supplying a high voltage necessary for writing or erasing data in the EEPROM. Wherein the booster circuit uses a capacitor comprising a lower electrode, an upper electrode, and a dielectric layer sandwiched between these electrodes, and the dielectric layer comprises a first layer constituting the double-layer polysilicon structure. The same material as the insulating layer formed between the polysilicon film and the second polysilicon film, for example, an insulating layer formed by sequentially stacking a silicon oxide film, a silicon nitride film, and a silicon oxide film. .
[0141]
When a two-layer polysilicon structure is manufactured in an EEPROM cell, the above-mentioned capacitor in the booster circuit can be formed at the same time, so that the capacitor can be formed without burdening the process, and the dielectric layer is made of a silicon oxide film, a nitride film. When the capacitor is formed of a layer in which a silicon film and a silicon oxide film are stacked in this order, the area of the capacitor can be reduced due to the presence of the silicon nitride film having a high dielectric constant. In addition, the presence of the silicon oxide film in the dielectric layer indicates that the upper electrode and the lower electrode of the capacitor are formed of a polysilicon film, and that the electrode and the dielectric layer are different from each other when the silicon nitride film is in direct contact with the electrode. Can be alleviated at the boundary of.
[Brief description of the drawings]
FIG. 1 is a device sectional view showing a configuration of an EEPROM according to a first embodiment of the present invention.
FIG. 2 is a device plan view showing an arrangement of memory cells of the EEPROM according to the first embodiment of the present invention.
FIG. 3 is a graph showing a breakdown voltage characteristic of the EEPROM according to the first embodiment of the present invention.
FIG. 4 is a partial cross-sectional view of the device in each step for explaining the method for manufacturing the EEPROM according to the first embodiment of the present invention.
FIG. 5 is a device cross-sectional view illustrating a configuration of a semiconductor device according to a second embodiment of the present invention.
FIG. 6 is a process flow chart showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention.
FIGS. 7A to 7C are cross-sectional views of a device in respective steps for describing a method of manufacturing a semiconductor device according to a second embodiment of the present invention.
FIG. 8 is a device sectional view showing a configuration of three types of semiconductor devices according to a third embodiment of the present invention.
FIGS. 9A to 9C are cross-sectional views of a semiconductor device in respective steps for describing a method of manufacturing one semiconductor device according to a third embodiment of the present invention.
FIGS. 10A to 10C are cross-sectional views of a device in respective steps for describing a method of manufacturing another semiconductor device according to the third embodiment of the present invention.
FIG. 11 is a device sectional view showing a configuration of a conventional EEPROM cell.
FIG. 12 is a plan view and a sectional view of a device showing a configuration of a conventional EEPROM cell.
FIG. 13 is a device sectional view showing a configuration of a conventional EEPROM cell arranged in a matrix.
FIG. 14 is a device cross-sectional view showing a configuration of a conventional EEPROM cell and a high breakdown voltage transistor mounted on the same chip as the EEPROM cell.
[Explanation of symbols]
10 Substrate
21a, 21b Drain region
22a, 23a, 25a, 22b, 23b, 25b N⁻Impurity diffusion region
24a, 24b TN⁻Impurity diffusion region
26 Source area
27a, 27b N⁻Impurity diffusion region
30 Gate oxide film
32 Tunnel oxide film
52a, 54b floating gate
74a, 74b control gate

Claims (8)

In a semiconductor device in which a plurality of EEPROM cells having a selection transistor and a memory transistor are arranged such that memory transistors of adjacent cells have a common source region,
The memory transistor,
A tunnel insulating film formed on a surface of the semiconductor substrate having the first conductivity type;
A floating gate formed on the tunnel insulating film;
An insulating layer formed on the floating gate;
A control gate formed on the insulating layer,
A first impurity diffusion region of a second conductivity type formed in the semiconductor substrate surface layer corresponding to a partial region immediately below the floating gate;
A second conductivity type source region formed in the semiconductor substrate surface layer beside the floating gate ;
A second impurity diffusion region of a second conductivity type having a lower impurity concentration than the source region formed in the substrate surface layer adjacent to the source region;
An opening that penetrates the control gate, the insulating layer and the floating gate,
A semiconductor device having a second conductivity type third impurity diffusion region having an impurity concentration lower than that of the first impurity diffusion region in a substrate surface layer corresponding to the opening region . The select transistor has a second conductive type drain region formed on the side of the gate electrode of the select transistor and a substrate surface layer adjacent to the gate electrode side of the drain region, the second conductive type having a lower impurity concentration than the drain region. A second impurity-type fourth impurity diffusion region;
It said second impurity diffusion region, said third impurity diffusion region, and the fourth impurity diffusion region, the semiconductor device according to claim 1, characterized in that it has substantially the same impurity concentration. Further, it has a peripheral circuit area of the EEPROM,
The peripheral circuit region is operable at a high voltage required for writing or erasing the data in the EEPROM, and the region and the gate are formed on the substrate surface layer at the gate side end of the source region and the drain region. 2. The semiconductor device according to claim 1, further comprising a high-breakdown-voltage MOS transistor having an impurity diffusion region of the same conductivity type as these so as to partially overlap with a channel formation region immediately below the electrodes. Further, it has a peripheral circuit area of the EEPROM,
A booster circuit for supplying a high voltage necessary for writing or erasing data in the EEPROM to the peripheral circuit area ;
In the booster circuit, having a capacitor consisting of an upper electrode and a lower electrode and a dielectric layer sandwiched between these electrodes,
2. The semiconductor device according to claim 1, wherein the dielectric layer includes the same layer as the insulating layer of the EEPROM . In a method of manufacturing a semiconductor device in which a plurality of EEPROM cells having a selection transistor and a memory transistor are arranged such that memory transistors of adjacent cells have a common source region ,
Forming a first impurity diffusion region of the second conductivity type in a part of the first conductivity type substrate surface layer of the memory transistor formation region;
Forming a gate insulating film of a select transistor on the substrate surface;
Removing the gate insulating film on the memory transistor forming region and forming a tunnel insulating film in the removed region;
Sequentially forming a first polysilicon film, an insulating layer, and a second polysilicon film on the gate insulating film and the tunnel insulating film;
Etching the first polysilicon film, the insulating layer, and the second polysilicon film, respectively, to form respective gate patterns of a select transistor and a memory transistor having an opening ;
Forming a plurality of second-conductivity-type low-concentration impurity diffusion regions in the substrate surface layer by an ion implantation method using the gate patterns as an implantation mask;
Forming side walls on the side walls of each of the gate patterns, and using these as an implantation mask, forming source / drain regions as high-concentration impurity diffusion regions of the second conductivity type by ion implantation,
The step of forming the low concentration impurity diffusion region includes forming the low concentration impurity diffusion region partially overlapping the source region together with the low concentration impurity diffusion region partially overlapping the drain region and the first impurity diffusion region. A method of manufacturing a semiconductor device. In the step of forming the gate insulating film, simultaneously forming a gate insulating film in the peripheral circuit region,
  In the step of sequentially forming the first polysilicon film, the insulating layer, and the second polysilicon film, the first polysilicon film, the insulating layer, and the second polysilicon film are simultaneously formed on the gate insulating film in the peripheral circuit region. Formed sequentially,
  In the step of forming each of the gate patterns, the first polysilicon film, the insulating layer and the second polysilicon film are simultaneously etched in the peripheral circuit region to form a gate pattern of a high voltage MOS transistor;
In the step of forming the second conductivity type low concentration impurity diffusion region, simultaneously using the gate pattern of the peripheral circuit region as an implantation mask, forming a second conductivity type low concentration impurity diffusion region;
  Thereafter, sidewalls are formed on the sidewalls of each of the gate patterns, and using the sidewalls as implantation masks, high-concentration impurity diffusion of the second conductivity type is performed by ion implantation into the substrate surface layer in the EEPROM cell formation region and the high breakdown voltage MOS transistor formation region. 6. The method according to claim 5, wherein the source / drain regions are formed.   In the step of forming the gate insulating film, simultaneously forming a gate insulating film in the peripheral circuit region,
  In the step of sequentially forming the first polysilicon film, the insulating layer, and the second polysilicon film, the first polysilicon film, the insulating layer, and the second polysilicon film are simultaneously formed on the gate insulating film in the peripheral circuit region. Formed sequentially,
  In the step of forming each of the gate patterns, the first polysilicon film, the insulating layer, and the second polysilicon film are simultaneously etched in the peripheral circuit region, and the first polysilicon film is used as a lower electrode, and the insulating layer is formed. 6. The method according to claim 5, wherein a capacitor pattern is formed using the first polysilicon film as a dielectric layer and the second polysilicon film as an upper electrode. In the step of forming the first impurity diffusion region, simultaneously forming a first impurity diffusion region in a substrate surface layer of the peripheral circuit region;
  In the step of forming the gate insulating film, simultaneously forming a gate insulating film in the peripheral circuit region,
  In the step of sequentially forming the first polysilicon film, the insulating layer, and the second polysilicon film, simultaneously forming at least the first polysilicon film on the gate insulating film in the peripheral circuit region;
  In the step of forming each of the gate patterns, the first polysilicon film and the gate insulating film are simultaneously etched in the peripheral circuit region, the first impurity diffusion region is used as a lower electrode, and the gate insulating film is made of a dielectric material. 6. The method according to claim 5, wherein a capacitor pattern is formed as a layer and the first polysilicon film is used as an upper electrode.

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