JPH07193200A - Involatile semiconductor memory - Google Patents

Abstract

PURPOSE:To improve the drive capacity of a transistor in a low voltage peripheral circuit region and to increase its performance without spoiling drain breakdown strength. CONSTITUTION:This memory comprises a high voltage peripheral circuit and a low voltage peripheral circuit. Transistors constituting the high voltage peripheral circuit and the low voltage peripheral circuit are LDD type transistors. Lightly-doped regions 72, 72b, and 72c of the transistor formed in the low voltage peripheral circuit region have a distribution of an impurity density higher than in the lightly-doped region of the transistor formed in the high voltage peripheral circuit region. Two lighly-doped regions of the transistors in the high voltage and low voltage peripheral circuits can be built separately by two ion implantations of different depths without adding a special masking step and the like utilizing a dlifference in thickness of a remaining gate oxide film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device and a method for manufacturing the same, and more particularly to a high voltage peripheral circuit transistor to which a high voltage is applied and a low voltage applied without adding a special process. The present invention relates to a nonvolatile semiconductor memory device capable of realizing optimization of a transistor of a low voltage peripheral circuit and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, in a non-volatile semiconductor memory device, a circuit using a high voltage of about 10 V or more (about 10 V to about 20 V) is provided in addition to the 5 V system which is the standard power supply voltage of the present LSI. There is. This is because channel hot electron injection (CHE injection) or FN (Fowler-Nord) is performed in order to inject or extract charges to the floating gate electrode surrounded by the insulating film.
This is because a physical phenomenon that requires a strong electric field, such as heim) tunnel injection, is used.

A large-capacity EEPROM (Electrica) will be described below as an example of a conventional nonvolatile semiconductor memory device.
ly Erasable and Program
A flash memory, which is attracting attention as an "Able Read Only Memory", will be described in detail.

First, the schematic structure and operation of the flash memory will be described with reference to FIGS. Figure 3
Reference numeral 0 is a partial cross-sectional view showing the cross-sectional structure of one memory transistor forming the flash memory. The transistor of the flash memory shown in FIG. 30 is called a stacked gate type. FIG. 31 is a schematic plan view showing a planar arrangement of a conventional stacked gate flash memory. 32 is a partial cross-sectional view taken along the line AA in FIG.

Referring to FIGS. 30 and 32, an n-type drain region 184 and an n-type source region 185 are formed at an interval on the main surface of p-type region 183 provided on a silicon substrate. There is. These n-type drain regions 18
4 and the n-type source region 185,
A control gate electrode 186 and a floating gate electrode 187 are formed so as to form a channel region. The floating gate electrode 187 is the gate insulating film 1 having a film thickness of about 100Å on the channel region.
90 is formed.

The control gate electrode 186 is formed on the floating gate electrode 187 so as to be electrically separated from the floating gate electrode 187.
88 is formed. The floating gate electrode 187 is made of polycrystalline silicon. The control gate electrode 186 is formed of polycrystalline silicon or a laminated film of polycrystalline silicon and a refractory metal. The oxide film 18 is formed so as to cover the floating gate electrode 187 and the control gate electrode 186.
9 is formed, and a smooth coat film 195 is formed on the oxide film 189.

Contact holes are formed in the smooth coat film 195 located on the n-type drain region 184. A bit line 191 is formed on the inner surface of the contact hole and on the smooth coat film 195. As a result, the bit line 191 is electrically connected to the n-type drain region 184. This portion becomes the drain contact portion 196.

Referring to FIG. 31, control gate electrodes 186 are formed as word lines connected to each other and extending in the lateral direction (row direction). The bit line 191 is arranged so as to be orthogonal to the word line 186,
The n-type drain regions 184 arranged in the vertical direction (column direction) are connected to each other. As described above, the bit line 191 is provided in the drain contact portion 196 for each n-type drain region 1.
It is electrically connected to 84. n-type source region 185
Extend in the direction in which the word line 186 extends and are formed in a region surrounded by the word line 186 and the field oxide film 192. Each n-type drain region 184 is also formed in a region surrounded by the word line 186 and the field oxide film 192.

The operation of the flash memory having the above configuration will be described with reference to FIG. First, at the time of writing, a voltage V _{D of} about 6 to 8 V and a voltage V _{G of} about 10 to 15 V are applied to the n-type drain region 184 and the control gate electrode 186, respectively. At this time, the n-type source region 185 and the p-type region 183 are held at the ground potential. As a result, a current of about several 100 μA flows in the channel region of the memory transistor.

Among the electrons flowing from the source region to the drain region, the electrons accelerated in the vicinity of the drain become electrons having high energy in this vicinity, so-called channel hot electrons. This electron is generated by the electric field generated by the voltage V _G applied to the control gate electrode 186 in FIG.
At 0, it is injected into the floating gate electrode 187, as indicated by the arrow (1). In this way, electrons are accumulated in the floating gate electrode 187,
The threshold voltage V _th of the memory transistor becomes higher than a predetermined value. A state in which the threshold voltage V _th is higher than a predetermined value in this way is written, which is called “0”. Usually, this writing operation requires several to several tens of μs.

Next, the erase operation will be described. At the time of erasing, a voltage V _{S of} about 10 to 12 V is applied to the n-type source region 185, and the control gate electrode 186 and the p-type region 183 are held at the ground potential. Then, the n-type drain region 184 is held in a floating state.
Electrons in the floating gate electrode 187 are n-type source region 1 as shown by an arrow (2) in FIG.
An electric field generated by the voltage V _S applied to 85 passes through the thin gate insulating film 190 by a tunnel phenomenon.

As a result, the floating gate electrode 1
The electrons in 87 will be extracted. In this way, the electrons in the floating gate electrode 187 are extracted, so that the threshold voltage V _th of the memory transistor becomes lower than a predetermined value. This threshold voltage V
_The state where _th is lower than a predetermined value is the erased state,
It is called "1". Since the source regions of the memory transistors are connected to each other as shown in FIG. 31, it is possible to collectively erase the information in all the memory cells by this erase operation. For this erase operation,
It usually takes several 100 μS to several seconds.

Next, the read operation will be described. At the time of reading, a voltage V _G ′ of about 5 V is applied to the control gate electrode 186, and a voltage V _D ′ of about 1 to 2 V is applied to the n-type drain region 184. At this time, the determination of "1" or "0" is made depending on whether or not a current flows in the channel region of the memory transistor, that is, whether the memory transistor is in the on state or the off state. This read operation usually requires about 100 ns.

As described above, a high voltage is required for the operation of a nonvolatile semiconductor memory device such as a flash memory. Therefore, the peripheral circuit is provided with a circuit that operates at a high voltage. The peripheral circuit that operates at a high voltage in this manner is referred to as a “high voltage peripheral circuit” in this specification. In the above flash memory, this high voltage peripheral circuit is mainly used for applying a high voltage to the memory cell, such as a write or erase operation.

On the other hand, the peripheral circuit is also provided with a circuit which operates at a standard low voltage (for example, a voltage of about 5V). Peripheral circuits that operate at this low voltage will be referred to as "low voltage peripheral circuits" in this specification. As described above, there are two types of peripheral circuits, a high voltage peripheral circuit and a low voltage peripheral circuit.

Conventionally, as a basic element of the above peripheral circuit, an LDD (Light) as shown in FIG. 33 is generally used.
Tly Doped Drain) type transistors have been used. FIG. 33 is a sectional view showing an example of an LDD type transistor which has been conventionally used as a basic element of a peripheral circuit.

Referring to FIG. 33, p-type semiconductor substrate 201
N on the main surface of the
Low-concentration-type impurity regions 206a and 207a are formed at a predetermined interval. A gate electrode 204 is formed on the channel region 205 with a gate insulating film 202 interposed. In addition, on the main surface of the p-type semiconductor substrate 201, the gate electrode 2 is formed on the main surface of the n-type low-concentration impurity regions 206a and 207a rather than the end portions on the surface of the p-type semiconductor substrate 201.
N-type high-concentration impurity region 206 which has an end portion at a position apart from 04 and extends in a direction away from the gate electrode 204.
b, 207b are formed.

The n-type high-concentration impurity region 206b and the n-type low-concentration impurity region 206a described above form an n-type drain region 206. An n-type source region 207 is composed of the n-type low-concentration impurity region 207a and the n-type high-concentration impurity region 207b. p-type semiconductor substrate 2
01, an interlayer insulating film 209 is formed, and a contact hole is provided in a portion of the interlayer insulating film 209 located above the n-type drain region 206. From the inner surface of this contact hole to the interlayer insulating film 209
The wiring layer 211 is formed on the upper part.

As described above, it has been attempted to secure high withstand voltage by using the LDD type transistor as the basic element of the peripheral circuit. Here, the breakdown voltage of the transistor will be described.

The breakdown voltage of a transistor is generally called an off breakdown voltage or an on breakdown voltage. The OFF breakdown voltage is a source-drain breakdown voltage (BV _{DS 0} ) when the voltage applied to the gate electrode is 0 V, and the ON breakdown voltage is the source when the voltage applied to the gate electrode is changed.・ Minimum drain breakdown voltage (BV _DS )
Is meant. In a normal transistor, B
Since V _DS ≧ BV _{DS 0} , the operating voltage (between source and drain) V _DS of the transistor must satisfy at least the following condition. V _DS > BV _DS By the way, the withstand voltage between the source and drain when the transistor operates is E.V. Sun, J. et al. Moll, J.M. Berge
r, and B. Alders, "Breakdown
Mechanism in Short-Channel
el MOS Transistors, “IEEE T
ech Dig, Int. Electron Devi
ce Meet, Washington D.C. C. 19
78, p. 478. It is a kind of parasitic bipolar effect, as the mechanism is analyzed by. FIG. 34 shows
It is explanatory drawing for demonstrating a parasitic bipolar effect. In the short-channel MOSFET, when the drain voltage is increased, the electric field in the channel direction becomes extremely large near the drain, causing avalanche breakdown. As a result, a large number of electron-hole pairs are generated.

Of the generated carriers, the holes are p-type silicon substrate 301 as shown in FIG.
Flows to the side, becomes a substrate current (I _{su B} ), and partly flows into the n-type source region 303. This n-type source region 30
N-type source region 30
The voltage in the vicinity of 3 is pushed down, and the p between the source region and the substrate is reduced.
When the potential is higher than the built-in potential of the n-junction, a forward current starts flowing in the pn junction between the source region and the substrate.

That is, electrons flow from the n-type source region 303 into the p-type silicon substrate 301. As a result, a parasitic bipolar transistor operation consisting of source-substrate-drain occurs. This becomes a breakdown voltage breakdown phenomenon of the MOS transistor. In FIG. 34, a gate electrode 305 is formed on the channel region with a gate insulating film 304 interposed. Further, a source region 303 and a drain region 302 are formed so as to define the channel region.

The following equations can be given as conditions for the above breakdown voltage breakdown. I _H × R _sub > V _{build-in In the} above formula, I _H represents the current flowing into the source region, and R _sub represents the resistance along the path through which the hole current flows between the substrate and the source region. ing. Also, V
_build-in indicates the built-in potential of the pn junction between the source region and the substrate.

From the above description, it can be said that in order to improve the breakdown voltage of the transistor, it is essential to reduce the hole current generated by the avalanche breakdown. Substrate current (I
_sub ) is a direct barometer of the avalanche breakdown phenomenon. It is also an important parameter used to predict hot carrier deterioration. This substrate current strongly depends on the maximum electric field strength in the channel direction near the drain region, and is generally expressed by the following equation.

I _sub ∝Id · Em ^{n +1 In the} above formula, Id represents the drain current, and Em represents the maximum electric field strength in the channel direction. Also, n≈7
Is. Therefore, from the above equation, it can be said that it is necessary to reduce the maximum electric field intensity Em in order to reduce the substrate current (hole current).

As one method for reducing the maximum electric field intensity Em, it is conceivable to reduce the concentration of the low concentration impurity region in the LDD type transistor. As a result, the depletion layer can be sufficiently extended in the low concentration impurity region, and the electric field strength in that portion can be reduced. FIG. 35 shows the amount of impurity (phosphorus) implanted (dose) in the low-concentration impurity region and the electric field intensity at the channel direction position, which are disclosed in Koyanagi, Kenko, Shimizu, Proceedings of Japan Society of Applied Physics (Autumn 1983). It is a figure which shows a relationship.

As shown in FIG. 35, it can be seen that the maximum value of the horizontal electric field ε _{Y in} the channel is reduced in this case by reducing the amount of lindose. That is, the maximum electric field strength is decreasing.

As described above, in order to improve the breakdown voltage BV _DS of the transistor, it is necessary to suppress the parasitic bipolar effect that determines the breakdown voltage. For that purpose, the hole current must be reduced. For that purpose, it is necessary to suppress the maximum electric field strength Em to be small. As one method for that purpose, it can be said that it is effective to reduce the concentration of the low concentration impurity region of the LDD type transistor.

[0029]

However, as described above, in the peripheral circuit, when the concentration of the low concentration impurity region in the vicinity of the drain region is uniformly lowered so that the source-drain breakdown voltage can be sufficiently secured, However, the following problems will occur.

FIG. 36 shows the drain current I _D (mA),
It is a figure which shows the relationship with the impurity concentration of a low concentration impurity region. Since the resistance of the low concentration impurity region is relatively high, lowering the concentration of the low concentration impurity region increases the resistance value of that portion. As a result, FIG.
As shown in (1), the drain current is reduced by lowering the concentration of the low concentration impurity region.

That is, the operating speed is reduced. As a result, there arises a problem that the driving ability of the transistor is deteriorated. This problem greatly affects the read time. That is, the low-voltage peripheral circuit and the high-voltage peripheral circuit are uniformly reduced in the concentration of the low-concentration impurity region in the vicinity of the drain region as described above, and as a result, the performance such as the reading speed is deteriorated. . On the other hand, regarding the write operation or erase operation,
Since most of the time required for injection or extraction of electrons is taken, it can be said that it does not depend so much on the driving ability of the transistors used in the peripheral circuits.

The present invention has been made to solve the above problems, and one object of the present invention is to reduce the high voltage peripheral circuit without impairing the high breakdown voltage of the transistor in the high voltage peripheral circuit. It is an object of the present invention to provide a non-volatile semiconductor memory device capable of ensuring the driving ability of a transistor of a circuit.

Another object of the present invention is to increase the withstand voltage of a transistor in a high-voltage peripheral circuit and improve the drive capability of a transistor in a low-voltage peripheral circuit without adding an extra step to the conventional manufacturing process. Another object of the present invention is to provide a method for manufacturing a nonvolatile semiconductor memory device.

[0034]

The nonvolatile semiconductor memory device of the present invention has a memory cell array for storing information and a peripheral circuit for controlling the operation of the memory cell array. The peripheral circuit includes a high voltage peripheral circuit having a first transistor to which a relatively high voltage is applied and a low voltage peripheral circuit having a second transistor to which a relatively low voltage is applied. A nonvolatile semiconductor memory device according to the present invention includes a pair of first low-concentration impurity regions of a second conductivity type, a first gate electrode, a pair of first high-concentration impurity regions of a second conductivity type, and A pair of second conductivity type second low-concentration impurity regions, a second gate electrode, and a pair of second conductivity type second high-concentration impurity regions are provided. The first low concentration impurity region is formed on the main surface of the first conductivity type semiconductor substrate so as to define the first channel region of the first transistor. The first gate electrode is formed on the first channel region with an insulating film interposed. The first high-concentration impurity region is located on the main surface of the semiconductor substrate, and the first high-concentration impurity region is first
Has an end portion at a position away from the first gate electrode by a distance of, and extends in a direction away from the first gate electrode. The second low concentration impurity region is formed on the main surface of the semiconductor substrate so as to define the second channel region of the second transistor. The second gate electrode is formed on the second channel region with an insulating film interposed. The second high-concentration impurity region is located on the main surface of the semiconductor substrate at a position separated from the second gate electrode by a first distance from the end of the second low-concentration impurity region on the second channel region side. Has an end portion and extends in a direction away from the second gate electrode.

A nonvolatile semiconductor memory device as defined above, wherein in the device according to claim 1, the second low concentration impurity region has the same concentration distribution as the first low concentration impurity region. The third low concentration impurity region and the fourth low concentration impurity region having a shallower concentration distribution than the first low concentration impurity region.

Further, in the nonvolatile semiconductor memory device defined as described above, in the device according to claim 2, the second low concentration impurity region has an impurity concentration higher than that of the first low concentration impurity region. It has a high concentration distribution.

According to the method of manufacturing a non-volatile semiconductor memory device of the present invention, first, the high voltage peripheral circuit forming region and the low voltage peripheral circuit forming region are insulated on the main surface of the first conductivity type semiconductor substrate. A gate electrode is formed with the film interposed. Using the gate electrode as a mask, ions are implanted into the high-voltage peripheral circuit formation region and the low-voltage peripheral circuit formation region at the first implantation depth to form the second conductivity type first low-concentration impurity region. It By selectively ion-implanting only the first low-concentration impurity region formed in the low-voltage peripheral circuit formation region at the second implantation depth shallower than the first implantation depth, the second conductivity type second Low-concentration impurity regions are formed. A sidewall insulating film is formed on the sidewall of the gate electrode. A second conductivity type high concentration impurity region is formed in the high voltage peripheral circuit forming region and the low voltage peripheral circuit forming region using the gate electrode and the sidewall insulating film as a mask.

According to the method for manufacturing a non-volatile semiconductor memory device of the fourth aspect, in the step of forming the gate electrode,
A gate electrode is formed with a first insulating film having a first film thickness formed on the high voltage peripheral circuit forming region, and the gate electrode is formed to have a thickness smaller than that of the first film formed on the low voltage peripheral circuit forming region. The gate electrode is formed with the second insulating film having a smaller second film thickness interposed.

According to the method of manufacturing a nonvolatile semiconductor memory device of the fifth aspect, in the step of forming the second low concentration impurity region, the second low concentration impurity region is formed by using the gate electrode and the first insulating film as a mask. Ion implantation is performed so as to pass through the insulating film to form the second low concentration impurity region only in the first low concentration impurity region of the low voltage peripheral circuit formation region.

[0040]

According to the nonvolatile semiconductor memory device of the present invention, the low-concentration impurity region of the low-voltage peripheral circuit has a low-concentration impurity region having the same concentration distribution as the high-voltage peripheral circuit, It is formed of a low concentration impurity region having a concentration distribution shallower than the peripheral circuit. Therefore, the low-concentration impurity region of the low-voltage peripheral circuit is formed to have a concentration distribution with a relatively high impurity concentration.

According to another aspect of the nonvolatile semiconductor memory device of the present invention, the low-concentration impurity region of the low-voltage peripheral circuit has a higher concentration distribution than the low-concentration impurity region of the high-voltage peripheral circuit. .

Therefore, according to the nonvolatile semiconductor memory device of the first and second aspects, it is possible to increase the withstand voltage of the transistor of the high-voltage peripheral circuit as in the conventional case, and at the same time, the transistor of the low-voltage peripheral circuit. Is formed so that the resistance value of the low-concentration impurity region is sufficiently low, and the driving capability of the transistor of the low-voltage peripheral circuit is improved.

According to the method of manufacturing a non-volatile semiconductor memory device of the third aspect, the low-concentration impurity region is formed by performing the common ion implantation step in the high-voltage peripheral circuit forming region and the low-voltage peripheral circuit forming region. It is formed. Further, the low-concentration impurity region of the low-voltage peripheral circuit forming region is formed by selectively ion-implanting the low-voltage peripheral circuit forming region at an implantation depth shallower than the above-mentioned ion implantation process. By thus performing the ion implantation process twice with different implantation depths, the transistor of the high-voltage peripheral circuit is made to have a high breakdown voltage and the resistance value of the low-concentration impurity region of the transistor of the low-voltage peripheral circuit is lowered. The driving ability of the transistors of the low voltage peripheral circuit can be improved.

According to the method for manufacturing a nonvolatile semiconductor memory device according to claims 4 and 5, the film thickness of the insulating film (gate insulating film) formed in the high voltage peripheral circuit forming region and the low voltage peripheral circuit forming region. By utilizing the difference between the two, the ion implantation process is performed twice with different implantation depths. As a result, the second ion implantation can be selectively performed only in the low-voltage peripheral circuit formation region without using an additional mask. Therefore, it is possible to easily manufacture a nonvolatile semiconductor memory device in which the driving capability of the transistors of the low-voltage peripheral circuit is improved and the withstand voltage of the transistors of the high-voltage peripheral circuit is increased without adding an extra step to the conventional manufacturing process. be able to.

[0045]

Embodiments of the present invention will be described below with reference to FIGS. 1 is a block diagram of a nonvolatile semiconductor memory device according to an embodiment of the present invention. Referring to FIG. 1, the nonvolatile semiconductor memory device includes an address buffer 107 to which an address of a memory cell to be stored is input, a column decoder 108 to which a column address is input, and a row (ro).
w) A row decoder 109 to which an address is input, a high voltage switch 110 for switching the potential of a word line, an input / output buffer 111 for inputting / outputting data, and a write circuit 112 for holding write data. A sense amplifier 113 for amplifying the read data, a Y gate 114 for selecting a predetermined bit line, a memory cell array 115 composed of memory cells arranged in a matrix, and a memory cell array 115. A high voltage control circuit 120 for controlling a high voltage, a control signal buffer 121 to which a control signal is input, a control circuit 122 for controlling various operations, and a memory cell (memory transistor) forming a memory cell array 115. An array source switch 123 for switching the source potential is included.

In the nonvolatile semiconductor memory device having the above structure, the high voltage peripheral circuit region 101 has a high voltage switch 110, a write circuit 112, and a Y gate 114.
Array source switch 123 and high voltage control circuit 1
Including 20 and. Then, in the peripheral circuit formation region, a region other than the high voltage peripheral circuit region becomes the low voltage peripheral circuit region 102.

A plurality of memory transistors 119 are formed in the memory cell array 115. Each memory transistor 119 has one bit line 116 and one word line 1
It is located at the intersection with 17. The drain region of each memory transistor 119 is connected to the bit line 116, and the control gate electrode is connected to the word line 117. The source region of each memory transistor 119 is commonly connected to the source line 118, and the source line 1
One end of 18 is connected to the array source switch 123.

Next, the operation of the nonvolatile semiconductor memory device configured as described above will be described. The operation of this non-volatile semiconductor memory device is divided into writing, erasing and reading, but the information contained in the memory transistors at all addresses must be erased before the writing operation. .

First, the write operation will be described. The address data of the address to be written is input via the address buffer 107, and the control signal enabling writing is input via the control signal buffer 121. Next, the high voltage V _PP is applied to the high voltage control circuit 120. The input address data is decoded by the row decoder 109 and one word line is selected. On the other hand, the input high voltage V _PP is controlled by the high voltage control circuit 120 and applied to the high voltage switch 110.

High voltage switch 11 for the selected word line
0 brings the selected word line to a high voltage, and the high voltage switches of the other unselected word lines output 0V. On the other hand, the data input via the input / output buffer 111 is latched in the write circuit 112. The write circuit 112 is a Y selected by the column decoder 108.
Through the gate 114, the high voltage V _BL is applied to the bit line including the bit for writing the information “0”, and the potential of 0 V is applied to the bit line including the bit for writing the information “1”. At this time, the potential of the source line 118 is maintained at 0V by the array source switch 123 switched based on the signal output from the control circuit 122.

Next, the batch erase operation will be described. In batch erasing, a high voltage is applied to the high voltage control circuit 120 and a control signal for enabling batch erasing is supplied to the control signal buffer 121.
This is done by typing in. The input high voltage is controlled by the high voltage control circuit 120 and applied to the array source switch 123. Array source switch 123 receives a control signal from control circuit 122, that is, an erase start signal, and outputs high voltage V _PP to source line 118.

At this time, all the word lines 117 of the memory cell array 115 have the potential of 0 V, and all the bit lines 116 are kept in the floating state. In this state, the source regions of all the memory transistors have a high voltage V _PP and the control gate electrodes have a voltage of 0.
The V and drain regions are in a floating state.

As a result, a high electric field is generated between the floating gate electrode and the source region of each memory transistor, and the electrons contained in the floating gate electrode move to the source region by the tunnel phenomenon. As a result, the threshold voltage of the memory transistor becomes lower than that before the erase operation.

Next, the read operation will be described. In the read operation, address data designating the address of the memory cell holding the information to be read is written in the address buffer 107. Then, one word line 117 of the memory cell array 115 is selected by the same operation as the write operation. On the other hand, a predetermined bit line 116 is selected by the Y gate 114 based on the information decoded by the column decoder 108. Only the selected word line 117 has the power supply voltage _Vcc , and the potentials of the other word lines are 0V.

The word line 117 selected in this way
The sense amplifier 11 connected to the selected bit line 116 determines whether the memory transistor connected to the ON state is in the ON state (low threshold voltage) or in the OFF state (high threshold voltage).
Detect with 3. If it is in the ON state, the information "1" is OF
In the F state, information "0" is output to the outside via the input / output buffer 111.

The structure of the non-volatile semiconductor memory device having the above structure and operating will be described in more detail below. FIG. 2 is a partial cross-sectional view showing a high-voltage peripheral circuit region (a), a low-voltage peripheral circuit region (b) and a memory cell array (c) of a nonvolatile semiconductor memory device having the above structure according to an embodiment of the present invention. Is.

Referring to FIG. 2, in the high voltage peripheral circuit region, n well 11 and p well 13 are formed on the main surface of p type silicon substrate 1, respectively. Source / drain regions 78 are formed in the n-well 11 so as to define a channel region. The gate electrode 47a is formed on the channel region through the silicon oxide film 41a.
Are formed. A sidewall insulating film 73a is formed on the sidewall of the gate electrode 47a.

On the other hand, a low concentration impurity region 72a is formed in the p well region 13 so as to define a channel region, and a gate electrode 47a is formed on the channel region via a silicon oxide film 41a. There is. A high-concentration impurity region 76a having an end portion at a position farther from the gate electrode 47a than the low-concentration impurity region 72a and extending in a direction away from the gate electrode 47a is formed. Further, a high-concentration impurity region 99a for making ohmic contact is formed in a contact portion with the upper wiring layer. A sidewall insulating film 73a is formed on the sidewall of the gate electrode 47a.

A silicon oxide film 61, a silicon nitride film 62, and a smooth coat film 63 are formed on the gate electrode 47a.
Are formed respectively. Contact holes are formed in these layers, and an aluminum wiring layer 65 is formed in a predetermined shape from the inner surface of the contact hole to the smooth coat film 63. A smooth coat film 67 is further formed on the aluminum wiring layer 65 and the smooth coat film 63. A contact hole is also provided at a predetermined position in the smooth coat film 67, and an aluminum wiring layer 69 is formed from the inner surface of the contact hole to the smooth coat film 67.

On the other hand, the transistor formed in the low voltage peripheral circuit region has substantially the same structure as the transistor formed in the high voltage peripheral circuit region. However, in this embodiment, the concentration of the low-concentration impurity region 72 is the same as that of the low-concentration impurity region 72a formed in the high-voltage peripheral circuit region, and the concentration of the low-concentration impurity region that is shallowly ion-implanted as described below. It is the sum of the density of the area. The other structure is similar to that of the transistor formed in the high voltage peripheral circuit region.

A p well 13 is formed in the memory cell array, and a source region 56 and a drain region 58 are formed on the surface of the p well 13 so as to define a channel region. A floating gate electrode 49 is formed on the channel region via the silicon oxide film 29, and in this case, an interlayer insulating film having a three-layer structure is formed on the floating gate electrode 49. A control gate electrode 51 is formed on this interlayer insulating film. A silicon oxide film 61, a silicon nitride film 62, and a smooth coat film 63 are formed on the control gate electrode 51, respectively.

A contact hole is provided in a portion of the smooth coat film 63 located on the drain region 58.
An aluminum wiring layer 65 is formed from the inner surface of the contact hole to the smooth coat film 63. An impurity region 99 for making ohmic contact is formed at a contact portion between the aluminum wiring layer 65 and the drain region 58. Aluminum wiring layer 65
A smooth coat film 67 is formed on the smooth coat film 67, and an aluminum wiring layer 69 patterned into a predetermined shape is formed on the smooth coat film 67.

As described above, the concentration of the low concentration impurity region 72 in the low voltage peripheral circuit region is set to the low concentration impurity region 7 of the transistor formed in the high voltage peripheral circuit region.
2a and the concentration of the shallowly ion-implanted impurity region, that is, higher than the concentration of the low-concentration impurity region 72a of the high-voltage peripheral circuit region, the low-voltage peripheral circuit region is formed. It is possible to improve the performance such as the driving ability of the formed transistor. Further, at this time, since the concentration of the low concentration impurity region of the transistor formed in the high voltage peripheral circuit region is almost the same as that of the conventional one, it is possible to secure a high drain breakdown voltage. That is, it is possible to ensure high performance such as driving capability of the transistor formed in the low voltage peripheral circuit without deteriorating various characteristics such as reliability of the transistor formed in the high voltage peripheral circuit.

Next, the structure of each transistor formed in the high voltage peripheral circuit and the low voltage peripheral circuit will be described in more detail with reference to FIGS. 3 and 4. Figure 3
FIG. 4A is a cross-sectional view showing one transistor formed in a high-voltage peripheral circuit region and a diagram showing an impurity concentration distribution in the transistor. Referring to FIG. 3, an end portion of low concentration impurity region 72a in the vicinity of the surface of p well 13 is located below gate electrode 47a, and high concentration impurity region 7 is formed.
The end of 6a near the surface of the p-well 13 is located under the sidewall insulating film 73a.

The concentration of the high concentration impurity region 76a in this case
Is preferably 10^{twenty one}(/ Cm ³) Is about. Well
The concentration of the low concentration impurity region 72a is preferably 1
0^{1 8}(/ Cm³) Is about. Also, in the channel area
The concentration is preferably 10^{1 7}(/ Cm³)
ing.

[0066]

[Table 1]

The values shown in Table 1 are also applied to the following examples.

In contrast to the transistors formed in the high voltage peripheral circuit described above, the transistors formed in the low voltage peripheral circuit are shown in FIG. FIG. 4 is a cross-sectional view of a transistor formed in a low voltage peripheral circuit and a diagram showing an impurity concentration distribution of the transistor.

Referring to FIG. 4, the end portions of the low concentration impurity regions 72b and 72c of the transistor formed in the low voltage peripheral circuit near the surface of the p well 13 are located under the gate electrode 47, and the high concentration impurity regions are formed. The end of the region 76 near the surface of the p well 13 is located below the sidewall insulating film 73. The concentration of the entire low-concentration impurity region 72 is the concentration of the low-concentration impurity region 72a of the transistor of the high-voltage peripheral circuit (the low-concentration impurity region 72c of the transistor of the low-voltage peripheral circuit).
Concentration) and a low concentration impurity region 7 formed by shallow ion implantation
2b concentration. By setting the concentration of the low concentration impurity region 72b by shallow ion implantation to be high,
The total concentration can be made much higher than the concentration of the low concentration impurity region 72a of the high voltage peripheral circuit. As a result, the drivability of the transistors in the low voltage peripheral circuit can be improved. As a result, characteristics such as read speed can be improved.

At this time, the concentration of the high concentration impurity region 76
Is preferably about 10^{twenty one}(/ Cm ³) Is about
The concentration of the low concentration impurity region 72 is preferably 10^{1 9}
(/ Cm³) Is about. Also, in the channel area
The concentration is preferably 10^{1 7}(/ Cm³)
ing. Transistors formed in low-voltage peripheral circuits
Width Lg (μm) of the gate electrode 47 and channel length L2
Are shown in Table 1 above. Also shown in Table 1 above.
Each value to be applied also applies to the following examples.

Next, with reference to FIGS. 5 to 29, a method of manufacturing the nonvolatile semiconductor memory device in the embodiment having the above structure will be described. 5 to 29 are cross-sectional views showing the first to twenty-third steps of the manufacturing process of the nonvolatile semiconductor memory device in the example having the above structure. In addition,
For convenience of description, FIGS. 5 to 20 show the peripheral circuit region (I) and the memory cell array region (II). 21 to 24 show a high voltage peripheral circuit area (a) and a low voltage peripheral circuit area (b). 25 and 2
Reference numeral 6 denotes a high voltage peripheral circuit area (a), a low voltage peripheral circuit area (b), and a memory cell array area (c). 27 to 29 show the peripheral circuit area (I) and the memory cell array area (II).

First, referring to FIG. 5, a silicon oxide film 3 having a film thickness of about 300 Å is formed on the main surface of a p-type <100> silicon substrate 1. Next, a low pressure CVD (Chemical Vapor) is formed on the silicon oxide film 3.
The silicon nitride film 5 having a film thickness of about 500 Å is formed by the deposition method. Then, a resist 7 is deposited on the silicon nitride film 5, and the silicon nitride film 5 on the region where the n well is to be formed is removed by using a photolithography technique and an etching technique. Using this resist 7 as a mask, phosphorus (P) is ion-implanted into the p-type silicon substrate 1. The conditions are 60 KeV, 1.
It is 0 × 10 ¹³ / cm ² . Then, the resist 7 is removed.

Then, referring to FIG. 6, using silicon nitride film 5 as a mask, thermal oxidation is performed to form oxide film 9 having a thickness of about 5000 Å.
Then, the silicon nitride film 5 is removed. Then, using the oxide film 9 as a mask, boron (B) is ion-implanted into the region where the p well is formed. The condition is 100 Ke
V, 4.0 × 10 ¹² / cm ² .

Next, referring to FIG. 7, the impurities implanted into silicon substrate 1 are diffused to form n well 11 and p
Well 13 is formed. The conditions are 1200 ° C. for 6 hours. Then, the oxide film 9 is removed. After that, as shown in FIG. 8, on the main surface of the silicon substrate 1, a silicon oxide film 15 having a film thickness of about 300Å, a polycrystalline silicon film 17 having a film thickness of about 500Å, and a film thickness of about 1000Å. A silicon nitride film 19 and a resist 21 are formed. Then, the silicon nitride film 1 located on the region where the field oxide film is to be formed by using the photolithography technique.
9 and the polycrystalline silicon film 17 are selectively removed.

Next, referring to FIG. 9, after removing resist 21, 700 using silicon nitride film 19 as a mask.
A field oxide film 27 having a film thickness of about 0Å is formed. Then, the silicon nitride film 19 and the polycrystalline silicon film 17 are removed. Next, the silicon substrate 1 in the above state
A resist (not shown) is formed on the main surface of, and only the p well region 13 is removed. Then, using this resist as a mask, the p ⁺ channel stopper layer 25 is formed.
Ion implantation of boron for forming a. The condition is 27
It is 0 KeV and 3.5 × 10 ¹² / cm ² . As a result, the p ⁺ channel stopper layer 25 is formed.

Next, referring to FIG. 10, the silicon oxide film 15 is removed, and a silicon oxide film 29 having a film thickness of about 100 Å is formed on the entire main surface of the silicon substrate 1 by the thermal oxidation method. To do. Then, on the silicon oxide film 29,
A polycrystalline silicon film 31 having a film thickness of about 1000 Å is formed by using the CVD method. This polycrystalline silicon film 31
Becomes the floating gate electrode. A resist 33 is formed on the polycrystalline silicon film 31, and the resist 33 in the peripheral circuit forming region is removed as shown in FIG. Then, using this resist 33 as a mask,
The polycrystalline silicon film 31 located on the peripheral circuit formation region is removed. FIG. 12 is a diagram showing a cross section of the memory cell region shown in FIG. 11 taken along line BB.

Next, as shown in FIG. 13, after removing the resist 33, C is formed on the entire main surface of the silicon substrate 1.
A silicon oxide film 35 having a film thickness of about 150 Å is formed by the VD method. C on the silicon oxide film 35
A silicon nitride film 37 having a film thickness of about 150 Å is formed by using the VD method. After that, two n-channel transistors and p-channel transistors are formed in the peripheral circuit region.
To control the threshold voltage of various types of transistors,
A resist is formed on the entire surface, and first, only the resist formed in the element formation region of the n-channel transistor is removed. Then, using this resist as a mask, the silicon nitride film 37 is etched, and boron (B) is set to 50 KeV, 1
The implantation is performed under the condition of × 10 ¹² / cm ² , and the silicon oxide film 35 and the silicon oxide film 29 are removed by etching. A similar process is performed for p-channel transistors. The implantation conditions are as follows: Boron (B) 20 Ke
V, 2 × 10 ¹² / cm ² .

Thereafter, referring to FIG. 14, a silicon oxide film 41 having a film thickness of about 200Å is formed by a thermal oxidation method. Next, a resist (not shown) is formed on the entire main surface of the silicon substrate in that state, and only the resist formed in the low voltage peripheral circuit region is removed. By etching the silicon oxide film using this resist pattern as a mask, only the silicon oxide film formed in the low voltage peripheral circuit region is removed. After removing the resist, a silicon oxide film having a film thickness of about 150Å is formed again by the thermal oxidation method. As a result, the film thickness of the silicon oxide film in the low voltage peripheral circuit region becomes about 150Å, and the film thickness of the silicon oxide film in the high voltage peripheral circuit region becomes about 300Å due to the thermal oxidation process at this time. In this way, the gate oxide films of the transistors in the low voltage peripheral circuit region and the transistors in the high voltage peripheral circuit region are formed separately. By this oxidation treatment, the outermost surface of the silicon nitride film 37 formed on the upper surface of the memory cell region is converted into the silicon oxide film 42 having a film thickness of about 20Å.

Then, referring to FIG. 15, a polycrystalline silicon film 43 having a film thickness of about 2500 Å is formed on silicon oxide film 41 and silicon oxide film 42 by the CVD method. The polycrystalline silicon film 43 serves as a control gate electrode in the memory cell array region and serves as a gate electrode in the peripheral circuit region. A resist 45 is deposited on the polycrystalline silicon film 43, and the resist 45 is subjected to predetermined patterning. And the resist 45
Is used as a mask to etch the polycrystalline silicon film 43,
As shown in FIG. 16, the gate electrode 47 is formed.
After that, the resist 45 is removed. After etching, a gate oxide film having a film thickness of about 50 Å remains on the active region formation surface of the silicon substrate in the low voltage peripheral circuit region and about 200 Å on the active region formation surface of the silicon substrate in the high voltage peripheral circuit region. ing.

Next, referring to FIG. 17, the silicon substrate 1
A resist 53 is deposited on the entire main surface of. This resist 53 is subjected to a predetermined patterning, and using the resist 53 as a mask, the polycrystalline silicon film 43, the silicon oxide film 42, the silicon nitride film 37, the silicon oxide film 35, and the polycrystalline silicon film 31 in the memory cell array region are formed. It is sequentially removed by etching. As a result, the control gate electrode 51 and the floating gate electrode 49 are formed. FIG. 18 is a view showing a cross section taken along the line CC in FIG.

Next, referring to FIG. 19, after removing resist 53, resist 55 is deposited again on the entire main surface of silicon substrate 1. And this resist 55
Is subjected to predetermined patterning to remove the resist 55 located on the source region of the memory cell array region. Then, using the resist 55 as a mask, phosphorus (P) and arsenic (As) are implanted to form the source region 56 of the memory transistor.

Next, after removing the resist 55, FIG.
As shown in, a resist 57 is deposited on the entire main surface of the silicon substrate 1. By performing a predetermined patterning on the resist 57, the resist 57 located on the drain region of the memory cell array region is removed by etching. Then, using this resist 57 as a mask, holon (B) and arsenic (As) are implanted to form the drain region 58 of the memory transistor.

In order to explain the following steps, for convenience, FIGS. 21 to 24 show a high voltage peripheral circuit region (a) and a low voltage peripheral circuit region (b) in the peripheral circuit region.

Referring to FIG. 21, after removing resist 57, resist 71 is deposited on the entire main surface of silicon substrate 1. By subjecting resist 71 to a predetermined patterning, as shown in FIG. 21, p well 1 in the high voltage peripheral circuit region and the low voltage peripheral circuit region is formed.
The resist 71 located above 3 is removed. Then, phosphorus (P) is ion-implanted using the resist 71 and the gate electrodes 47 and 47a as a mask to form low-concentration impurity regions 72c and 72a. The conditions are 60 KeV, 2
It is × 10 ¹³ / cm ² . In the high voltage peripheral circuit region, this low concentration impurity region 72a becomes the low concentration impurity region itself of the transistor.

Subsequently, arsenic (As) is ion-implanted with very low energy. Conditions are 10 KeV, 2x
It is 10 ¹⁴ / cm ² . When the voltage of arsenic is 10 KeV, the depth (R _p ) into which the ions enter is about 100Å, so in the high voltage peripheral circuit region, it is almost implanted into the remaining gate oxide film (about 200Å film thickness). . However, in the low voltage peripheral circuit area,
Since the remaining gate oxide film (a film thickness of about 50 Å) is thin, most of the ions are implanted into the silicon substrate and the shallow low-concentration impurity region 72b is formed. Therefore, in the transistor in the low voltage peripheral circuit region, the low concentration impurity regions 72c and 72b form the low concentration impurity region 72 of the transistor.

In this way, by utilizing the difference in the thickness of the remaining film of the gate oxide film on the silicon substrate, the concentrations of the low-concentration impurity regions of the transistors in the high-voltage peripheral circuit region and the low-voltage peripheral circuit region are made different. be able to. This allows
It is possible to improve the drivability of the transistor in the low voltage peripheral circuit region and increase the performance of the transistor without adding an extra step.

Next, the resist 71 is removed, and CV is used.
Using the D method, a silicon oxide film having a film thickness of about 1500 Å is formed on the entire main surface of the silicon substrate 1. By subjecting this silicon oxide film to anisotropic etching, as shown in FIG. 22, gate electrodes 47, 4 are formed.
Sidewall insulating films 73 and 73a are formed on the side walls of 7a.

Next, referring to FIG. 23, the silicon substrate 1
A resist 75 is deposited on the entire main surface of. By performing a predetermined patterning on the resist 75, the resist 75 located on the p well 13 in the high voltage peripheral circuit region and the low voltage peripheral circuit region is removed. Then, using the resist 75, the gate electrodes 47, 47a and the sidewall insulating films 73, 73a as a mask, arsenic (As)
High concentration impurity region 7
6, 76a are formed. The conditions are 35 KeV, 4 × 10
It is ¹⁵ / cm ² .

Next, after removing the resist 77,
As shown in FIG. 24, a resist 79 is deposited on the entire main surface of silicon substrate 1. By performing a predetermined patterning on the resist 79, the resist 79 located on the n well 11 in the low voltage peripheral circuit region and the high voltage peripheral circuit region is removed. Then, the resist 79, the gate electrodes 47, 47a, the sidewall insulating films 73, 7
Source / drain regions 78 are formed by ion-implanting BF ₂ using 3a as a mask. The conditions are 20 KeV and 2.0 × 10 ¹⁵ / cm ² .

Next, referring to FIG. 25, after removing the resist 79, a silicon oxide film 61, a silicon nitride film 62 and a smooth coat film 63 are formed. Next, referring to FIG. 26, source / drain regions 7
8 and the high-concentration impurity regions 76, 76a and the region located on the drain region 58, a contact hole 66 is formed.

Then, a resist 81 is deposited on the entire main surface of the silicon substrate 1. By performing a predetermined patterning on the resist 81, the resist 81 located on the p well region 13 in the low voltage peripheral circuit region and the high voltage peripheral circuit region and the resist 81 formed in the memory cell array region are removed. Then, phosphorus (P) is ion-implanted to form high-concentration impurity regions 99 and 99a for making ohmic contact. The conditions are 60 KeV and 2.0 × 10 ¹⁴ / cm ² .

Then, referring to FIG. 27, an aluminum wiring layer 65 is formed on the smooth coat film 63 by the sputtering method. As a result, the contact hole 6
The aluminum wiring layer 65 is electrically connected to the drain region 58 in the memory cell array region and the source region and the drain region in the peripheral circuit region via 6. Then, the aluminum wiring layer 65 is subjected to predetermined patterning.

Next, referring to FIG. 28, the silicon substrate 1
A smooth coat film 67 is formed on the entire main surface of the. Through holes 70 are provided at predetermined positions on the smooth coat film 67.
To form. Then, the aluminum wiring layer 69 is formed on the smooth coat film 67. The aluminum wiring layer 69 and the aluminum wiring layer 65 are electrically connected to each other through a through hole 70. Then, as shown in FIG. 29, the aluminum wiring layer 69 is subjected to predetermined patterning. Through the above steps, the nonvolatile semiconductor memory device shown in FIG. 2 is formed.

Although the present invention is applied to the n-channel transistor in each of the above-mentioned embodiments, the present invention can also be applied to the p-channel transistor.

Further, although phosphorus (P) ions are used as impurity ions in order to form the low-concentration impurity regions 72c and 72a near the drain region of the n-channel transistor in the above embodiment, arsenic (As) ions are used. May be used. Although arsenic (As) ions are used as impurity ions for forming the low-concentration impurity region 72b, phosphorus (P) ions may be used. Further, although BF ₂ is used as the impurity ions for forming the source / drain regions of the p-channel transistor, boron (B) may be used. Furthermore, although the ion implantation angle is not inclined in the above-mentioned embodiment, the oblique continuous rotation implantation method may be used. The implantation depth (R _p ) and the implantation amount of phosphorus (P) for forming the low-concentration impurity regions 72c and 72a are merely examples in the embodiment, and may be freely selected. The implantation depth (R _p ) of arsenic (As) for forming the low concentration impurity region 72b is in the range of about ¼ to ⅔ of the remaining film of the gate oxide film of the transistor in the high voltage peripheral circuit region. You may choose freely. There is no limitation on the ion implantation amount for forming the low concentration impurity region 72b.

[0096]

As described above, according to the non-volatile semiconductor memory device according to the first and second aspects, the LDD type transistor formed in the high voltage peripheral circuit region does not impair the breakdown voltage of the low voltage peripheral circuit. It is possible to enhance the driving ability of the transistor formed in the circuit region. This makes it possible to obtain a nonvolatile semiconductor memory device with higher performance and higher reliability.

According to the method for manufacturing a non-volatile semiconductor memory device according to the third, fourth and fifth aspects, the LDD type transistor in the low voltage peripheral circuit region can be formed without adding a special process to the conventional manufacturing process. It is possible to improve driving ability and performance.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a nonvolatile semiconductor memory device in one embodiment according to the present invention.

FIG. 2 is a partial sectional view showing a nonvolatile semiconductor memory device according to a first embodiment of the present invention (a), (b),
It is (c).

FIG. 3 is a cross-sectional view showing a transistor formed in a high voltage peripheral circuit region and an impurity concentration distribution in an embodiment according to the present invention.

4A and 4B are a sectional view and a diagram showing an impurity concentration distribution of a transistor formed in a low voltage peripheral circuit region in an example according to the present invention.

FIG. 5 is a sectional view (I) showing a first step of a method for manufacturing a nonvolatile semiconductor memory device according to an embodiment of the invention.
(II).

FIG. 6 is a sectional view (I) showing a second step of the method for manufacturing a nonvolatile semiconductor memory device according to the embodiment of the invention.
(II).

FIG. 7 is a sectional view (I) showing a third step of the method for manufacturing a nonvolatile semiconductor memory device according to the embodiment of the invention.
(II).

FIG. 8 is a sectional view (I) showing a fourth step of the method for manufacturing a nonvolatile semiconductor memory device according to the embodiment of the invention.
(II).

FIG. 9 is a sectional view (I) showing a fifth step of the method for manufacturing a nonvolatile semiconductor memory device according to the embodiment of the invention.
(II).

FIG. 10 is a sectional view (I), (II) showing a sixth step of the method for manufacturing a nonvolatile semiconductor memory device in an example according to the present invention.

FIG. 11 is a sectional view (I), (II) showing a seventh step of the method for manufacturing the nonvolatile semiconductor memory device in the example according to the present invention.

12 is a view showing a cross section taken along line BB shown in FIG.

FIG. 13 is a sectional view (I), (II) showing an eighth step of the method for manufacturing a nonvolatile semiconductor memory device in an example according to the present invention.

FIG. 14 is a sectional view (I), (II) showing a ninth step of the method for manufacturing a nonvolatile semiconductor memory device in an example according to the present invention.

FIG. 15 is a cross sectional view (I), (II) showing a tenth step of the method for manufacturing a nonvolatile semiconductor memory device in an example according to the present invention.

FIG. 16 is a sectional view (I), (II) showing an eleventh step of the method for manufacturing the nonvolatile semiconductor memory device in the example based on the present invention.

FIG. 17 is a sectional view (I), (II) showing a twelfth step of the method for manufacturing the nonvolatile semiconductor memory device in the example based on the present invention.

FIG. 18 is a diagram showing a cross section taken along line C-C in FIG. 17.

FIG. 19 is a sectional view (I), (II) showing a thirteenth step of the method for manufacturing a nonvolatile semiconductor memory device in an example according to the present invention.

FIG. 20 is a sectional view (I), (II) showing a fourteenth step of the method for manufacturing a nonvolatile semiconductor memory device in an example according to the present invention.

FIG. 21 is a sectional view (a), (b) showing a fifteenth step of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention.

FIG. 22 is a sectional view (a), (b) showing a sixteenth step of the method for manufacturing a nonvolatile semiconductor memory device in an example according to the present invention.

FIG. 23 is a sectional view (a), (b) showing a seventeenth step of the method for manufacturing a nonvolatile semiconductor memory device in an example according to the present invention.

FIG. 24 is a sectional view (a), (b) showing an eighteenth step of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention.

FIG. 25 is a sectional view (a), (b), (c) showing a nineteenth step of the method for manufacturing a nonvolatile semiconductor memory device in an example according to the present invention.

FIG. 26 is a sectional view (a), (b), (c) showing a twentieth step of the method for manufacturing the nonvolatile semiconductor memory device in the example based on the present invention.

FIG. 27 is a sectional view (I), (II) showing a 21st step of the method for manufacturing the nonvolatile semiconductor memory device in the example based on the present invention.

FIG. 28 is a sectional view (I), (II) showing a twenty-second step of the method for manufacturing the nonvolatile semiconductor memory device in the example based on the present invention.

FIG. 29 is a sectional view (I), (II) showing a twenty-third step of the method for manufacturing a nonvolatile semiconductor memory device in an example according to the present invention.

FIG. 30 is a cross-sectional view showing a memory transistor in a conventional nonvolatile semiconductor memory device.

FIG. 31 is a partial plan view of a memory cell array of a conventional nonvolatile semiconductor memory device.

FIG. 32 is a diagram showing a cross section taken along line AA in FIG. 31.

FIG. 33 is a cross-sectional view showing an LDD type transistor formed in a peripheral circuit region of a conventional nonvolatile semiconductor memory device.

FIG. 34 is a cross-sectional view of a transistor for explaining a parasitic bipolar effect.

FIG. 35 is a diagram showing a relationship between a position of a transistor in a channel direction and electric field strength in a channel horizontal direction.

FIG. 36 shows an impurity concentration (× 10 ¹⁸ / cm ³ ) and a drain current (m) in a low-concentration impurity region of an LDD transistor.
It is a figure which shows the relationship with A).

[Explanation of symbols]

 1 p-type silicon substrate 41, 41a silicon oxide film 13 p-well 47, 47a gate electrode 73, 73a sidewall insulating film 72, 72a, 72b, 72c low-concentration impurity region 76, 76a high-concentration impurity region 101 high-voltage peripheral circuit region 102 Low voltage peripheral circuit area

Claims (5)

[Claims] 1. A memory cell array for storing information, and a peripheral circuit for controlling the operation of the memory cell array, wherein the peripheral circuit has a first transistor to which a relatively high voltage is applied. A nonvolatile semiconductor memory device including a high-voltage peripheral circuit and a low-voltage peripheral circuit having a second transistor to which a relatively low voltage is applied, wherein a first channel region of the first transistor is defined. And a pair of first low-concentration impurity regions of the second conductivity type formed on the main surface of the semiconductor substrate of the first conductivity type, and an insulating film interposed on the first channel region. A first gate electrode and a first surface of the main surface of the semiconductor substrate, the first low-concentration impurity region being closer to the first channel region than an end of the first low-concentration impurity region on the first channel region side;
A pair of first high-concentration impurity regions of a second conductivity type having an end portion at a position distant from the first gate electrode and extending in a direction away from the first gate electrode; A pair of second conductivity type second low-concentration impurity regions formed on the main surface of the semiconductor substrate so as to define the second channel region of the transistor, and an insulating film on the second channel region. On the main surface of the semiconductor substrate and the second gate electrode formed so as to be interposed, the first distance from the end of the second low-concentration impurity region on the second channel region side is the first distance. A pair of second high-concentration impurity regions of the second conductivity type, the second low-concentration impurity regions having an end portion apart from the second gate electrode and extending in a direction away from the second gate electrode. The impurity region is the first low concentration impurity region. Non-volatile semiconductor memory device including a third low-concentration impurity region having the same concentration distribution as the region and a fourth low-concentration impurity region having a shallower concentration distribution than the first low-concentration impurity region. . 2. A memory cell array for storing information, and a peripheral circuit for controlling the operation of the memory cell array, wherein the peripheral circuit has a first transistor to which a relatively high voltage is applied. A nonvolatile semiconductor memory device including a high-voltage peripheral circuit and a low-voltage peripheral circuit having a second transistor to which a relatively low voltage is applied, wherein a first channel region of the first transistor is defined. And a pair of first low-concentration impurity regions of the second conductivity type formed on the main surface of the semiconductor substrate of the first conductivity type, and an insulating film interposed on the first channel region. A first gate electrode and a first surface of the main surface of the semiconductor substrate that is closer to the first channel region than an end of the first low-concentration impurity region on the first channel region side;
A pair of first high-concentration impurity regions of a second conductivity type having an end portion at a position distant from the first gate electrode and extending in a direction away from the first gate electrode; A pair of second conductivity type second low-concentration impurity regions formed on the main surface of the semiconductor substrate so as to define the second channel region of the transistor, and an insulating film on the second channel region. On the main surface of the semiconductor substrate and the second gate electrode formed so as to be interposed, the first distance from the end of the second low-concentration impurity region on the second channel region side is the first distance. A pair of second high-concentration impurity regions of the second conductivity type, the second low-concentration impurity regions having an end portion apart from the second gate electrode and extending in a direction away from the second gate electrode. The impurity region is the first low concentration impurity region. A nonvolatile semiconductor memory device having a concentration distribution in which an impurity concentration is higher than a region. 3. A memory cell array for storing information, and a peripheral circuit for controlling the operation of the memory cell array, wherein the peripheral circuit has a first transistor to which a relatively high voltage is applied. A method of manufacturing a nonvolatile semiconductor memory device, comprising: a high-voltage peripheral circuit; and a low-voltage peripheral circuit having a second transistor to which a relatively low voltage is applied, the main surface of a semiconductor substrate of a first conductivity type. Forming a gate electrode on the high-voltage peripheral circuit forming region and the low-voltage peripheral circuit forming region with an insulating film interposed therebetween; and using the gate electrode as a mask, the high-voltage peripheral circuit forming region and the low-voltage peripheral circuit forming region. Forming a first low-concentration impurity region of the second conductivity type by ion-implanting a voltage peripheral circuit forming region at a first implantation depth; A second low-concentration impurity region of the second conductivity type is formed by selectively ion-implanting only the first low-concentration impurity region with a second implantation depth shallower than the first implantation depth. A step of forming a sidewall insulating film on the side wall of the gate electrode, a step of forming a sidewall insulating film on the high voltage peripheral circuit forming region and the low voltage peripheral circuit forming region using the gate electrode and the sidewall insulating film as a mask. And a step of forming a two-conductivity-type high-concentration impurity region. 4. The step of forming the gate electrode, the step of forming the gate electrode with a first insulating film having a first film thickness formed on the high voltage peripheral circuit forming region interposed therebetween. 4. A step of forming a gate electrode with a second insulating film having a second film thickness smaller than the first film thickness formed on the low voltage peripheral circuit forming region interposed therebetween. A method for manufacturing a non-volatile semiconductor memory device according to item 1. 5. The step of forming the second low-concentration impurity region is performed by implanting ions using the gate electrode and the first insulating film as a mask so as to pass through the second insulating film. 5. The method for manufacturing a nonvolatile semiconductor memory device according to claim 4, further comprising forming the second low-concentration impurity region only in the first low-concentration impurity region of the low-voltage peripheral circuit formation region.