KR0165474B1 - Mask rom cell & method of fabricating transistor for protecting stand-by - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mask ROM cell for forming a transistor that blocks the flow of leakage current between string blocks and a method for manufacturing a transistor for preventing standby.

Each string block constituting the mask ROM cell of the present invention includes a string select line, a plurality of word lines formed in parallel with the string select lines, a plurality of bit lines and a Vss line formed perpendicular to the string select lines, and the word lines. And a bit line contact to which the bit line is connected, a Vss line contact to which the Vss line is connected, and a standby line formed parallel to the left and right sides of the Vss line, wherein the string block is disposed between the upper and lower adjacent string blocks. A standby prevention transistor connected to the standby line SB / L is formed.

The present invention can increase the operating margin of the device by increasing the string current by increasing the width of the standby prevention transistor, and because the standby prevention transistor is connected to the standby line by a metal, there is no process problem. It can be minimized.

Description

Mask ROM Cell and its manufacturing method for preventing standby transistor

1 is a plan view showing the layout of a conventional mask ROM cell according to the prior art.

FIG. 2 is an equivalent circuit diagram showing a part of FIG. 1.

3 is a plan view showing the layout of a mask ROM cell according to the prior art in which the number of standby lines is reduced.

4 is a plan view showing the layout of a mask ROM cell according to the present invention.

FIG. 5 is an equivalent circuit diagram showing a part of FIG.

6 through 10 are cross-sectional views illustrating a fabrication procedure of a standby prevention transistor according to the mask ROM structure of the present invention along the cutting line A-A 'of FIG.

* Explanation of symbols for main parts of the drawings

A: String block 10: Bitline contact

20: Vss line contact 30: Standby line contact

ST: Standby prevention transistor SB / L: Standby line

S / L: String Selection Line W / L: Word Line

V / L: Vss Line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mask rom cell and a method for manufacturing a transistor for preventing standby thereof, and more particularly to a mask rom cell for blocking leakage current in a standby state by forming transistors shared between upper and lower adjacent string blocks. It relates to a transistor manufacturing method.

Strings in which transistors constituting a main cell (one transistor per cell), which is a structural feature of a NAND type mask ROM cell, are connected in series are two-dimensionally arranged. Each string is sequentially connected to a string select transistor having a string selection function and a cell transistor storing information in a bit line (B / L). The gate electrode of the cell transistor is connected to a gate electrode of a neighboring string by a word line (W / L), and the string select transistor gate electrode is connected by a string select line (S / L). It is connected to a string select transistor gate electrode of a neighboring string. Bit line contacts forming a path for sensing data when a specific cell transistor of a mask ROM cell is selected are formed in the bit line.

On the other hand, in the case of the product with the Bit Correction Scheme, the leakage current occurs in the standby cell during standby, even though the failure cell is saved. This can be Therefore, to prevent this, a standby prevention transistor is provided at the end of the string to block the flow of leakage current. The standby prevention transistors of each string are connected to each other by a standby by line (SB / L).

Hereinafter, the configuration and operation of the mask ROM cell according to the prior art will be described in detail with reference to the accompanying drawings.

Referring to FIG. 1, a conventional mask ROM cell includes a plurality of string blocks A connected in series in a vertically symmetrical structure based on a bit line contact 110. The string block A includes two string selection lines S / L formed horizontally, a plurality of word lines W / L and one standby line formed in parallel with the string selection lines S / L. (SB / L) and a plurality of bit lines (B / L) formed vertically in the same figure so as to be perpendicular to all the lines and connected to the bit line contact 110, and the bit lines (B / L) and Vss line (V / L) formed in parallel and the Vss line (V / L) is connected to the Vss line contact 120 is connected.

In more detail with reference to FIG. 2, each string is connected to the word line (W / L) and connected to the cell transistors (C1, ... Cn) for inputting and outputting information, and to the string selection line (S / L). The string selection transistors S1 and S2 for determining whether to select a string, and a standby prevention transistor ST connected to the standby line SB / L to block leakage current during standby, respectively. Serially connected with (B / L).

One of the two string select transistors S1 and S2 present in each string is a channel enhancement mode transistor, and the other is composed of a channel depletion mode transistor. In addition, the string select transistor of a neighboring string connected through the channel increase transistor and the string select line S / L is configured as a channel depletion type, and likewise, the channel depletion transistor and the string select line S / L The string select transistors of the neighboring strings connected through C1 are configured in channel increments.

The reason is that the channel increasing transistor has a threshold voltage (V _T ) has a positive value, and the channel depletion transistor has a characteristic that the threshold voltage (V _T ) has a negative value. This is to allow only one string to be selectively connected by two strings connected to the bit lines B / L by opposite voltages applied to the two string select lines S1 and S2.

The standby prevention transistor ST is configured as a channel enhancement mode transistor, and in the standby state, the gate is turned to a low level so that current flows to the Vss line. In operation, the gate is turned to a high level to be turned on to form a path of current flow to the Vss line.

The mask ROM cells according to the related art are formed one by one for each string to prevent leakage current in the standby state, and a standby prevention transistor ST connected to the standby line SB / L is used in each string. Since it acts as a resistor, it is a factor that lowers the string current when the mask ROM cell operates.

In addition, since one standby line (SB / L) is formed for each string block, the standby line (SB / L) is a factor of increasing the size of the chip and a factor of lowering the yield due to process defects.

In order to solve the above-described problem, a mask ROM cell in which the number of standby lines is cut in half by sharing one standby line up and down with adjacent string blocks is shown in FIG. 3.

Referring to FIG. 3, a string block B of a conventional mask ROM cell includes a string select line S / L formed horizontally to connect a gate electrode of a string select transistor included in each string, and left and right sides of each string. A plurality of word lines (W / L) formed in parallel with the string select line (S / L) to connect the gate electrodes of neighboring cell transistors to each other, and a plurality of bits formed vertically in the same direction so as to be perpendicular to all the lines. A line B / L, a Vss line V / L formed in parallel with the bit line B / L, and a Vss line contact 120 to which the Vss line V / L is connected.

A bit line contact 110 to which the bit line B / L is connected is formed at an upper end of the string block B so that the string block connected upward is formed symmetrically, and the string block B is formed. The standby line SB / L is formed in parallel with the word line W / L so that the string blocks connected to the lower side are symmetrically formed.

The Vss line contacts 120 are formed one by one symmetrically up and down with respect to the standby line SB / L.

Hereinafter, the functions of the mask ROM cell of the related art having the above configuration will be briefly described by dividing the functions into a standby state and an operating state.

When the mask ROM cell is in the standby state, the leakage current generated is turned off to turn off the standby prevention transistor connected to the standby line SB / L to prevent a current flow path, thereby preventing an overcurrent fault. Over Fail). In addition, when the mask ROM cell is in an operating state, the stored standby data SB / L is turned on to generate a string current path so that the stored information data is read through the bit line B / L.

The mask ROM cell of the prior art as described above has the advantage of reducing the chip size by sharing one standby line with two adjacent strings up and down, but the standby line SB / L is a word line. Lay-out parallel to the W / L), the standby line (SB / L) and the word line (W / L) may be caused by various factors of the particle or photolithography process in the polysilicon stage of the manufacturing process. The case where L) shorts frequently occurs.

When the standby line SB / L and the word line W / L are shorted, the standby line SB / L maintains a high level in the standby state and the word line W / L maintains a low level so that a path of leakage current is formed, causing a standby current fail during the test. In addition, there is a problem that causes a function failure in the operating state.

Accordingly, an object of the present invention is to solve the above problems, a mask ROM that can lay out the standby line of the string perpendicular to the word line of the cell transistor to reduce the functional defect and at the same time block the leakage current To provide a cell.

Another object of the present invention is to provide a mask ROM cell capable of increasing the margin of operation of a device by increasing a string current by controlling a distance between string blocks to increase a width of a standby prevention transistor.

It is still another object of the present invention to provide a method for manufacturing a standby prevention transistor of a mask ROM cell which blocks a leakage current in the mask ROM cell as described above.

In order to achieve the above object, the present invention provides a mask ROM cell in which a plurality of string blocks are connected in series, wherein each string block includes two string selection lines S / L and the string selection lines S. / L) a plurality of word lines (W / L) formed in parallel, a plurality of bit lines (B / L) formed perpendicular to the string selection line (S / L) and the word line (W / L), A bit line contact (B / L contact) to which the bit line (B / L) is connected, a Vss line (V / L) formed in parallel with the bit line (B / L), and the Vss line (V / L) ) Is composed of a Vss line contact (V / L contact) and two standby lines (SB / L) formed in parallel to the left and right sides of the Vss line (V / L), the string block adjacent to the upper and lower Between the standby line (SB / L) is characterized in that the standby prevention transistor is connected via a standby line contact Mask ROM provides a cell.

According to a preferred embodiment of the present invention, the one standby protection transistor is formed to be simultaneously connected to the source terminals of two strings sharing one bit line, and the standby prevention transistor and the standby line are made of metal. ).

The standby prevention transistor is formed of a channel increasing type NMOS formed at a predetermined angle or perpendicular to the cell transistor connected to the word line.

According to another aspect of the present invention, a string select line and a word line are formed in parallel, and a bit line, a Vss line, and a standby line are formed to perpendicularly cross the string select line and the word line, respectively. A method for manufacturing a mask ROM cell in which a plurality of string blocks are connected in series; Forming gates so as to be left-right symmetrical with respect to the Vss line formation position with the active regions between the upper and lower adjacent field regions of the string block; Doping the impurity to form a source / drain region that is simultaneously connected to source terminals of two strings sharing the bit line; And forming an insulating layer on the entire surface of the resultant, and forming a contact hole connected to the gate and a part of the source / drain region at the Vss line forming position, respectively, and connected to the source / drain region through the contact hole. A method of manufacturing a standby prevention transistor of a mask ROM cell, the method comprising forming a Vss line and a standby line connected to the gate.

According to a preferred embodiment of the present invention, the source / drain regions are formed in an N + type, and the Vss line and the standby line are formed of metal.

In the present invention, since the standby line is formed parallel to the bit line, the width of the standby prevention transistor increases according to the interval between the string blocks, thereby increasing the string current, thereby increasing the operating margin of the device. Since the gate of the standby prevention transistor is connected to the standby line above the insulating layer through the standby line contact, a short with the word line is prevented, thereby minimizing a process problem.

Hereinafter, a method for manufacturing a mask ROM cell and a standby prevention transistor thereof according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

4 is a plan view of a mask ROM cell according to the present invention, FIG. 5 is an equivalent circuit diagram showing part of FIG. 4, and FIGS. 6 to 10 are procedures for manufacturing a standby prevention transistor of the mask ROM cell of the present invention. It is sectional drawing to show.

Referring to FIG. 4, a plurality of string blocks A are connected in series. Each string block A includes two string select lines S / L, a plurality of word lines W / L formed in parallel with the string select lines S / L, and the string select lines S / L) and a plurality of bit lines B / L formed to vertically intersect the word lines W / L and bit line contacts B / L contacts 10 to which the bit lines B / L are connected. ), A Vss line (V / L) formed in parallel with the bit line (B / L), a Vss line contact 20 to which the Vss line (V / L) is connected, and the Vss line (V / L). ) Two standby lines (SB / L) formed parallel to the left and right sides, a standby line contact (30) to which the standby lines (SB / L) are connected, and the standby lines (SB / L). The gate is connected and the source / drain region includes a standby prevention transistor ST formed to be connected to an end of the string and the Vss line V / L.

The bit line contacts 10 are positioned at the top of the string block A, and each string block adjacent to each other in the vertical direction is symmetrically formed with respect to the bit line contacts 10. In addition, the standby prevention transistor ST is located at the lower end of the string block A and is shared with the string block adjacent to the lower side.

In more detail with reference to FIG. 5, two strings share one bit line B / L. Each string includes string select transistors S1 and S2 connected to the string select line S / L, cell transistors C1, Cn connected to the word line W / L, and a standby line The standby prevention transistors ST connected to SB / L are sequentially connected in series.

The word line W / L is formed of polysilicon (ploy-Si), and the Vss line V / L is formed of metal.

6 to 10, the manufacturing sequence of the standby prevention transistor ST is performed by first forming a gate oxide film (Gox) 31 using the field regions of the string blocks A adjacent to each other vertically as an active region. , Poly 32 and tungsten silicide (WSi) 33 are sequentially stacked and subjected to an etching process to form a gate (FIG. 6).

Thereafter, an N + type impurity is doped between the gates to form a source / drain region 34 (FIG. 7).

The first insulating layer 35 is formed on the entire surface of the resultant, and the contact hole 36 is formed to expose a portion of the source / drain region 34 at the position where the Vss line V / L is formed by performing an etching process. do. At this time, a contact hole (not shown) for forming a standby line contact connected to the gate is also simultaneously formed (FIG. 8).

After deposition using metal to be embedded in the contact hole 36, an etching process is performed to form a Vss line (V / L) 37 and a standby line 37 '. Degree).

A second insulating layer 38 is again formed on the entire surface of the resultant product (FIG. 10).

In the present invention as described above, the standby line (SB / L) is in a low state during the standby state by turning off the standby prevention transistor (ST) in the cell (cell) Shut off the flow of leakage current.

In the operating state, the standby line SB / L is high, the word line W / L of the selected cell transistor is low, and the word line W / L of the non-selected cell transistor is ) Becomes a high state.

As described above, in the present invention, since the standby line is formed in parallel with the bit line, the width W of the standby prevention transistor increases according to the interval between the string blocks A, thereby increasing the string. Increasing the current has the effect of increasing the operating margin of the device.

In addition, since the standby prevention transistor is connected to the standby line by a metal, it is possible to minimize a process problem by preventing a short with the word line.

The present invention is not limited to the above embodiments, and it is apparent that many modifications can be made by those skilled in the art within the technical idea of the present invention.

Claims (6)

A mask ROM cell in which a plurality of string blocks are connected in series; Each string block includes two string select lines S / L, a plurality of word lines W / L formed in parallel with the string select lines S / L, and the string select lines S / L. ) And a plurality of bit lines (B / L) formed perpendicular to the word line (W / L), bit line contacts (B / L contact) to which the bit lines (B / L) are connected, and the bit lines ( Vss lines (V / L) formed in parallel with B / L), Vss line contacts (V / L contact) to which the Vss lines (V / L) are connected, and the left and right sides of the Vss lines (V / L). A mask comprising two standby lines (SB / L) formed in parallel and having a standby prevention transistor connected to the standby lines (SB / L) between the string blocks adjacent to each other. Rom Cell. The mask ROM cell of claim 1, wherein the one standby protection transistor is formed to be simultaneously connected to source terminals of two strings sharing one bit line. The mask ROM cell of claim 1, wherein the stevane preventing transistor and the standby line are connected through a standby line contact. The mask ROM cell of claim 1, wherein the standby prevention transistor is formed at a predetermined angle or perpendicular to a cell transistor connected to a word line. Fabrication of a mask ROM cell in which a string selection line and a word line are formed in parallel, and a bit line, a Vss line, and a standby line are formed to cross each other perpendicularly to the string selection line and the word line, respectively. In the method; Forming gates so as to be left-right symmetrical with respect to the Vss line formation position with the active regions between the upper and lower adjacent field regions of the string block; Doping the impurity to form a source / drain region that is simultaneously connected to source terminals of two strings sharing the bit line; And forming an insulating layer on the entire surface of the resultant, and forming a contact hole for connecting a portion of the source / drain region and the gate at the Vss line forming position, respectively, and connecting the source / drain region through the contact hole. And forming a standby line connected to the Vss line and the gate. The method of claim 5, wherein the Vss line and the standby line are formed of metal.