KR900004730B1 - Semiconductor memory device and method for production thereof - Google Patents

Abstract

Semiconductor memory has a semiconductor body of a first conductivity type, a memory cell zone with a number of memory cells in pt. of the body and a peripheral switching zone (Q1-Q5) on another pt. of the body. There is a first switching zone of switching elements operating at a first switching zone of switching elements operating at a first voltage and a second switching zone of elements operating at a second lower voltage. The elements of the first zone consist of first IGFET with channels of the second conductivity type, whilst the elements of the second zone consist of several pairs of good IGFETs having channels of the first conductivity type and channels of the secon conductivity type.

Description

Semiconductor memory device and manufacturing method thereof

1 is a block diagram of an essential part of an erasable programmable ROM (EPROM) according to the present invention.

FIG. 2 is a partial equivalent circuit diagram of the EPROM shown in FIG.

3 is a cross-sectional view of a portion of a memory cell portion and a peripheral circuit portion of the EPROM shown in FIG.

4 is a partial sectional view of a high voltage application circuit with high breakdown voltage.

5A to 5I are cross-sectional views at each step showing manufacturing steps of the memory cell portion and the peripheral circuit portion shown in FIG.

6A to 6C are cross-sectional views in the process showing important steps of the manufacturing process of the high voltage application circuit portion shown in FIG.

The present invention relates to semiconductor memory devices, in particular erasable programmable ROM (hereinafter referred to as EROM).

In the EPROM, the memory cell portion and the peripheral circuit portion are generally composed of an N-channel type metal insulator semiconductor effect transistor (hereinafter referred to as MISFET) to achieve high burning and high integration.

In this case, in order to reduce the current consumption, the present inventors have studied the configuration of the peripheral circuit part as a complementary MOS (hereinafter referred to as CMOS), but it has been found that the following problem occurs when only the CMOS is formed.

In other words, wells are commonly formed in an N-type semiconductor substrate, and N-channel MISFETs are placed in the P-type wells. A connection area for well grounding is connected to the periphery of the wells in relation to the wiring between the elements. You must place it. As a result, the distance between the device and the connection region is increased. As a result, especially in the part where high voltage (21 V or 25 V for memory operation) is applied, when the hole discharged from the drain side to the center of the well moves to the connection area during operation, the electrical resistance becomes large, and thus the voltage drop. The minute causes the well to rise in potential. In this case, because of the CMOS structure, a thyristor structure of the PNPN formed between the drain (N-type) -P-type well ... N-type substrate ... P-type diffusion region of the P-channel is formed. As the rise of the well potential described above becomes a trigger and becomes conductive, a so-called latch up phenomenon may occur, resulting in destruction of the device.

As a countermeasure against this, the inventors of the present invention employ an offset gate in the above CMOS structure to provide a low concentration region (N-type or P-type) on each drain side to provide high breakdown voltage. I) Attempt to make it possible, but in this case, the low concentration area should be laid in each drain area, which makes the process complicated and not very desirable. Furthermore, in particular, 21V (in memory operation) and 5v (in call operation) are applied to the drain of the MISFET in the well, and accordingly the well potential varies between 21V and 5V. The operation becomes unstable. Moreover, in the above CMOS structure, the distance between each well and between the well-diffusion regions needs to be sufficiently held, which is very disadvantageous when it is required to reduce the size of the chip and to reduce the size of the chip.

The inventors of the present invention have completed the present invention based on the above knowledge.

It is a first object of the present invention to provide a semiconductor memory device capable of reducing current consumption without causing latch over. A second object of the present invention is to provide a semiconductor memory device capable of reducing current consumption and increasing the degree of integration while preventing latch-up from occurring, and a third object of the present invention is to prevent consumption by causing latch over. It is possible to provide a semiconductor memory device capable of reducing current and stably performing memory and recall switching operations. It is a fourth object of the present invention to provide a manufacturing method which can easily make the above-described semiconductor memory device.

Next, an embodiment in which the present invention is applied to an EPROM will be described in detail with reference to the drawings.

FIG. 1 shows a block diagram of the main circuit disposed on the EPROM. The selection signal from the address buffer AB is supplied to the memory cell M-CEL through the X decoder X-DEC and the Y decoder Y-DEC, respectively. Input and output signals from the buffer IOB are supplied through the sense amplifier SA and the memory operation circuit WC. It should be noted that each decoder X-DEC, Y-DEC, sense amplifier (SA), and input / output buffer IOBemd to which the low voltage (5V) is applied at the same level as the call operation voltage are composed of the above-described CMOS. The memory operation circuits to which high voltage (21V or 25V) is applied are all composed of N-channel MISFTFs attached to the P-type substrate itself.

In FIG. 2, the decoder, the memory cell portion, the memory operation circuit, and the equivalent circuit of the input / output buffer are shown partially in FIG. The memory operation circuit here is equivalent to the high voltage application circuit to which the memory operation voltage Vpp is applied. And calling the voltage V _cc is applied to part are distinct from the stored operating the voltmeter (電壓系) of the call as applied voltage.

In FIG. 2, the N-channel MIS FET (Q _M1-1 ..... Q _M1-n ) to (Q5 ⁵ ... Q of the double gate structure of the floating gate and the control gate is ^shown . Each memory cell is formed vertically and horizontally by _Mm-n ).

The excellent word lines W ₁ , .... W _m connecting each control gate and the common bit lines D ₁ .... D _n connecting each drain are matrix They are arranged crosswise in shape. Each word line is connected to the X decoder X-DEC, respectively, via a transfer gate Q _T1 ..... Q _T1 of a depletion mode on one side thereof. The other end of each word line is connected to the power supply terminal V _pp through a high resistance small R ₁ ..... R _m constituting a pull up circuit for word line charging. Each is connected. Each bit line is connected to the memory circuit WC and the input / output buffer IOB by a common bit line through a MISFET Q _s1 ..... Q _sm for switching. . The gates of FET Q _s1 ..... Q _sm are connected to Y-DEC through deflation mode transition gates Q ' _T1 ..... Q _Tm ', respectively, and the FET Q _s1 .... The high-resistance elements R ' ₁ ..... R _m ' of the fly-up circuit are connected between the power supply terminal V _pp between .Q _sm and MISFET Q ' _T1 ..... Q _Tm ' of the transition gate. have.

In the X decoder X-DEC, a pair of P-channel MISFET Q ₆ and an N-channel MISFET Q ₇ are paired with each other. The Y decoder Y-DEC consists of a pair of P-channel MISFET Q ₈ and N-channel MISFET Q ₉ pairs. Also input and output bapeo IOB also is composed of those that form the pair of the MISFET Q _5, like the P-channel MISFET and an N-channel Q ₄ of that described above. A low voltage is applied to the above-described X decoder X-DEC, Y decoder Y-DEC and the input / output buffer. The above-described memory operation circuit WC is constituted by the N-channel MISFETs Q ₁ , Q ₂ , and Q ₃ . Among these MISFETs are Q ₂ , deflation mode. A high voltage is applied to a circuit composed of such a single channel MISFET. Next, with reference to FIG. 3, the structure of the main part which concerns on a present Example is demonstrated.

FIG. ₃ is a cross-sectional view of a part of the memory cell M-CEL together with the cross-sectional views of the memory operation circuit WC and the MISFETs Q ₁ , Q ₂ , Q ₃ and Q5 in the input / output buffer IOB shown in FIG. 2. That is, each device region is separated by a field SiO ₂ a film 2 formed on one main surface of a common P-type silicon substrate 1, and respective MISFETs are formed in the device region. The high voltmeter to be applied is composed of all N-channel MIFETs, and the low voltmeter to which the call operation voltage is applied is characterized by a CMOS including an N type well 3. The high-voltage of the MISFET Q ₁ the source region 4 of N ₊ type in ~Q ₃ eda sense amplifier SA is connected to the drain of Q ₁ and Q ₂ are common N ⁺ type region 5, the high voltage V _pp is applied again Q ₂ is The impurity doping layer 6 of the channel portion is a deflation mode. N and the other of Q ₂ ^- Q ₃ type diffusion region 7 and the common and the N ⁺ type source region 8 of the Q ₃ is grounded. The gate electrodes 9, 10 and ₁₁ of each of the FETs Q _{1 to} Q ₃ are all formed of polysilicon of the first layer.

12, 13, 14, and 15 are aluminum electrodes or wirings. The same applies to the following, but 16 is a gate oxide film, 17 is a surface oxide film of a polysilicon film, and 18 is a phophosilicate glass film.

On the other hand, the low-voltage input buffer is composed of CMOS by N-channel MISFET Q ₃ and P-channel MISFET Q ₄ . The N ⁺ type source region 19 of Q ₅ is grounded, and in the N ⁺ type drain region 20 thereof, Q ₄ is connected to the P ⁺ type diffusion region 21 and the aluminum wiring 22. The other P ⁺ type region 23 of Q ₄ is connected to the low voltage power supply together with the N ⁺ type power feeding region 24 of the well 3. Each of the gate electrodes 25 and 26 of the two FETs Q ₄ and Q ₅ is formed of the polysilicon film of the second layer and is also connected to each other. Like 22, 27, 28, and 29 are aluminum electrodes or wirings, and 30 is a surface oxide film of a polysilon film.

The memory cell M-CEL has a two-layer polysilicon gate, and has a gate structure in which the control gate 32 is stacked on the floating gate 31. N ⁺ type diffusion regions 33, 34, 35 are formed between the gates, and among them, the region 33 is connected to a data line 36 made of aluminum.

As described above, since the high voltage meters of the peripheral circuits are all made of N-channel MISFETs made on the semiconductor substrate itself, and no device is placed in the well as in the CMOS, as described above, even if a high voltage V _pp is applied to the diffusion region, the well potential remains high. What happens is that nothing happens. Therefore, the latch potential due to the variation of the well potential causes the P ⁺ type region to exist. As described above, the well potential changes when a high voltage is applied, and this causes a trigger action. The PNP thyristors appearing between the N ⁺ type diffusion regions of the metals become conductive, but the thyristors themselves do not exist in the structure of this embodiment. Moreover, in the present embodiment, the carrier generated at the time of applying the high voltage in the high voltmeter is emitted through the substrate 1 itself, and its moving distance is only about the thickness of the substrate 1. Therefore, since the potential variation of the substrate 1 is small, the latching phenomenon is unlikely to occur even with the FET Q ₄ side of the low voltage meter.

In this connection, since the N-type well 3 is fixed to the low voltage (5V) in the CMOS of the low voltage meter, a potential change does not occur, and thus there is no source of the trigger on the well side, so that the latch-up phenomenon can be sufficiently prevented. It is. Therefore, the peripheral circuit portion of the present embodiment becomes stable even in the switching operation of the memory operation and the recall operation as a whole. In addition, since the high-voltage system has a structure in which the leading edge well is not formed as described above, the size of the device region can be reduced by that amount, and thus the integration density can be increased.

The flip-up resistor R shown in FIG. 2 may be formed of, for example, a high-resistance polysilicon film formed over the substrate 1 with an insulating film interposed therebetween. Alternatively, the polysilicon film may be selectively doped with an impurity to form a P ⁺ type source and drain region, and a P channel MISFET structure may be formed on the substrate 1 as a channel using polysilicon between these two regions. With the structure of the MISFET as described above, it may be brought into a conductive state during the memory operation and may be fixed, but the impurities may be doped into the channel to become the load resistance of the deflation mode. In any case, since the P-channel MISFET is insulated from the substrate 1, there is no fear of latching as described above through the substrate 1 when the high voltage V _pp is applied.

In this embodiment, since all the memory cells are formed of N channels, the switch FET which is necessary when the memory cells are formed of P-channel MISFETs is not necessary at all, thereby increasing the degree of integration.

Although the peripheral circuit according to the present embodiment has a sufficient breakdown voltage characteristic especially during the memory operation, it is preferable to have an offset gate structure as shown in FIG. That is, for example, in the MISFET Q ₁ , its gate is composed of the polysilicon film 9 of the first layer and the polysilicon film 37 of the second layer partially overlapped thereon, and a low concentration of N ^{− is applied} to the drain side of the polysilicon film 9. The mold region 38 is formed adjacent to each other with a high concentration of N ⁺ -type region 5. The high voltage V _pp is applied to both the polysilicon film 37 and the drain region 56 of the second layer, or a separate voltage is applied to the polysilicon film 37. In this way, the drain high electric field is relaxed by the depletion layer extending between the low concentration region 38 and the substrate 1, so that the amount of carrier from the 4-axis region of the source region or the substrate from the DN junction portion is reduced. The amount of holes emitted into the interior of 1 is reduced. As a result, the negative resistance caused by the concentration of carriers on the drain side is reduced, thereby improving the breakdown voltage BV _DS between the source and the drain.

Next, a method of manufacturing the EPROM shown in FIG. 3 will be described with reference to FIGS. 5A to 5I.

First, as shown in FIG. 5A, ion-implantion and drive diffusion are performed on one main surface of the substrate 1, and an N-type well 3 and a field are selected by a selective oxidation technique using a Si ₃ N ₄ film 39 as a mask. SiO ₂ film 2 is formed.

In the figure, the P ⁺ channel stopper is omitted for simplicity. (The same is true in Figure 3.)

Subsequently, as shown in FIG. 5B, the Si ₃ N ₄ film 39 and the underlying SiO ₂ film 40 are sequentially removed by etching, and then a gate oxide film 16 is formed in each device region by a gate oxidation technique such as thermal oxidation. . Then, a mask 41 such as a photoresist is made into a predetermined shape, and the arsenic (AS-AS) ion beam 42 is injected at a low dose to form a shallow ion implantation region 6 for the MISFET of the deflation mode. The mask 41 may have a thickness difference in the SiO ₂ film on the surface of the substrate 1, but the ion implantation may be performed only through the SiO ₂ portion where the film thickness is thin.

Next, as shown in FIG. 5C, the polysilicon film formed on the entire surface by chemical vapor deposition (hereinafter referred to as CVD method) is treated with phosphorus (phosphorus (P) as impurity). Only the gate electrodes, 9, 10, and 11 of the polysilicon film 43 covering the entire upper surface of the mem-cell part and patterning by photo-etching technique and the MISFETs of the high voltage application circuits in the peripheral circuit. Leave each one.

Then, as shown in FIG. 5D, a wet SiO ₂ film 17 is formed on the surfaces of each of the polysilicon films 9 to 11 and 43 by thermal oxidation, and then a second layer of polysilicon film 44 is formed on the entire surface by CVD. . Thereafter, phosphorus is doped (phosphorized) on the polysilicon film 44.

Next, as shown in FIG. 5E, the photoresist 45 is exposed to light and developed to form a mask of a predetermined pattern to cover the circuit portion of the high voltage meter of the peripheral circuit portion, and to cover both polysilicon films 44 and 43 of the memory cell portion. The polysilicon film 44 and the SiO ₂ films 17 and 16 of the low voltage meter of the peripheral circuit part are etched. This leaves the polysilicon films 32 and 31 of the double gate structure in the memory cell portion, and leaves the polysilicon films 25 and 26 in the form of gate electrodes in the low voltage circuit portion of the peripheral circuit.

Subsequently, as shown in FIG. 5f, this time, the polysilicon film 44 and the SiO ₂ film 17 and 16 of the high voltage circuit circuit part are sequentially covered by covering the memory cell part and the surrounding low voltage circuit part with a separate photoresist 46 as a mask. Etching is performed.

Subsequently, a thin SiO ₂ film is grown from the surface of each polysilicon film from the surface of each polysilicon film to the exposed surface of the substrate 1 by thermal oxidation, as shown in FIG. 5g. Remove some and leave.

In this state, arsenic ion beams are implanted at a high dose, and ions are applied to predetermined areas using the polysilicon films 9-11, 25, 26, 31, 32, the field SiO ₂ film 2 and the photoresist film 47 as masks. Optional injection. In this way, N ⁺ type source or drain regions 4,5,7,8,19,20,33,34,35 of each FET are formed on both sides of each gate electrode in a self-aligned manner, and well 3 Form an N ⁺ -type contact region 24. As the mask for injecting the arsenic ion beam, a SiO ₂ film formed by the CVD method may be used.

Next, as shown in FIG. 5h, another photoresist film 49 is covered, and the ion beam 50 of boron (B) is implanted using the mask, so that the P ⁺ type source region 21 and the drain region 23 are formed on both sides of the polysilicon film 25 (in the well). Form each. The mask used for implanting the ion beam 50 may also be a SiO ₂ film formed by the CVD method.

Then, as shown in FIG. 5I, each contact hole is formed by sequentially etching the insilicate glass film 18 deposited on the entire surface by the CVD method and the SiO ₂ film thereunder. Subsequently, aluminum is attached to the entire surface by a vacuum deposition technique and patterned by photoetching techniques to form each aluminum electrode and wiring shown in FIG.

6A to 6C show a method of forming the offset gate structure shown in FIG. In this form the same structure if you would like to claim 5b separate step ion implantation area replicon Orientation Modal formed wider bit 6 and to the FET Q ₂ and a low concentration of N over the FET Q ₁ branches ^at-the implantation region 6 of the type ion as the 6a help Form. Then, as shown in FIGS. 5C to 5D, as shown in FIG. 6A, the polysilicon film 44 of each of the gate electrodes 9, 10 and the second layer is formed.

Next, as shown in FIG. 6B, the polysilicon film 37 of the second layer is etched by using the photoresist 46 as a mask so that the polysilicon film of the second layer remains so as to partially overlap the polysilicon film 9 by the process of FIG. 5F. Form.

Subsequently, as in FIG. 6C, as in FIG. 5G, SiO ₂ films 17 and 30 are grown by thermal oxidation, and an ion beam 48 of arsenic is irradiated on the entire surface. In this way, arsenic ions are selectively implanted into regions where the polysilicon films 9, 10 and 37 do not exist, thereby forming a high concentration of N ⁺ type regions 4, 5 and 7 by self-aligning.

Subsequent steps are the same as those in Figs. 5h to 5i, and the detailed description thereof will be omitted. It is important, however, that the ion implantation region 6 is divided by the N ⁺ type region 5 by the above ion implantation, so that one side of the deflection mode FET Q ₂ becomes the channel portion and the other portion of the offset gate FET Q ₁ . It will remain in the low concentration area 38. Therefore, the structure of FIG. 4 is that the low concentration region 38 is formed in the same ion implantation process as the ion implantation region 6 of FET Q _{2 in} the same ion implantation process, and as shown in FIGS. It will be made up to. The manufacturing process is simplified with pictures, which improves workability.

In case that hayeoteul CMOS screen as previously described the peripheral circuit of the voltmeter for the fourth diagram in chamber pressed flower, and N-channel cheukhwa along the P-channel side as well a low concentration at the time that can, as shown in ^- the gate (i.e. P-type) region It is necessary to form the electrode in Han Chinese. In this case, the N-channel side can be made by the method as described in FIG. 6c, but the P ^- type region on the P ^- channel side requires an implantation process of separate ions (eg boron ions), so that the number of maneuvers increases. The castle will be lowered. Although the embodiments of the present invention have been described above, the above-described embodiments may be further modified based on the cardinality of the present invention. For example, each of the semiconductor regions described above may convert the conductivity type into a reverse conductivity type. The gate electrodes of the low voltage application circuit may be formed of the polysilicon film of the first layer with respect to each gate electrode of the peripheral circuit portion, and each gate electrode may be formed of a different material. In addition, if the ratio between the channel width and the channel length of the deflation mode FET Q ₂ of the memory operation circuit is reduced, the current during the call operation can be reduced. In addition, a high resistance element may be used instead of the FET Q ₂ of the implementation mode. In this case, the current during the call operation decreases. In addition, the present invention can be applied to other ROMs, such as EEPROM (electrically erasable and programmable ROM), in which the memory operation is performed in addition to the EPROM.

Claims (14)

A semiconductor body having a P-conducting semiconductor region, a memory cell portion having a plurality of memory cells formed in a portion of the semiconductor body, and another portion of the semiconductor region where the memory cell is not formed, the memory cell portion A first circuit portion composed of circuit elements capable of applying a voltage by a first voltage equal to the supplied memory operation voltage and a first voltage equal to the call operation voltage supplied to the memory cell portion A first circuit portion composed of circuit elements capable of applying a voltage, and a second circuit composed of circuit elements capable of applying voltage by a second voltage which is the same voltage as the call operation voltage supplied to the memory cell portion In the peripheral circuit portion of the negative portion, the second voltage is lower than the first voltage, and the circuit elements of the first circuit portion are N-type source and drain. First insulated gate type FETs having an inverse, and the circuit elements of the second circuit portion include a second FET having an N-type source and drain region and a Hanan FET having a P-type source and drain region. Wherein the second insulated gate string FETs having a P-type source and drain region are formed in an N-type well region in the semiconductor region and have a N-type source and drain region. 1. The erasable programmable semiconductor memory device of claim 1, wherein the insulated gate type FETs are formed in the semiconductor region. The semiconductor memory device according to claim 1, wherein the first voltage is a high power supply voltage Vpp, and the second voltage is a low power supply voltage Vcc. The semiconductor memory device according to claim 1, wherein the first circuit portion is a memory operation circuit portion for the memory cell portion. The semiconductor memory device according to claim 1, wherein the second circuit portion is an input / output buffer. The semiconductor memory device according to claim 1, wherein said second circuit portion is a decoder. A semiconductor body having a P-conducting semiconductor region, separated by a field insulating film formed on one main surface of the semiconductor region and separating the one main surface of the semiconductor region into multiple regions, and a floating gate and a control gate Each of the memory cells having a gate having a stacked structure of a plurality of first insulating gate FETs formed at different portions of the one main surface of the semiconductor region is separated by the field insulating film, and a single gate and an N-type source And each of the first insulated gate FETs having a drain region and a plurality of second insulated gate type FETs formed up to another part of the one main surface of the semiconductor region by the field insulating film, N-type source and drain regions formed in the semiconductor region and one insulated gate type FET each having a single gate And the first insulated gate type FETs are supplied with a first voltage equal to a storage operation voltage, and the second insulated gate type FETs have a second voltage equal to a call operation voltage. And wherein said second voltage is lower than said first voltage. 8. The semiconductor memory device according to claim 7, wherein the field insulating film is a SiO ₂ film. 8. The semiconductor memory device according to claim 7, wherein the gate of the stacked structure of each memory cell is composed of two layers of polycrystalline silicon gates. The method according to claim 7, wherein the first insulated gate type FET has a gate electrode that is a first polycrystalline silicon film and a second polycrystalline silicon film partially overlapped on the first polycrystalline silicon film. A semiconductor memory device, characterized in that. 12. The semiconductor device according to claim 11, wherein the first insulated gate type FET includes a semiconductor region having an N conductivity type low impurity concentration formed under the second polycrystalline silicon film and a semiconductor region having a low impurity concentration. And a drain region adjacent to each other and having a higher impurity concentration than that of the low impurity concentration semiconductor region. The field insulating film selectively separating the area of one main surface of the first conductive semiconductor body into the one main surface of the semiconductor body in at least several areas of the first, second, and third regions. Forming an insulating film; forming a well region of the conductivity type in FIG. 2 in the first region; forming a first polycrystalline silicon layer on the first, second, and third regions; Selectively removing the first polycrystalline silicon film to form a plurality of gate electrodes on the second region and forming a first polycrystalline silicon film on the third region, each of the second region and the third Forming an insulating film on the surfaces of the plurality of gate electrodes and the first polycrystalline silicon film formed on the region of the second electrode; forming a second polycrystalline silicon film on the first, second, and third regions; 2, polycrystalline Selectively removing the licon film to form a gate electrode of a memory cell comprising the polycrystalline silicon film of the well region of the first region and the second polycrystalline silicon film, wherein the first, second, and third Forming a plurality of semiconductor regions of the second conductivity type by introducing the second impurities into the first, second, and third regions by using the plurality of gate electrodes formed on the regions as masks; Forming an insulating film in the first, second, and third region yarns and selectively removing the insulating film to form contact holes; and forming a metal wiring layer connecting the plurality of semiconductor regions through the contact holes. A method of manufacturing a semiconductor memory device comprising the step. The method of manufacturing a semiconductor memory device according to claim 13, wherein said first conductivity type is P type and said second conductivity type is N type. The method of manufacturing a semiconductor memory device according to claim 13, wherein said first and second polycrystalline silicon films are formed by a chemical vapor deposition method. The process of claim 13, wherein a step of introducing a second conductivity type impurity into the first, second, and third regions by using the plurality of gate electrodes as a mask is performed by ion implantation. A method of manufacturing a semiconductor memory device.

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