JPH0793380B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A mask ROM provided with a redundant memory cell is provided with a floating gate for the redundant memory cell in the same step as the word line of the mask ROM without increasing a signal delay in the word line. A semiconductor substrate, a word line formed by patterning a polycide layer formed on the semiconductor substrate via a gate insulating film, and a part of the word line serving as a gate electrode. A mask ROM having as memory cells MOS transistors formed as sources and drains by selectively introducing impurities into the semiconductor substrate, a floating gate formed by patterning the polycide layer, and impurities in the semiconductor substrate Memory cell consisting of single-layer gate type EPROM composed of source and drain formed by selectively introducing And is provided.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a mask ROM (Read only Memory) having redundant memory cells.

[Conventional technology]

With the recent increase in capacity, mask ROM chip yields have declined. The main reason for this is the dust attached with a certain probability per unit area on the surface of the semiconductor substrate in the manufacturing process.
This is because defective transistors are more likely to occur as the area of each MOS transistor forming the memory cell decreases or the chip size increases.

Conventionally, a method has been adopted in which a spare memory cell, that is, a redundant memory cell is provided on a semiconductor substrate and a defective memory cell is functionally replaced by this redundant memory cell. In the case of a mask ROM, since data is already fixed in the memory cell in which a defect is found after manufacturing, the redundant memory cell replaced with the defective memory cell should be fixed in the defective memory cell. Data must be writable and non-volatile so that this data can be fixed. That is, a writable ROM is required as the redundant memory cell. As such a redundant memory cell, an electrically writable ROM, that is, an EPROM (Electr
romically Programmable ROM) is appropriate.

[Problems to be Solved by the Invention]

By the way, in the mask ROM, M for fixed data storage
The gate of the OS transistor doubles as the word line. Therefore, in order to reduce the signal delay, the gate and the word line are configured by using a silicide that has a lower resistance than polysilicon.

On the other hand, in a normal EPROM, as shown in FIG. 3, a floating gate 20 and a control gate 21 have a two-layer structure, and a polysilicon layer is used as the floating gate 20. This is a floating gate
This is to avoid deterioration of the insulation characteristics of the insulation layer between the control gate 21 and the control gate 21.

That is, generally, the oxide film formed on the silicide has a low withstand voltage and a large leak current. Therefore, when polycide is used for the floating gate 20, the insulating layer between the floating gate 20 and the control gate 21 has a structure in contact with the silicide forming the upper layer of the polycide, which easily causes dielectric breakdown at the time of writing, and control The charge accumulated in the gate 21 leaks, which makes it difficult to hold write data. On the other hand, since the oxide film formed on the polysilicon has good insulation characteristics, polysilicon is used for the floating gate 20.

When a redundant memory cell composed of an EPROM having the above-mentioned two-layer floating gate 20 and control gate 21 is formed on the mask ROM substrate, the word line of the mask ROM, that is, the gate of the fixed data memory MOS transistor It is desirable to form the floating gate 20 and the floating gate 20 from the same conductive layer from the viewpoint of the process. However, for the above reason, the word line must be formed of a polysilicon layer having a relatively high resistance. As the word line width becomes finer with the increase in the capacity of the mask ROM, the resistance value increases more and more, and as a result, the read speed of the mask ROM decreases significantly.

It is an object of the present invention to enable redundant memory cells to be provided side by side without increasing the signal delay in the word line of the mask ROM.

[Means for Solving the Problems]

The above object is to provide a semiconductor substrate, a word line formed by patterning a polycide layer formed on the semiconductor substrate via a gate insulating film, a part of the word line as a gate electrode, and an impurity in the semiconductor substrate. A mask ROM having, as a memory cell, a MOS transistor serving as a source and a drain formed by selectively introducing the impurity, a floating gate formed by patterning the polycide layer, and an impurity selectively introduced into the semiconductor substrate. Single-layer gate type EP composed of source and drain formed by
The present invention is achieved by a semiconductor device of the present invention, which is provided with a redundant memory cell composed of a ROM.

[Work]

An EPROM having a single layer structure as shown in FIG. 4 has been proposed in contrast to an EPROM having a two-layer structure of floating gate and control gate shown in FIG. 3 (Japanese Patent Laid-Open No. 62-07667).
9).

In this structure, the impurity region 3 formed by diffusing impurities in the silicon substrate 1 constitutes a control gate. The write voltage applied to the electrode 6 is divided by the gate oxide film 4 into the floating gate 5. As a result, carriers flowing between the source / drain (not shown) are injected / stored in the floating gate, and writing is performed.

According to the structure of FIG. 4, polycide can be used for the floating gate 5. That is, since the lower layer forming the polycide is polysilicon, the insulating layer between the control gate 3 and the floating gate 5 does not come into silicide contact, and as a result, the dielectric breakdown voltage and the accumulated charge retention characteristic deteriorate as described above. There is no fear.

Therefore, if the EPROM having a single-layer gate structure as shown in FIG. 4 is used as the redundant memory cell of the mask ROM, both the gate of the fixed data memory MOS transistor, that is, the word line and the floating gate of the redundant memory cell EPROM are used. Can be made of polycide. As a result, redundant memory cells can be provided without sacrificing the operating speed of the mask ROM, and there is no need to increase the number of steps.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

1 and 2 are respectively the mask ROM of the present invention.
FIG. 3 is a schematic configuration diagram of a single-layer gate type EPROM for a redundant memory cell and a fixed data memory cell unit that configures the above.

In FIG. 1, (a) and (b) are a cross-sectional view and a plan view, respectively, of a main part, showing, for example, an n-type in a predetermined region A of a p-type silicon substrate 1 separated by an isolation insulating layer 2. Impurity region 3 is formed. Silicon substrate 1
On the surface, a gate oxide film made of SiO ₂ and having a thickness of 200 to 300 Å
4, and a floating gate 5 which is in contact with the gate oxide film 4 is formed.

Impurity region 3 functions as a control gate, and when a write voltage is applied through electrode 6, this write voltage is divided into floating gate 5. as a result,
N-type source and drain 10 formed in the region B
The electrons flowing in the intervening channel region 11 are accelerated and injected into the floating gate 5. Writing is performed in this manner. In the figure, reference numeral 7 indicates, for example, PSG.
Interlayer insulating layer 7 made of (phosphosilicate glass), reference numerals 12 and 13
Are a source / drain contact and a control gate contact, respectively.

The floating gate 5 is conventionally composed of a single polysilicon layer, but in the present invention, the lower layer 5A of polysilicon having a thickness of about 2000Å and a thickness of, for example, tungsten silicide (WSi ₂ ) are composed. 2000Å Upper layer 5B
It is composed of a so-called polycide layer having a two-layer structure.

On the other hand, in FIG. 2 (a), the same silicon substrate 1 as described above is provided with source and drain regions 8 formed by implanting n-type impurities, for example, and the silicon substrate between each source and drain region 8 is formed. A word line 9 which is in contact with the silicon substrate 1 is formed on one surface through the same gate oxide film 4 as described above. The word line 9 extends in the direction perpendicular to the paper surface and runs between another source and drain region (not shown) equivalent to the source and drain region 8.

One MOS transistor is composed of the pair of source and drain regions 8 and the word line 9. Therefore, the source and drain regions 8 and the word lines 9 as shown
From the group, a MOS transistor Tr column in which the source and the drain are connected in series as shown in FIG. 2B is constructed. Both ends of the MOS transistor array are connected to a bit line BL and a power supply line (not shown), for example, Vss. MOS like this
A plurality of rows of transistor Trs are arranged in parallel to form a mask ROM.

In the mask ROM, the word line 9 is also a polycide layer,
That is, the lower layer 9A made of polysilicon and, for example, WSi ₂
And an upper layer 9B consisting of. Lower layer 9A and upper layer 9B
Are the lower layer 5A and the upper layer in FIG. 1 (a), respectively.
It is formed by patterning the same polysilicon layer and WSi ₂ layer as 5B.

Both the polysilicon layer forming the lower layers 5A and 9A and the WSi ₂ layer forming the upper layers 5B and 9B are well known in the above.
It is deposited on the silicon substrate 1 using the CVD method. In addition,
Like the ordinary mask ROM, in the mask ROM shown in FIG. 2 as well, all of the fixed data storage MOS transistors Tr are made to be enhancement type, and only the MOS transistors Tr to which fixed data is not written are converted to depletion type. To be done. After that, a polycide layer forming the floating gate 5 and the word line 9 is formed.

The polycide layer is patterned into floating gates 5 and word lines 9. This patterning can be performed by the well-known RIE (Reactive Ion Etching). For example, using a resist mask, the upper layers 5B and 9B and the lower layers 5A and 9A are continuously etched using a fluorine-based gas or a chlorine-based gas as an etching agent.

After that, an interlayer insulating layer 7 made of PSG, for example, is formed on the silicon substrate 1, and a contact hole is formed in a predetermined region of the interlayer insulating layer 7. Then, for example, an aluminum thin film is deposited on the interlayer insulating layer 7, and this is patterned to form the electrode 6 connected to the impurity region 3 to complete the mask ROM of the present invention.

〔The invention's effect〕

According to the present invention, it is possible to avoid the signal delay in the word line of the mask ROM due to the provision of the redundant memory cell, and it is possible to improve the chip yield in the manufacturing of the mask ROM of large capacity and high speed. is there.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a redundant memory cell according to the present invention, FIG. 2 is a schematic configuration diagram of a fixed data memory cell portion according to the present invention, and FIGS. 3 and 4 are cross-sectional views of essential parts of a conventional EPROM. Is. In the figure, 1 is a silicon substrate, 2 is an isolation insulating layer, 3 is an impurity region, 4 is a gate oxide film, 5 and 20 are floating gates, 5A and 9A are lower layers, 5B and 9B are upper layers, 6 is an electrode, and 7 is An interlayer insulating layer, 8 is a source / drain region, 9 is a word line, 10 is a source / drain, 11 is a channel region, 12 is a source / drain contact, 13 is a control gate contact, and 21 is a control gate.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 27/105 27/112 29/788 29/792 H01L 29/78 371 8832-4M 21/82 R

Claims (1)

[Claims] 1. A semiconductor substrate, a word line formed by patterning a polycide layer formed on the semiconductor substrate via a gate insulating film, a part of the word line serving as a gate electrode, and the semiconductor substrate being formed on the semiconductor substrate. A mask ROM having as memory cells MOS transistors formed as sources and drains by selectively introducing impurities, a floating gate formed by patterning the polycide layer, and impurities selectively in the semiconductor substrate A redundant memory cell comprising a single-layer gate type EPROM composed of a source and a drain formed by introduction, and a semiconductor device.