KR100204541B1 - Semiconductor device and its making method - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, which improve the structure and programming method of a read-only semiconductor device and reduce the manufacturing cost and time of the semiconductor device. Forming a plurality of device isolation regions and a plurality of device active regions having a predetermined interval; Sequentially forming a gate dielectric film, a gate conductive film, and a silicon dioxide film pattern on the semiconductor substrate; Etching the gate conductive layer using the silicon dioxide layer pattern as a mask; Implanting primary impurity ions using the gate conductive layer and the silicon dioxide layer pattern as a mask; Forming spacers on both sides of the gate conductive layer and the silicon dioxide layer pattern; Implanting secondary impurity ions into the source-drain region using the silicon dioxide layer pattern and the spacer as a mask; Forming a first conductive layer pattern on the semiconductor substrate such that the source-drain regions are electrically connected to each other; Forming a planarized oxide film on the semiconductor substrate including the first conductive layer pattern; A contact forming process for electrical connection to the oxide film; Forming a second conductive layer on the high temperature oxide film; Patterning the second conductive layer to form a second conductive layer pattern, wherein the planarized oxide film under the second conductive layer pattern is etched to overetch within a predetermined range; Forming a photoresist pattern on the planarized oxide film including the second conductive layer pattern with a protective film therebetween; And selectively etching the passivation layer, the planarized oxide layer, and the first conductive layer using the photoresist pattern and the second conductive layer as a mask. By such an apparatus and method, not only can the misalignment margin be secured during impurity ion implantation, but also the degradation of the activity ratio of the ion implantation impurity and the deterioration of the yield and characteristics of the semiconductor device can be prevented. It can solve the problem of wasting manufacturing cost and time.

Description

A semiconductor device and method of fabricating the same

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device and a method for manufacturing the same by improving the structure and programming method of the read-only semiconductor device to reduce the manufacturing cost and time of the semiconductor device. will be.

Among the semiconductor devices, there is a read-only semiconductor element called a ROM (read only memory) as a semiconductor device for storing fixed data.

The most distinguishing feature of this semiconductor device from other semiconductor devices is that the data desired by a particular user is ordered, written and stored in the semiconductor device during the manufacturing process, and supplied to the user.

Fig. 1 shows a schematic layout of a conventional read only semiconductor element as described above.

Referring to FIG. 1, a conventional read-only semiconductor device includes a device active region 16 that is repeatedly extended in parallel with the device isolation region 12 interposed therebetween, the device isolation region 12, and the device active region ( A word line 20, 22, 24, and 26 orthogonal to the two regions 12 and 16 on the 16 and having a predetermined interval therebetween, and the isolation region 12 and the word line Source-drain regions formed by ion implantation using 20, 22, 24, and 26 as masks, and at predetermined intervals on the word lines 20, 22, 24, and 26; Bit lines 32 and 34 overlapping portions of the isolation region 12 and formed to contact one side of the device active region 16 and the word lines 20, 22, and 24. Reduce the string select lines 28 and 30 formed below the bit lines 32 and 34 and bit line capacitance in parallel with Include; (18 bank select line) to the bank selection lines.

Here, a cell transistor implemented by the device isolation region 12 and the device active region 16 and the word lines 20, 22, 24, and 26 orthogonal to the device isolation region 12 are formed in a predetermined unit. The strings are connected in series to form a string, which is disposed between the bit lines 32 and 34 and the ground line 14. In addition, since the bit lines 32 and 34 cannot reduce a design rule like the device active region 16 of the cell transistor, two strings are connected to one bit line 32 and 34 together. Accordingly, two string selection lines 28 and 30 are provided in order to select each string as needed.

The operation of the conventional read-only semiconductor device having the configuration as described above will be briefly described as follows.

First, a voltage having a constant potential is applied to the selected bit line, the bank selection transistors of the selected block are turned on, and each one of the enhancement transistor and the depletion transistor is depletion. Of the two string selection transistors in which tr.) is alternately arranged, when the power supply voltage Vcc is applied to the incremental string selection transistor existing in the selected string, and the ground potential (0V) is applied to the depletion string selection transistor, A current path is formed between the bit line and the ground line. In this case, when the power supply voltage Vcc is applied to the unselected word line of the memory cell region and the ground potential (0V) is applied to the selected word line, the cell transistor is increased in the bit line depending on whether it is an increase type or a depletion type. Since the discharge current flowing to the ground line changes, the current change of the bit line is sensed so that the high level and the low level are read.

3 and 4 are cross-sectional views schematically illustrating a structure of a read-only semiconductor device having the configuration as shown in FIGS. 1 and 2.

3 and 4 show cross-sectional views of the semiconductor device of FIG. 1 in the direction of A-A 'and B-B', respectively, and FIG. 5 shows an equivalent circuit diagram of the semiconductor device of FIG.

3 and 4, in a conventional read-only semiconductor device having the above-described configuration and operation, the on / off of the cell transistor for programming data is mainly a threshold voltage due to ion implantation. It is determined by the control of 'Vth'). In general, the cell transistors of all n-type channels are initialized to depletion at the beginning of the process, and then high energy boron, which is a counter ion, is used in the second half of the process. The method of increasing the Vth by changing the channel concentration by selectively ionizing ()) on the gate is widely used. In this case, the former depletion cell transistors 22 and 26 become 'on' cell transistors, and the latter B + PGM (boron ProGraMmed) cells become 'off' cell transistors.

In the read-only semiconductor device, the programming time of data is ordered and delivered in view of the characteristics of the read-only semiconductor device which writes, stores and supplies data according to the user's order as mentioned above. The time to turn, ie turn around time, is a very important variable that determines the competitiveness of a product.

Therefore, in recent years, an after gate programming (AGP) process for programming after forming a gate electrode, an after contact programming (ACP) process for programming after forming an interlayer insulating film, an after metal programming (AMP) for programming after forming a bit line by metallization, Among the after passivation programming (APP) programming after the final protective film is formed, AMP and APP are the most popular in terms of shortening the TAT.

However, as shown in FIGS. 3 and 4, such a programming method is difficult to secure misaligned margins that are covered when the ion is implanted according to the pattern of the upper portion of the interlayer insulating layer, that is, the bit line. As a result, since the hot temperate anneal cannot be performed, a decrease in the activation rate of the ion implantation impurity is caused.

In addition, the lowering of the activation ratio affects the cell string current flowing from the bit line to the ground line, as shown in FIG. 5, resulting in deterioration of the yield and characteristics of the semiconductor device, and also the gate Many difficulties have been involved in injecting impurity ions through the film deposited on top of the electrode. Therefore, a problem arises in that the manufacturing cost and time of the semiconductor device are wasted.

Accordingly, the present invention proposed to solve the above problems, to provide a semiconductor device and a method for manufacturing the semiconductor device that can reduce the manufacturing cost and time of the semiconductor device by improving the structure and programming method of the read-only semiconductor device Its purpose is to.

1 is a layout schematically showing a configuration of a conventional semiconductor device;

2 is a layout showing a programming structure of the semiconductor device of FIG. 1;

3 and 4 are cross-sectional views illustrating a vertical structure of the semiconductor device of FIG. 1;

5 is an equivalent circuit diagram of the semiconductor device of FIG. 1;

6 is a layout schematically showing a configuration of a semiconductor device according to an embodiment of the present invention;

7 is a layout showing a programming structure of the semiconductor device of FIG. 6;

8 and 9 are cross-sectional views illustrating a vertical structure of the semiconductor device of FIG. 6;

10 is an equivalent circuit diagram of the semiconductor device of FIG. 6;

11 through 17 are process diagrams sequentially illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* Explanation of symbols on the main parts of the drawing

10: semiconductor substrate, 12: device isolation region, 14: ground line, 16: device active region, 20, 22, 24, 26: word line, 28, 30: string select line, 32, 34: bit line, 31: Interlayer insulation film

(Configuration)

According to one aspect of the present invention for achieving the above object, a plurality of gate electrode layers formed on a semiconductor substrate with a gate dielectric film interposed therebetween, and the plurality of gate electrode layers as masks, and impurity ions on the semiconductor substrate. A method of manufacturing a semiconductor device including a source-drain region formed by implanting a metal, the method comprising: forming a first conductive layer pattern on the semiconductor substrate including the plurality of gate electrode layers such that the source-drain regions are electrically connected to each other; Process; Forming a second insulating film on the first insulating film pattern including the first conductive layer pattern; Forming a second conductive layer on the second insulating film; Patterning the second conductive layer to form a second conductive layer pattern, wherein the second insulating layer under the second conductive layer pattern is etched to self-align etching to the second conductive layer within a predetermined range; Forming a third insulating film on the second insulating film including the second conductive layer pattern; Forming a photoresist pattern on the third insulating film; And selectively etching the third insulating film, the second insulating film, and the first conductive layer by using the photoresist pattern and the second conductive layer pattern as a mask.

In a preferred embodiment of this method, the first conductive layer uses polycrystal silicon doped with impurities.

In a preferred embodiment of this method, the second insulating film 31b uses any one of a high temperature oxide film, a BPSG film, and a double layer composed of a high temperature oxide film and a BPSG film.

In a preferred embodiment of this method, the third insulating film 43 uses any one of silicon dioxide, silicon nitride film, and a double layer made of silicon dioxide and silicon nitride film.

According to another aspect of the present invention for achieving the above object, a semiconductor device includes a plurality of device active regions repeatedly formed in parallel with each other with device isolation regions interposed therebetween, and a predetermined interval on the plurality of device active regions. 12. A semiconductor device comprising: a plurality of word lines spaced apart from each other and formed at right angles to the plurality of device active regions; and source-drain regions formed by implanting impurity ions into both sides of the plurality of word lines. A plurality of word lines are formed orthogonally to the plurality of word lines such that the source and drain regions are electrically connected to each other with a first insulating layer interposed therebetween, and at predetermined intervals so as to overlap the plurality of device active regions. A first conductive layer spaced apart and repeatedly parallel; A second conductive layer formed on the first conductive layer so as to be orthogonal to the plurality of word lines with a second insulating film interposed therebetween, the second conductive layer being formed to be aligned with the device isolation region at a predetermined interval in parallel with each other; Including a third insulating film formed on the second conductive layer has a structure in which the third insulating film, the second insulating film, and the first conductive layer on the cell transistor selectively removed according to the type of the cell transistor,

In a preferred embodiment of the device, the first conductive layer is polycrystallin silicon doped with impurities.

In a preferred embodiment of the device, the second insulating film is any one of a high temperature oxide film, a BPSG film, and a double layer composed of a high temperature oxide film and a BPSG film.

In a preferred embodiment of the device, the first insulating film is silicon dioxide.

In a preferred embodiment of the device, the third insulating film uses any one of silicon dioxide, silicon nitride film, and a double layer made of silicon dioxide and silicon nitride film.

Example

Best Mode for Carrying Out the Invention Embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

Referring to FIG. 17A, a method of fabricating a semiconductor device according to an exemplary embodiment of the present invention includes forming a plurality of field oxide films at predetermined intervals on a semiconductor substrate, thereby forming a plurality of device isolation regions having a predetermined interval and a plurality of device isolation regions. Defining a device active region, sequentially forming a gate dielectric film, a gate conductive film, and a silicon diocy film pattern on the semiconductor substrate, using the silicon dioxide film pattern as a mask, and using the gate conductive film Etching, implanting primary impurity ions using the silicon dioxide film and the gate conductive film pattern as a mask, forming a spacer on both sides of the gate conductive film pattern, the silicon dioxide film pattern, and Process of injecting secondary impurity ions for forming the source-drain by using a spacer as a mask Forming a polycrystalline silicon film pattern on the semiconductor substrate such that the source-drain regions are electrically connected to each other; and forming a planarized oxide film on the semiconductor substrate including the polycrystalline silicon film pattern. And forming a metal layer on the planarized oxide film, and patterning the metal layer to form a metal layer pattern, wherein the planarized oxide film under the metal layer pattern is formed on the metal layer pattern within a predetermined range. Etching to self-align and etch; forming a photoresist pattern on the planarized oxide film including the metal layer pattern; and using the photoresist pattern and the metal layer pattern as masks. Etching the passivation film, the high temperature oxide film, and the polycrystalline silicon film pattern And it includes a step. By such a device, the yield and characteristics of the semiconductor device can be prevented from being deteriorated, and the problem that the manufacturing cost and time of the semiconductor device are wasted can be solved.

In FIGS. 6 to 17, the same reference numerals are used for components that perform the same functions as those of the semiconductor device illustrated in FIGS. 1 to 5.

5 and 6 schematically show the configuration of a semiconductor device according to an embodiment of the present invention.

5 and 6, a read-only semiconductor device according to an exemplary embodiment of the present invention may include a plurality of device active regions 16 repeatedly formed in parallel with each other with device isolation regions 12 interposed therebetween. A plurality of word lines 20, 22, 24, and 26 formed on the plurality of device active regions 16 and spaced apart at predetermined intervals, and orthogonal to the plurality of device active regions 16; Source-drain regions formed by implanting impurity ions into both sides of the plurality of word lines 20, 22, 24, and 26, and a first insulating layer on the plurality of word lines 20, 22, 24, and 26. (Not shown) and a plurality of the source-drain regions are formed orthogonal to the plurality of word lines so as to be electrically connected to each other, and spaced apart at predetermined intervals so as to overlap the plurality of device active regions 16 repeatedly. First conductive layer 33a elongated in parallel And orthogonal to the plurality of word lines 20, 22, 24, and 26 with a second insulating film (not shown on the layout) interposed on the first conductive layer 33a. A plurality of second conductive layers 32 and 34 that are matched with the device isolation regions 12 at intervals of and a plurality of second conductive layers parallel to the word lines 20, 22, 24, and 26. The string selection lines 28 and 30 formed below the 32 and 34 and the bank selection lines 18 for reducing the capacitance of the second conductive layers 32 and 34 are included. Here, the first conductive layer 33a is polycrystalline silicon doped with impurities, and the second conductive layers 32 and 34 are metal.

8 and 9 show the structure of a semiconductor device having the above-described configuration, and FIG. 10 shows an equivalent circuit diagram of the semiconductor device.

8 and 9, unlike the bit lines 32a and 34a of the semiconductor device of FIG. 3 and FIG. 4, the semiconductor device according to the embodiment of the present invention, ie, the channel interval of the cell transistor, The bit lines 32a, 32b, and 34a are formed on each device isolation region 12a, 12b, and 12c. In addition, a programming layer of the first conductive layer 33 electrically connecting each source-drain region is formed on an upper portion of each cell transistor, and an unetched portion of the programming layer 33 ( 33a) acts as an 'on' cell and the etched portion 33b acts as an 'off' cell.

The operation of the semiconductor device having such a structure will be described with reference to FIG. 10 as follows.

First, referring to FIG. 10, there is a cell transistor connected in series between a bit line and a ground line, and an 'on' cell connects an initial incremental transistor to a source and a drain of the transistor. It consists of a resistor, and the 'off' cell consists only of the initial incremental transistor, with no resistor connecting the source and drain.

Thus, a predetermined voltage is applied to the bit line, Vcc is applied to the incremental string select line SSL of the selected cell string, 0 V is applied to the other string select line SSL, and the selected word line is applied. When 0 V and Vcc are applied to the WL and the unselected word line WL, and Vcc is applied to the ground select line GSL, the current flowing from the bit line to the ground line if the selected cell transistor is an incremental transistor. Is intercepted to become an 'off' cell. Likewise, a cell transistor electrically connected to a source-drain becomes an 'on' cell because current is always flowing regardless of whether the voltage is on the word line WL.

A method of manufacturing a semiconductor device having the above-described configuration will be described below with reference to FIGS. 11 to 17.

11A to 17A show cross-sectional views of the semiconductor device of FIG. 6 taken along the direction A-A ', and FIGS. 11B to 17B show the semiconductor device of FIG. 6 B-B. The cross section cut in the direction of 'is shown.

First, referring to FIG. 11A, a plurality of field oxide films 12 are formed on a semiconductor substrate 10 at predetermined intervals to form a plurality of device isolation regions 12 and a plurality of device active regions having a predetermined interval. Next, as shown in FIG. 11B, the gate dielectric film 11, the gate conductive film, and the first insulating film pattern 31a are sequentially formed on the semiconductor substrate 10 including the plurality of field oxide films 12. Form. The first insulating layer 31a is a silicon dioxide layer.

Next, in FIGS. 12A and 12B, the gate insulating film is etched using the first insulating film pattern 31 a as a mask, and the source conductive patterns of the gate conductive film patterns 22, 24, 26 and the semiconductor substrate 10 are removed. After defining the drain region, the first impurity ion 27 is implanted into the source-drain region using the first insulating layer pattern 31a as a mask.

Subsequently, as shown in FIGS. 13A and 13B, spacers are formed on both sides of the gate conductive layers 22, 24, and 26 and the first insulating layer pattern 31 a, and the first insulating layer pattern 31 a and the spacer are formed. The second impurity ion 29 is implanted into the source-drain region using a as a mask.

14, a first conductive layer pattern 33 is formed on the front surface of the semiconductor substrate 10 so that the source-drain regions into which the impurity ions 27 and 29 are injected are electrically connected to each other. The first conductive layer pattern 33 is formed of a polycrystalline silicon film doped with impurities.

Next, in FIG. 15, after the second insulating layer 31b is formed on the first insulating layer pattern 31a including the first conductive layer pattern 33, the second insulating layer 31b is formed on the second insulating layer 31b. A second conductive layer and then patterning the second conductive layer to form second conductive layer patterns 32 and 34, wherein the second insulating layer 31b under the second conductive layer patterns 32 and 34 is formed. 16) is etched to self-align etching to the second conductive layer within a predetermined range as shown in FIG.

The second insulating layer 31b may be any one selected from a high temperature oxide film (HTO), a boron phosphorus silicate glass, and a double layer including a high temperature oxide film and a BPSG film. Conductive layers 32 and 34 are bit lines using metal.

Finally, referring to FIG. 17, a photoresist pattern 43 is formed on the second insulating layer 31b including the second conductive layer patterns 32 and 34 with the third insulating layer 42 interposed therebetween. After the lower limit, the third insulating film 42, the second insulating film 31b, and the first conductive layer 33 are formed by using the photoresist pattern 43 and the second conductive layer patterns 32 and 34 as masks. Etch selectively. In this case, the third insulating layer 42 may be any one of a silicon dioxide, a silicon nitride film, and a double layer made of silicon dioxide and a silicon nitride film as a passivation film.

According to the conventional semiconductor device, when the cell transistor of the semiconductor device is initialized to the depletion type and the counter ion is implanted in the subsequent process to program the incremental cell transistor, it is difficult to secure a misalignment margin. Since it could not be carried out, the activity ratio of the ion implantation impurity was reduced.

In addition, the lowering of the activation ratio affects the cell string current flowing from the bit line to the ground line, resulting in deterioration of the yield and characteristics of the semiconductor device and injecting impurity ions through the film deposited on the gate electrode. Many difficulties were followed. Therefore, a problem arises in that the manufacturing cost and time of the semiconductor device are wasted.

In order to solve this problem, the present invention is to initialize the cell transistor of the semiconductor device to an incremental type, and then selectively etch the programming layer connecting the source-drain to 'on' and 'off' in a subsequent process. Perform cell programming.

Therefore, misalignment margin in the cell transistor programming process can be ensured, and the activity ratio of the ion implantation impurities can be prevented from being lowered. Therefore, deterioration in yield and characteristics of the cell transistor can be prevented, and the manufacturing cost and time TAT of the semiconductor element can be reduced.

Claims (9)

A plurality of gate electrode layers (22, 31a, (24, 31a), (26, 31a) formed on the semiconductor substrate 10 with the gate dielectric film 11 interposed therebetween, and the plurality of gate electrode layers ((22) , 31a), (24, 31a), (26, 31a), and a semiconductor device including a source-drain region formed by implanting impurity ions 27 and 29 on the semiconductor substrate 10. In the manufacturing method of A first conductive layer pattern such that the source-drain regions are electrically connected to each other on the semiconductor substrate 10 including the plurality of gate electrode layers 22, 31a, 24, 31a, and 26a, 31a. (33) forming step; Forming a second insulating film (31b) on the first insulating film pattern (31a) including the first conductive layer pattern (33); Forming a second conductive layer on the second insulating film (31b); The second conductive layer is patterned to form second conductive layer patterns 32 and 34, but the second insulating layer 31b under the second conductive layer patterns 32 and 34 is in a predetermined range within the second range. Etching to align self-etched on the conductive layer; Forming a third insulating film (42) on the second insulating film (31b) including the second conductive layer patterns (32, 34); Forming a photoresist pattern (43) on the third insulating film (42); The third insulating layer 42, the second insulating layer 31b, and the first conductive layer 33 are selectively etched using the photoresist pattern 43 and the second conductive layer patterns 32 and 34 as masks. The manufacturing method of the semiconductor device characterized by including the process of doing. The method of manufacturing a semiconductor device according to claim 1, wherein the first conductive layer (33) uses polycrystal silicon doped with impurities. The method of manufacturing a semiconductor device according to claim 1, wherein said second insulating film (31b) uses any one of a high temperature oxide film, a BPSG film, and a double layer made of a high temperature oxide film and a BPSG film. The method of manufacturing a semiconductor device according to claim 1, wherein said third insulating film (43) uses any one of a silicon dioxide, a silicon nitride film, and a double layer made of silicon dioxide and a silicon nitride film. A plurality of device active regions 16 repeatedly formed in parallel with each other with the device isolation region 12 interposed therebetween, and the plurality of device active regions 16 spaced apart from each other at predetermined intervals. A plurality of word lines 20, 22, 24, and 26 formed to be orthogonal to the device active region 16, and a source formed by implanting impurity ions into both sides of the plurality of word lines 20, 22, 24, and 26- In a semiconductor device having a drain region, The plurality of word lines 20, 22, 24, and 26 so that the source-drain regions are electrically connected to each other with a first insulating layer 31 a therebetween on the plurality of word lines 20, 22, 24, and 26. A plurality of first conductive layers 33 formed orthogonal to each other and spaced apart at predetermined intervals so as to overlap the plurality of device active regions 16 and repeatedly extended in parallel; The plurality of word lines 20, 22, 24, and 26 are orthogonal to each other on the first conductive layer 33 with the second insulating layer 31b interposed therebetween. Second conductive layers 32 and 34 mated with the device isolation region 12 and formed in plural; The third insulating film 42, the second insulating film 31b, and the first insulating film on the cell transistor, including the third insulating film 42 formed on the second conductive layers 32 and 34, according to the cell transistor type. A semiconductor device characterized by having a structure in which the conductive layer (33) is selectively removed. 6. A semiconductor device according to claim 5, wherein the first conductive layer (33) is polycrystalline silicon doped with impurities. 6. A semiconductor device according to claim 5, wherein said first insulating film (31a) is silicon dioxide. 6. The semiconductor device according to claim 5, wherein the second insulating film (31b) uses any one of a high temperature oxide film, a BPSG film, and a double layer composed of a high temperature oxide film and a BPSG film. 6. The semiconductor device according to claim 5, wherein the third insulating film (42) uses any one of silicon dioxide, silicon nitride film, and a double layer made of silicon dioxide and silicon nitride film.