JPS62229933A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a fine impurity introduced region in a semiconductor substrate without deteriorating the finness of a converged ion beam by a method wherein the converged ion beam which is not vertical to the substrate surface is applied to a thin film with a stepped part formed on the semiconductor substrate. CONSTITUTION:A thin film 2 is formed on a semiconductor substrate 1 so as to have the side plane 2' of its stepped part vertical to the surface of the semiconductor substrate 1. Then a converged ion beam 3 which have an incident angle theta of an acute angle against the surface of the semiconductor substrate 1 is applied and scanned parallel to the substrate surface to the direction of an arrow so as to cross the side plane 2' to form an impurity introduced region 4. If the projected range of an ion is denoted by Rp, the depth X of the formed impurity introduced region 4 and the penetration distance DELTA of the region 4 under the thin film 2 are expressed by X = Rp.cos theta and thetaL = Rp.sin theta. Therefore, by scanning the ion beam parallel to the semiconductor substrate surface while being applied with the acute incident angle against the substrate, impurity can be introduced into a three-dimensional minute region under the thin film.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device suitable for use in ion implantation using a focused ion beam without using a mask. .

[Conventional technology]

Conventionally, when forming an impurity layer in a semiconductor substrate by ion implantation, resist, silicon oxide film (Si
) or using the processed gate material as a mask, 1
An impurity ion beam with a beam diameter of ~ several beams was irradiated to form an impurity layer only in the desired region. However, in recent years,
``Japanese Journal of Applied Physics
As reported in "Al of Applied Physics)", Volume 22, No. 5, 1983, PL287, ions are implanted into a semiconductor substrate using a finely focused impurity ion beam, and the diameter of the beam is approximately Techniques are being developed to form fine impurity-introduced regions with a size of With the development of liquid metal ion sources that can be extracted by brightness,
This is because it has become possible to easily focus these ions to 0.1 or less.

If the above-mentioned focused ion beam is used, it is possible to introduce impurities into a fine region of 0.1- or less,
However, when applied to the manufacturing of semiconductor devices, impurity atoms implanted in fine regions are diffused laterally during the subsequent high-temperature heat treatment process during the entire manufacturing process, and the fineness is degraded. This causes the problem of damage. One way to suppress this lateral diffusion of impurities is to perform ion implantation using a focused ion beam as late as possible in the entire manufacturing process. But in that case,
Sun, film, polysilicon (PolySi) film, phosphorus glass (PSA) already formed on the semiconductor substrate
Ions must be implanted through a thin film such as or a laminated film thereof, which not only requires a focused ion beam with a high acceleration voltage, but also allows the ions to collide with the constituent atoms of the film as they pass through the thin film. The beam is scattered, effectively expanding the beam diameter. It is known that the spread of the ion beam in this thin film usually extends to the extent of the film thickness, which impairs the fineness of the focused ion beam.

[Problem that the invention seeks to solve]

The present inventors previously developed an FA (
Floatinl(Gate AvalancheI
(Japanese Patent Application Laid-Open No. 60-53083). However, due to the above-mentioned causes, the impurities introduced by the focused ion beam spread laterally, resulting in an abnormally high threshold voltage of the FAMO 8, causing a problem in which the write voltage of the FAMOS memory becomes high.

The purpose of the present invention is to solve the above-mentioned problems in the prior art,
An object of the present invention is to provide a method for manufacturing a semiconductor device that can form a fine impurity-introduced region in a semiconductor substrate without impairing the fineness of a focused ion beam.

[Means for solving problems]

The above objectives are (a) forming a plurality of thin films having steps on a semiconductor substrate; (b) making the ion beam irradiated onto the semiconductor substrate surface non-perpendicular to the substrate surface; and
This is achieved by using a manufacturing method that includes a step of scanning in parallel in a direction that successively crosses the stepped portions of each of the thin films.

[Effect]

The operation of the present invention will be explained with reference to the sectional view shown in FIG. After forming a thin film 2 on a semiconductor substrate, for example a silicon substrate 1, such that the side surface 2' of the stepped portion is perpendicular to the surface of the semiconductor substrate 1, a focused ion beam 3 is directed at an acute angle to the surface of the semiconductor substrate 1. While irradiating the beam at an incident angle of 0, the impurity-introduced region 4 is formed by scanning parallel to the side surface 2', that is, in the direction indicated by the arrow as the scanning direction of the beam in the figure.

The following relationship exists between the depth of the formed impurity introduction region 4, the penetration distance ΔL into the lower part of the thin film 2, and the above-mentioned incident angle 0.

x = RP-cos O・=-(1) ΔL = Rp-sinθ ・・・・・・
(2) Here, RP is the average ion penetration distance determined by the acceleration energy of the ion beam, a quantity called the so-called projected range. For example, when a boron (B) ion beam with an accelerating voltage of 100 keV is implanted into a silicon substrate at an incident angle of 0=45 degrees, Rp #0, 34.
X#0.2IIIm, ΔL:0.2t1m, and a fine impurity-introduced region can be formed directly under the stepped portion of the thin film 2.

As described above, according to the present invention, impurities can be introduced into a three-dimensional micro region at the bottom of a thin film by scanning the ion beam parallel to the semiconductor substrate surface while irradiating it at an acute angle of incidence. It has become possible to apply it to the manufacturing process of various semiconductor devices, and its technical effects are very large.

[Embodiments of the invention]

Hereinafter, one aspect of the present invention will be explained in detail.

Example 1 In this example, the present invention was applied to a floating gate type MO8flX field effect transistor (hereinafter abbreviated as FAMO8FET), which is a type of nonvolatile memory element.
An example of application to the invention will be explained with reference to FIG. 2. The present inventors first partially introduced impurities into the channel part of the FAMO8FET using a focused ion beam, thereby significantly lowering the data writing voltage without changing the threshold voltage during data erasing. proposed a FAMO3FET capable of
(See No. 83). FIG. 2 is a cross-sectional view for explaining the manufacturing process when the present invention is applied to manufacturing the FAMO5FET, and each process is shown in order.

FIG. 2(a) shows a thermal oxide film 5 with a thickness of 20 na+ formed by oxidizing (dry oxidation) in dry oxygen at 1000° C. for 20 minutes on a p-type (100) plane, 10 Ω' (m) silicon substrate 1. is grown, and further abbreviated as CVD method (hereinafter abbreviated as CVD method).
A silicon nitride film 6 is grown to a thickness of 30 Ωm using a photo-etching method.
The silicon nitride film 6 other than the part where the ET is to be formed is removed, and B ions are implanted at an acceleration voltage of 70 keV and f on the silicon substrate 1 in the part where the silicon nitride film 6 is removed by a normal ion implantation method. 3 x 10”cm-
After implantation under the following conditions, wet oxidation was performed at 1000° C. for 2 hours, and a field oxide film 7 and a channel stopper layer 8 formed by the above ion implantation were formed under the field oxide film 7.

Next, as shown in FIG. 2(b), 1g of silicon nitride
6 and the thermal oxide film 5 are removed by etching,
A gate oxide lll9 with a thickness of 30 nn+ was grown by dry oxidation for 25 minutes, and then grown by low pressure CVD and doped with phosphorus (P) using phosphorus oxychloride (poca3) as a diffusion source, and then by photoetching. processed. p! J resistance 5oΩ/mouth, thickness 0.2. A first polysilicon (hereinafter referred to as poly 5i) WXlo is formed, and further a first polysilicon (7) poly 5ilFJi is formed.

was oxidized by dry oxidation at 1100°C for 20 minutes,
A floating gate oxide film 11 is grown, and a low pressure CV
A second p layer grown by the D method and doped with P using Poc113 as a diffusion source, with a resistance of 40 Ω/hole and a thickness of 0.3-
olySi 11112 is formed.

After that, as shown in FIG. 2(c), the second poly
Si IFJ12, floating gate oxidation [11, and first
The ρolysi film 10 is etched by anti-film putter etching.
The floating gate 13 is processed by turning lithography processing.
After forming the control gate 14 and the control gate 14,
4. Using the laminated film consisting of the floating gate oxide film 11 and the floating gate 13 as a mask, the silicon substrate 1 is vertically irradiated with an arsenic (A s ) ion beam 15 with an acceleration voltage of 70 keV, with an implantation amount of 3 x 10" cm. The source 16 and the drain 17 are formed by implantation at 950° C. for 30 minutes in a nitrogen atmosphere.

Next, as shown in FIG. 2(d), the acceleration voltage is 50 keV.
A focused B ion beam 3 with a beam diameter of 0.2 am is scanned at an incident angle of 30 degrees with respect to the silicon substrate 1 parallel to the channel direction from the source 16 to the drain 17 to generate 5XIO "co+-". Implantation is performed at an implantation amount of 1, and short-time lamp annealing is performed at 1050° C. for 10 seconds in a nitrogen atmosphere to form a fine impurity-introduced region 4.6 After that, as shown in FIG. The MOSFET was completed by forming contact holes, and forming aluminum electrodes 19.

The performance of FAMO8FET completed through the above process.

Focusing B in non-perpendicular incidence, parallel scanning according to this embodiment
When compared with a FAMO8FET without the fine impurity implanted region 4 formed by ion beam implantation, the rate of increase in threshold voltage during data erasing was 5% at maximum, while the data write voltage was less than 50%. It was found that the data write characteristics of the FAMO8FET can be improved by the manufacturing method of this example.

Example 2 In this example, the manufacturing method of the present invention is applied to LDD (Light
An example in which this method is applied to the manufacture of a MO5FET having a doped drain structure will be described with reference to FIG. Figure 3 (
a) to (e) are MO8FETs in the middle of the manufacturing process of this example
Each step will be explained in order below using cross-sectional views.

In FIG. 3(a), a field oxide film 7 and a channel stopper layer 8 are formed under the field oxide film 7 on a p-type (100) plane, 10Ω"On silicon substrate 1 in a region other than the area where the MOSFET is to be formed. After that, a gate oxide film 9 with a thickness of 20 nm is grown by dry oxidation at 1000° C. for 20 minutes, polySi is grown by low pressure CVD, and after doping with P using poca as a diffusion source, it is processed by photoetching. layer resistance 50Ω/mouth, thickness 0.2
The state in which the gate 13 of - is formed is shown.

Next, as shown in FIG. 3(b), the acceleration voltage is 60 keV.
The silicon substrate 1 was irradiated with the As ion beam 15 perpendicularly to the implantation amount of 3×10''Ql-''.

Source 16 and drain 17 regions are formed.

Next, as shown in FIG. 3 (Q), the acceleration voltage is 30 keV.
A P ion beam 20 of A fine impurity-introduced region 4 is formed.

Furthermore, as shown in FIG. 3(d), under the same implantation conditions as in FIG. 3(c), the P ion beam 21 tilted in the opposite direction to the above case is scanned parallel to the silicon substrate. By doing so, a fine impurity introduced region 4 is also formed on the source 16 side.

Finally, as shown in FIG. 3 (θ), the MOSFET is completed by forming an insulating film 18, drilling contact holes, and forming an aluminum electrode 19.

By the method of this embodiment described above, the fine impurity doped region 4 of the LDD structure MO8FET as shown in FIG. 3(e). The gate 13, the source 16, and the drain 17 are processed once by lithographic processing (processing of the gate 13).
Each could be manufactured in a self-aligned manner and with high precision. As a result, the following problems with the conventional manufacturing method of forming the fine impurity-introduced region 4 by ion implantation using the sidewall of the oxide film formed by reactive sputter etching as a mask, namely, the variation in the processing dimensions of the sidewall. The variation in the gain constant of MOSFET caused by this amounted to about ±15%, but it was found that according to the method of this example, the variation in the gain constant, drain breakdown voltage, etc. could be controlled to less than ±5%. .

This is achieved by using the manufacturing method of the present invention, LDD structure MO5
This shows that the FET can be manufactured reliably, and the effectiveness of the present invention is confirmed.

Note that the P ion beams 20 and 21 in this example
Similar effects were obtained by using a focused P ion beam with a beam diameter of 1 #m instead.

〔Effect of the invention〕

According to the present invention, a thin film having a step formed on a semiconductor substrate is irradiated with an ion beam that is non-perpendicular to the substrate surface, thereby forming a fine impurity-introduced region in the semiconductor substrate at the edge of the thin film. This method is difficult to form using conventional ion implantation. Impurity concentration in the micro region at the bottom of the thin film.

It becomes possible to introduce impurities by controlling the junction depth etc. with high precision, and as a result, it can be applied to FAMoS transistors to reduce their threshold voltage.

The write voltage of FAMOS memory can be significantly reduced.

Furthermore, the present invention was applied to a manufacturing method of an LDD structure MOS transistor, and a comparison was made with a manufacturing method in which a fine impurity doped region is formed by ion implantation using a side wall of an oxide film formed by reactive sputter etching as a mask. Therefore, in the conventional method, the variation in the gain constant of the MOS transistor due to the variation in the processing dimensions of the sidewall was as much as ±15%, whereas according to the present invention, the variation in the gain constant, drain breakdown voltage, etc. It was confirmed that the difference could be controlled to within ±5%. Therefore, compared to the conventional method, it is possible to realize higher performance and higher reliability of MO8IC.

[Brief explanation of drawings]

Fig. 1 is a sectional view for explaining the operation of the present invention, Fig. 2(a),
(b), (c), (d), and (e) are cross-sectional views in the middle of each process of an embodiment of the present invention;
(d) and (e) are cross-sectional views in the middle of each step of another embodiment of the present invention. Explanation of symbols>

Claims (1)

[Claims] 1. A step of forming a plurality of thin films having steps on a semiconductor substrate, and irradiating the surface of the semiconductor substrate with an ion beam non-perpendicular to the substrate surface; 1. A method of manufacturing a semiconductor device, comprising the step of scanning in parallel in a direction that successively traverses a section. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the ion beam is a focused ion beam.