CN209169147U - Semiconductor devices - Google Patents

Abstract

The disclosure provides a kind of semiconductor devices, and wherein the semiconductor devices includes: semiconductor substrate, and the semiconductor substrate includes conducting channel；First doped region, positioned at the first side of the conducting channel；Second doped region, positioned at second side of the conducting channel；Lightly doped district, the concentration of Doped ions changes with the variation of the depth of the conducting channel between first doped region and the conducting channel and second doped region and the conducting channel, and in the lightly doped district.The disclosure is by improving processing technology, the lightly doped district of ion concentration gradual change is formed, while making the length of conducting channel elongated with the increase of the depth of the conducting channel, the risk that junction is collapsed is occurred to reduce semiconductor devices with this, inhibit hot carrier's effect, reduces leakage current.

Description

Semiconductor devices

Technical field

This disclosure relates to technical field of semiconductors, in particular to a kind of semiconductor devices.

Background technique

Metal Oxide Semiconductor Field Effect Transistor (Metal Oxide Semiconductor in integrated circuit Field Effect Transistor, abbreviation MOSFET) device after a period of work, the electric property of device can gradually be sent out Changing.

Currently, the channel dimensions of semiconductor devices have entered a micron epoch of receiving, device in operation, short-channel effect Especially severe.The drain induced barrier generated under the effect of high drain bias reduces effect (Drain Induced Barrier Lowering, abbreviation DIBL) cause threshold voltage to decline to a great extent, so that short-channel effect becomes even more serious.Due to nanoscale Other device shortens in PN junction energy bit distribution space, has more deepened the leakage electricity of short-channel effect and hot carrier injection effect Flow the influence to device property.

Therefore, the technical solution of the prior art can because caused by short-channel effect and hot carrier injection effect threshold voltage it is big Leakage current caused by width reduction and hot carrier injection effect generates bad shadow to the service life of device and stability It rings, there is also the places that has much room for improvement.

It should be noted that information is only used for reinforcing the reason to the background of the disclosure disclosed in above-mentioned background technology part Solution, therefore may include the information not constituted to the prior art known to persons of ordinary skill in the art.

Utility model content

The disclosure is designed to provide a kind of semiconductor devices, for being overcome at least to a certain extent due to related skill In art because caused by short-channel effect and hot carrier injection effect threshold voltage be greatly reduced and hot carrier injection effect institute The leakage current of generation leads to the problem of adverse effect to the service life of device and stability.

According to one aspect of the disclosure, a kind of semiconductor devices is provided, comprising:

Semiconductor substrate, the semiconductor substrate include conducting channel；

First doped region, positioned at the first side of the conducting channel；

Second doped region, positioned at second side of the conducting channel；

Lightly doped district is located at first doped region and the conducting channel and second doped region and the conduction Between channel, and the concentration of Doped ions changes with the variation of the depth of the conducting channel in the lightly doped district.

In a kind of exemplary embodiment of the disclosure, the length of the conducting channel with the conducting channel depth Increase and be incremented by.

In a kind of exemplary embodiment of the disclosure, adulterated in first lightly doped district and second lightly doped district The concentration of ion is successively decreased with the increase of the depth of the conducting channel.

In a kind of exemplary embodiment of the disclosure, further includes:

Gate structure is located on the conducting channel；

Wall is coated on the side wall of the gate structure, and the wall is made of at least 2 layers of spaced-apart sidewalls；

Wherein the boundary of the lightly doped district and the conducting channel by the spaced-apart sidewalls thickness limit.

In a kind of exemplary embodiment of the disclosure, the lightly doped district is the ion implanting by multiple various concentration It is formed.

The semiconductor devices that the embodiment of the present disclosure provides, by light between conducting channel and source/drain electrodes area The doping concentration of doped region is controlled, and the lightly doped district with modulation concentration is formed, so that the length of conducting channel is with institute State the increase of the depth of conducting channel and elongated, with this come effectively increase below silicon face channel between the source/drain region of both ends away from From, reduce drain electrode and silicon substrate against it is inclined when maximum field intensity with improve MOSFET short-channel effect, hot carrier injection effect, It reduces leakage current and increases breakdown voltage, promote the reliability of semiconductor devices.

It should be understood that above general description and following detailed description be only it is exemplary and explanatory, not The disclosure can be limited.

Detailed description of the invention

The drawings herein are incorporated into the specification and forms part of this specification, and shows the implementation for meeting the disclosure Example, and together with specification for explaining the principles of this disclosure.It should be evident that the accompanying drawings in the following description is only the disclosure Some embodiments for those of ordinary skill in the art without creative efforts, can also basis These attached drawings obtain other attached drawings.

Fig. 1 is the structural schematic diagram of the semiconductor devices with LDD traditional in the related technology.

Fig. 2 is drain current path schematic diagram under hot carrier injection effect in the related technology.

Fig. 3 is to collapse current path schematic diagram under tunneling effect in the related technology.

Fig. 4 is the schematic diagram of semiconductor devices in the embodiment of the present disclosure.

Fig. 5 is the flow chart of the production method of semiconductor devices in the embodiment of the present disclosure.

Fig. 6 is the implementation flow chart of manufacturing method of semiconductor device in an embodiment of the present disclosure.

Fig. 7 is the diagrammatic cross-section in an embodiment of the present disclosure after the completion of step S601.

Fig. 8 is the diagrammatic cross-section in an embodiment of the present disclosure after the completion of step S602.

Fig. 9 is the diagrammatic cross-section in an embodiment of the present disclosure after the completion of step S603.

Figure 10 is the diagrammatic cross-section in an embodiment of the present disclosure after the completion of step S604.

Figure 11 is the diagrammatic cross-section in an embodiment of the present disclosure after the completion of step S605.

Figure 12 is the diagrammatic cross-section in an embodiment of the present disclosure after the completion of step S606.

Figure 13 is the diagrammatic cross-section in an embodiment of the present disclosure after the completion of step S607.

Figure 14 is the diagrammatic cross-section in an embodiment of the present disclosure after the completion of step S608.

Figure 15 is the diagrammatic cross-section in an embodiment of the present disclosure after the completion of step S609.

Figure 16 is the diagrammatic cross-section in an embodiment of the present disclosure after the completion of step S610.

Figure 17 is the diagrammatic cross-section in an embodiment of the present disclosure after the completion of step S611.

Figure 18 is the diagrammatic cross-section in an embodiment of the present disclosure after the completion of step S612.

Figure 19 is the diagrammatic cross-section in an embodiment of the present disclosure after the completion of step S613.

Figure 20 is the diagrammatic cross-section in an embodiment of the present disclosure after the completion of step S614.

Figure 21 is the diagrammatic cross-section in an embodiment of the present disclosure after the completion of step S615.

Figure 22 is the diagrammatic cross-section in an embodiment of the present disclosure after the completion of step S616.

Figure 23 is the diagrammatic cross-section in an embodiment of the present disclosure after the completion of step S617.

Specific embodiment

Example embodiment is described more fully with reference to the drawings.However, example embodiment can be with a variety of shapes Formula is implemented, and is not understood as limited to example set forth herein；On the contrary, thesing embodiments are provided so that the disclosure will more Fully and completely, and by the design of example embodiment comprehensively it is communicated to those skilled in the art.Described feature, knot Structure or characteristic can be incorporated in any suitable manner in one or more embodiments.In the following description, it provides perhaps More details fully understand embodiment of the present disclosure to provide.It will be appreciated, however, by one skilled in the art that can It is omitted with technical solution of the disclosure one or more in the specific detail, or others side can be used Method, constituent element, device, step etc..In other cases, be not shown in detail or describe known solution to avoid a presumptuous guest usurps the role of the host and So that all aspects of this disclosure thicken.

In addition, attached drawing is only the schematic illustrations of the disclosure, identical appended drawing reference indicates same or similar portion in figure Point, thus repetition thereof will be omitted.Some block diagrams shown in the drawings are functional entitys, not necessarily necessary and object The entity managed or be logically independent is corresponding.These functional entitys can be realized using software form, or in one or more These functional entitys are realized in hardware module or integrated circuit, or in heterogeneous networks and/or processor device and/or microcontroller These functional entitys are realized in device.

In the related embodiment of the disclosure, as grid width constantly reduces, the channel length under grid structure is also continuous Reduce, in order to effectively prevent short-channel effect, lightly doped drain (Lightly Doped is introduced in integrated circuit fabrication process Drain, abbreviation LDD).

Fig. 1 is the structural schematic diagram of traditional semiconductor devices with LDD, as shown in Figure 1, semiconductor devices 100 wraps Include substrate 101, trap 102, source doping region 103, drain doping region 104, close source doping region 103 and drain doping region 104 The gate structure that lightly mixed drain area 105, grid oxic horizon 106 and the gate electrode 107 of setting form, and the covering grid With the wall 108 of side wall on structure, wherein substrate 101 can be Si substrate, and grid oxic horizon 106 can be silica SiO2。

Fig. 2 is drain current path schematic diagram under hot carrier injection effect, as shown in Fig. 2, wherein N is indicated by taking NMOS as an example Electronics, P indicate hole, and S indicates that source electrode, D indicate drain electrode, and G indicates grid, source S ground connection, due to drain D voltage V_DGreater than source Pole D voltage V_S.There is reverse current to flow through between substrate and source, leakage, channel, the electric field that the electronics in substrate is depleted area pulls out And accelerate to channel mobile, when PN junction face is sufficiently high against the electric field near inclined maximum field, these electronics have enough energy Substrate Si and the interface grid oxygen SiO2 can be reached, and is injected into SiO2, the threshold voltage, leakage current and operation of device are caused The deterioration in service life is more deepened however as the reduction of semiconductor device channel size since PN junction energy bit distribution space is shortened The influence of short-channel effect and hot carrier injection effect to device property.

Fig. 3 is that current path schematic diagram is collapsed under tunneling effect, as shown in figure 3, generating on depletion region boundary by source electrode stream To the collapse electric current of drain electrode, with the diminution of device channel size, can also be more easier so that tunneling collapse (Punch- Through Breakdown) voltage decline.

Series resistance when break-over of device is reduced to meet, and the ability of driving current is promoted, before semiconductor devices In section processing procedure, source/drain region needs high concentration ion to inject.It is highly concentrated due to source/drain region in spite of the presence of LDD structure After spending ion implanting, it is tempered by subsequent high temperature, often horizontal proliferation enters channel region to the highly doped element of source/drain region, makes It obtains the distance that both ends source electrode and drain electrode is interregional below silicon face channel to shorten (as shown in Figure 1), causes threshold voltage with short Channelling effect causes the unstable of device operation process, increase drain electrode and silicon substrate against it is inclined when maximum field intensity, cause tight The hot carrier effect of weight, leads to the increase of leakage current and the decline of tunneling voltage.

Based on above-mentioned, the design for how carrying out LDD optimization effectively inhibits caused by short channel and hot carrier injection effect Threshold voltage is greatly reduced, reduces leakage current and how to improve breakdown voltage, the raising for performance of semiconductor device It is significant.

The disclosure can provide a kind of with modulation under the premise of not increasing exposure mask number to inhibit process costs increased The lightly mixed drain area of concentration effectively increases the distance below silicon face channel between the source/drain region of both ends with this, reduces drain electrode With silicon substrate against it is inclined when maximum field intensity with improve MOSFET short-channel effect, hot carrier injection effect, reduce leakage electricity Stream and the manufacturing method thereof for increasing breakdown voltage.

Disclosure example embodiment is described in detail with reference to the accompanying drawing.

Fig. 4 is the schematic diagram of semiconductor devices in the embodiment of the present disclosure.

As shown in figure 4, the semiconductor devices that the disclosure provides includes: semiconductor substrate 401, the semiconductor substrate 401 Including the first doped region 403, the second doped region 404, lightly doped district and conducting channel, the first doped region 403 is located at the conduction First side of channel, the second doped region 404 are located at second side of the conducting channel.Lightly doped district is located at first doped region Between 403 and the conducting channel and second doped region 404 and the conducting channel, and adulterated in the lightly doped district The concentration of ion and distributed areas change with the variation of the depth of the conducting channel.

As shown in figure 4, the lightly doped district in the present embodiment includes the first lightly doped district 405 and the second lightly doped district 406, the One lightly doped district 405 is between first doped region 403 and the conducting channel；Second lightly doped district 406 is located at described Between second doped region 404 and the conducting channel.

Based on the semiconductor devices that the embodiment of the present disclosure provides, by between conducting channel and source/drain electrodes area Lightly doped district doping concentration and distributed areas controlled, form the lightly doped district with modulation concentration, while to lead The length of electric channel is elongated with the increase of the depth of the conducting channel, can effectively increase both ends below silicon face channel Distance between source/drain region, reduce drain electrode and silicon substrate against it is inclined when maximum field intensity with improve MOSFET short-channel effect, Hot carrier injection effect reduces leakage current and increases breakdown voltage.

By taking semiconductor devices shown in Fig. 4 as an example, in the semiconductor device, conducting channel and doped region specifically can positions In the trap 402 that semiconductor substrate 401 is formed through overdoping, the concentration of Doped ions changes with conducting channel in lightly doped district, The length of the conducting channel is elongated with the increase of the depth of the conducting channel simultaneously.

In a kind of exemplary embodiment of the disclosure, the concentration of Doped ions changes with conducting channel and has in lightly doped district Body are as follows: the concentration of Doped ions is successively decreased with the increase of the depth of the conducting channel in the lightly doped district, the conduction The length of channel is incremented by with the increase of the conducting channel depth.

In a kind of exemplary embodiment of the disclosure, since the lightly doped district includes the first lightly doped district 405 and the Two lightly doped districts 406, wherein in first lightly doped district 405 and second lightly doped district 406 Doped ions concentration with The increase of the depth of the conducting channel and successively decrease, while the length of conducting channel is incremented by with the increase of depth.Variation Trend is as shown in figure 4, be located at the first lightly doped district 405 and conduction ditch of the first side of conducting channel (left side as shown in Figure 4) The boundary in road shows along the increase of the depth of conducting channel and gradually tilts to the direction far from conducting channel, opposite, It is showed positioned at second lightly doped district 406 of conducting channel second side (right side as shown in Figure 4) and the boundary of conducting channel It is gradually tilted to the direction far from conducting channel along the increase of the depth of conducting channel.

In a kind of exemplary embodiment of the disclosure, wherein the lightly doped district apart from first doped region and/or The position of wall of the farthest boundary of second doped region by the wall on the gate structure sidewall limits Fixed, the lightly doped district is apart from the nearest boundary of first doped region and/or second doped region by the wall Position restriction far from the wall on the gate structure sidewall.

In a kind of exemplary embodiment of the disclosure, as shown in figure 4, in the semiconductor device in addition to above structure it Outside, further includes: the gate structure that grid oxic horizon 407, gate electrode 410 and grid protection layer 415 form, the gate structure position On the conducting channel, grid oxic horizon 407 is formed in the surface of semiconductor substrate 401.

In addition, in semiconductor devices further include: wall is covered on the side wall of the gate structure, wherein wall by At least 2 layers of spaced-apart sidewalls composition.Specifically, wall includes gate structure the first side wall (left side wall as shown in Figure 4) surface The first wall 408 and gate structure second sidewall (right side wall as shown in Figure 4) surface the second wall 409.One In exemplary embodiment, first wall 408 and second wall 409 are made of at least 2 layers of spaced-apart sidewalls.Specifically , the ingredient of the spaced-apart sidewalls is identical or different or part is different.In an example embodiment, the spaced-apart sidewalls are by between first It is formed every side wall and the second spaced-apart sidewalls, first spaced-apart sidewalls are silicon nitride, and second spaced-apart sidewalls are silica.? Another example embodiment, the spaced-apart sidewalls are silicon nitride or silica.The thickness of the spaced-apart sidewalls is identical or different Or part is different, and it is identical in the thickness of an example embodiment, the spaced-apart sidewalls, it is 2nm, is formed using spaced-apart sidewalls light The distribution of doped region and the boundary of conducting channel change linearly, and the length of conducting channel is linearly incremented by with the variation of depth. In a further exemplary embodiment, the thickness of the spaced-apart sidewalls is not identical or part is different, with the first spaced-apart sidewalls and second For spaced-apart sidewalls, first spaced-apart sidewalls utilize spaced-apart sidewalls with a thickness of 2nm, second spaced-apart sidewalls with a thickness of 3nm The distribution of the lightly doped district of formation and the boundary of conducting channel are in nonlinear change, the length of conducting channel with the variation of depth and Monotonic increase.

In a kind of exemplary embodiment of the disclosure, the first doped region 403 can be source area 403, the second doped region 404 can be drain region 404, therefore further include source electrode 412 that corresponding source area 403 is formed in semiconductor substrate 401 and right The drain electrode 411 for answering drain region 404 to be formed.In addition, gate contact 413 is also formed on gate electrode 410, gate contact 413 The metal electrode of different location can be respectively formed at through same layer metal etch with source electrode 412 and drain electrode 411.

It should also be noted that, between source electrode 412 and source area 403, drain electrode 411 and drain region 404 between and grid Ohmic contact regions 414 are respectively formed between electrode 410 and gate contact 413.Wherein in Fig. 4 only to an ohmic contact regions (i.e. pair Answer the ohmic contact regions of drain region 404) it is marked, and actually on corresponding source area 403 and gate electrode 410 also With the presence of ohmic contact regions.Ohmic contact refers to that the resistance value of contact surface when contact of the metal with semiconductor is much smaller than semiconductor The resistance of itself, so that most voltage drop is in behaviour area without realizing that ohm connects in contact surface when operation of semiconductor devices The major measure of touching is to carry out highly doped in semiconductor surface layer or introduce a large amount of complex centres.

In a kind of exemplary embodiment of the disclosure, the lightly doped district (the first lightly doped district and the second lightly doped district) To be formed by the ion implanting of multiple various concentration.The concentration and energy of ion implanting when carrying out multiple ion implanting are not yet Together, wherein first time ion implanting when ion concentration it is maximum, the energy of ion implanting is minimum, to determine first time ion implanting Maximum in the doping concentration that lightly doped district is formed, incorporation depth is most shallow, i.e., near 401 surface of semiconductor substrate.Then, every time It is gradually reduced ion concentration when ion implanting, increases the energy of ion implanting, that is, is more proximate to 401 surface of semiconductor substrate Position Doped ions concentration it is bigger, the position Doped ions concentration far from 401 surface of semiconductor substrate is smaller, thus shape Successively decrease the lightly doped district of variation at ion concentration.In an example embodiment, the ion energy of first time ion implanting is 1KeV, dense Degree is 5E14 every square centimeter, and the ion energy of second of ion implanting is 6KeV, and concentration is 5E13 every square centimeter.Another In example embodiment, the ion energy and concentration relationship can also be set by a certain percentage, the ion of first time ion implanting Energy is 1KeV, and concentration is 5E14 every square centimeter, and second of ion implantation energy is the ion energy of first time ion implanting 1.5 times, i.e. 1.5KeV, second ion implantation concentrations be 0.8 times of concentration of first time ion implanting, i.e. every square of 4E14 Centimetre, and so on third time ion implantation energy and concentration, the 4th secondary ion Implantation Energy and concentration, the injection of the 5th secondary ion Energy and concentration ..., to form the lightly doped region of linear modulation.When carrying out multiple ion implanting, the ion implanting Type is identical or different or part is different.In an example embodiment, P-type ion injection is phosphonium ion.Implement in another example Example, P-type ion is injected to phosphonium ion and arsenic ion, specifically, by taking ion implanting three times as an example, first time ion implanting be phosphorus from Son, second of ion implanting are arsenic ion, and third time ion implanting is phosphonium ion.

It should also be noted that, when in use, the grid of semiconductor devices connects scan signal line, to imitate to MOS Should pipe grid input grid voltage Vg.Drain electrode connection data line, so as to the drain electrode input data voltage of metal-oxide-semiconductor field effect transistor Vd。

In conclusion due to the LDD region of modulation ion concentration distribution in the semiconductor devices provided in the embodiment of the present disclosure The presence in domain so that the conducting channel lateral length in silicon substrate (semiconductor substrate 401) will be from silicon face to silicon substrate inside Gradually it is incremented by avoid short-channel effect, and can avoid tunneling collapse simultaneously, or promote tunneling breakdown voltage, due to LDD region domain Concentration is successively decreased, it will change (or reduce) between LDD and silicon substrate PN junction against it is inclined when maximum field position and reduce its electricity Field size, reduces leakage current caused by hot carrier effect, makes the working heat carrier injection effect of semiconductor devices, reduces leakage Electric current and increase breakdown voltage, promote the reliability of semiconductor devices.

For above-mentioned semiconductor device, by taking NMOS tube as an example, semiconductor substrate 401 can use N-type substrate, in N-type The p-well 402 that incorporation P-type ion (such as boron+trivalent ion) is formed is provided on substrate 401, the first doped region 403, second are mixed The ionic type in miscellaneous area 404, the first lightly doped district 405 and the incorporation of the second lightly doped district 406 is also N-type ion, such as phosphorus P or arsenic As Deng+5 valence ions.Similarly, if it is PMOS tube, then the corresponding adjustment of the needs such as Doped ions type, details are not described herein again.

Fig. 5 is the flow chart of the production method of semiconductor devices in the embodiment of the present disclosure, comprising the following steps:

As shown in figure 5, providing semiconductor substrate in step S501.Specifically, the semiconductor substrate is silicon substrate, One of gallium nitride, GaAs and silicon-on-insulator substrate, the semiconductor substrate can directly be P type substrate or N-type lining Bottom, the N trap that can also be the p-well formed in N-type substrate or formed in P type substrate.

As shown in figure 5, in step S502, gate structure is formed on the semiconductor substrate, under the gate structure Conducting channel is formed in the semiconductor substrate of side.

As shown in figure 5, forming the first spaced-apart sidewalls on the side wall of the gate structure, and pass through in step S503 First spaced-apart sidewalls define is lightly doped ion implanted regions for the first time.

As shown in figure 5, ion implanted regions are lightly doped according to the first time and carry out the first secondary ion in step S504 Injection.

As shown in figure 5, forming the second spaced-apart sidewalls on first spaced-apart sidewalls surface, and pass through in step S505 Second spaced-apart sidewalls define is lightly doped ion implanted regions for the second time, wherein described be lightly doped ion implanted region for the second time Domain is less than is lightly doped ion implanted regions for the first time.

As shown in figure 5, carrying out the second secondary ion according to the ion implanted regions that are lightly doped for the second time in step S506 Injection.

As shown in figure 5, in step s 507, the first time ion implanted regions and second of ion implanted regions Form lightly doped district.

As shown in figure 5, in step S508, the first doped region is respectively formed in the two sides of the conducting channel, second is mixed Miscellaneous area, the lightly doped district between first doped region and the conducting channel and second doped region with it is described Between conducting channel.

It should be noted that needing at least to carry out the formation and the injection of 2 secondary ions of 2 minor tick side walls in this example, i.e., The patterning processes that step S505 is repeated several times form spaced-apart sidewalls and the ion implantation technology of step S506.Specifically, described The ingredient of spaced-apart sidewalls is identical or different or part is different.In an example embodiment, the spaced-apart sidewalls are by the first spaced-apart sidewalls It is formed with the second spaced-apart sidewalls, first spaced-apart sidewalls are silicon nitride, and second spaced-apart sidewalls are silica.Show another Example embodiment, the spaced-apart sidewalls are silicon nitride or silica.The thickness of the spaced-apart sidewalls is identical or different or part Difference, it is identical in the thickness of an example embodiment, the spaced-apart sidewalls, it is 2nm, the lightly doped district formed using spaced-apart sidewalls Distribution and the boundary of conducting channel be linearly distributed, the length of conducting channel is linearly incremented by with the variation of depth.Another In exemplary embodiment, the thickness of the spaced-apart sidewalls is not identical or part is different, with the first spaced-apart sidewalls and the second interval side For wall, first spaced-apart sidewalls are formed with a thickness of 3nm using spaced-apart sidewalls with a thickness of 2nm, second spaced-apart sidewalls The distribution of lightly doped district and the boundary of conducting channel are in nonlinear change, the length of conducting channel with the variation of depth and dullness is passed Increase.

In a kind of exemplary embodiment of the disclosure, the energy of second of ion implanting be greater than the first time from The energy of son injection, so that the depth in lightly doped district injection ion is gradually deepened.The concentration of second of ion implanting is small In the concentration of the first time ion implanting, so that the concentration in lightly doped district injection ion gradually subtracts with the increase of depth It is few.In the ion implanting at least more than 2 times, rear injection ion concentration is less than previous ion implantation concentration, rear secondary ion note Enter depth greater than previous ion implanting depth.In an example embodiment, the ion energy of first time ion implanting is 1KeV, concentration It is 5E14 every square centimeter, the ion energy of second of ion implanting is 6KeV, and concentration is 5E13 every square centimeter.Show another In example embodiment, the ion energy and concentration relationship can also be set by a certain percentage, the ion energy of first time ion implanting Amount is 1KeV, and concentration is 5E14 every square centimeter, and second of ion implantation energy is the ion energy of first time ion implanting 1.5 times, i.e. 1.5KeV, second of ion implantation concentration are 0.8 times of the concentration of first time ion implanting, i.e. every square li of 4E14 Rice, and so on third time ion implantation energy and concentration, the 4th secondary ion Implantation Energy and concentration, the 5th secondary ion inject energy Amount and concentration ..., to form the lightly doped region of linear modulation.When carrying out multiple ion implanting, the kind of the ion implanting Class is identical or different or part is different.In an example embodiment, P-type ion injection is phosphonium ion.In another example embodiment, P-type ion is injected to phosphonium ion and arsenic ion, specifically, first time ion implanting is phosphonium ion by taking ion implanting three times as an example, Second of ion implanting is arsenic ion, and third time ion implanting is phosphonium ion.

In a kind of exemplary embodiment of the disclosure, first secondary ion note before further include: carry out Halo from Son injection.

Following figure 6 combines a specific example that the production method of above-mentioned semiconductor device is introduced, and includes the following steps:

Step S601, on a semiconductor substrate deposition oxide.Fig. 7 shows the diagrammatic cross-section after the completion of step S601, Oxide 702 is formed i.e. in semiconductor substrate 701.Wherein the type of semiconductor substrate 701 can be N-type or p-type, this implementation In example by taking NMOS tube as an example, N-type semiconductor substrate can be used.

Step S602 carries out well region ion implanting, forms trap 703 on the semiconductor substrate 701 in certain depth region. Fig. 8 shows the diagrammatic cross-section after the completion of step S602, i.e., trap 703 is formed in semiconductor substrate 701.Still it is with NMOS tube Example, forming p-well, whereas if being PMOS tube by ion implanting on N-type semiconductor substrate is then in P-type semiconductor substrate It is upper to form N trap by ion implanting.

Step S603 adjusts threshold voltage by ion implanting.Fig. 9 shows the diagrammatic cross-section after the completion of step S603. The factor for usually influencing threshold voltage is more, such as can be realized pair by controlling the modes such as oxidated layer thickness and ion implanting The adjustment of metal-oxide-semiconductor threshold voltage (is leading to threshold voltage just by injecting boron ion at semiconductor substrate surface in the present embodiment Offset) or the foreign ions such as phosphonium ion (leading to threshold voltage negative offset), by accurately controlling the energy and concentration of injection ion, To adjust semiconductor surface impurity concentration, to achieve the purpose that adjust threshold voltage.

Step S604 is annealed and is removed oxide.Figure 10 shows the diagrammatic cross-section after the completion of step S604.Ion It anneals after injection, injection silicon wafer can be heated, oxidation generates protective film, repairs lattice damage, can be realized ion and divide again Cloth, reduction impurity concentration is poor, and foreign atom is made to be moved to lattice-site, activates implanted dopant.It also needs to remove oxide after annealing 702, such as oxide can be removed using dry etching.

Step S605 forms grid oxic horizon.Figure 11 shows the diagrammatic cross-section after the completion of step S605, on trap 703 Form grid oxic horizon 704.

Step S606 carries out the production of grid material, and the grid material can be polysilicon and ion implanting is formed.Figure 12 show the diagrammatic cross-section after the completion of step S606, on grid oxic horizon 704 deposition form polycrystalline silicon material, then into Row ion implanting, if it is NMOS tube, then the ionic type of step intermediate ion injection is the N-type ions such as phosphorus；If it is PMOS Pipe, then the ionic type of step intermediate ion injection is the P-type ions such as boron.

Step S607 anneals to the polysilicon gate material of injection ion.Figure 13 is shown after the completion of step S607 Diagrammatic cross-section, the annealing in the step is identical as process with the annealing theory of step S604, and oxidation generates protective film, repairs brilliant Lattice damage can be realized ion redistribution, and reduction impurity concentration is poor, and foreign atom is made to be moved to lattice-site, activate implanted dopant, To form gate electrode 705 on grid oxic horizon 704.In addition, further in one layer of protection of deposition on gate electrode 705 after annealing Layer 706.

Step S608 defines active region channel by etch process.Figure 14 shows the section after the completion of step S608 and shows It is intended to, leaves partial gate oxide 704, gate electrode 705 and protective layer 706 by etching technics.Beginning in the present embodiment Technique can according to need selection wet etching or dry etching method realizes that details are not described herein again.

Step S609 carries out deposition and the etching of the first spaced-apart sidewalls layer to define first time LDD ion implanted regions. Figure 15 shows the diagrammatic cross-section after the completion of step S609, and the deposition of SiN/SiO is carried out in the structure shown in Figure 14, forms the One spaced-apart sidewalls layer (the second spaced-apart sidewalls layer that the first spaced-apart sidewalls layer and later step are formed use 707 indicate), then passes through Over etching technique etches away redundance, only retains the side for being covered on grid oxic horizon 704, gate electrode 705 and protective layer 706 The part of wall defines first time LDD ion implanted regions, as shown in figure 15.

Step S610 is carried out halo ion implanting (Halo implant).Figure 16 shows the section after the completion of step S610 Schematic diagram carries out halo ion implanting in the first time LDD ion implanted regions of definition, thus conducting channel as shown in figure 16 Region forms halo region at the position of doped region.Wherein, the ionic type of halo region and the ionic species of lightly doped district are injected For type on the contrary, the ion energy of injection halo region is greater than the ion energy of injection lightly doped district, the ion concentration for injecting halo region is small In the ion concentration of injection lightly doped district, improves HCI effect by halo ion implanting, avoid tunneling breakdown effect, the step Suddenly it can according to need and be selectively increasing in entire processing procedure.For making NMOS, the ionic species of lightly doped district are injected Type is N-type, then the ionic type of injection halo region is p-type, the ion energy that halo region is injected in the present embodiment is 10~ 60KeV, concentration are 5E12~5E13 every square centimeter.

Step S611 carries out first time LDD ion implanting.Figure 17 shows the diagrammatic cross-section after the completion of step S611, the The concentration highest of primary ions injection, energy is minimum, and the depth of ion implanting is most shallow, close to silicon substrate.In the present embodiment The ion energy of injection lightly doped district is 1KeV for the first time, and concentration is 5E14 every square centimeter.

Step S612 carries out deposition and the etching of the second spaced-apart sidewalls layer to define second of LDD ion implanted regions. Figure 18 shows the diagrammatic cross-section after the completion of step S612, principle and process with above-mentioned steps S609, and details are not described herein again. As shown in figure 18, which is to continue to deposit on the basis of above-mentioned steps, and second spaced-apart sidewalls are formed in described first On the surface of spaced-apart sidewalls (the first spaced-apart sidewalls and the second spaced-apart sidewalls are only to be formed by several times, and material is identical with depositional mode, Therefore it is indicated with 707).

Step S613 carries out second of LDD ion implanting.Figure 19 shows the diagrammatic cross-section after the completion of step S613, the The concentration of secondary ion injection is less than previous implantation concentration, and the energy of energy ratio first time ion implanting is big, so that ion implanting The more previous injection depth of depth it is deeper, the surface apart from silicon substrate is farther.Then and so on, complete n times spaced-apart sidewalls layer Deposition-etch and LDD ion implanting.The ion energy of second of injection lightly doped district is 2KeV in the present embodiment, and concentration is 3E14 is every square centimeter.

Step S614 carries out last first time LDD ion implanting.Figure 20 shows the section signal after the completion of step S614 The concentration of figure, last time ion implanting is minimum, and energy is maximum, and the depth of ion implanting is most deep, to complete doping LDD injection Technique.The ion energy for injecting lightly doped district in the present embodiment for the last time is 6KeV, and concentration 5E13 is every square centimeter.

Step S615 carries out source-drain electrode side wall (Side Wall) dielectric layer deposition and etching to define source/drain region. Figure 21 shows the diagrammatic cross-section after the completion of step S615, that is, dielectric layer (the first spaced-apart sidewalls layer and the second interval side formed Parietal layer 707) define the region of source electrode and drain electrode positioned at 703 both sides of trap.

Step S616 carries out source/drain region ion implanting.Figure 22 shows the diagrammatic cross-section after the completion of step S616, point Two region 708' and 709' are not formed in trap.

Step S617, anneals.Figure 23 shows the diagrammatic cross-section after the completion of step S617, and the annealing in the step is same The annealing theory of step S604 and step S607 are identical as process, form source area 708 and drain region 709 in trap respectively, and Lightly doped district 710 is formed between source area 708 and conducting channel and between drain region 709 and conducting channel.This please be adulterated Area 710 is made up of first time ion implanted regions and second of ion implanted regions.

It is etched again by exposure mask after the step, defines electrode contact hole region (i.e. ohmic contact regions), go forward side by side Row ion implanting and annealing, to reduce contact resistance.Such as respectively in the corresponding window of gate structure and source area and leakage The corresponding window in polar region is respectively formed three ohmic contact regions.Then, it carries out metal electrode deposition and MOSFET device is completed in etching Part finally obtains device as shown in Figure 4, is performed etching by the metal layer to deposition, and grid can be formed on gate structure Pole contact, forms source electrode on source area, and drain electrode is formed on drain region.

Based on above-mentioned steps S601 to step S617, the diagrammatic cross-section in conjunction with shown in Fig. 7 to Figure 23 can be seen that this reality The production method of example offer is applied after completing halo ion implanting, utilizes LDD doped chemical ion implanting and spacer deposition Etch process repeatedly carries out back and forth, wherein the implantation concentration of Doped ions will increase with injection number and sequentially successively decrease, and inject Energy is sequentially incremented by with number, to complete the LDD region domain of descending concentrations distribution.

In conclusion by using the production method of semiconductor devices provided in this embodiment, due to LDD region domain and from Sub- concentration becomes smaller with the increase of conducting channel depth, so that the conducting channel lateral length in silicon substrate will be from silicon face to silicon Gradually it is incremented by inside substrate to avoid short-channel effect, and can avoid tunneling collapse simultaneously, or promotes tunneling breakdown voltage, due to LDD region domain concentration is successively decreased, it will change (or reduce) between LDD and silicon substrate PN junction against it is inclined when maximum field position and drop Its low electric field level, reduces leakage current caused by hot carrier effect, makes working heat carrier injection effect, the drop of semiconductor devices Low current leakage and increase breakdown voltage, promote the reliability of semiconductor devices.

Person of ordinary skill in the field is it is understood that the various aspects of the utility model can be implemented as system, side Method or program product.Therefore, the various aspects of the utility model can be with specific implementation is as follows, it may be assumed that complete hardware is real The embodiment combined in terms of applying mode, complete Software Implementation (including firmware, microcode etc.) or hardware and software, Here it may be collectively referred to as circuit, " module " or " system ".

In addition, above-mentioned attached drawing is only the schematic of the processing according to included by the method for the utility model exemplary embodiment Illustrate, rather than limits purpose.It can be readily appreciated that the time that above-mentioned processing shown in the drawings did not indicated or limited these processing is suitable Sequence.In addition, be also easy to understand, these processing, which can be, for example either synchronously or asynchronously to be executed in multiple modules.

Those skilled in the art will readily occur to the disclosure after considering specification and practicing utility model disclosed herein Other embodiments.This application is intended to cover any variations, uses, or adaptations of the disclosure, these modifications are used Way or adaptive change follow the general principles of this disclosure and including the disclosure it is undocumented in the art known in Common sense or conventional techniques.The description and examples are only to be considered as illustrative, and the true scope of the disclosure and design are by weighing Benefit requires to point out.

Claims (5)

1. a kind of semiconductor devices characterized by comprising

Semiconductor substrate, the semiconductor substrate include conducting channel；

First doped region, positioned at the first side of the conducting channel；

Second doped region, positioned at second side of the conducting channel；

Lightly doped district is located at first doped region and the conducting channel and second doped region and the conducting channel Between, and the concentration of Doped ions and distributed areas become with the variation of the depth of the conducting channel in the lightly doped district Change.

2. semiconductor devices as described in claim 1, which is characterized in that the length of the conducting channel is with the conductive ditch The increase of road depth and be incremented by.

3. semiconductor devices as described in claim 1, which is characterized in that the lightly doped district includes the first lightly doped district and the Two lightly doped districts, and in first lightly doped district and second lightly doped district Doped ions concentration with the conductive ditch The increase of the depth in road and successively decrease.

4. semiconductor devices as described in claim 1, which is characterized in that further include:

Gate structure is located on the conducting channel；

Wall is coated on the side wall of the gate structure, and the wall is made of at least 2 layers of spaced-apart sidewalls；

Wherein the boundary of the lightly doped district and the conducting channel by the spaced-apart sidewalls thickness limit.

5. semiconductor devices as claimed in claim 4, which is characterized in that the lightly doped district is by multiple various concentration Ion implanting is formed.