JPH0974191A - Manufacture of silicon carbide semiconductor device - Google Patents
Manufacture of silicon carbide semiconductor deviceInfo
- Publication number
- JPH0974191A JPH0974191A JP7229485A JP22948595A JPH0974191A JP H0974191 A JPH0974191 A JP H0974191A JP 7229485 A JP7229485 A JP 7229485A JP 22948595 A JP22948595 A JP 22948595A JP H0974191 A JPH0974191 A JP H0974191A
- Authority
- JP
- Japan
- Prior art keywords
- groove
- semiconductor layer
- silicon carbide
- semiconductor
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 182
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 66
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 60
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 37
- 239000010410 layer Substances 0.000 claims abstract description 163
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 239000013078 crystal Substances 0.000 claims abstract description 13
- 239000002344 surface layer Substances 0.000 claims abstract description 6
- 238000010030 laminating Methods 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 49
- 230000003647 oxidation Effects 0.000 claims description 20
- 238000007254 oxidation reaction Methods 0.000 claims description 20
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 9
- 229910052799 carbon Inorganic materials 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 6
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims 1
- 150000002500 ions Chemical class 0.000 abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 9
- 229920005591 polysilicon Polymers 0.000 abstract description 9
- 230000003247 decreasing effect Effects 0.000 abstract description 2
- 239000012535 impurity Substances 0.000 description 22
- 230000000694 effects Effects 0.000 description 18
- 230000015572 biosynthetic process Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 11
- 230000015556 catabolic process Effects 0.000 description 8
- 239000000463 material Substances 0.000 description 7
- 238000013461 design Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 230000009257 reactivity Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000000349 field-emission scanning electron micrograph Methods 0.000 description 1
- NRQNMMBQPIGPTB-UHFFFAOYSA-N methylaluminum Chemical compound [CH3].[Al] NRQNMMBQPIGPTB-UHFFFAOYSA-N 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
- H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/048—Making electrodes
- H01L21/049—Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、炭化珪素半導体
装置の製造方法に関するものであり、その用途としては
例えば、絶縁ゲート型電界効果トランジスタ、とりわけ
大電力用の縦型ＭＯＳＦＥＴ等の製造方法に用いて好適
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a silicon carbide semiconductor device, which is used, for example, in a method for manufacturing an insulated gate field effect transistor, especially a vertical MOSFET for high power. Is suitable.
【０００２】[0002]
【従来の技術】近年、電力用トランジスタとして炭化珪
素単結晶材料を使用した縦型パワーＭＯＳＦＥＴが提案
されている。電力用トランジスタの損失を低減するため
にはオン抵抗の低減が必要であり、効果的にオン抵抗低
減が可能な素子構造として図１１に示す溝ゲート型パワ
ーＭＯＳＦＥＴ（例えば、特開平４−２３９７７８号公
報）が提案されている。図１１における溝ゲート型パワ
ーＭＯＳＦＥＴは炭化珪素の基板３０上に第１半導体領
域３１が形成され、第１半導体領域３１上に第２半導体
領域３２が形成され、さらに、第２半導体領域３２の所
定領域に第３半導体領域３３が形成されている。又、第
３半導体領域３３と第２半導体領域３２を貫通して第１
半導体領域３１に達する溝３４が形成され、溝３４内に
はゲート絶縁膜３５を介してゲート電極３６が充填され
ている。ゲート電極３６の上面には絶縁膜３７が形成さ
れ、絶縁膜３７上を含む第３半導体領域３３上にはソー
ス電極膜３８が形成されている。又、基板３０の表面に
はドレイン電極膜３９が形成されている。2. Description of the Related Art In recent years, a vertical power MOSFET using a silicon carbide single crystal material has been proposed as a power transistor. In order to reduce the loss of the power transistor, it is necessary to reduce the on-resistance, and as a device structure capable of effectively reducing the on-resistance, the trench gate type power MOSFET shown in FIG. 11 (for example, Japanese Patent Laid-Open No. 4-239778) is used. Gazette) has been proposed. In the trench gate type power MOSFET in FIG. 11, the first semiconductor region 31 is formed on the substrate 30 made of silicon carbide, the second semiconductor region 32 is formed on the first semiconductor region 31, and the predetermined second semiconductor region 32 is formed. The third semiconductor region 33 is formed in the region. In addition, the first semiconductor region 33 and the second semiconductor region 32 are penetrated and
A trench 34 reaching the semiconductor region 31 is formed, and the trench 34 is filled with a gate electrode 36 via a gate insulating film 35. An insulating film 37 is formed on the upper surface of the gate electrode 36, and a source electrode film 38 is formed on the third semiconductor region 33 including the insulating film 37. A drain electrode film 39 is formed on the surface of the substrate 30.
【０００３】製造の際には、前述の第１および第２半導
体領域３１，３２を炭化珪素のエピタキシャル層で形成
してそのエピタキシャル成長時に不純物を途中から導入
して、第２半導体領域３２の表層部に第３半導体領域３
３を形成するとともに、ソース電極膜３８とコンタクト
をとるための領域に不純物を導入して所定領域にのみ第
３半導体領域３３を配置する。そして、第２半導体領域
３２を貫いて第１半導体領域３１に達するように溝３４
を堀り込み、溝３４内にゲート電極３６を嵌め込む。炭
化珪素は不純物の熱拡散が困難であるが、このようにす
ることにより、第１および第２半導体領域３１，３２に
対して後から不純物を拡散させずに第２半導体領域３２
を形成できる。In manufacturing, the first and second semiconductor regions 31 and 32 described above are formed of an epitaxial layer of silicon carbide, and impurities are introduced from the middle during the epitaxial growth to form a surface layer portion of the second semiconductor region 32. In the third semiconductor region 3
3 is formed, impurities are introduced into a region for making contact with the source electrode film 38, and the third semiconductor region 33 is arranged only in a predetermined region. Then, the groove 34 is formed so as to penetrate the second semiconductor region 32 and reach the first semiconductor region 31.
Is dug, and the gate electrode 36 is fitted into the groove 34. Although it is difficult for silicon carbide to diffuse impurities thermally, by doing so, the second semiconductor region 32 can be formed without diffusing impurities into the first and second semiconductor regions 31 and 32 later.
Can be formed.
【０００４】又、ゲート電極３６を溝３４内に埋め込ん
だ構造とし、溝３４の側面のゲート絶縁膜３４に接する
第２半導体領域３２の部分をチャネル形成面としてい
る。さらに、炭化珪素の許容最大電界強度が高い特長を
利用してその第１半導体領域３１内の電界強度を高く設
定することにより電界効果トランジスタの耐圧を向上す
るとともに、この電界強度の設定値に合わせて第１半導
体領域３１の厚さを最適化することにより電界効果トラ
ンジスタの順方向電圧の低減を可能にできるとしてい
る。Further, the gate electrode 36 is buried in the groove 34, and the portion of the second semiconductor region 32 in contact with the gate insulating film 34 on the side surface of the groove 34 is used as the channel formation surface. Further, the breakdown voltage of the field effect transistor is improved by setting the electric field strength in the first semiconductor region 31 to be high by utilizing the feature that silicon carbide has a high allowable maximum electric field strength, and the electric field strength is adjusted to the set value. By optimizing the thickness of the first semiconductor region 31, it is possible to reduce the forward voltage of the field effect transistor.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、図１１
に示すような溝ゲート型パワーＭＯＳＦＥＴを製造する
場合、チャネル形成面の不純物濃度は第２半導体領域３
２の不純物濃度と同じ濃度となっていた。パワーＭＯＳ
ＦＥＴを設計する上で第２半導体領域３２の不純物濃度
と膜厚はソース・ドレイン間の耐圧を決定する上での主
要な設計パラメータであり、一方チャネル形成面の不純
物濃度はゲートの閾値電圧とチャネルでのドロップ電圧
を決定する上での主要な設計パラメータである。パワー
ＭＯＳＦＥＴを高耐圧、低オン抵抗でかつ閾値電圧を小
さく設計するためには第２半導体領域３２とチャネル形
成面の不純物濃度を独立で制御できることがデバイス設
計上重要であるが、チャネル形成面と第２半導体領域３
２のキャリア濃度を従来の方法では独立に制御できない
という問題があった。However, as shown in FIG.
When manufacturing the trench gate type power MOSFET as shown in FIG. 3, the impurity concentration of the channel formation surface is set to the second semiconductor region 3
The concentration was the same as the impurity concentration of 2. Power MOS
In designing the FET, the impurity concentration and the film thickness of the second semiconductor region 32 are the main design parameters in determining the breakdown voltage between the source and the drain, while the impurity concentration on the channel formation surface is the threshold voltage of the gate. It is a major design parameter in determining the drop voltage in the channel. In order to design the power MOSFET with high withstand voltage, low on-resistance and small threshold voltage, it is important in device design to control the impurity concentration of the second semiconductor region 32 and the channel formation surface independently. Second semiconductor region 3
There is a problem that the carrier concentration of No. 2 cannot be controlled independently by the conventional method.
【０００６】又、前述の溝３４はドライエッチングによ
り形成される場合は、チャネル形成面にイオンエッチン
グによるダメージが生じＭＯＳ界面特性が劣化し、ＭＯ
Ｓスイッチング特性が劣化するという問題があった。When the groove 34 is formed by dry etching, the channel forming surface is damaged by ion etching and the MOS interface characteristics are deteriorated, resulting in MO
There is a problem that the S switching characteristic is deteriorated.
【０００７】そこで、この発明の目的は、高耐圧、低オ
ン抵抗でかつ閾値電圧を小さくでき、さらに、チャネル
形成面にイオンダメージや凹凸を低減することでＭＯＳ
界面特性を改善しスイッチング特性に優れた炭化珪素半
導体装置の製造方法を提供することにある。Therefore, an object of the present invention is to have a high withstand voltage, a low on-resistance, a small threshold voltage, and further reduce ion damage and irregularities on the channel formation surface to form a MOS.
An object of the present invention is to provide a method for manufacturing a silicon carbide semiconductor device having improved interface characteristics and excellent switching characteristics.
【０００８】[0008]
【課題を解決するための手段】請求項１に記載の発明
は、第１導電型の低抵抗半導体層と第１導電型の高抵抗
半導体層と第２導電型の第１の半導体層とを順に積層し
て単結晶炭化珪素よりなる半導体基板を形成するととも
に、前記第１の半導体層内の表層部の所定領域に第１導
電型の半導体領域を形成する第１工程と、前記半導体領
域と前記第１の半導体層を貫通し前記高抵抗半導体層に
達する溝を形成する第２工程と、前記溝の内壁における
少なくとも側面に、単結晶炭化珪素よりなる第２の半導
体層を形成する第３工程と、前記溝内における前記第２
の半導体層の表面にゲート酸化膜を形成する第４工程
と、前記溝内における前記ゲート酸化膜の表面にゲート
電極膜を形成する第５工程と、前記第１の半導体層の表
面と前記半導体領域の表面のうちの少なくとも前記半導
体領域の表面に第１の電極を形成するとともに、前記低
抵抗半導体層の表面に第２の電極を形成する第６工程と
を備えた炭化珪素半導体装置の製造方法をその要旨とす
る。According to a first aspect of the present invention, there is provided a first conductivity type low resistance semiconductor layer, a first conductivity type high resistance semiconductor layer, and a second conductivity type first semiconductor layer. A first step of forming a semiconductor substrate made of single-crystal silicon carbide by laminating in order, and forming a first conductivity type semiconductor region in a predetermined region of a surface layer portion in the first semiconductor layer; A second step of forming a groove penetrating the first semiconductor layer and reaching the high resistance semiconductor layer, and a third step of forming a second semiconductor layer made of single crystal silicon carbide on at least a side surface of the inner wall of the groove. Process and the second in the groove
A fourth step of forming a gate oxide film on the surface of the semiconductor layer, a fifth step of forming a gate electrode film on the surface of the gate oxide film in the trench, a surface of the first semiconductor layer and the semiconductor A sixth step of forming a first electrode on at least the surface of the semiconductor region among the surface of the region and forming a second electrode on the surface of the low resistance semiconductor layer. The method is the gist.
【０００９】請求項２に記載の発明は、請求項１に記載
の発明における前記半導体基板を構成する炭化珪素が六
方晶系であり、かつ表面の面方位が略（０００１）カー
ボン面である請求項１に記載の炭化珪素半導体装置の製
造方法をその要旨とする。According to a second aspect of the present invention, in the first aspect of the present invention, the silicon carbide forming the semiconductor substrate is a hexagonal crystal system, and the plane orientation of the surface is a (0001) carbon plane. The gist of the method is the method for manufacturing a silicon carbide semiconductor device according to Item 1.
【００１０】請求項３に記載の発明は、請求項１又は２
に記載の発明における前記第３工程は、前記第１の半導
体層および半導体領域の表面と前記溝の側面および底面
に第２の半導体層を形成するものであり、その後に、前
記溝の側面における前記第２の半導体層に比べ前記第１
の半導体層および半導体領域の表面と前記溝の底面にお
ける前記第２の半導体層を厚く熱酸化して前記溝の側面
にのみ前記第２の半導体層を残す工程を含む炭化珪素半
導体装置の製造方法をその要旨とする。[0010] The invention described in claim 3 is the invention according to claim 1 or 2.
In the third step of the invention described in (1) above, the second semiconductor layer is formed on the surface of the first semiconductor layer and the semiconductor region and the side surface and the bottom surface of the groove, and then on the side surface of the groove. Compared to the second semiconductor layer, the first semiconductor layer
Of the semiconductor layer and the semiconductor region and the bottom surface of the groove, the second semiconductor layer being thickly thermally oxidized to leave the second semiconductor layer only on the side surface of the groove. Is the gist.
【００１１】請求項４に記載の発明は、請求項１〜３の
いずれか１項に記載の発明における前記第３工程は、前
記第２の半導体層をエピタキシャル成長法により形成す
る炭化珪素半導体装置の製造方法をその要旨とする。According to a fourth aspect of the present invention, in the third step of the invention according to any one of the first to third aspects, the silicon carbide semiconductor device in which the second semiconductor layer is formed by an epitaxial growth method is used. The manufacturing method is the gist.
【００１２】請求項５に記載の発明は、請求項１〜４の
いずれか１項に記載の発明における前記第１工程は、前
記半導体領域をエピタキシャル成長法にて形成する炭化
珪素半導体装置の製造方法をその要旨とする。According to a fifth aspect of the invention, in the first step of the invention according to any one of the first to fourth aspects, the method for manufacturing a silicon carbide semiconductor device comprises forming the semiconductor region by an epitaxial growth method. Is the gist.
【００１３】請求項６に記載の発明は、請求項１〜４の
いずれか１項に記載の発明における前記第２工程は、前
記溝の内壁における底面に比べ側面が薄い酸化膜を形成
および除去する工程を含む炭化珪素半導体装置の製造方
法をその要旨とする。According to a sixth aspect of the present invention, in the second step of the invention according to any one of the first to fourth aspects, an oxide film whose side surface is thinner than a bottom surface of the inner wall of the groove is formed and removed. The gist is a method of manufacturing a silicon carbide semiconductor device including the steps of:
【００１４】請求項７に記載の発明は、請求項１〜４の
いずれか１項に記載の発明における前記第２工程は、ド
ライエッチングにより前記溝を形成するとともに、溝の
内壁における底面に比べ側面が薄い酸化膜を形成および
除去する工程を含む炭化珪素半導体装置の製造方法をそ
の要旨とする。According to a seventh aspect of the present invention, in the second step of the invention according to any one of the first to fourth aspects, the groove is formed by dry etching, and the second step is different from the bottom surface of the inner wall of the groove. The gist is a method of manufacturing a silicon carbide semiconductor device including a step of forming and removing an oxide film having a thin side surface.
【００１５】請求項８に記載の発明は、請求項１〜４の
いずれか１項に記載の発明における前記第３工程は、異
方性エピタキシャル成長法により前記溝の内壁において
底面に比べ側面が厚い前記第２の半導体層を形成する炭
化珪素半導体装置の製造方法をその要旨とする。According to an eighth aspect of the present invention, in the third step in the invention according to any one of the first to fourth aspects, the side surface of the inner wall of the groove is thicker than the bottom surface by an anisotropic epitaxial growth method. The gist is a method of manufacturing a silicon carbide semiconductor device for forming the second semiconductor layer.
【００１６】請求項９に記載の発明は、請求項１〜４の
いずれか１項に記載の発明における前記第４工程は、異
方性熱酸化法により前記溝の内壁における底面に比べ側
面が薄い前記ゲート酸化膜を形成する炭化珪素半導体装
置の製造方法をその要旨とする。 （作用）請求項１に記載の発明によれば、第１工程によ
り、第１導電型の低抵抗半導体層と第１導電型の高抵抗
半導体層と第２導電型の第１の半導体層とを順に積層し
て単結晶炭化珪素よりなる半導体基板が形成されるとと
もに、第１の半導体層内の表層部の所定領域に第１導電
型の半導体領域が形成される。そして、第２工程により
半導体領域と第１の半導体層を貫通し高抵抗半導体層に
達する溝が形成され、第３工程により、溝の内壁におけ
る少なくとも側面に、単結晶炭化珪素よりなる第２の半
導体層が形成される。さらに、第４工程により溝内にお
ける第２の半導体層の表面にゲート酸化膜が形成され、
第５工程により溝内におけるゲート酸化膜の表面にゲー
ト電極膜が形成される。第６工程により、第１の半導体
層の表面と半導体領域の表面のうちの少なくとも半導体
領域の表面に第１の電極が形成されるとともに、低抵抗
半導体層の表面に第２の電極が形成される。The invention according to claim 9 is characterized in that in the fourth step in the invention according to any one of claims 1 to 4, a side surface is formed by an anisotropic thermal oxidation method as compared with a bottom surface of an inner wall of the groove. The gist is a method of manufacturing a silicon carbide semiconductor device in which the thin gate oxide film is formed. (Operation) According to the invention described in claim 1, the first conductive type low resistance semiconductor layer, the first conductive type high resistance semiconductor layer, and the second conductive type first semiconductor layer are formed by the first step. Are sequentially laminated to form a semiconductor substrate made of single crystal silicon carbide, and a first conductivity type semiconductor region is formed in a predetermined region of the surface layer portion in the first semiconductor layer. Then, in the second step, a groove that penetrates the semiconductor region and the first semiconductor layer and reaches the high resistance semiconductor layer is formed, and in the third step, at least a side surface of the inner wall of the groove is formed of a second single crystal silicon carbide. A semiconductor layer is formed. Further, a gate oxide film is formed on the surface of the second semiconductor layer in the groove by the fourth step,
By the fifth step, a gate electrode film is formed on the surface of the gate oxide film in the groove. By the sixth step, the first electrode is formed on at least the surface of the semiconductor region among the surface of the first semiconductor layer and the surface of the semiconductor region, and the second electrode is formed on the surface of the low resistance semiconductor layer. It
【００１７】このように、第１工程における高抵抗半導
体層および第１の半導体層の形成と、第３工程における
第２の半導体層の形成とが、独立に行われる。よって、
チャネルを形成する第２の半導体層の不純物濃度を、ソ
ース・ドレイン間耐圧を設計するのに必要な高抵抗半導
体層と第１の半導体層の不純物濃度に対して独立に設計
でき任意な値とすることができる。その結果、チャネル
移動度の不純物散乱を抑えることでチャネル部でのドロ
ップ電圧を小さくし、かつ閾電圧が低い高耐圧低損失パ
ワーＭＯＳＦＥＴを得ることができる。As described above, the formation of the high resistance semiconductor layer and the first semiconductor layer in the first step and the formation of the second semiconductor layer in the third step are performed independently. Therefore,
The impurity concentration of the second semiconductor layer forming the channel can be designed independently with respect to the impurity concentrations of the high resistance semiconductor layer and the first semiconductor layer necessary for designing the breakdown voltage between the source and the drain, and can be set to an arbitrary value. can do. As a result, it is possible to obtain a high-breakdown-voltage low-loss power MOSFET having a low drop voltage in the channel portion and a low threshold voltage by suppressing the impurity scattering of the channel mobility.
【００１８】又、第３工程において溝内に第２の半導体
層が形成されるので、この第２の半導体層においてはイ
オンダメージの無い半導体層が配置できる。よって、チ
ャネル形成面にイオンダメージや凹凸を低減することで
ＭＯＳ界面特性が改善されスイッチング特性に優れた炭
化珪素半導体装置が製造される。Further, since the second semiconductor layer is formed in the groove in the third step, a semiconductor layer free from ion damage can be arranged in this second semiconductor layer. Therefore, a silicon carbide semiconductor device having improved MOS interface characteristics and excellent switching characteristics can be manufactured by reducing ion damage and unevenness on the channel formation surface.
【００１９】請求項２に記載の発明によれば、請求項１
に記載の発明の作用に加え、半導体基板を構成する炭化
珪素が六方晶系であり、かつ表面の面方位が略（０００
１）カーボン面となっており、その他の面に対して化学
反応性の高い面を表面としたので、プロセス温度を下げ
ることが可能で、またプロセス時間を短くできる。According to the second aspect of the present invention, the first aspect is provided.
In addition to the effect of the invention described in (3), the silicon carbide forming the semiconductor substrate is a hexagonal system, and the surface orientation of the surface is approximately (000
1) Since it is a carbon surface and has a surface having high chemical reactivity with other surfaces, the process temperature can be lowered and the process time can be shortened.
【００２０】請求項３に記載の発明によれば、請求項１
又は２に記載の発明の作用に加え、第３工程において、
第１の半導体層および半導体領域の表面と溝の側面およ
び底面に第２の半導体層が形成され、その後に、溝の側
面における第２の半導体層に比べ第１の半導体層および
半導体領域の表面と溝の底面における第２の半導体層が
厚く熱酸化されて溝の側面にのみ第２の半導体層が残さ
れる。つまり、溝側面の酸化膜は薄く、基板表面、溝底
面の酸化膜は厚くできる。このことは図９に示すように
本発明者らの実験により明らかにされたＳｉＣ酸化異方
性の発見に基づく。この異方酸化工程により第２の半導
体層の除去を最小限に抑えて、基板表面と溝底面の不必
要な第２の半導体層を取り除くことが可能となる。According to the invention of claim 3, according to claim 1,
Or in addition to the function of the invention described in 2, in the third step,
A second semiconductor layer is formed on the surfaces of the first semiconductor layer and the semiconductor region, and on the side surfaces and the bottom surface of the groove, and thereafter, the surfaces of the first semiconductor layer and the semiconductor area on the side surface of the groove as compared with the second semiconductor layer. The second semiconductor layer on the bottom surface of the groove is thickly thermally oxidized, and the second semiconductor layer is left only on the side surface of the groove. That is, the oxide film on the side surface of the groove can be thin, and the oxide film on the substrate surface and the bottom surface of the groove can be thick. This is based on the discovery of SiC oxidation anisotropy revealed by the experiments of the present inventors as shown in FIG. By this anisotropic oxidation step, the removal of the second semiconductor layer can be minimized, and the unnecessary second semiconductor layer on the substrate surface and the groove bottom surface can be removed.
【００２１】請求項４に記載の発明によれば、請求項１
〜３のいずれか１項に記載の発明の作用に加え、第３工
程において、第２の半導体層がエピタキシャル成長法に
より形成される。よって、溝の側面に一様に第２の半導
体層を高品位に形成できる。この方法により得られた第
２の半導体層は移動度がその他の層の不純物の影響を受
けず移動度が大きい。According to the invention of claim 4, claim 1
In addition to the effect of the invention described in any one of to 3, the second semiconductor layer is formed by the epitaxial growth method in the third step. Therefore, the second semiconductor layer can be uniformly formed on the side surface of the groove with high quality. The mobility of the second semiconductor layer obtained by this method is high without being affected by impurities in the other layers.
【００２２】請求項５に記載の発明によれば、請求項１
〜４のいずれか１項に記載の発明の作用に加え、第１工
程において、半導体領域がエピタキシャル成長法にて形
成される。よって、厚いソース領域を形成することがで
き、また低抵抗なソース領域をエピタキシャル成長法に
より形成することができる。According to the invention of claim 5, claim 1
In addition to the effect of the invention described in any one of to 4, the semiconductor region is formed by the epitaxial growth method in the first step. Therefore, a thick source region can be formed and a low resistance source region can be formed by an epitaxial growth method.
【００２３】請求項６に記載の発明によれば、請求項１
〜４のいずれか１項に記載の発明の作用に加え、第２工
程において、溝の内壁における底面に比べ側面が薄い酸
化膜が形成および除去される。よって、局所異方性熱酸
化法により相対的に薄い酸化膜が形成され、溝内壁にイ
オンダメージの無い溝を形成することで、この溝側面に
形成する第２の半導体層を高品位に形成でき、この第２
の半導体層に形成されるＭＯＳ界面は良好なものとな
る。According to the invention of claim 6, claim 1
In addition to the effect of the invention described in any one of 1 to 4, in the second step, an oxide film whose side surface is thinner than the bottom surface of the inner wall of the groove is formed and removed. Therefore, a relatively thin oxide film is formed by the local anisotropic thermal oxidation method, and a groove without ion damage is formed on the inner wall of the groove, so that the second semiconductor layer formed on the side surface of the groove is formed with high quality. Yes, this second
The MOS interface formed in the semiconductor layer is excellent.
【００２４】請求項７に記載の発明によれば、請求項１
〜４のいずれか１項に記載の発明の作用に加え、第２工
程において、ドライエッチングにより溝が形成されると
ともに、溝の内壁における底面に比べ側面が薄い酸化膜
が形成および除去される。よって、溝側面に形成する第
２の半導体層を高品位に形成でき、この第２の半導体層
に形成されるＭＯＳ界面は良好なものとなる。According to the invention of claim 7, claim 1
In addition to the effect of the invention described in any one of to 4, in the second step, a groove is formed by dry etching, and an oxide film whose side surface is thinner than the bottom surface of the inner wall of the groove is formed and removed. Therefore, the second semiconductor layer formed on the side surface of the groove can be formed with high quality, and the MOS interface formed on the second semiconductor layer becomes favorable.
【００２５】請求項８に記載の発明によれば、請求項１
〜４のいずれか１項に記載の発明の作用に加え、第３工
程は、異方性エピタキシャル成長法により溝の内壁にお
いて底面に比べ側面が厚い第２の半導体層が形成され
る。つまり、異方性エピタキシャル成長法により第２の
半導体層を形成することで、溝側面にホモエピタキシャ
ル成長でき、かつ溝側面のエピタキシャル層の厚さを基
板表面及び溝底面のエピタキシャル層の厚さに対して１
０倍以上厚く成長できる。このことは図１０に示すよう
に本発明者らの実験により明らかにされた炭化珪素のエ
ピタキシャル成長速度の発見に基づく。According to the invention described in claim 8, according to claim 1,
In addition to the effect of the invention described in any one of to 4, the second semiconductor layer having a thicker side surface than the bottom surface on the inner wall of the groove is formed in the third step by the anisotropic epitaxial growth method. That is, by forming the second semiconductor layer by the anisotropic epitaxial growth method, homoepitaxial growth can be performed on the groove side surface, and the thickness of the epitaxial layer on the groove side surface can be compared with the thickness of the epitaxial layer on the substrate surface and the groove bottom surface. 1
It can grow thicker than 0 times. This is based on the discovery of the epitaxial growth rate of silicon carbide revealed by the experiments of the present inventors as shown in FIG.
【００２６】請求項９に記載の発明によれば、請求項１
〜４のいずれか１項に記載の発明の作用に加え、第４工
程において異方性熱酸化法により溝の内壁における底面
に比べ側面が薄いゲート酸化膜が形成される。つまり、
ゲート酸化膜を熱酸化法により形成することによりＭＯ
Ｓゲート構造とすることができる。この方法では側面の
酸化膜を選択的に薄くでき、基板表面、溝底面のフィー
ルド酸化膜は厚くできる。よって、チャネルを形成する
部位のみに薄い酸化膜を形成できる。According to the invention of claim 9, according to claim 1,
In addition to the effect of the invention described in any one of 1 to 4, in the fourth step, an anisotropic thermal oxidation method is used to form a gate oxide film whose side surface is thinner than the bottom surface of the inner wall of the groove. That is,
By forming the gate oxide film by the thermal oxidation method, MO
It can have an S-gate structure. According to this method, the oxide film on the side surface can be selectively thinned, and the field oxide film on the substrate surface and the groove bottom surface can be thickened. Therefore, a thin oxide film can be formed only on the part where the channel is formed.
【００２７】[0027]
【発明の実施の形態】以下、この発明を具体化した実施
の形態を図面に従って説明する。図１に、本実施の形態
における溝ゲート型パワーＭＯＳＦＥＴ（縦型パワーＭ
ＯＳＦＥＴ）の断面図を示す。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a trench gate power MOSFET (vertical power M
OSFET) is shown.
【００２８】図２から図８に従って製造工程を説明す
る。まず、図２に示すように、低抵抗半導体層としての
ｎ+ 型単結晶ＳｉＣ基板１を用意する。このｎ+ 型単結
晶ＳｉＣ基板１は、六方晶系であり、かつ表面の面方位
が略（０００１）カーボン面となっている。そして、そ
のｎ+ 型単結晶ＳｉＣ基板１の表面に、高抵抗半導体層
としてのｎ型エピタキシャル層２と第１の半導体層とし
てのｐ型エピタキシャル層３とを順に積層する。ｎ型エ
ピタキシャル層２は、キャリア密度が１×１０16ｃｍ-3
程度で、厚さが１０μｍ程度である。又、ｐ型エピタキ
シャル層３は、キャリア密度が１×１０17ｃｍ-3程度
で、厚さが２μｍ程度である。The manufacturing process will be described with reference to FIGS. First, as shown in FIG. 2, an n + type single crystal SiC substrate 1 as a low resistance semiconductor layer is prepared. This n + type single crystal SiC substrate 1 is a hexagonal crystal system, and the surface plane orientation is a (0001) carbon surface. Then, on the surface of the n + type single crystal SiC substrate 1, an n type epitaxial layer 2 as a high resistance semiconductor layer and a p type epitaxial layer 3 as a first semiconductor layer are sequentially laminated. The n-type epitaxial layer 2 has a carrier density of 1 × 10 16 cm −3.
The thickness is about 10 μm. The p-type epitaxial layer 3 has a carrier density of about 1 × 10 17 cm −3 and a thickness of about 2 μm.
【００２９】このようにして、ｎ+ 型単結晶ＳｉＣ基板
１、ｎ型エピタキシャル層２及びｐ型エピタキシャル層
３とからなる半導体基板４を形成する。続いて、図３に
示すように、ｐ型エピタキシャル層３に対しマスク材５
を用いてイオン注入法によりｐ型エピタキシャル層３の
表層部の所定領域に半導体領域としてのｎ+ ソース領域
６を形成する。ｎ+ ソース領域６は、表面のキャリア濃
度が１×１０19ｃｍ-3程度で、接合深さが０．５μｍ程
度である。Thus, the semiconductor substrate 4 composed of the n + type single crystal SiC substrate 1, the n type epitaxial layer 2 and the p type epitaxial layer 3 is formed. Then, as shown in FIG. 3, a mask material 5 is applied to the p-type epitaxial layer 3.
Is used to form an n + source region 6 as a semiconductor region in a predetermined region of the surface layer portion of the p-type epitaxial layer 3 by ion implantation. The n + source region 6 has a carrier concentration on the surface of about 1 × 10 19 cm −3 and a junction depth of about 0.5 μm.
【００３０】この際、ｎ+ ソース領域６がイオン注入法
にて形成されるので、ｎ+ ソース領域６をｐ型エピタキ
シャル層３の任意の箇所に形成することができ、ｐ型エ
ピタキシャル層３（すなわちボディー層）とソース領域
６の各表面の面積割合を自由に設計できる。At this time, since the n + source region 6 is formed by the ion implantation method, the n + source region 6 can be formed at an arbitrary position of the p type epitaxial layer 3 and the p type epitaxial layer 3 ( That is, the area ratio of each surface of the body layer) and the source region 6 can be freely designed.
【００３１】次に、図４に示すように、マスク材７，８
を用いてドライエッチングにより半導体基板４の表面か
らｎ+ ソース領域６とｐ型エピタキシャル層３を貫通し
ｎ型エピタキシャル層２に達する溝９を形成する。この
溝９は、幅が例えば２μｍで、深さが例えば２μｍであ
る。又、溝９の内壁は側面９ａと底面９ｂとを有してい
る。Next, as shown in FIG. 4, mask materials 7 and 8 are formed.
A groove 9 penetrating the n + source region 6 and the p-type epitaxial layer 3 from the surface of the semiconductor substrate 4 to reach the n-type epitaxial layer 2 is formed by dry etching using. The groove 9 has a width of, for example, 2 μm and a depth of, for example, 2 μm. The inner wall of the groove 9 has a side surface 9a and a bottom surface 9b.
【００３２】そして、図５に示すように、マスク材７を
耐酸化マスクとして使用し、例えば１１００℃の熱酸化
法により例えば５時間程度の熱酸化を行い、溝９の内壁
に熱酸化膜１０を形成する。ここで、溝９の側面９ａに
おいては１００ｎｍ程度の酸化膜１０ａが形成されると
ともに、溝９の底面９ｂにおいては５００ｎｍ程度の酸
化膜１０ｂが形成される。さらに、熱酸化膜１０とマス
ク材７をエッチング除去する。Then, as shown in FIG. 5, the mask material 7 is used as an oxidation resistant mask, and thermal oxidation is performed for about 5 hours, for example, by a thermal oxidation method at 1100 ° C., and the thermal oxide film 10 is formed on the inner wall of the groove 9. To form. Here, an oxide film 10a of about 100 nm is formed on the side surface 9a of the groove 9, and an oxide film 10b of about 500 nm is formed on the bottom surface 9b of the groove 9. Further, the thermal oxide film 10 and the mask material 7 are removed by etching.
【００３３】引き続き、図６に示すように、ＣＶＤ法に
よるエピタキシャル成長により溝９の内壁とｎ+ ソース
領域６およびｐ型エピタキシャル層３の表面に、第２の
半導体層としてのエピタキシャル層１１を形成する。こ
のエピタキシャル成長により溝９の側面９ａには、厚さ
が例えば１００ｎｍ程度のエピタキシャル層１１ａが、
溝９の底面９ｂには、厚さが例えば１０ｎｍ程度のエピ
タキシャル層１１ｂが、基板表面には厚さが１０ｎｍ程
度のエピタキシャル層１１ｃが形成される。Subsequently, as shown in FIG. 6, an epitaxial layer 11 as a second semiconductor layer is formed on the inner wall of the trench 9, the n + source region 6 and the surface of the p-type epitaxial layer 3 by epitaxial growth by the CVD method. . By this epitaxial growth, an epitaxial layer 11a having a thickness of, for example, about 100 nm is formed on the side surface 9a of the groove 9.
An epitaxial layer 11b having a thickness of, for example, about 10 nm is formed on the bottom surface 9b of the groove 9, and an epitaxial layer 11c having a thickness of about 10 nm is formed on the surface of the substrate.
【００３４】このエピタキシャル層１１は任意の不純物
濃度にコントロールされる。より具体的には、ＳｉＨ4
ガスとＣ3 Ｈ8 とを原料ガスとして流しながらＣＶＤ法
により炭化珪素を気相成長する際にＮ2 ガス（又はトリ
メチルアルミニウムガス）の供給量を調整することによ
りエピタキシャル層１１の不純物濃度を１０15〜１０ 17
／ｃｍ3 で調整する。この際、不純物濃度を低くするこ
とができる。The epitaxial layer 11 is made of any impurities.
Controlled by concentration. More specifically, SiHFour
Gas and CThreeH8And CVD as a source gas
During the vapor phase growth of silicon carbide by N2Gas (or bird
Methyl aluminum gas)
The impurity concentration of the epitaxial layer 11 is set to 10Fifteen-10 17
/ CmThreeAdjust with. At this time, reduce the impurity concentration.
Can be.
【００３５】ここで、厚さが異なるエピタキシャル層１
１が形成されることは実験的に分かっている。これを図
１０を示す。図１０は溝における側面および底面を含む
領域でのＦＥ−ＳＥＭ像のスケッチを示す。このように
炭化珪素のエピタキシャル成長速度の違いにより、溝側
面にホモエピタキシャル成長でき、かつ溝側面のエピタ
キシャル層の厚さを基板表面及び溝底面のエピタキシャ
ル層の厚さに対して１０倍以上厚くホモエピタキシャル
層を成長できる。よって、エピタキシャル層１１がチャ
ネル形成領域となるが、チャネルのドロップ電圧を小さ
くでき、また歩留りよく形成でき、低損失で歩留りが高
い装置を製造できる。Here, the epitaxial layers 1 having different thicknesses
It is experimentally known that 1 is formed. This is shown in FIG. FIG. 10 shows a sketch of an FE-SEM image in a region including a side surface and a bottom surface in the groove. Due to the difference in the epitaxial growth rate of silicon carbide, homoepitaxial growth can be performed on the groove side surface, and the thickness of the epitaxial layer on the groove side surface is 10 times or more the thickness of the epitaxial layer on the substrate surface and the groove bottom surface. Can grow. Therefore, although the epitaxial layer 11 serves as a channel forming region, the channel drop voltage can be reduced, the device can be formed with high yield, and a device with low loss and high yield can be manufactured.
【００３６】又、前述したように熱酸化膜１０を形成お
よび除去することにより（局所異方性熱酸化法にて相対
的に薄い酸化膜１０を形成および除去することによ
り）、溝９の内壁にイオンダメージの無い溝が形成され
ているので、この溝側面に形成するエピタキシャル層１
１を高品位に形成でき、このエピタキシャル層１１に形
成されるＭＯＳ界面は良好なものとなり、スイッチング
特性に優れた装置を製造することができる。Further, as described above, by forming and removing the thermal oxide film 10 (by forming and removing the relatively thin oxide film 10 by the local anisotropic thermal oxidation method), the inner wall of the groove 9 is formed. Since a groove without ion damage is formed in the epitaxial layer 1, the epitaxial layer 1 formed on the side surface of the groove is
1 can be formed in high quality, the MOS interface formed in this epitaxial layer 11 becomes good, and a device having excellent switching characteristics can be manufactured.
【００３７】次に、図７に示すように、例えば１１００
℃の異方性熱酸化法により５時間程度の熱酸化を行い、
エピタキシャル層１１の表面にゲート熱酸化膜１２を形
成する。この熱酸化により溝９の側面９ａに位置するエ
ピタキシャル層１１ａにおいてはその表面に厚さが５０
ｎｍ程度の薄いゲート熱酸化膜１２ａが形成される。
又、溝９の底面９ｂにおけるエピタキシャル層１１ｂは
酸化され酸化膜に変化し厚さが５００ｎｍ程度の厚いゲ
ート熱酸化膜１２ｂが形成される。さらに、ｎ+ソース
領域６上およびｐ型エピタキシャル層３上におけるエピ
タキシャル層１１ｃは酸化膜に変化し厚さが５００ｎｍ
程度の厚いゲート熱酸化膜１２ｃが形成される。Next, as shown in FIG. 7, for example, 1100
Approximately 5 hours of thermal oxidation by anisotropic thermal oxidation at ℃
A gate thermal oxide film 12 is formed on the surface of the epitaxial layer 11. Due to this thermal oxidation, the epitaxial layer 11a located on the side surface 9a of the groove 9 has a thickness of 50.
A thin gate thermal oxide film 12a having a thickness of about nm is formed.
Further, the epitaxial layer 11b on the bottom surface 9b of the groove 9 is oxidized and converted into an oxide film, and a thick gate thermal oxide film 12b having a thickness of about 500 nm is formed. Further, the epitaxial layer 11c on the n + source region 6 and the p-type epitaxial layer 3 is changed to an oxide film and has a thickness of 500 nm.
A thick gate thermal oxide film 12c is formed.
【００３８】ここで、厚さが異なる熱酸化膜１２が形成
されることは実験的に分かっている。つまり、図９に示
すように、（０００１）カーボン面と角度θをなす斜状
面とを有する炭化珪素を用いて熱酸化膜の厚さを測定し
た。その結果、（０００１）カーボン面に比べ、θ＝９
０°である面｛（１１２バー０）面｝において膜厚が薄
くなる。この異方酸化工程によりエピタキシャル層１１
の除去を最小限に抑えて、基板表面と溝底面の不必要な
エピタキシャル層１１を取り除くことが可能となる。よ
って、一度の熱酸化にて簡便かつ歩留まりよく溝側面だ
けにエピタキシャル層１１を形成することができ、安価
に歩留まりよく製造することができる。Here, it has been experimentally known that the thermal oxide films 12 having different thicknesses are formed. That is, as shown in FIG. 9, the thickness of the thermal oxide film was measured using silicon carbide having a (0001) carbon surface and an inclined surface forming an angle θ. As a result, compared with the (0001) carbon surface, θ = 9
The film thickness becomes thin on the surface {(112 bar 0) surface} which is 0 °. By this anisotropic oxidation process, the epitaxial layer 11
It is possible to remove unnecessary unnecessary epitaxial layer 11 on the substrate surface and the groove bottom surface. Therefore, the epitaxial layer 11 can be formed only on the side surface of the groove easily and with a high yield by one thermal oxidation, and the manufacturing can be performed at a low cost and with a high yield.
【００３９】続いて、図８に示すように、溝９内を、ゲ
ート電極膜としての第１ポリシリコン膜１３ａ及び第２
ポリシリコン膜１３ｂにより順次埋め戻す。その結果、
溝９内におけるゲート熱酸化膜１２の内側に第１および
第２ポリシリコン膜１３ａ，１３ｂが配置される。ここ
で、第１および第２ポリシリコン膜１３ａ，１３ｂはｎ
+ ソース領域６上のゲート熱酸化膜１２ｃ上に形成され
てもよい。Subsequently, as shown in FIG. 8, the inside of the trench 9 is covered with the first polysilicon film 13a and the second polysilicon film 13a as gate electrode films.
The polysilicon film 13b is sequentially backfilled. as a result,
First and second polysilicon films 13 a and 13 b are arranged inside gate thermal oxide film 12 in trench 9. Here, the first and second polysilicon films 13a and 13b are n
It may be formed on the gate thermal oxide film 12c on the + source region 6.
【００４０】しかる後、図１に示すように、第１及び第
２ポリシリコン膜１３ａ，１３ｂ上を含めたゲート熱酸
化膜１２ｃ上に、ＣＶＤ法により層間絶縁層１４を形成
し、ソースコンタクト予定位置のｎ+ ソース領域６とｐ
型エピタキシャル層３の表面上にあるゲート熱酸化膜１
２ｃと層間絶縁層１４とを除去する。その後、ｎ+ ソー
ス領域６とｐ型エピタキシャル層３及び層間絶縁層１４
上に第１の電極としてのソース電極膜１５を形成すると
ともに、半導体基板４の裏面（ｎ+ 型単結晶ＳｉＣ基板
１の表面）に第２の電極としてのドレイン電極膜１６を
形成し、パワーＭＯＳＦＥＴを完成する。Thereafter, as shown in FIG. 1, an interlayer insulating layer 14 is formed by a CVD method on the gate thermal oxide film 12c including the first and second polysilicon films 13a and 13b, and a source contact is planned. Position n + source region 6 and p
Thermal oxide film 1 on the surface of the epitaxial layer 3
2c and the interlayer insulating layer 14 are removed. After that, the n + source region 6, the p-type epitaxial layer 3 and the interlayer insulating layer 14 are formed.
A source electrode film 15 as a first electrode is formed on the upper surface, and a drain electrode film 16 as a second electrode is formed on the back surface of the semiconductor substrate 4 (front surface of the n + -type single crystal SiC substrate 1). Complete the MOSFET.
【００４１】このように、本実施の形態では、炭化珪素
よりなる半導体基板４を用いてチャネルを形成するエピ
タキシャル層１１の不純物濃度をソース・ドレイン間耐
圧を設計するのに必要なｎ型エピタキシャル層２とｐ型
エピタキシャル層３の不純物濃度とは独立に任意に設計
することができるのでチャネル移動度の不純物散乱を抑
えることでチャネル部でのドロップ電圧を小さくし、か
つ低い閾電圧の高耐圧低損失パワーＭＯＳＦＥＴを製造
することができる。As described above, in the present embodiment, the impurity concentration of the epitaxial layer 11 forming the channel using the semiconductor substrate 4 made of silicon carbide is set to the n-type epitaxial layer necessary for designing the source-drain breakdown voltage. 2 and the impurity concentration of the p-type epitaxial layer 3 can be designed independently of each other, so that the drop voltage in the channel portion can be reduced by suppressing the impurity scattering of the channel mobility, and the high withstand voltage and low with a low threshold voltage. A loss power MOSFET can be manufactured.
【００４２】又、溝９内にエピタキシャル層１１が形成
されるので、このエピタキシャル層１１においてはイオ
ンダメージの無い半導体層が配置できる。よって、チャ
ネル形成面にイオンダメージや凹凸を低減することでＭ
ＯＳ界面特性が改善されスイッチング特性に優れた炭化
珪素半導体装置が製造できる。Since the epitaxial layer 11 is formed in the groove 9, a semiconductor layer without ion damage can be arranged in the epitaxial layer 11. Therefore, by reducing ion damage and unevenness on the channel formation surface, M
A silicon carbide semiconductor device having improved OS interface characteristics and excellent switching characteristics can be manufactured.
【００４３】又、半導体基板４を構成する炭化珪素が六
方晶系であり、かつ表面の面方位が略（０００１）カー
ボン面であるので、その他の面に対して化学反応性の高
い面を表面とでき、プロセス温度を下げ、プロセス時間
を短くできる。よって、安価なるデバイスとすることが
できる。Further, since the silicon carbide forming the semiconductor substrate 4 is a hexagonal system and the surface orientation of the surface is a (0001) carbon surface, the surface having a high chemical reactivity with the other surface is the surface. Therefore, the process temperature can be lowered and the process time can be shortened. Therefore, an inexpensive device can be obtained.
【００４４】又、チャネルを形成する第２の半導体層
（エピタキシャル層１１）をエピタキシャル成長にて形
成したので、溝９の側面に一様に第２の半導体層（エピ
タキシャル層１１）を高品位に形成できる。この方法に
より得られた第２の半導体層（エピタキシャル層１１）
は移動度がその他の層の不純物の影響を受けず移動度が
大きいという特長を有し、このエピタキシャル層１１に
形成したチャネルでのドロップ電圧を小さくでき、低損
失に製造することができる。さらに、異方性エピタキシ
ャル成長により低不純物濃度で形成したので、チャネル
の移動度が大きいチャネルを形成することができ、チャ
ネル部でのドロップ電圧を小さくできる。このように、
炭化珪素よりなる高耐圧低損失パワーＭＯＳＦＥＴをよ
り低損失に歩留まりよく製造することができる。Further, since the second semiconductor layer (epitaxial layer 11) forming the channel is formed by epitaxial growth, the second semiconductor layer (epitaxial layer 11) is uniformly formed on the side surface of the groove 9 with high quality. it can. Second semiconductor layer (epitaxial layer 11) obtained by this method
Has a characteristic that the mobility is large without being affected by impurities in other layers, and the drop voltage in the channel formed in the epitaxial layer 11 can be made small, so that it can be manufactured with low loss. Furthermore, since the film is formed by anisotropic epitaxial growth with a low impurity concentration, it is possible to form a channel having high channel mobility and reduce the drop voltage in the channel portion. in this way,
A high breakdown voltage and low loss power MOSFET made of silicon carbide can be manufactured with lower loss and high yield.
【００４５】又、ドライエッチングにより溝９が形成さ
れるので、溝９を微細に深く、垂直に近く形成でき、溝
９の側面９ａに形成されるエピタキシャル層１１の表面
積を増やすことで単位面積当たりのチャネル幅の総計を
大きくできチャネル部でのドロップ電圧を小さくするこ
とができ、より低損失化した装置を製造することができ
る。Further, since the groove 9 is formed by dry etching, the groove 9 can be formed finely deep and nearly vertical, and by increasing the surface area of the epitaxial layer 11 formed on the side surface 9a of the groove 9, the unit area per unit area is increased. The total channel width can be increased, the drop voltage in the channel portion can be decreased, and a device with lower loss can be manufactured.
【００４６】又、ゲート電極膜はポリシリコン膜よりな
るので、溝内壁に歩留まりよくゲート電極膜を形成で
き、高耐圧低損失の装置を歩留まり良く製造できる。
尚、本実施例では、六方晶系炭化珪素についてのみ説明
したが、他の結晶系（例えば立方晶系）の炭化珪素につ
いても同じ効果が得られる。Further, since the gate electrode film is made of a polysilicon film, the gate electrode film can be formed on the inner wall of the groove with a good yield, and a device with high breakdown voltage and low loss can be manufactured with a good yield.
In the present embodiment, only hexagonal system silicon carbide has been described, but the same effect can be obtained with other crystal system (eg, cubic system) silicon carbide.
【００４７】又、ｐ／ｎ／ｎ+ 構造の基板についてのみ
説明したが、半導体型のｎとｐを入れ換えた構造でも同
じ効果が得られることは言うまでもない。さらに、図７
に示すように、エピタキシャル層１１を形成した後に、
熱酸化膜１１を形成して溝９の側面にのみエピタキシャ
ル層１１を残すとともに、溝９の内壁における底面９ｂ
に比べ側面９ａが薄いゲート酸化膜を配置したが、エピ
タキシャル層１１を形成した後に、熱酸化膜を形成し、
溝９の側面にのみエピタキシャル層１１を残した後にこ
の酸化膜を除去する第１の熱酸化膜形成工程と、その後
において、熱酸化膜を形成し、溝９の内壁における底面
９ｂに比べ側面９ａが薄いゲート酸化膜を形成する第２
の熱酸化膜形成工程としてもよい。この第１の熱酸化膜
形成工程においては基板表面の不必要な第２の半導体層
を１回の酸化にて除去できる。又、第２の熱酸化膜形成
工程においては、異方性熱酸化法により側面の酸化膜を
選択的に薄くでき、基板表面、溝底面のフィールド酸化
膜は厚くでき、チャネルを形成する部位のみに薄い酸化
膜を形成できる。Although only the substrate having the p / n / n + structure has been described, it goes without saying that the same effect can be obtained even if the semiconductor type n and p are interchanged. Furthermore, FIG.
As shown in, after forming the epitaxial layer 11,
The thermal oxide film 11 is formed to leave the epitaxial layer 11 only on the side surface of the groove 9, and the bottom surface 9b on the inner wall of the groove 9 is formed.
Although a gate oxide film having a thinner side surface 9a than the above is arranged, a thermal oxide film is formed after forming the epitaxial layer 11.
The first thermal oxide film forming step of removing this oxide film after leaving the epitaxial layer 11 only on the side surface of the groove 9 and then the thermal oxide film is formed, and the side surface 9a compared to the bottom surface 9b on the inner wall of the groove 9 is formed. Second to form a thin gate oxide film
The thermal oxide film forming step may be performed. In this first thermal oxide film forming step, the unnecessary second semiconductor layer on the substrate surface can be removed by one-time oxidation. In the second thermal oxide film forming step, the oxide film on the side surface can be selectively thinned by the anisotropic thermal oxidation method, the field oxide film on the substrate surface and the groove bottom surface can be thickened, and only the portion where the channel is formed is formed. A thin oxide film can be formed on the surface.
【００４８】又、ｎ+ ソース領域６はイオン注入によら
ずに、ｐ型エピタキシャル層３の形成の際において成長
途中から不純物を含んだガスを供給することによりｐ型
エピタキシャル層３の表面にｎ+ ソース領域６を形成し
てもよい。このようにすると、厚いソース領域が形成す
ることができ、また低抵抗なソース領域をエピタキシャ
ル成長法により形成することができるのでソース領域で
のドロップ電圧を小さくすることができ、より低損失化
した装置を製造することができる。Further, the n + source region 6 does not depend on the ion implantation but is supplied to the surface of the p-type epitaxial layer 3 by supplying a gas containing impurities during the growth of the p-type epitaxial layer 3 during the formation thereof. + The source region 6 may be formed. By doing so, a thick source region can be formed, and a low-resistance source region can be formed by an epitaxial growth method, so that the drop voltage in the source region can be reduced and a device with lower loss can be formed. Can be manufactured.
【００４９】又、ソース電極膜１５は、少なくともｎ+
ソース領域６の表面に形成されていればよい。又、溝９
の形状は、Ｕ字状の他にもＶ字状であってもよい。The source electrode film 15 has at least n +.
It may be formed on the surface of the source region 6. Also, the groove 9
The shape of may be V-shaped as well as U-shaped.
【００５０】尚、本発明において（０００１）カーボン
面は、結晶学的にみて対称な面である（０００１バー）
カーボン面を含むものである。In the present invention, the (0001) carbon surface is a crystallographically symmetrical surface (0001 bar).
It includes a carbon surface.
【００５１】[0051]
【発明の効果】以上詳述したように、請求項１に記載の
発明によれば、高耐圧、低オン抵抗でかつ閾値電圧を小
さくでき、さらに、チャネル形成面にイオンダメージや
凹凸を低減することでＭＯＳ界面特性を改善しスイッチ
ング特性に優れた炭化珪素半導体装置の製造方法を提供
することができる優れた効果を発揮する。As described in detail above, according to the invention described in claim 1, it is possible to reduce the threshold voltage with a high breakdown voltage and a low on-resistance, and further to reduce ion damage and unevenness on the channel formation surface. As a result, the excellent effect of improving the MOS interface characteristics and providing a method for manufacturing a silicon carbide semiconductor device having excellent switching characteristics is exhibited.
【００５２】請求項２に記載の発明によれば、請求項１
に記載の発明の効果に加え、プロセス温度を下げたりプ
ロセス時間を短くでき、安価に製造することができる。
請求項３に記載の発明によれば、請求項１又は２に記載
の発明の効果に加え、一度の熱酸化にて簡便かつ歩留ま
りよく溝側面だけに第２の半導体層を形成でき、安価に
歩留まりよく製造することができる。According to the invention described in claim 2, according to claim 1
In addition to the effects of the invention described in 1), the process temperature can be lowered and the process time can be shortened, and the manufacturing can be performed at low cost.
According to the invention described in claim 3, in addition to the effect of the invention described in claim 1 or 2, the second semiconductor layer can be formed only on the side surface of the groove easily and with good yield by one thermal oxidation, which is inexpensive. It can be manufactured with high yield.
【００５３】請求項４に記載の発明によれば、請求項１
〜３のいずれか１項に記載の発明の効果に加え、第２の
半導体層に形成したチャネル部でのドロップ電圧を小さ
くでき、低損失に製造することができる。According to the invention of claim 4, claim 1
In addition to the effect of the invention described in any one of 1 to 3, it is possible to reduce the drop voltage in the channel portion formed in the second semiconductor layer and to manufacture with low loss.
【００５４】請求項５に記載の発明によれば、請求項１
〜４のいずれか１項に記載の発明の効果に加え、ソース
領域でのドロップ電圧を小さくすることができ、より低
損失化した装置を製造することができる。According to the fifth aspect of the present invention, the first aspect is provided.
In addition to the effect of the invention described in any one of to 4, it is possible to reduce the drop voltage in the source region and to manufacture a device with lower loss.
【００５５】請求項６に記載の発明によれば、請求項１
〜４のいずれか１項に記載の発明の効果に加え、ＭＯＳ
界面が良好なものとなり、スイッチング特性に優れた装
置を製造することができる。According to the invention described in claim 6, according to claim 1,
In addition to the effect of the invention described in any one of
The interface becomes good, and a device having excellent switching characteristics can be manufactured.
【００５６】請求項７に記載の発明によれば、請求項１
〜４のいずれか１項に記載の発明の効果に加え、ＭＯＳ
界面が良好なものとなり、スイッチング特性に優れた装
置を製造することができる。According to the invention of claim 7, claim 1
In addition to the effect of the invention described in any one of
The interface becomes good, and a device having excellent switching characteristics can be manufactured.
【００５７】請求項８に記載の発明によれば、請求項１
〜４のいずれか１項に記載の発明の効果に加え、チャネ
ル部でのドロップ電圧を小さくでき、また歩留まりよく
形成することができ、これにより低損失で歩留まりが高
い装置を製造できる。According to the invention of claim 8, claim 1
In addition to the effect of the invention described in any one of items 1 to 4, it is possible to reduce the drop voltage in the channel portion and to form the device with a high yield, whereby a device with low loss and high yield can be manufactured.
【００５８】請求項９に記載の発明によれば、請求項１
〜４のいずれか１項に記載の発明の効果に加え、ソース
・ドレイン間耐圧が高く、スイッチング速度の速い装置
を製造できる。According to the invention of claim 9, claim 1
In addition to the effect of the invention described in any one of items 1 to 4, a device having a high source-drain breakdown voltage and a high switching speed can be manufactured.
【図１】発明の実施の形態における炭化珪素半導体装置
及び製造工程を説明するための断面構造図。FIG. 1 is a cross-sectional structure diagram for illustrating a silicon carbide semiconductor device and a manufacturing process in an embodiment of the present invention.
【図２】図１に示す炭化珪素半導体装置の製造工程を説
明するための断面構造図。FIG. 2 is a cross-sectional structure diagram for illustrating the manufacturing process for the silicon carbide semiconductor device shown in FIG.
【図３】図１に示す炭化珪素半導体装置の製造工程を説
明するための断面構造図。FIG. 3 is a cross-sectional structure diagram for illustrating the manufacturing process for the silicon carbide semiconductor device shown in FIG.
【図４】図１に示す炭化珪素半導体装置の製造工程を説
明するための断面構造図。FIG. 4 is a cross-sectional structure diagram for illustrating the manufacturing process for the silicon carbide semiconductor device shown in FIG.
【図５】図１に示す炭化珪素半導体装置の製造工程を説
明するための断面構造図。5 is a cross-sectional structure diagram for illustrating the manufacturing process for the silicon carbide semiconductor device shown in FIG.
【図６】図１に示す炭化珪素半導体装置の製造工程を説
明するための断面構造図。6 is a cross-sectional structure diagram for illustrating a manufacturing process for the silicon carbide semiconductor device shown in FIG.
【図７】図１に示す炭化珪素半導体装置の製造工程を説
明するための断面構造図。7 is a cross-sectional structure diagram for illustrating the manufacturing process for the silicon carbide semiconductor device shown in FIG.
【図８】図１に示す炭化珪素半導体装置の製造工程を説
明するための断面構造図。8 is a cross-sectional structure diagram for illustrating the manufacturing process for the silicon carbide semiconductor device shown in FIG.
【図９】炭化珪素半導体材料の熱酸化の異方性を説明す
るための図。FIG. 9 is a diagram for explaining anisotropy of thermal oxidation of a silicon carbide semiconductor material.
【図１０】炭化珪素半導体材料のエピタキシャル成長の
異方性を説明するためのスケッチ図。FIG. 10 is a sketch diagram for explaining anisotropy of epitaxial growth of a silicon carbide semiconductor material.
【図１１】従来技術の炭化珪素半導体装置を説明するた
めの断面構造図。FIG. 11 is a cross-sectional structure diagram for illustrating a conventional silicon carbide semiconductor device.
１…低抵抗半導体層としてのｎ+ 型単結晶ＳｉＣ基板、
２…高抵抗半導体層としてのｎ型エピタキシャル層、３
…第１の半導体層としてのｐ型エピタキシャル層、４…
半導体基板、６…半導体領域としてのｎ+ ソース領域、
９…溝、９ａ…側面、９ｂ…底面、１０…熱酸化膜、１
１…第２の半導体層としてのエピタキシャル層、１２…
ゲート熱酸化膜、１３ａ…ゲート電極膜としての第１ポ
リシリコン層、１４…層間絶縁層、１５…第１の電極と
してのソース電極膜、１６…第２の電極としてのドレイ
ン電極膜1. n + type single crystal SiC substrate as a low resistance semiconductor layer,
2 ... n-type epitaxial layer as high resistance semiconductor layer, 3
... p-type epitaxial layer as first semiconductor layer, 4 ...
Semiconductor substrate, 6 ... n + source region as semiconductor region,
9 ... Groove, 9a ... Side surface, 9b ... Bottom surface, 10 ... Thermal oxide film, 1
1 ... Epitaxial layer as second semiconductor layer, 12 ...
Gate thermal oxide film, 13a ... First polysilicon layer as gate electrode film, 14 ... Interlayer insulating layer, 15 ... Source electrode film as first electrode, 16 ... Drain electrode film as second electrode
───────────────────────────────────────────────────── フロントページの続き (72)発明者 宮嶋 健 愛知県刈谷市昭和町１丁目１番地 日本電 装 株式会社内 (72)発明者 戸倉 規仁 愛知県刈谷市昭和町１丁目１番地 日本電 装 株式会社内 (72)発明者 夫馬 弘雄 愛知県愛知郡長久手町大字長湫字横道41番 地の１株式会社豊田中央研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Ken Miyajima, 1-1, Showa-cho, Kariya city, Aichi Prefecture, Nihon Denso Co., Ltd. Co., Ltd. (72) Inventor Hiroo Ozuma, Toyota Central Research Institute Co., Ltd., 41, Yokomichi, Nagakute-cho, Aichi-gun, Aichi
Claims (9)
型の高抵抗半導体層と第２導電型の第１の半導体層とを
順に積層して単結晶炭化珪素よりなる半導体基板を形成
するとともに、前記第１の半導体層内の表層部の所定領
域に第１導電型の半導体領域を形成する第１工程と、 前記半導体領域と前記第１の半導体層を貫通し前記高抵
抗半導体層に達する溝を形成する第２工程と、 前記溝の内壁における少なくとも側面に、単結晶炭化珪
素よりなる第２の半導体層を形成する第３工程と、 前記溝内における前記第２の半導体層の表面にゲート酸
化膜を形成する第４工程と、 前記溝内における前記ゲート酸化膜の表面にゲート電極
膜を形成する第５工程と、 前記第１の半導体層の表面と前記半導体領域の表面のう
ちの少なくとも前記半導体領域の表面に第１の電極を形
成するとともに、前記低抵抗半導体層の表面に第２の電
極を形成する第６工程とを備えたことを特徴とする炭化
珪素半導体装置の製造方法。1. A semiconductor substrate made of single crystal silicon carbide by sequentially laminating a low-resistance semiconductor layer of a first conductivity type, a high-resistance semiconductor layer of a first conductivity type, and a first semiconductor layer of a second conductivity type. A first step of forming and forming a semiconductor region of a first conductivity type in a predetermined region of a surface layer portion in the first semiconductor layer; and the high resistance semiconductor penetrating the semiconductor region and the first semiconductor layer. A second step of forming a groove reaching the layer, a third step of forming a second semiconductor layer made of single crystal silicon carbide on at least a side surface of the inner wall of the groove, and the second semiconductor layer in the groove A fourth step of forming a gate oxide film on the surface of the gate, a fifth step of forming a gate electrode film on the surface of the gate oxide film in the groove, a surface of the first semiconductor layer and a surface of the semiconductor region At least the semiconductor region And forming a first electrode on a surface, the method for manufacturing a silicon carbide semiconductor device is characterized in that a sixth step of forming a second electrode on the surface of the low-resistance semiconductor layer.
方晶系であり、かつ表面の面方位が略（０００１）カー
ボン面であることを特徴とする請求項１に記載の炭化珪
素半導体装置の製造方法。2. The silicon carbide semiconductor device according to claim 1, wherein the silicon carbide forming the semiconductor substrate is a hexagonal crystal system, and the plane orientation of the surface is a (0001) carbon plane. Production method.
よび半導体領域の表面と前記溝の側面および底面に第２
の半導体層を形成するものであり、その後に、前記溝の
側面における前記第２の半導体層に比べ前記第１の半導
体層および半導体領域の表面と前記溝の底面における前
記第２の半導体層を厚く熱酸化して前記溝の側面にのみ
前記第２の半導体層を残す工程を含むことを特徴とする
請求項１又は２に記載の炭化珪素半導体装置の製造方
法。3. In the third step, a second step is performed on the surface of the first semiconductor layer and the semiconductor region and the side surface and the bottom surface of the groove.
Of the first semiconductor layer and the semiconductor region on the side surface of the groove and the second semiconductor layer on the bottom surface of the groove as compared with the second semiconductor layer on the side surface of the groove. 3. The method for manufacturing a silicon carbide semiconductor device according to claim 1, further comprising a step of thickly thermally oxidizing and leaving the second semiconductor layer only on a side surface of the groove.
エピタキシャル成長法により形成することを特徴とする
請求項１〜３のいずれか１項に記載の炭化珪素半導体装
置の製造方法。4. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein in the third step, the second semiconductor layer is formed by an epitaxial growth method.
タキシャル成長法にて形成することを特徴とする請求項
１〜４のいずれか１項に記載の炭化珪素半導体装置の製
造方法。5. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein in the first step, the semiconductor region is formed by an epitaxial growth method.
底面に比べ側面が薄い酸化膜を形成および除去する工程
を含むことを特徴とする請求項１〜４のいずれか１項に
記載の炭化珪素半導体装置の製造方法。6. The method according to claim 1, wherein the second step includes a step of forming and removing an oxide film whose side surface is thinner than a bottom surface of the inner wall of the groove. Manufacturing method of silicon carbide semiconductor device.
り前記溝を形成するとともに、溝の内壁における底面に
比べ側面が薄い酸化膜を形成および除去する工程を含む
ことを特徴とする請求項１〜４のいずれか１項に記載の
炭化珪素半導体装置の製造方法。7. The second step includes the steps of forming the groove by dry etching and forming and removing an oxide film having a side surface whose inner wall is thinner than a bottom surface of the groove. 5. The method for manufacturing a silicon carbide semiconductor device according to any one of 4 above.
成長法により前記溝の内壁において底面に比べ側面が厚
い前記第２の半導体層を形成することを特徴とする請求
項１〜４のいずれか１項に記載の炭化珪素半導体装置の
製造方法。8. The third step of forming the second semiconductor layer in which the side surface of the inner wall of the groove is thicker than the bottom surface of the second semiconductor layer by an anisotropic epitaxial growth method. Item 1. A method for manufacturing a silicon carbide semiconductor device according to Item 1.
前記溝の内壁における底面に比べ側面が薄い前記ゲート
酸化膜を形成することを特徴とする請求項１〜４のいず
れか１項に記載の炭化珪素半導体装置の製造方法。9. The method according to claim 1, wherein in the fourth step, the gate oxide film whose side surface is thinner than the bottom surface of the inner wall of the groove is formed by an anisotropic thermal oxidation method. Item 8. A method for manufacturing a silicon carbide semiconductor device according to item.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22948595A JP3419163B2 (en) | 1995-09-06 | 1995-09-06 | Method for manufacturing silicon carbide semiconductor device |
| KR1019960038644A KR100199997B1 (en) | 1995-09-06 | 1996-09-06 | Silicon carbide semiconductor device |
| DE19636302A DE19636302C2 (en) | 1995-09-06 | 1996-09-06 | Silicon carbide semiconductor device and manufacturing method |
| FR9610880A FR2738394B1 (en) | 1995-09-06 | 1996-09-06 | SILICON CARBIDE SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREOF |
| US08/893,221 US5976936A (en) | 1995-09-06 | 1997-07-15 | Silicon carbide semiconductor device |
| US08/938,805 US6020600A (en) | 1995-09-06 | 1997-09-26 | Silicon carbide semiconductor device with trench |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22948595A JP3419163B2 (en) | 1995-09-06 | 1995-09-06 | Method for manufacturing silicon carbide semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0974191A true JPH0974191A (en) | 1997-03-18 |
| JP3419163B2 JP3419163B2 (en) | 2003-06-23 |
Family
ID=16892911
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22948595A Expired - Lifetime JP3419163B2 (en) | 1995-09-06 | 1995-09-06 | Method for manufacturing silicon carbide semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3419163B2 (en) |
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