JP2003229569A - Manufacturing method for superjunction semiconductor element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To fill a trench by epitaxial growth so as not to leave a void and to eliminate the void in the case that the void remains in manufacturing a semiconductor element having a superjunction structure. <P>SOLUTION: By inclining a trench side wall, and performing the epitaxial growth using a dichlorosilane as a gaseous raw material at the temperature ≥800°C and ≤1000°C and also by the pressure ≥1333.22 Pa and ≤13332.2 Pa, the trench is filled with an epitaxial layer 2 so as not to leave the void inside the epitaxial layer 2. Also, even in the case that the trench can not be fully filled by the epitaxial growth, the void inside the trench is eliminated by performing hydrogen reduction atmosphere annealing at the temperature above 900°C after the epitaxial growth. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a super-junction semiconductor device, and more particularly to a MOSFET (insulated gate type field effect transistor), an IGBT (insulated gate type bipolar transistor), a bipolar transistor, a diode and the like. The present invention relates to a method for manufacturing a super-junction semiconductor element that can achieve both high breakdown voltage and large current capacity that can be applied.

[0002]

2. Description of the Related Art In a conventional high breakdown voltage semiconductor element, a drift region having a high specific resistance is provided in a main current path in order to obtain a high breakdown voltage. There was a problem that would be high.

As a solution to this problem, the drift layer is formed by a parallel pn layer in which n-type and p-type regions having an increased impurity concentration are alternately stacked, and depleted in the off state to bear the breakdown voltage. A semiconductor device having such a structure is disclosed in, for example, Japanese Patent Publication No. 2-54661 and US Pat. No. 521.
No. 6275 and Japanese Patent Laid-Open No. 7-7154.

[0004]

In order to form such a super junction structure, a method of filling a trench structure by epitaxial growth or a method of repeating epitaxial growth and ion implantation on a planar substrate have been used.

However, the method of forming the trench structure and filling the trench portion has two problems. The first problem is that the width of the trench is 1 to 10 μm.
In the process of forming a trench structure having a high aspect ratio of 20 to 100 μm and an aspect ratio of 10 to 50, the substrate may be damaged by etching such as crystal defects, unevenness, residual stress, and impurities. The remaining problems are that plasma etching, sacrificial oxidation, annealing, and other steps increase in order to remove this damage, and damage that cannot be completely removed remains.

The second problem is that when the conventional epitaxial growth technique is used, the breakdown voltage class is 600, for example.
The V MOSFET has an aspect ratio of 10 to 20, but it is necessary to embed an extremely deep trench structure having such an aspect ratio, the opening of the trench is blocked during growth, and a space (void) is formed inside the trench. The problem remains. No guidance has previously been given to solve this problem due to epitaxial growth on trenches.

Further, in the forming method in which the epitaxial growth and the ion implantation are repeated, the number of steps is increased, the cost of the breakdown voltage structure portion becomes extremely high, and the process damage and the impurity contamination are increased due to the repetition of the lithography and the ion implantation, and the crystal quality is increased. There was a problem that it deteriorated. In addition, this method is a method for spreading impurities ion-implanted at a specific position by thermal diffusion,
There is a problem that the impurity distribution in the super junction region is non-uniform and this non-uniformity makes device characteristics unstable.

In order to solve these problems, it is desirable to introduce a technique capable of performing epitaxial growth even at the back of a trench having a high aspect ratio at a sufficiently high growth rate. Regarding such an epitaxial growth technique, there are conventionally the following two methods.

The first is a method of selectively growing by applying an atomic beam or a molecular beam only to a specific surface by using the straightness of a molecule by an epitaxy method using an atomic beam or a molecular beam. That is, this is a method in which an atomic beam or a molecular beam is selectively applied only to the bottom of the trench to promote epitaxial growth so that the sidewall is less likely to hit and growth of the sidewall is suppressed so that the opening is not blocked during the epitaxial growth.

Secondly, the anisotropic growth effect is utilized, and the difference between the growth on the surface which is flat and stable and has a slow growth rate and the growth on the surface which is rough and has a high growth rate is utilized. This is a method for selective growth. This anisotropic growth effect is caused by liquid phase growth (LPE: Liquid Phase E).
It appears most significantly in the pittaxy method, but vapor phase growth (C
VD: Chemical Vapor Deposition
Ion method. In this case, as the side surface of the trench, a surface that is likely to be flattened, for example, a (111) surface or a (100) surface is selected, and a surface that is easily roughened, for example, a (110) surface is selected. Do not block the opening. However, there is still room for improvement in such a solution.

By the way, a method of using dichlorosilane as a source gas when burying a trench by epitaxial growth is disclosed in, for example, Japanese Patent Application Laid-Open Nos. 1-214013 and 11-102870. However, the method disclosed in Japanese Patent Application Laid-Open No. 1-214013 is a method of growing single crystal silicon in a trench formed in a polysilicon layer, and is not strictly epitaxial growth.

Further, this method is unsuitable for manufacturing a super junction structure because the crystal orientation of single crystal silicon grown in a plurality of trenches may be different for each trench. On the other hand, the method disclosed in Japanese Unexamined Patent Publication No. 11-102870 is a method of epitaxially growing silicon in a trench having a bottom surface of silicon and a side surface of silicon dioxide, and thus the obtained structure is not a super junction structure.

The present invention has been made in view of the above circumstances. An object of the present invention is to provide a super-junction semiconductor device capable of filling a trench without leaving a void in the step of filling the trench by epitaxial growth. It is to provide a manufacturing method. Another object of the present invention is to provide a method for manufacturing a super-junction semiconductor device capable of eliminating voids in the trench even when the trench cannot be sufficiently filled by epitaxial growth.

[0014]

In order to achieve the above object, the invention according to claim 1 is a semiconductor substrate of the first conductivity type having a trench structure, in which dichlorosilane is used as a source gas, and the second conductivity type is used. Of the epitaxial layer.

The invention according to claim 2 is the step of growing an epitaxial layer of the second conductivity type on the semiconductor substrate of the first conductivity type having a trench structure, and the subsequent epitaxial growth in a hydrogen reducing atmosphere. And a step of performing annealing at a temperature higher than 900 ° C.

The invention described in claim 3 is the same as that of claim 2
In the invention described in (3), the epitaxial growth is performed by using dichlorosilane as a raw material gas.

The invention according to claim 4 is the same as claim 1.
1 to 3, the epitaxial growth is performed at a temperature of 800 ° C. or higher and 1000 ° C. or lower.

The invention described in claim 5 is the same as claim 1.
In the invention according to any one of 1 to 3, 1333.
It is characterized in that epitaxial growth is performed at a pressure of 22 Pa or more and 13332.2 Pa or less.

The invention according to claim 6 is the same as claim 1.
In the invention described in any one of 5 to 5, both trench sidewalls facing each other are less than 90 ° with respect to the substrate surface so that the trench opening gradually narrows from the substrate surface side toward the bottom surface of the trench. Inclined by an angle θ, and said angle θ
Between the trench and the aspect ratio AR of the trench AR <1/2 ×
A feature is that the trench is formed so that the relationship of tan θ is established.

The invention described in claim 7 is the same as claim 1.
The invention described in any one of 1 to 6 above is characterized by further including a step of removing, by polishing, a portion of the epitaxial layer deposited immediately above the non-opening portion of the trench.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a cross-sectional view of a super junction structure manufactured by the method of the present invention.
7 to 7 are cross-sectional views showing a manufacturing process of the super junction structure according to the embodiment of the present invention. In the figure, reference numeral 1 is an n-type semiconductor substrate, reference numeral 2 is a p-type epitaxial layer, and reference numeral 3 is an insulating mask such as an oxide film or a nitride film.

The present invention relates to the structure of the breakdown voltage region and the manufacturing method, and the source structure and the drain structure are arbitrary. Therefore, it is also applied to IGBTs, bipolar transistors, GTO thyristors, diodes and the like.

The method of manufacturing the super junction structure shown in FIG. 1 will be described below with reference to FIGS. First, a low resistance n-type semiconductor substrate 1 is prepared. Then, as shown in FIG. 2, an insulating mask 3 such as an oxide film or a nitride film serving as a mask for epitaxial growth is formed on the surface of the n-type semiconductor substrate 1. Then, as shown in FIG. 3, a striped window opening 3a is formed in the insulating mask 3 using a mask (not shown). Striped window opening 3a
The width of the insulating mask 3 is about 1 to 20 μm.

Next, as shown in FIG. 4, a region corresponding to the window opening 3a of the n-type semiconductor substrate 1 is removed by etching to remove a trench opening having a desired depth, for example, about 20 to 100 μm. 13 is formed so as to gradually narrow from the substrate surface side toward the bottom surface of the trench. Then, the insulating mask 3 is removed by etching. Here, both side walls of the trench facing each other are the substrate surface (strictly, a virtual surface obtained by extending the substrate surface onto the trench opening 13).
The angle θ formed by and is less than 90 °, and is inclined so as to satisfy the following expression (1) with respect to the trench aspect ratio AR. AR <1/2 × tan θ (1)

As described above, two types of dry etching and wet etching can be adopted as the method and conditions of the trench etching for inclining the side wall of the trench.

As the dry etching, for example, by plasma etching, dry etching having anisotropy such as RIE (Reactive Ion Etching), the exposed portion of the silicon which is not masked by the insulating mask 3 of the oxide film is vertical or vertical. Etch at an angle close to. In this case, there is a feature that the crystal plane orientation forming the trench is not limited.

As the wet etching, the trench can be formed by wet etching having anisotropy. In this case, the crystal plane orientation for forming the trench is limited, but it is characterized in that damage to the crystal can be made smaller than that in dry etching.

Then, as shown in FIG. 5, the p-type epitaxial layer 2 is formed in the trench opening 13 by the CVD method.
Are crystal-grown so as to have a thickness of ½ or more of the trench width. That is, assuming that the ideal epitaxial growth proceeds so that the epitaxial layer 2 having the same thickness adheres to the entire surface of the trench, the epitaxial layer 2
The trench is filled with the epitaxial layer 2 when the thickness of the trench becomes 1/2 of the trench width. Therefore, the crystal growth is made to have a thickness of ½ or more of the trench width. At this time, it is desirable that the growth rate around the trench window opening 3a does not exceed the growth rate of the trench opening 13.

In order to achieve such growth conditions, the probability of deposition of the raw material gas for epitaxial growth is reduced, and the mean free path of gas molecules is increased so that the reactive gas of the raw material can fly deep into the trench. This is very important. In order to reduce the sticking probability of the raw material gas, it is effective to use dichlorosilane as the raw material gas and control the growth temperature to a temperature of 800 ° C. or higher and 1000 ° C. or lower. Further, in order to increase the mean free path of gas molecules, it is effective to control the pressure in the chamber at a pressure of 1333.22 Pa or more and 133332.2 Pa or less during epitaxial growth.

Continuing epitaxial growth, FIG.
As shown in, the growth is completed when the epitaxial layer 2 grows sufficiently thick and the bottom of the trench becomes higher than the surface of the n-type semiconductor substrate 1. Then, in a hydrogen reducing atmosphere, 90
Annealing is performed at a temperature higher than 0 ° C. After that, the epitaxial layer 2 is polished so that the surface of the epitaxial layer 2 has the same height as the original surface of the n-type semiconductor substrate 1.
As a result, a super junction structure as shown in FIG. 7 is obtained.

Next, the reason why the angle θ is less than 90 ° will be described. First, if the angle θ is less than 90 °, the angle at which the trench sidewall is seen from the vapor phase in which the CVD source gas exists has a finite value. Therefore, the difference in sidewall film thickness between the lower part and the upper part of the trench is reduced, and the trench can be filled before the upper part of the trench opening 13 is blocked by the epitaxial growth in the vicinity thereof.

Next, the reason why it is necessary to satisfy the expression (1) will be described with reference to FIG. Assuming that the opening width of the trench opening 13 on the substrate surface is W and the trench depth is d, the following equation (2) is established from FIG. d = W / 2 × tan θ (2)

In order for the bottom of the trench to exist in the trench opening 13, the trench depth d must be shallower than W / 2 × tan θ. That is, the following expression (3) must hold. d <W / 2 × tan θ (3)

From the above equation (3), the following equation (4) is derived, and since the aspect ratio AR is d / W, the above equation (1) is derived. d / W <1/2 × tan θ (4)

FIG. 9 shows a schematic view of a cross-sectional photograph of a state where the trench side wall angle is 90 ° or 87 ° and the trench is buried by the CVD method using dichlorosilane as a source gas. 9A shows θ = 90 °, and FIG. 9B shows θ = 87 °, and the trenches indicated by the arrows in both figures are trenches having the same opening width. From Figure 9,
It is apparent that the embedded state is better when θ = 87 °.

Next, the reason why dichlorosilane is used as a raw material gas for epitaxial growth will be described. FIG. 10 shows a schematic view of a cross-sectional photograph at the stage of filling the trench by the CVD method with the raw material gas of trichlorosilane or dichlorosilane. FIG. 10 (a) uses trichlorosilane, and FIG. 10 (b) uses dichlorosilane. The trenches indicated by the arrows in both figures are trenches having the same opening width.

In the trench window opening 3a, an eave grows so as to block the trench opening 13. Therefore, in order to suppress it, it is necessary to grow it while performing an etching action in parallel. For that purpose, a source gas containing chlorine, such as trichlorosilane or dichlorosilane, is effective. In the case of trichlorosilane, the adhesion probability is 0.
Since it is as large as 1 or more, as shown in FIG. 10A, the window opening 3a is closed before the trench is completely filled.

On the other hand, with dichlorosilane, since the adhesion probability is as small as 0.01 or less, as shown in FIG. 10 (b), the growth rate is small, but it is almost conformally buried in the trench shape. Therefore, it is effective to use dichlorosilane as the source gas. Figure 11
[Fig. 4] is a schematic view of a cross-sectional photograph showing a state in which a trench is completely filled by a CVD method using dichlorosilane as a source gas.

Next, the epitaxial growth temperature is 800
The reason why the temperature is from 1000C to 1000C will be described. FIG. 12 shows a schematic diagram of a cross-sectional photograph at a stage in the middle of filling a trench by a CVD method using dichlorosilane as a raw material gas with an epitaxial growth temperature of 1100 ° C. or 900 ° C. Figure 12 (a) shows 1100 ° C
(B) is at 900 ° C., and the trenches indicated by the arrows in both figures are trenches having the same opening width.

The probability of deposition of the source gas is 100 when the growth temperature is 100.
As the temperature increases or decreases by 1 degree, the growth temperature increases or decreases by 1 digit.
The adhesion probability of dichlorosilane increases to about 0.1 at 0 ° C. Therefore, as shown in FIG. 12A, the window opening 3a is blocked during the epitaxial growth. This defect is likely to occur when the growth temperature exceeds 1000 ° C.

On the other hand, when the growth temperature is 900 ° C., as shown in FIG. 12 (b), the window opening 3a is not covered and the trench shape is almost conformally filled. As described above, the growth temperature may be 1000 ° C. or lower, but if the growth temperature is less than 800 ° C., the growth rate becomes remarkably low, which is not suitable for mass production. Therefore, it is suitable that the growth temperature is 800 ° C. or higher and 1000 ° C. or lower.

Next, the pressure during epitaxial growth is 1
The reason why the pressure is 333.22 Pa or more and 13332.2 Pa or less will be described. In FIG. 13, the epitaxial growth pressure is 101324.72 Pa or 5332.8.
CV using dichlorosilane as raw material gas at 8 Pa
The schematic diagram of the cross-sectional photograph in the step of filling the trench by the D method is shown. FIG. 13A shows 1011324.7.
2Pa, 5332.88Pa in the figure (b)
The trenches indicated by the arrows in both figures are trenches having the same opening width.

The pressure is changed from 101324.72 Pa to 533.
When it is reduced to 2.88 Pa, the mean free path of the molecule increases 19 times in inverse proportion to it. Therefore, when the pressure is lowered, even in a trench having a large aspect ratio, the molecules penetrate deep into the trench, making it easier to conformally fill the trench shape. As is clear from FIG. 13, the low pressure produces smaller voids in the trench.

However, when the pressure is less than 1333.22 Pa, the growth rate becomes remarkably low, which is not suitable for mass production. Further, if the pressure exceeds 13332.2 Pa, large voids remain that are difficult to fill even if the subsequent hydrogen reducing atmosphere annealing step is performed. Therefore, the pressure during epitaxial growth is 1333.22 Pa.
It is suitable that it is above 13332.2 Pa and below.

Next, following the epitaxial growth,
The reason why annealing is performed at a temperature higher than 900 ° C. in a hydrogen reducing atmosphere will be described. In Figure 14, 900 ℃
Alternatively, a schematic view of a cross-sectional photograph of a trench portion annealed at 1000 ° C. is shown. 14 (a) is at 900 ° C., and FIG. 14 (b) is at 1000 ° C. In addition,
In order to clarify the annealing effect, annealing is performed before embedding the epitaxial layer, and FIG. 14 shows a cross section of the trench.

Focusing on the portion surrounded by a circle in FIG. 14, when the annealing temperature is 900 ° C., no increase in the radius of curvature is seen at the upper corners or the lower corners of the trench. It has increased. In other words, by annealing at 1000 ° C,
It can be seen that the surface migration of silicon is much more likely to occur. Such an increase in the radius of curvature,
That is, the surface migration of silicon easily occurs when the annealing temperature is higher than 900 ° C. Therefore, even if voids remain in the epitaxial layer 2 during epitaxial growth, the voids can be completely eliminated by annealing at a temperature higher than 900 ° C.

FIG. 15 is a sectional perspective view showing the structure of a vertical MOSFET having a planar structure to which the superjunction structure according to the embodiment is applied. Note that the oxide film, the source electrode, and the like formed on the surface of the semiconductor substrate are omitted for easy understanding of the description (the same applies to FIG. 16). An oxide film and a polysilicon gate electrode layer (not shown) are formed on the surface of the n-type semiconductor substrate 1 having the epitaxial layer 2 formed as described above, and the oxide film and the gate electrode layer are used as a mask for p-type etching. The base region 6 and the n source region 7 are sequentially formed by diffusion.

In this example, the p base region 6 has a stripe shape and is formed so as to be orthogonal to the stripe direction of the epitaxial layer 2. By being orthogonal to each other in this manner, the p base region 6 surely comes into contact with the epitaxial layer 2 and the n-type semiconductor substrate 1,
It is not necessary to increase the accuracy of alignment, which facilitates manufacturing.

FIG. 16 is a sectional perspective view showing the structure of a vertical MOSFET having a trench structure to which the superjunction structure according to the embodiment is applied. For the n-type semiconductor substrate 1 having the epitaxial layer 2 formed as described above, p
The base region 8 is formed, and then the stripe-shaped n-type source region 9 is formed by a method such as diffusion or ion implantation.
Then, a trench is formed on the n source region by etching, and an oxide film 10 and a polysilicon gate electrode 11 are formed in the trench to form a vertical structure M having a trench structure.
Form OSFET.

In the example shown in FIG. 16 as well, as in the example shown in FIG. 15, the stripe direction of the p base region 8 and the stripe direction of the epitaxial layer 2 are orthogonal to each other. In the example shown in FIG. 15 or 16, the stripe direction of the p base regions 6 and 8 and the stripe direction of the epitaxial layer 2 are
The directions may not be orthogonal but the same direction.

According to the above embodiment, the sidewall of the trench is inclined and dichlorosilane is used as the source gas at a temperature of 800 ° C. or more and 1000 ° C. or less and 133
Since the epitaxial growth is performed at a pressure of 3.22 Pa or more and 13332.2 Pa or less, the trench can be filled with the epitaxial layer 2 so that no void remains in the epitaxial layer 2. In addition, even if the trench cannot be filled sufficiently by epitaxial growth,
Voids in the trench can be eliminated by performing hydrogen reducing atmosphere annealing at a temperature higher than 900 ° C. after the epitaxial growth. Therefore, it is possible to obtain a super-junction semiconductor device having no void in the epitaxial layer 2.

[0052]

According to the present invention, when a trench provided in a semiconductor substrate is filled by epitaxial growth,
The trench can be filled with an epitaxial layer so that no voids remain in the epitaxial layer. Further, even if voids remain during the epitaxial growth, the voids in the trench can be eliminated by performing high-temperature hydrogen reduction atmosphere annealing after the epitaxial growth. Therefore, it is possible to obtain a void-free super-junction semiconductor element.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a super junction structure manufactured by a manufacturing method according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of the super junction structure according to the embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a manufacturing process of the super junction structure according to the embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a manufacturing process of the super junction structure according to the embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a manufacturing process of the super junction structure according to the embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a manufacturing process of the super junction structure according to the embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a manufacturing process of the super junction structure according to the embodiment of the present invention.

FIG. 8 is a schematic view of a trench for explaining the reason for limiting the sidewall angle of the trench.

FIG. 9 is a schematic view of a cross-sectional photograph showing the result of examining the trench sidewall angle dependence of the epitaxial growth grown in the trench.

FIG. 10 is a schematic diagram of a cross-sectional photograph showing the result of examining the source gas dependency of epitaxial growth that is embedded in a trench.

FIG. 11: CV using dichlorosilane as a source gas
It is a schematic diagram of a cross-sectional photograph showing a state in which a trench is completely buried by the D method.

FIG. 12 is a schematic diagram of a cross-sectional photograph showing the results of examining the temperature dependence of epitaxial growth that is embedded in a trench.

FIG. 13 is a schematic view of a cross-sectional photograph showing the results of examining the pressure dependence of the epitaxial growth for burying in a trench.

FIG. 14 is a schematic view of a cross-sectional photograph showing the results of examining the temperature dependence of the effect of high-temperature hydrogen reduction atmosphere annealing.

FIG. 15 is a sectional perspective view showing the structure of a vertical MOSFET having a planar structure to which the super junction structure according to the embodiment of the present invention is applied.

FIG. 16 is a cross-sectional perspective view showing the structure of a vertical MOSFET having a trench structure to which the superjunction structure according to the embodiment of the present invention is applied.

[Explanation of symbols]

1 Semiconductor substrate 2 Epitaxial layer 13 Trench opening

Continued front page    (72) Inventor Daisuke Kishimoto             2-2-1 Nagasaka, Yokosuka City, Kanagawa Prefecture             Inside the Fuji Electric Research Institute (72) Inventor Katsunori Ueno             2-2-1 Nagasaka, Yokosuka City, Kanagawa Prefecture             Inside the Fuji Electric Research Institute (72) Inventor Satoshi Oka             2-13-1, Isobe, Annaka-shi, Gunma Shinetsuhan             Conductor Co., Ltd. Semiconductor Isobe Laboratory

Claims (7)

[Claims] 1. A semiconductor substrate of a first conductivity type having a trench structure, wherein dichlorosilane is used as a source gas to form a second semiconductor substrate.
A method of manufacturing a super-junction semiconductor device, comprising the step of growing a conductive type epitaxial layer. 2. A step of growing a second-conductivity-type epitaxial layer on a first-conductivity-type semiconductor substrate having a trench structure, and a step of growing the second-conductivity-type epitaxial layer in a hydrogen-reducing atmosphere.
A method of manufacturing a super-junction semiconductor device, comprising: a step of annealing at a temperature higher than 00 ° C. 3. The method for manufacturing a super-junction semiconductor device according to claim 2, wherein dichlorosilane is used as a source gas to perform epitaxial growth. 4. The epitaxial growth is performed at a temperature of 800 ° C. or higher and 1000 ° C. or lower.
4. The method for manufacturing a super junction semiconductor device according to any one of 3 to 3. 5. 1333.22 Pa or more 133333.2.
The method for producing a super-junction semiconductor device according to claim 1, wherein epitaxial growth is performed at a pressure of Pa or less. 6. An angle θ of less than 90 ° with respect to the substrate surface such that the two trench sidewalls facing each other face each other so that the trench opening gradually narrows from the substrate surface side toward the bottom surface of the trench.
And the aspect ratio A of the trench
The trench is formed so that a relation of AR <1/2 × tan θ is established between R and R.
5. The method for manufacturing a super junction semiconductor device according to any one of 5 above. 7. The super junction according to claim 1, further comprising a step of removing a portion of the epitaxial layer, which is deposited on the non-opening portion of the trench, by polishing. Manufacturing method of semiconductor device.