JP2004158835A - Method of manufacturing super junction semiconductor element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To promote the epitaxial growth of a semiconductor on the bottom of a trench and fill the trench with the semiconductor without generating a void or a crystal lattice deviation by suppressing the growth in a trench opening part, in manufacturing a super junction structure growing a second conductivity semiconductor epitaxially in the trench formed on a first conductivity semiconductor substrate. <P>SOLUTION: The upper half part 31 of a trench, in which a sidewall 32 is vertical or nearly vertical to a substrate surface 21 and inclines so as to become narrower toward the bottom of the trench, is formed on an n-type semiconductor substrate 2. Following under it, a lower half part 36 of the trench, which a sidewall 37 inclines more gentler than the sidewall 32 of the upper half part 31 of the trench so that a longitudinal section is formed into a V-shaped. A p-type semiconductor 4 is grown epitaxially in the trench 3 consisting of the upper half part 31 and the lower half part 36 of the trench. <P>COPYRIGHT: (C)2004,JPO

Description

  The present invention relates to a method for manufacturing a super-junction semiconductor device, and more specifically, to a method for manufacturing a MOSFET (insulated gate type field effect transistor), an IGBT (insulated gate type bipolar transistor), a bipolar transistor, a diode, and the like. The present invention relates to a method for manufacturing a super-junction semiconductor element capable of achieving both high current capacity.

  Conventional high-breakdown-voltage semiconductor elements are provided with a high-resistivity drift region in the main current path in order to obtain a high breakdown voltage, and the higher the breakdown voltage, the greater the voltage drop in this portion, so the on-voltage increases. There was a problem. As a solution to this problem, the drift layer is composed of a parallel pn layer in which an n-type semiconductor region and a p-type semiconductor region with an increased impurity concentration are alternately stacked (this is called a super-junction structure). In such a case, a semiconductor device having a structure that is depleted to bear the breakdown voltage is known (for example, refer to Patent Literature 1, Patent Literature 2, Patent Literature 3, and Patent Literature 4).

  In order to mass-produce the above-mentioned super junction structure at low cost, a method of forming a plurality of trenches in an n-type (or p-type) semiconductor substrate and epitaxially growing a p-type (or n-type) semiconductor in the trenches has been developed. Have been. In addition to the super-junction structure, a technique for epitaxially growing a semiconductor in a trench (for example, see Patent Documents 5 and 6) and a technique for filling the trench by a CVD method (for example, see Patent Document 7). It is known.

European Patent Application No. 0053854 U.S. Pat. No. 5,216,275 U.S. Pat. No. 5,438,215 JP-A-9-26631 JP 2000260982 A JP 2000-340578 A JP-A-11-307767

  However, the conventional technique of epitaxially growing a semiconductor in a trench has a problem that the trench opening is closed with voids (bubbles) remaining in the trench. This is because, as shown in FIG. 19, the flow 13 of the material gas flows from the opening to the bottom in the trench 11 according to the diffusion process, but loses material atoms in the process. That is, the concentration of the growth gas becomes lower from the trench opening toward the trench bottom, whereby the epitaxial growth layer 12 grows thicker at the trench opening than at the trench bottom.

  Therefore, as shown in FIG. 20, the trench 14 is formed so that its vertical sectional shape is V-shaped, and a semiconductor is epitaxially grown therein, so that the trench is filled with the semiconductor before the trench opening is closed. There is a way to embed. In this method, in order to set the aspect ratio of the trench 14 to 10 or more, it is necessary to set the taper angle of the trench side wall 15 to 85 ° or more and less than 90 °. The problem that the department is blocked cannot be fully solved.

  Here, as shown in FIG. 20, the aspect ratio of the trench is represented by [d / w], where d and w are the depth of the trench 14 and the opening width of the trench 14 on the substrate surface, respectively. The taper angle of the trench side wall refers to an angle α of the trench side wall 15 with respect to a virtual plane parallel to the substrate surface 16, for example, a virtual plane 17 parallel to the substrate surface 16 passing through the bottom of the trench.

  When epitaxial growth is performed on a trench having a taper angle of 85 ° on the side wall of the trench, as shown in FIG. 21, nano-scale voids 18 and dislocations (crystal lattices) are formed in the epitaxial growth layer 12 at the final stage of the epitaxial growth. (Displacement) 19 occurs. This is considered to be caused by the fact that the growth surfaces of the epitaxial growth layers 12 grown from the opposing trench sidewalls 15 toward the center of the trench 14 are united in parallel from both sides.

  The present invention has been made in view of the above problems, and promotes the epitaxial growth of a semiconductor at the bottom of a trench and suppresses the growth at the opening of the trench, so that voids and crystal lattice misalignment do not occur. It is another object of the present invention to provide a method of manufacturing a super junction semiconductor device which can fill a trench with a semiconductor, thereby easily manufacturing a super junction semiconductor device with good mass productivity.

  In order to achieve the above object, the invention according to claim 1 is characterized in that a trench of a second conductivity type is provided in a trench having a depth d and an opening width w in a substrate surface provided in a semiconductor substrate of the first conductivity type. In manufacturing a super-junction semiconductor device having a structure in which a semiconductor is embedded, a step of forming an upper half of a trench whose side wall is perpendicular to or substantially perpendicular to the substrate surface in a semiconductor substrate of the first conductivity type; Subsequent to the upper half of the trench, a lower side wall is formed, the side wall of which is more gradually inclined than the side wall of the upper half of the trench, and whose depth from the boundary with the upper half of the trench is h. And a step of epitaxially growing a second conductivity type semiconductor in a trench formed by the upper half portion of the trench and the lower half portion of the trench. According to the present invention, since the vertical cross section of the lower half of the trench is V-shaped or substantially V-shaped, the supply of atomic layer steps in the lower half of the trench becomes active during epitaxial growth, and the growth of the bottom of the trench is increased. The rate is relatively faster than the growth rate of the trench opening.

  According to a second aspect of the present invention, in the first aspect, [h <d / 2] is satisfied. Here, the reason why the depth h of the lower half of the trench is smaller than の of the depth d of the entire trench is that the total charge amount of the semiconductor substrate of the first conductivity type and the second conductivity are lower in the upper half of the trench. Although the balance with the total charge of the semiconductor of the type is maintained, in the lower half of the trench, the total charge of the semiconductor of the second conductivity exceeds the total charge of the semiconductor substrate of the first conductivity, and the balance is lost. Because. The breakdown voltage tends to fall in the region where the balance is lost. Therefore, it is desirable that the depth h occupied by the region h where the balance is lost is less than half of the total depth d of the trench. According to the present invention, from the above, it is possible to maintain a high breakdown voltage, which is a feature of the super junction structure, and to realize a shape that facilitates epitaxial growth.

  According to a third aspect of the present invention, in the first or second aspect, the side wall of the lower half of the trench is inclined at an angle of 85 ° or less with respect to a virtual plane parallel to the substrate surface passing through the bottom of the trench. The lower half of the trench has a V-shaped vertical cross section. According to the present invention, during epitaxial growth, the supply of atomic layer steps in the lower half of the trench becomes active, and the growth rate at the bottom of the trench becomes relatively faster than the growth rate at the opening of the trench. Here, by setting the taper angle of the side wall of the lower half of the trench to 85 ° or less, the material gas is easily adsorbed on the side wall by the time it reaches the tip, or voids and dislocations are easily left even if the growth rate of the side wall increases. Can be prevented.

  According to a fourth aspect of the present invention, in the first aspect of the present invention, [10 ≦ d / w] is satisfied. According to the present invention, even in a deep trench having an aspect ratio of 10 or more, the supply of atomic layer steps in the lower half of the trench becomes active during epitaxial growth, and the growth rate of the trench bottom is lower than the growth rate of the trench opening. Is also relatively fast.

  According to a fifth aspect of the present invention, in the invention according to any one of the first to fourth aspects, the sidewall of the lower half of the trench or the sidewall of the lower half and the upper half of the trench forms a facet. Low index surface. If these sidewalls are not low-index faces that form facets, nucleation is likely to occur throughout the sidewalls, and nucleation is particularly active near the opening where the material gas concentration is high, and the epitaxial growth rate is increased and the epitaxial growth rate is increased. It becomes easier to close the part. According to the present invention, since the side wall is a facet and a stable crystal plane, nucleation is unlikely to occur, and the epitaxial growth rate becomes zero or extremely slow even near the opening where the material gas concentration is high. However, since the supply of atomic layer steps continues at the bottom of the trench, the epitaxial growth is fast, so that the trench can be filled with the epitaxial layer without closing the opening.

  According to a sixth aspect of the present invention, in the first aspect of the present invention, the temperature of the semiconductor substrate is reduced such that the temperature in the substrate decreases from the opening of the trench toward the bottom of the trench. The semiconductor of the second conductivity type is epitaxially grown in the trench by liquid phase growth or vapor phase growth at about 1000 ° C. or higher in the trench. According to the present invention, during epitaxial growth, in addition to the active supply of atomic layer steps in the lower half of the trench and the low temperature of the trench bottom, the growth rate of the trench bottom is reduced by the growth rate of the trench opening. Much faster than before.

  The invention according to claim 7 is the invention according to any one of claims 1 to 5, wherein the temperature of the semiconductor substrate is increased from the opening of the trench toward the bottom of the trench. And a semiconductor of the second conductivity type is epitaxially grown in the trench by vapor phase growth at about 1000 ° C. or less. According to the present invention, during epitaxial growth, in addition to the active supply of atomic layer steps in the lower half of the trench, the high temperature of the trench bottom allows the growth rate of the trench bottom to be reduced by the growth rate of the trench opening. Much faster than before.

  According to an eighth aspect of the present invention, in the first aspect of the present invention, a semiconductor of the second conductivity type is epitaxially grown in the trench by a low pressure CVD method. According to the present invention, during epitaxial growth by the low pressure CVD method, the supply of atomic layer steps in the lower half of the trench becomes active, and the growth rate at the bottom of the trench is relatively higher than the growth rate at the opening of the trench.

  According to a ninth aspect of the present invention, in the invention according to any one of the first to eighth aspects, a pipe is inserted into the trench from an opening, and a material gas for epitaxial growth is passed through the pipe to form a bottom portion of the trench. It is characterized in that it is supplied only to According to the present invention, during epitaxial growth, in addition to the active supply of atomic layer steps in the lower half of the trench, the growth gas concentration at the trench bottom becomes higher than the growth gas concentration at the trench opening. As a result, the growth rate at the bottom of the trench becomes much higher than the growth rate at the opening of the trench.

  According to another aspect of the present invention, there is provided a super junction semiconductor device having a structure in which a semiconductor of a second conductivity type is embedded in a trench provided in a semiconductor substrate of a first conductivity type. Forming a trench in the semiconductor substrate of the first conductivity type, and holding the semiconductor substrate so that the temperature in the substrate decreases from the opening of the trench toward the bottom of the trench, Epitaxially growing a second conductivity type semiconductor by liquid phase growth or vapor phase growth at about 1000 ° C. or higher in the trench. According to the present invention, at the time of epitaxial growth, the temperature at the bottom of the trench is low, so that the growth rate at the bottom of the trench is relatively higher than the growth rate at the opening of the trench.

  According to an eleventh aspect of the present invention, in manufacturing a super junction semiconductor element having a structure in which a semiconductor of a second conductivity type is embedded in a trench provided in a semiconductor substrate of a first conductivity type, the first conductivity type is used. Forming a trench in the semiconductor substrate, and holding the semiconductor substrate so that the temperature in the substrate increases from the opening of the trench toward the bottom of the trench. Epitaxially growing a semiconductor of the second conductivity type by vapor phase growth. According to the present invention, since the trench bottom is at a high temperature during epitaxial growth, the growth rate at the trench bottom is much higher than the growth rate at the trench opening.

  According to a twelfth aspect of the present invention, in the tenth or eleventh aspect, a semiconductor of the second conductivity type is epitaxially grown in the trench by a low pressure CVD method. According to the present invention, the growth rate of the trench bottom is relatively higher than the growth rate of the trench opening because the temperature at the bottom of the trench is low during the epitaxial growth by the low pressure CVD method.

  According to another aspect of the present invention, there is provided a super-junction semiconductor device having a structure in which a semiconductor of a second conductivity type is embedded in a trench provided in a semiconductor substrate of a first conductivity type. Forming a trench in a semiconductor substrate of the first conductivity type, inserting a pipe into the trench through an opening, and supplying a material gas for epitaxial growth only to the trench bottom through the pipe. And epitaxially growing a second conductivity type semiconductor in the trench. According to the present invention, at the time of epitaxial growth, the growth gas concentration at the trench bottom becomes higher than the growth gas concentration at the trench opening, so that the growth rate at the trench bottom is relatively higher than the growth rate at the trench opening. Become.

  According to the present invention, during epitaxial growth, the supply of atomic layer steps in the lower half of the trench becomes active, and the growth rate at the bottom of the trench becomes relatively faster than the growth rate at the opening of the trench. The trench can be filled with the semiconductor without causing a lattice shift. Therefore, a super-junction semiconductor element can be easily manufactured with good mass productivity.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Since the present invention relates to a method for manufacturing a super junction structure forming a breakdown voltage region, the structures of the source and drain and the manufacturing process thereof are arbitrary, and are omitted in the following description and the accompanying drawings. . Therefore, the present invention is applied to a MOSFET, an IGBT, a bipolar transistor, a GTO thyristor or a diode. In the following description, the first conductivity type is n-type, and the second conductivity type is p-type. The same applies to the opposite case.

Embodiment 1 FIG.
FIG. 1 is a vertical cross-sectional view showing the configuration of the super-joined structure manufactured by the manufacturing method according to the first embodiment of the present invention. As shown in FIG. 1, a plurality of trenches 3 having a depth d are formed in an n-type semiconductor substrate 2, and these trenches 3 are filled with an epitaxially grown p-type semiconductor 4. The trench 3 has a depth h from the boundary between the upper half portion 31 of the trench and the lower half portion 31 following the upper half portion 31 of the trench. And the lower half portion 36 of the trench.

  The side wall 32 of the trench upper half 31 is, for example, perpendicular to the substrate surface 21. That is, the taper angle of the side wall 32 of the trench upper half portion 31 is, for example, 90 °. The taper angle of the side wall 37 of the lower half portion 36 of the trench is, for example, 85 ° or less. The trench lower half portion 36 is formed such that its vertical cross section has, for example, a V-shape.

  Here, although not particularly limited, for example, the depth h of the lower trench portion 36 may be smaller than １ ／ of the depth d of the entire trench. That is, it is preferable to satisfy [h <d / 2]. Further, assuming that the opening width of the trench 3 on the substrate surface 21 is w, the general aspect ratio d / w of the trench 3 in the super junction structure is 10 or more. The sidewall 37 of the lower trench half 36 is preferably a low index surface forming a facet. More specifically, when silicon is used as a semiconductor material, facets are easily formed on the (1,1,1) plane, the (1,0,0) plane, the (3,1,1) plane, and the (4,1) plane. , 1,1) planes, and other than these, there are plane orientations in which facets are easily formed depending on conditions such as the substrate temperature during epitaxial growth, the degree of vacuum, or the supply pressure of material atoms.

  Next, a manufacturing method according to the first embodiment of the present invention will be described with reference to FIGS. First, an n-type semiconductor substrate 2 having a low resistance is prepared, and its surface 21 is covered with an insulating mask 5 such as an oxide film or a nitride film serving as a mask for epitaxial growth (FIG. 2). Then, using a mask (not shown), the insulating mask 5 is subjected to, for example, but not limited to, striping window opening (FIG. 3).

  The width of the window opening, that is, the trench opening width w, and the distance s between adjacent window openings are about 1 to 20 μm. Here, w and s may or may not be the same. However, in the final finished structure of the super junction structure shown in FIG. 1, the n-type semiconductor substrate 2 and the p-type semiconductor 4 are alternately formed in a columnar shape. It is important that the electric charge is balanced in the regions arranged in a row.

  Next, a region of the semiconductor substrate 2 that is not covered with the insulating mask 5 is etched from the substrate surface 21 to a depth [dh] by anisotropic etching to form the upper half portion 31 of the trench (FIG. 4). ). At that time, for example, a plasma etcher or RIE (reactive ion etching) is used as an etching method. The etching condition is such that the taper angle of the side wall 32 of the upper half portion 31 of the trench is 90 °.

  Subsequently, in a portion where the depth from the substrate surface 21 is [dh] to d, that is, in a portion having a depth h below the upper half portion 31 of the trench, the side wall 37 of the lower half portion 36 of the trench is laid down. Then, anisotropic etching is performed under the condition that the taper angle is less than 90 °, preferably 85 ° or less, to form the lower half portion 36 of the trench (FIG. 5). At this time, it is preferable that the trench lower half portion 36 has a vertical cross-sectional shape of, for example, a V shape, and that there is no plane parallel to the substrate surface between the opposing side walls 37. Here, the angle θ formed by the V-shape of the lower half portion 36 of the trench is preferably in the range of 10 °.

  This is because if the V-shaped tip has a sharp acute angle, the material gas passes through a small area and is not sufficiently supplied to the tip, and is adsorbed on the sidewall before reaching the tip, so that even if the growth rate of the sidewall increases, Voids and dislocations are likely to remain. Therefore, the taper angle of the side wall 37 of the lower half portion 36 of the trench needs to be 85 ° or less. Even if the side wall 32 exists above the side wall 37, the same problem as described above occurs if only the region of the side wall 37 is taken out. That is, the above problem occurs regardless of the presence or absence of the side wall 32. Therefore, even if the side wall 37 is easy to form a facet on a low index surface, it is not preferable that the taper angle of the side wall 37 is almost vertical.

  Next, a p-type semiconductor 4 is epitaxially grown inside the trench 3 (FIG. 6). When epitaxial growth is performed without removing the insulating mask 5 as described above, a gas having an etching effect is simultaneously flowed into the chamber in order to prevent polycrystal from adhering to the surface of the insulating mask 5. For example, when epitaxial growth is performed by low pressure CVD using silicon as a semiconductor material, a halogen such as chlorine (Cl) is mixed into a growth gas. Specifically, dichlorosilane (SiHCl) or trichlorosilane (SiHCl) may be used as a growth gas. Alternatively, silane (SiH) or disilane (SiH) is used as a growth gas, and an etching gas such as HCl or Cl is supplied into the chamber together with the gas.

  Here, the V-shaped structure portion (the portion surrounded by a circle in FIG. 6) at the bottom of the trench during the epitaxial growth is enlarged, and when viewed microscopically at the atomic layer level, as shown in FIG. There is an atomic layer step 41. The atomic layer step 41 has a nano-scale structure having a height of one or several crystal lattices. If the side wall 37 forms a stable facet, the atomic layer step 41 hardly exists on the side wall 37, and the atomic layer step 41 exists at the vertex of the V-shape at high density.

  In the atomic layer step 41, the crystal growth is fast because material atoms are actively incorporated into the crystal. As shown in FIG. 10, as the crystal growth proceeds, the region 42 newly fixed to the crystal expands, and the atomic layer step 41 advances. Then, even if one atomic layer step 41 advances, the next atomic layer step 41 is newly supplied from the top of the V-shape. Therefore, at the bottom of the trench, the incorporation of material atoms into the crystal is maintained in a vigorous state, so that the growth rate does not decrease (recess angle effect).

  FIG. 11 is a schematic cross-sectional view when the side wall is wider than the stable facet surface indicated by a dotted line, and FIG. 12 is a schematic cross-sectional view when the side wall 37 is also narrower than the facet surface. This is shown in FIG. In this case, since material atoms are actively taken in each step, epitaxial growth occurs simultaneously at all positions on the side wall 37. In addition, the higher the concentration of the material gas, the more the gas is taken in and the higher the epitaxial growth rate, which is disadvantageous for filling the trench.

  However, in the shapes as shown in FIGS. 11 and 12, if the existing atomic layer steps can take in the atoms and move forward to form the facets indicated by the dotted lines, the same shape as in FIG. The angle-of-incidence effect can be used. In order to form a facet from the state shown in FIGS. 11 and 12, anisotropic etching is performed using an etching gas, or a material gas is supplied in an initial stage of epitaxial growth, and epitaxial growth is performed at a low speed to form a stabilized surface. For example, it is possible to make it easier.

  On the other hand, in the crystal plane which is flat on the macro scale, that is, on the side wall 32 of the upper half portion 31 of the trench, since the existence density of the atomic layer steps 41 is extremely low, material atoms are hardly taken into the crystal. Further, even if one atomic layer step occurs on the side wall 32 of the trench upper half portion 31 due to, for example, damage to the surface, a new atomic layer step is not supplied to the trace where the atomic layer step has advanced. Therefore, the crystal growth does not continue. Therefore, the growth rate of the sidewall 32 of the upper half portion 31 of the trench is lower than that of the V-shaped structure at the bottom of the trench.

  As a result, as shown in FIG. 6, the epitaxially grown p-type semiconductor 4 becomes extremely thick at the bottom of the trench 3 and becomes thin at the trench opening. Therefore, as shown in FIG. 7, the inside of the trench 3 is filled with the p-type semiconductor 4 without leaving a void inside the trench. After the epitaxial growth is completed, the insulating mask 5 is removed, and the super junction structure having the configuration shown in FIG. 1 is completed. After that, a desired semiconductor element is completed by forming a source and a drain.

  According to the above-described first embodiment, the supply of the atomic layer steps 41 in the lower half portion 36 of the trench becomes active during the epitaxial growth, and the growth speed of the trench bottom is relatively faster than the growth speed of the trench opening. Therefore, the p-type semiconductor 4 gradually grows epitaxially from the trench bottom toward the trench opening, so that the inside of the trench 3 can be filled with the p-type semiconductor 4 without generating voids or crystal lattice shift. Therefore, a super-junction semiconductor element can be easily manufactured with good mass productivity.

  In the first embodiment, when epitaxially growing the p-type semiconductor 4 inside the trench 3, the insulating mask 5 may be removed in advance. In this case, as shown in FIG. 8, since the entire surface of the n-type semiconductor substrate 2 is covered with the p-type semiconductor 4, the p-type semiconductor 4 on the substrate surface 21 is polished and removed after the completion of the epitaxial growth. Then, the surface 21 of the n-type semiconductor substrate 2 may be exposed.

  Further, in the first embodiment, as shown in FIG. 13, lower trench portion 36 may be formed in a shape having a plane 38 parallel to substrate surface 21 between opposed side walls 37. In this case, at the initial stage of the epitaxial growth of the p-type semiconductor 4, a V-shape may be formed at the bottom of the trench as shown in FIG.

  In the first embodiment, the side wall 32 of the upper half portion 31 of the trench preferably has a plane orientation that forms a facet (a stabilized flat surface). Specifically, when silicon is used as a semiconductor material, facets are easily formed on the (1,1,1) plane, the (1,0,0) plane, the (3,1,1) plane, and the (4,1) plane. In addition to these, there are plane orientations in which facets are easily formed depending on conditions such as the substrate temperature, the degree of vacuum, or the supply pressure of material atoms during epitaxial growth. In this manner, an effect is obtained that the trench opening is more difficult to close during the epitaxial growth of the p-type semiconductor 4.

  14 and 15 show specific examples including the plane orientations of the wafer and the trench. 14 and 15, the plane orientations exposed before the formation of the epitaxial growth layer 4 are shown. In FIG. 14, a (1,1,0) wafer is used as the first semiconductor substrate 1, and the (0,0,1) plane is formed on the side wall 32 of the trench and the (1,1,1) plane is formed on the side wall 37. Each corresponds. Both are low index surfaces that form facets. The (0,0,1) plane is equivalent to the (1,0,0) plane, and the (1, -1,0) plane is equivalent to the (1,1,0) plane.

  In FIG. 15, a (1,0,0) wafer is used as the first semiconductor substrate 1, and the (0,1,1) plane is formed on the side wall 32 of the trench and the (1,1,1) plane is formed on the side wall 37. Corresponding. The (1,1,1) plane is a low index plane forming a facet. In this case, if a taper angle of about 2 to 3 ° is provided in advance on the side wall 32 and then the side wall 32 is laid down, rapid epitaxial growth in the opening can be canceled out, and the opening can be hardly blocked.

  In the first embodiment, the side wall 32 of the upper half portion 31 of the trench does not necessarily have to stand vertically at a taper angle of 90 ° and may be slightly laid, but the trench 3 has an aspect ratio d / w. Considering that it is 10 or more, the taper angle of the side wall 32 of the upper half portion 31 of the trench is desirably 85 ° or more. FIG. 16 shows a state of a cross-sectional photograph in the middle of filling the trench in which the side wall 32 of the upper half portion 31 of the trench is lying with the epitaxial growth layer. In FIG. 16, the initial trench shape is indicated by a dotted line. Thus, it can be seen that the trench in which the side wall 32 of the trench upper half 31 is lying is advantageous for filling.

  In the first embodiment, it is not always necessary to use RIE or plasma etcher when forming the upper half portion 31 of the trench. For example, wet etching with anisotropy may be performed. Specifically, for example, when a silicon (1,1,0) wafer is subjected to anisotropic etching using a mixed solution of KOH, isopropyl alcohol and water, a facet is formed on the trench side wall 32. The effect of easily exposing the (1,1,1) plane is obtained.

  Further, in the first embodiment, it is not always necessary to use RIE or a plasma etcher to form the trench lower half portion 36 having the above-described shape. For example, after forming the upper half portion 31 of the trench, the lower half portion 36 having a V-shaped vertical cross section can be formed by performing anisotropic etching with an etching gas. In this case, if the material of the semiconductor substrate 2 is silicon, HCl or Cl2 may be used as an etching gas.

Embodiment 2 FIG.
In the manufacturing method according to the second embodiment of the present invention, when a semiconductor is epitaxially grown in a trench, the growth rate of the trench bottom is reduced by providing a temperature difference between the trench opening and the trench bottom. This is a method of making the growth rate relatively higher than the growth rate. In the second embodiment, the vertical sectional shape of the trench bottom may be V-shaped or substantially V-shaped as in the first embodiment described above, or may be a planar shape parallel to the substrate surface. Good.

  For example, when the semiconductor material is silicon and epitaxial growth is performed by a low-pressure CVD method using dichlorosilane as a growth gas, the reaction rate at the bottom of the trench is increased every time the temperature of the bottom of the trench becomes 1 ° C. higher than the temperature of the opening of the trench. Increases by 2%. Therefore, the epitaxial growth at the bottom of the trench can be promoted by increasing the reaction rate at the bottom of the trench by making the temperature at the bottom of the trench higher than the temperature of the opening of the trench by, for example, 1 ° C. or more.

  In this manner, while the semiconductor substrate is held so that the temperature in the substrate decreases from the opening of the trench toward the bottom of the trench, the second phase is formed in the trench by liquid phase growth or vapor phase growth at about 1000 ° C. or higher. A conductive semiconductor is epitaxially grown. As a result, in addition to the active supply of atomic layer steps in the lower half of the trench during epitaxial growth, the growth rate of the trench bottom is higher than that of the trench opening due to the low temperature of the trench bottom. It is much faster.

  In a state where the semiconductor substrate is held so that the temperature in the substrate increases from the opening of the trench toward the bottom of the trench, a semiconductor of the second conductivity type is epitaxially grown in the trench by vapor phase growth at about 1000 ° C. or less. You may make it do. As a result, in addition to the active supply of atomic layer steps in the lower half of the trench during epitaxial growth, the high temperature at the bottom of the trench makes the growth rate at the bottom of the trench higher than that at the opening of the trench. It is much faster.

  Here, in liquid phase growth, the growth rate increases as the wafer temperature decreases, and the growth rate decreases as the temperature increases. Therefore, assuming that the trench is buried using liquid phase growth, it is preferable to lower the temperature at the bottom of the trench and increase the temperature at the opening of the trench.

  Further, in the vapor phase growth, at a low temperature of about 1000 ° C. or lower, the growth rate increases as the wafer temperature increases, and the growth rate decreases as the temperature decreases. Accordingly, assuming a relatively low temperature condition in the vapor phase growth, it is preferable to increase the temperature at the bottom of the trench and lower the temperature at the opening of the trench. On the other hand, at a high temperature of about 1000 ° C. or more, the etching effect by chlorine becomes dominant, so that the growth rate may be slower as the wafer temperature is higher, and may be higher as the temperature is lower. Therefore, assuming relatively high temperature conditions in the vapor phase growth, it is preferable to lower the temperature at the bottom of the trench and increase the temperature at the opening of the trench.

  Further, the adhesion probability (growth rate) η assuming an isotropic material such as polysilicon, ignoring the plane orientation dependence, is expressed by the following equation.

    η = Aexp (-E / RT)

  Here, E is activation energy (per mole), R is molar gas constant, and T is wafer temperature. E varies depending on the gas type and the experimental system. For example, in the case of silane (SiH), [E / R ≒ 2.0e4 K]. That is, η = Aexp (−2.0e4 / T).

  In a temperature region around T = 1200 K where epitaxial growth is performed, if the temperature increases by 1 ° C., the growth rate increases by about 2%. Thereby, the difference in growth rate between the trench opening and the trench bottom caused by the material supply amount can be canceled by the temperature difference.

  Specifically, as shown in FIG. 17, the internal structure of the CVD apparatus has a structure including a heater 71 for heating the front side of the semiconductor wafer 6 and a heater 72 for heating the back side of the semiconductor wafer 6, What is necessary is just to provide a difference between the output of the heater 71 on the front side and the output of the heater 72 on the back side. By doing so, a temperature gradient can be provided along the thickness direction of the wafer 6. However, if the temperature gradient is too large, a problem such as occurrence of slip dislocation occurs. Therefore, it is appropriate that the temperature gradient is 2000 ° C./cm or less.

  According to the second embodiment described above, during the epitaxial growth, since the trench bottom is at a high temperature, the growth rate of the trench bottom is relatively higher than the growth rate of the trench opening. Since the semiconductor gradually grows epitaxially toward it, the inside of the trench can be filled with the semiconductor without generating a void or a crystal lattice shift. Therefore, a super-junction semiconductor element can be easily manufactured with good mass productivity.

Embodiment 3 FIG.
In the manufacturing method according to the third embodiment of the present invention, when the semiconductor is epitaxially grown in the trench, the growth rate of the trench bottom is reduced by providing a concentration difference of the growth gas between the trench opening and the trench bottom. This is a method of making the growth rate relatively higher than the growth rate of the trench opening. In the third embodiment, the vertical sectional shape of the trench bottom may be V-shaped or substantially V-shaped as in the first embodiment described above, or may be a planar shape parallel to the substrate surface. Good.

  In the case where the growth gas is supplied by a diffusion process from the opening to the bottom of the trench as in the related art, the gas concentration becomes high at the trench opening, so that the epitaxial growth rate near the trench opening increases. I will. This is not preferable for filling the trench so as not to cause voids. Therefore, by supplying the growth gas directly to the trench bottom, the growth gas concentration is increased at the trench bottom and reduced at the trench opening.

  More specifically, as shown in FIG. 18, during epitaxial growth, a pipe 8 made of, for example, carbon nanotubes is inserted into the trench 3, and a growth gas is supplied to the trench 3 through the pipe 8. In this manner, as indicated by an arrow 9 in FIG. 18, the growth gas flows toward the bottom of the trench, turns at the bottom of the trench, and flows toward the opening of the trench. And becomes lower toward the trench opening.

  According to the third embodiment described above, during epitaxial growth, the growth gas concentration at the trench bottom becomes higher than the growth gas concentration at the trench opening, so that the growth rate at the trench bottom is higher than the growth rate at the trench opening. Since the semiconductor becomes relatively faster and the semiconductor gradually grows epitaxially from the bottom of the trench toward the opening of the trench, the inside of the trench 3 can be filled with the semiconductor without generating a void or a crystal lattice shift. Therefore, a super-junction semiconductor element can be easily manufactured with good mass productivity.

  In the above, the present invention is not limited to the above-described embodiments, but can be variously modified. For example, the pattern of the trench is not limited to the stripe shape, but may be a lattice shape or a column shape. Further, Embodiments 1 to 3 may be appropriately combined.

  As described above, the method for manufacturing a super junction semiconductor device according to the present invention is useful for manufacturing a super junction structure in which a second conductivity type semiconductor is epitaxially grown in a trench formed in a first conductivity type semiconductor substrate. In particular, by promoting the epitaxial growth of the semiconductor at the bottom of the trench and suppressing the growth at the opening of the trench, it is suitable for filling the trench with the semiconductor without generating a void or a crystal lattice shift. .

FIG. 2 is a longitudinal sectional view illustrating a configuration of a super-joined structure manufactured by the manufacturing method according to the first embodiment of the present invention. FIG. 2 is a vertical cross-sectional view showing a configuration of the super-joined structure manufactured by the manufacturing method according to the first embodiment of the present invention during manufacture. FIG. 2 is a vertical cross-sectional view showing a configuration of the super-joined structure manufactured by the manufacturing method according to the first embodiment of the present invention during manufacture. FIG. 2 is a vertical cross-sectional view showing a configuration of the super-joined structure manufactured by the manufacturing method according to the first embodiment of the present invention during manufacture. FIG. 2 is a vertical cross-sectional view showing a configuration of the super-joined structure manufactured by the manufacturing method according to the first embodiment of the present invention during manufacture. FIG. 2 is a vertical cross-sectional view showing a configuration of the super-joined structure manufactured by the manufacturing method according to the first embodiment of the present invention during manufacture. FIG. 2 is a vertical cross-sectional view showing a configuration of the super-joined structure manufactured by the manufacturing method according to the first embodiment of the present invention during manufacture. FIG. 2 is a vertical cross-sectional view showing a configuration of the super-joined structure manufactured by the manufacturing method according to the first embodiment of the present invention during manufacture. FIG. 2 is an enlarged longitudinal sectional view showing a V-shaped structure portion during the epitaxial growth of the super junction structure manufactured by the manufacturing method according to the first embodiment of the present invention. FIG. 2 is an enlarged longitudinal sectional view showing a V-shaped structure portion during the epitaxial growth of the super junction structure manufactured by the manufacturing method according to the first embodiment of the present invention. FIG. 2 is an enlarged longitudinal sectional view showing a V-shaped structure portion during the epitaxial growth of the super junction structure manufactured by the manufacturing method according to the first embodiment of the present invention. FIG. 2 is an enlarged longitudinal sectional view showing a V-shaped structure portion during the epitaxial growth of the super junction structure manufactured by the manufacturing method according to the first embodiment of the present invention. FIG. 4 is a longitudinal sectional view showing a configuration in which a plane exists at the bottom of the trench in the configuration of the super junction structure manufactured by the manufacturing method according to the first embodiment of the present invention; FIG. 4 is an explanatory diagram showing a plane orientation exposed before forming an epitaxial growth layer of a super junction structure manufactured by the manufacturing method according to the first embodiment of the present invention. FIG. 4 is an explanatory diagram showing a plane orientation exposed before forming an epitaxial growth layer of a super junction structure manufactured by the manufacturing method according to the first embodiment of the present invention. It is explanatory drawing which shows the mode of the cross-section photograph in the middle of filling the trench in which the side wall 32 of the trench upper half part 31 is lying with an epitaxial growth layer. FIG. 9 is a schematic diagram for explaining the manufacturing method according to the second embodiment of the present invention. FIG. 9 is a schematic diagram for explaining the manufacturing method according to the third embodiment of the present invention. FIG. 11 is a longitudinal sectional view schematically showing a state in which a thick epitaxial growth layer is formed in a trench opening by a conventional method for manufacturing a super junction semiconductor element. It is a longitudinal cross-sectional view which shows typically the semiconductor substrate in which the vertical cross-sectional shape formed the V-shaped trench in the manufacturing method of the conventional super junction semiconductor element. It is a longitudinal cross-sectional view which shows typically the state where the vertical cross-sectional shape was filled with the epitaxial growth layer in the manufacturing method of the conventional super junction semiconductor element.

Explanation of reference numerals

2 Semiconductor substrate of first conductivity type 3 Trench 4 Semiconductor of second conductivity type 8 Pipe 21 Substrate surface 31 Upper half of trench 32 Side wall of upper half of trench 36 Lower half of trench 37 Side wall of lower half of trench

Claims (13)

In manufacturing a superjunction semiconductor device having a structure in which a semiconductor of the second conductivity type is embedded in a trench having a depth of d and an opening width of w on the substrate surface provided in a semiconductor substrate of the first conductivity type. ,
Forming, on a semiconductor substrate of the first conductivity type, an upper half of a trench whose side walls are perpendicular or substantially perpendicular to the substrate surface;
Subsequent to the upper half of the trench, a lower side wall is formed, the side wall of which is more gradually inclined than the side wall of the upper half of the trench, and whose depth from the boundary with the upper half of the trench is h. Process and
Epitaxially growing a semiconductor of the second conductivity type in a trench formed by the upper half of the trench and the lower half of the trench;
A method for manufacturing a super-junction semiconductor device, comprising:   2. The method according to claim 1, wherein h <d / 2 is satisfied.   Side walls of the lower half of the trench are inclined at an angle of 85 ° or less with respect to an imaginary plane parallel to the substrate surface passing through the bottom of the trench, and the lower half of the trench has a V-shaped vertical sectional shape. The method for manufacturing a super junction semiconductor device according to claim 1, wherein:   The method for manufacturing a super junction semiconductor device according to claim 1, wherein [10 ≦ d / w] is satisfied.   The ultra-thin surface according to any one of claims 1 to 4, wherein a sidewall of the lower half of the trench or a sidewall of the lower half and the upper half of the trench is a low index surface forming a facet. A method for manufacturing a junction semiconductor device.   In a state where the semiconductor substrate is held so that the temperature in the substrate decreases from the opening of the trench toward the bottom of the trench, the second conductive layer is formed in the trench by liquid phase growth or vapor phase growth of about 1000 ° C. or more. The method for manufacturing a super-junction semiconductor device according to claim 1, wherein a semiconductor of a type is epitaxially grown.   In a state where the semiconductor substrate is held so that the temperature in the substrate increases from the opening of the trench toward the bottom of the trench, a semiconductor of the second conductivity type is formed in the trench by vapor phase growth at about 1000 ° C. or less. The method for manufacturing a super junction semiconductor device according to claim 1, wherein the super junction semiconductor device is grown epitaxially.   8. The method according to claim 1, wherein a semiconductor of a second conductivity type is epitaxially grown in the trench by a low pressure CVD method.   The super-junction semiconductor according to any one of claims 1 to 8, wherein a pipe is inserted into the trench from an opening, and a material gas for epitaxial growth is supplied only to the bottom of the trench through the pipe. Device manufacturing method. In manufacturing a super junction semiconductor device having a structure in which a semiconductor of a second conductivity type is embedded in a trench provided in a semiconductor substrate of a first conductivity type,
Forming a trench in a semiconductor substrate of a first conductivity type;
In a state where the semiconductor substrate is held so that the temperature in the substrate decreases from the opening of the trench toward the bottom of the trench, the second conductive layer is formed in the trench by liquid phase growth or vapor phase growth of about 1000 ° C. or more. Epitaxially growing a semiconductor of a mold type;
A method for manufacturing a super-junction semiconductor device, comprising: In manufacturing a super junction semiconductor device having a structure in which a semiconductor of a second conductivity type is embedded in a trench provided in a semiconductor substrate of a first conductivity type,
Forming a trench in a semiconductor substrate of a first conductivity type;
In a state where the semiconductor substrate is held so that the temperature in the substrate increases from the opening of the trench toward the bottom of the trench, a semiconductor of the second conductivity type is formed in the trench by vapor phase growth at about 1000 ° C. or less. A step of epitaxial growth;
A method for manufacturing a super-junction semiconductor device, comprising:   The method according to claim 10, wherein a semiconductor of a second conductivity type is epitaxially grown in the trench by a low-pressure CVD method. In manufacturing a super junction semiconductor device having a structure in which a semiconductor of a second conductivity type is embedded in a trench provided in a semiconductor substrate of a first conductivity type,
Forming a trench in the semiconductor substrate of the first conductivity type;
Inserting a pipe into the trench from an opening, and epitaxially growing a second conductivity type semiconductor in the trench while supplying a material gas for epitaxial growth only to the bottom of the trench through the pipe;
A method for manufacturing a super-junction semiconductor device, comprising:

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