JP7318553B2 - Method for manufacturing switching element - Google Patents

Description

The technology disclosed in this specification relates to a method for manufacturing a switching element.

A switching element disclosed in Patent Document 1 has a trench provided on the surface of a semiconductor substrate. A gate electrode is provided in the trench. The trench extends through the p-type body region to the n-type drift region. A bottom p-type region is provided in contact with the bottom surface of the trench. By providing the bottom p-type region, it is possible to increase the withstand voltage of the switching element.

JP 2005-252204 A

In the manufacturing method of the switching element of Patent Document 1, first, a body region is formed on the drift region. Next, a trench is formed in the surface of the semiconductor substrate to reach the drift region through the body region. Next, a p-type impurity is implanted into the bottom surface of the trench to form a bottom p-type region in contact with the bottom surface of the trench. After that, a gate insulating film and a gate electrode are formed in the trench. In this manufacturing method, when the p-type impurity is implanted into the bottom surface of the trench, the p-type impurity is also implanted into the side surface of the trench. As a result, crystal defects are formed in the body region near the sidewalls of the trench. A body region near the side of the trench is a region where a channel is formed when the switching element is turned on. The formation of crystal defects in this region increases the channel resistance. This specification proposes a manufacturing method of a switching element having a bottom p-type region, which is capable of suppressing the formation of crystal defects in the body region near the side surface of the trench.

A method for manufacturing a switching element, comprising: forming a first trench in a surface of a semiconductor substrate having an n-type semiconductor layer where the n-type semiconductor layer is exposed; and epitaxially growing a p-type semiconductor layer on the n-type semiconductor layer; and forming a second trench wider than the first trench in the surface of the semiconductor substrate above the first trench. separating the p-type semiconductor layer under the second trench from the p-type semiconductor layer on the n-type semiconductor layer; forming a gate insulating film in the second trench; forming a gate electrode insulated from the n-type semiconductor layer and the p-type semiconductor layer by the gate insulating film.

In this manufacturing method, a p-type semiconductor layer is epitaxially grown in the first trench and on the n-type semiconductor layer, and then a second trench is formed so that the p-type semiconductor layer below the second trench is grown on the n-type semiconductor layer. is separated from the p-type semiconductor layer of The p-type semiconductor layer below the second trench becomes the bottom p-type region. Also, the p-type semiconductor layer on the n-type semiconductor layer becomes a body region. In this manufacturing method, the bottom p-type region is formed by epitaxial growth rather than by ion implantation, so ions are not implanted into the body region when forming the bottom p-type region. Therefore, it is possible to suppress the formation of crystal defects in the body region near the side surfaces of the trench.

Sectional drawing of FET. FIG. 2 is an explanatory diagram of the manufacturing method of Example 1; FIG. 2 is an explanatory diagram of the manufacturing method of Example 1; FIG. 2 is an explanatory diagram of the manufacturing method of Example 1; FIG. 2 is an explanatory diagram of the manufacturing method of Example 1; FIG. 2 is an explanatory diagram of the manufacturing method of Example 1; Explanatory drawing of the manufacturing method of Example 2. FIG. Explanatory drawing of the manufacturing method of Example 2. FIG. Explanatory drawing of the manufacturing method of Example 2. FIG.

Additional features of the technology disclosed herein are listed below. Each feature listed below is independently useful.

An example manufacturing method disclosed in this specification may further include a step of epitaxially growing a second n-type semiconductor layer on the p-type semiconductor layer after the step of epitaxially growing the p-type semiconductor layer. In forming a second trench, the second trench is formed so as to penetrate the second n-type semiconductor layer.

According to this configuration, the second n-type semiconductor layer can function as an electron supply layer (for example, source region).

In one example of the manufacturing method disclosed in this specification, the step of epitaxially growing the p-type semiconductor layer to the step of epitaxially growing the second n-type semiconductor layer may be performed in a common chamber.

According to this configuration, the p-type semiconductor layer and the second n-type semiconductor layer can be formed with higher quality.

FIG. 1 shows an FET (field effect transistor) 10 manufactured by the manufacturing method of the embodiment. The FET 10 has a silicon carbide substrate 12 (hereinafter referred to as SiC substrate 12). A trench 14 is formed in the upper surface of the SiC substrate 12 . Although only one trench 14 is shown in FIG. 1 , a plurality of trenches 14 are formed in the upper surface of the SiC substrate 12 . The inner surface of trench 14 is covered with gate insulating film 16 . A gate electrode 18 is arranged in the trench 14 . Gate electrode 18 is insulated from SiC substrate 12 by gate insulating film 16 . An upper surface of the gate electrode 18 is covered with an interlayer insulating film 20 . The upper surface of SiC substrate 12 and the surface of interlayer insulating film 20 are covered with source electrode 22 . Gate electrode 18 is insulated from source electrode 22 by interlayer insulating film 20 . The lower surface of SiC substrate 12 is covered with drain electrode 24 .

SiC substrate 12 has source region 30 , contact region 32 , body region 34 , drift region 36 , bottom p-type region 38 and drain region 40 . Source region 30 is an n-type region and is in contact with source electrode 22 and gate insulating film 16 . Contact region 32 is a p-type region and is in contact with source electrode 22 . The body region 34 is a p-type region having a p-type impurity concentration lower than that of the contact region 32 . Body region 34 is located below source region 30 and contact region 32 . Body region 34 is in contact with gate insulating film 16 below source region 30 . Drift region 36 is an n-type region and is arranged below body region 34 . Drift region 36 is separated from source region 30 by body region 34 . The drift region 36 is in contact with the gate insulating film 16 below the body region 34 . Bottom p-type region 38 is in contact with gate insulating film 16 at the bottom of trench 14 . Bottom p-type region 38 is surrounded by drift region 36 . Bottom p-type region 38 is separated from body region 34 by drift region 36 . The drain region 40 is an n-type region having a higher n-type impurity concentration than the drift region 36 . Drain region 40 is located below drift region 36 . The drain region 40 contacts the drain electrode 24 .

When the FET 10 is in use, a potential higher than that of the source electrode 22 is applied to the drain electrode 24 . When a potential equal to or higher than the gate threshold is applied to the gate electrode 18, a channel is formed in the body region 34 near the gate insulating film 16. FIG. As a result, electrons flow from source region 30 through channel and drift region 36 to drain region 40 . That is, the FET 10 is turned on. When the potential of gate electrode 18 is lowered below the gate threshold, the channel disappears and FET 10 is turned off. When FET 10 is turned off, a depletion layer spreads from body region 34 to drift region 36 . A depletion layer also extends from the bottom p-type region 38 to the drift region 36 . By spreading the depletion layer in the drift region 36 in this way, the insulation of the drift region 36 is ensured. In this FET, since the depletion layer spreads from the bottom p-type region 38 to the drift region 36, electric field concentration near the lower end of the trench 14 is suppressed. Therefore, the FET 10 has high withstand voltage performance.

Next, the method of Example 1 for manufacturing the FET 10 will be described. In the manufacturing method of Example 1, first, as shown in FIG. 2, the SiC substrate 12 in which the drift region 36 is laminated on the drain region 40 is prepared. For example, the SiC substrate 12 of FIG. 2 can be obtained by epitaxially growing the drift region 36 on the drain region 40 .

Next, as shown in FIG. 3, trenches 50 are formed in the upper surface of SiC substrate 12 by selectively etching the upper surface of SiC substrate 12 . Here, trench 50 is formed so that trench 50 does not reach drain region 40 .

Next, as shown in FIG. 4, a p-type semiconductor layer 52 made of SiC is epitaxially grown on the inner surface of the trench 50 and the upper surface of the drift region 36 . Here, the p-type semiconductor layer 52 is formed so that the inside of the trench 50 is filled with the p-type semiconductor layer 52 without gaps.

Next, n-type and p-type impurity ions are selectively implanted into the surface layer portion of the p-type semiconductor layer 52 (the portion constituting the upper surface of the SiC substrate 12). As a result, as shown in FIG. 5, the n-type source region 30 and the high-concentration p-type contact region 32 are formed in the surface layer portion of the p-type semiconductor layer 52 .

Next, as shown in FIG. 6, trenches 14 are formed in the upper surface of SiC substrate 12 by selectively etching the upper surface of SiC substrate 12 . Here, trenches 14 are formed in the upper surface of SiC substrate 12 above trenches 50 . Also, the trench 14 is formed so that the width of the trench 14 is wider than the width of the trench 50 . Further, the trench 14 is formed so that the trench 14 penetrates the source region 30 and the p-type semiconductor layer 52 (more specifically, the p-type semiconductor layer 52 formed in the trench 50) remains under the trench 14. Form. By forming the trenches 14 in this way, the p-type semiconductor layer 52 is formed on the lower portion of the trenches 14 and the portions laterally adjacent to the trenches 14 (that is, on the upper surface of the drift region 36). part). The p-type semiconductor layer 52 at the bottom of the trench 14 is the bottom p-type region 38 . The p-type semiconductor layer 52 laterally adjacent to the trench 14 is the body region 34 .

Next, as shown in FIG. 1, a gate insulating film 16 and a gate electrode 18 are formed within the trench 14 . Next, an interlayer insulating film 20 is formed on the gate electrode 18 . Next, source electrode 22 is formed to cover the upper surface of SiC substrate 12 and interlayer insulating film 20 . Next, a drain electrode 24 is formed on the lower surface of the SiC substrate 12 . Through the above steps, the FET 10 shown in FIG. 1 is completed.

As described above, in the manufacturing method of Example 1, the bottom p-type region 38 is formed by epitaxial growth instead of ion implantation. Therefore, in this manufacturing method, there is no step of implanting ions into the bottom surface of trench 14 . Therefore, ions are not implanted into the side surfaces of the trench 14 either. Therefore, the formation of crystal defects in the body region 34 (that is, the region where the channel is formed) near the side surface of the trench 14 is suppressed. Therefore, the FET 10 manufactured by this manufacturing method has a low channel resistance. In addition, variations in gate threshold value due to crystal defects are also suppressed.

Further, in the conventional manufacturing method (manufacturing method for forming the bottom p-type region by implanting ions into the bottom of the trench), it was necessary to implant ions into the bottom p-type region and the body region respectively. In contrast, in the manufacturing method of Example 1, the bottom p-type region 38 and the body region 34 can be simultaneously formed by epitaxial growth, so the number of steps can be reduced.

Next, the method of Example 2 which manufactures FET10 is demonstrated. In the manufacturing method of Example 2, processing is performed up to the state shown in FIG. 3 in the same manner as in the manufacturing method of Example 1. Next, as shown in FIG. 7, a p-type semiconductor layer 52 made of SiC is epitaxially grown on the inner surface of the trench 50 and the upper surface of the drift region 36 . Here, the p-type semiconductor layer 52 is formed so that the inside of the trench 50 is filled with the p-type semiconductor layer 52 without gaps. Moreover, in Example 2, the p-type semiconductor layer 52 having a smaller thickness than that in Example 1 is formed.

Next, as shown in FIG. 8, an n-type semiconductor layer 54 made of SiC is epitaxially grown on the p-type semiconductor layer 52 .

Next, as shown in FIG. 9, a contact region 32 is formed by implanting a p-type impurity into a portion of the surface of the n-type semiconductor layer 54 . The remaining n-type semiconductor layer 54 is the source region 30 .

Trench 14 is then formed through source region 30 to isolate bottom p-type region 38 from body region 34, as shown in FIG. After that, the FET 10 is completed by processing in the same manner as in the first embodiment.

As described above, the bottom p-type region 38 is also formed by epitaxial growth in the manufacturing method of the second embodiment. Therefore, the formation of crystal defects in the body region 34 (that is, the region where the channel is formed) near the side surface of the trench 14 is suppressed. Therefore, the FET 10 manufactured by this manufacturing method has a low channel resistance. In addition, variations in gate threshold value due to crystal defects are also suppressed.

In addition, in Example 2, the step of epitaxially growing the p-type semiconductor layer 52 and the step of epitaxially growing the n-type semiconductor layer 54 can be performed in a common chamber. That is, the n-type semiconductor layer 54 can be epitaxially grown in the same chamber without removing the SiC substrate 12 from the chamber after epitaxially growing the p-type semiconductor layer 52 . Thereby, the p-type semiconductor layer 52 and the n-type semiconductor layer 54 can be formed with high quality. Alternatively, the p-type semiconductor layer 52 and the n-type semiconductor layer 54 may be formed by one epitaxial growth process. That is, the p-type semiconductor layer 52 and the n-type semiconductor layer 54 may be formed continuously by switching the material gas from p-type to n-type during the epitaxial growth process. Also by this method, the p-type semiconductor layer 52 and the n-type semiconductor layer 54 can be formed with high quality. Moreover, according to this method, the number of steps can be further reduced.

Although the embodiments have been described in detail above, they are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or in the drawings exhibit technical usefulness either singly or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques exemplified in this specification or drawings simultaneously achieve a plurality of purposes, and achieving one of them has technical utility in itself.

10: FETs
12: SiC substrate 14: trench 16: gate insulating film 18: gate electrode 20: interlayer insulating film 22: source electrode 24: drain electrode 30: source region 32: contact region 34: body region 36: drift region 38: bottom p-type Region 40: drain region 50: trench 52: p-type semiconductor layer 54: n-type semiconductor layer

Claims (1)

A method for manufacturing a switching element,
forming a first trench in a surface of a semiconductor substrate having an n-type semiconductor layer where the n-type semiconductor layer is exposed;
epitaxially growing a p-type semiconductor layer in the first trench and on the n-type semiconductor layer so as to fill the first trench;
By forming a second trench wider than the first trench in the surface of the semiconductor substrate above the first trench, the p-type semiconductor layer below the second trench is replaced with the n-type semiconductor layer. separating from the p-type semiconductor layer above;
forming a gate insulating film in the second trench;
forming a gate electrode in the second trench insulated from the n-type semiconductor layer and the p-type semiconductor layer by the gate insulating film;
A manufacturing method having

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