JP2020096080A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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JP2020096080A
JP2020096080A JP2018232913A JP2018232913A JP2020096080A JP 2020096080 A JP2020096080 A JP 2020096080A JP 2018232913 A JP2018232913 A JP 2018232913A JP 2018232913 A JP2018232913 A JP 2018232913A JP 2020096080 A JP2020096080 A JP 2020096080A
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semiconductor substrate
mask layer
forming
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清水　智子
Tomoko Shimizu
智子 清水
渡辺　行彦
Yukihiko Watanabe
行彦 渡辺
泰 浦上
Yasushi Uragami
泰 浦上
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Toyota Motor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution

Abstract

To provide a method of manufacturing a semiconductor device for suppressing formation of a large amount of crystal defects and also suppressing manufacturing costs.SOLUTION: The method of manufacturing a semiconductor device includes the steps of: forming a JFET resistance reduction region at a position in contact with both a drift region and a body region by ion-implanting a first conduction type impurity toward a first range of a semiconductor substrate surface exposed from an opening of a second mask layer; and forming a source region on the body region by ion-implanting the first conduction impurity towards the first range of the semiconductor substrate surface exposed through the opening of the second mask layer.SELECTED DRAWING: Figure 1

Description

本明細書が開示する技術は、トレンチゲートを備える半導体装置の製造方法に関する。 The technique disclosed in the present specification relates to a method for manufacturing a semiconductor device including a trench gate.

特許文献１は、トレンチゲートの底面を覆うように設けられているｐ型の電界緩和領域を備えている半導体装置を開示する。このような電界緩和領域は、トレンチゲートの底面に集中する電界を緩和することができる。これにより、半導体装置の耐圧が向上する。 Patent Document 1 discloses a semiconductor device including a p-type electric field relaxation region provided so as to cover the bottom surface of the trench gate. Such an electric field relaxation region can relax the electric field concentrated on the bottom surface of the trench gate. This improves the breakdown voltage of the semiconductor device.

このようなｐ型の電界緩和領域が設けられていると、ｐ型の電界緩和領域からｎ型のドリフト領域内に伸びてくる空乏層によって抵抗が増加すること、即ち、ＪＦＥＴ抵抗の増加が懸念される。このようなＪＦＥＴ抵抗の増加を抑えるために、特許文献１は、ドリフト領域よりも不純物濃度が濃いｎ型のＪＦＥＴ抵抗低減領域（特許文献１では、電流分散領域と称される）を設ける技術を提案する。ＪＦＥＴ抵抗低減領域が設けられていると、電界緩和領域から伸びてくる空乏層を迂回するように電流が流れることができるので、ＪＦＥＴ抵抗の増加が抑えられる。 If such a p-type electric field relaxation region is provided, there is concern that the depletion layer extending from the p-type electric field relaxation region into the n-type drift region may increase the resistance, that is, the JFET resistance may increase. To be done. In order to suppress such an increase in JFET resistance, Patent Document 1 discloses a technique of providing an n-type JFET resistance reduction region (referred to as a current dispersion region in Patent Document 1) having an impurity concentration higher than that of the drift region. suggest. When the JFET resistance reduction region is provided, a current can flow so as to bypass the depletion layer extending from the electric field relaxation region, so that an increase in JFET resistance can be suppressed.

特開２０１７−５０５１６号公報JP, 2017-50516, A

このような半導体装置を製造する場合、製造コストを抑えるために、ｐ型のボディ領域とｐ型のボディコンタクト領域とｎ型のＪＦＥＴ抵抗低減領域とｎ型のソース領域の各々をイオン注入によって形成することが望まれる。この場合、ボディコンタクト領域をイオン注入で形成するとき、多量のｐ型の不純物をイオン注入しなければならない。このため、ボディコンタクト領域の下方には、イオン注入時に形成された結晶欠陥が多量に存在することとなる。ボディコンタクト領域の下方には、ボディ領域が設けられている。このボディ領域をイオン注入で形成するときも、結晶欠陥が形成される。さらに、ボディコンタクト領域の下方であってドリフト領域とボディ領域の間にＪＦＥＴ抵抗低減領域が設けられていると、そのＪＦＥＴ抵抗低減領域をイオン注入で形成するときに形成される結晶欠陥も、ボディコンタクト領域の下方に形成されることとなる。 When manufacturing such a semiconductor device, in order to suppress the manufacturing cost, each of a p-type body region, a p-type body contact region, an n-type JFET resistance reduction region, and an n-type source region is formed by ion implantation. It is desirable to do. In this case, when forming the body contact region by ion implantation, a large amount of p-type impurities must be ion-implanted. Therefore, a large amount of crystal defects formed during the ion implantation exist below the body contact region. A body region is provided below the body contact region. Crystal defects are also formed when this body region is formed by ion implantation. Further, when the JFET resistance reducing region is provided below the body contact region and between the drift region and the body region, the crystal defects formed when the JFET resistance reducing region is formed by ion implantation are also included in the body. It will be formed below the contact region.

このように、ｐ型のボディ領域とｐ型のボディコンタクト領域とｎ型のＪＦＥＴ抵抗低減領域とｎ型のソース領域の各々をイオン注入によって形成する場合、ボディコンタクト領域の下方に多量の結晶欠陥が形成される可能性がある。このような多量の結晶欠陥は、リーク電流が増大する原因となる。本願明細書は、多量の結晶欠陥の形成が抑えられるとともに、製造コストも抑えられた半導体装置の製造方法を提供する。 As described above, when each of the p-type body region, the p-type body contact region, the n-type JFET resistance reduction region, and the n-type source region is formed by ion implantation, a large number of crystal defects are formed below the body contact region. May be formed. Such a large amount of crystal defects causes an increase in leak current. The present specification provides a method for manufacturing a semiconductor device in which a large number of crystal defects are suppressed and the manufacturing cost is also suppressed.

本明細書で開示する半導体装置の製造方法は、第１導電型のドリフト領域が表面に露出する半導体基板を準備する工程と、前記半導体基板の前記表面に向けて第２導電型不純物をイオン注入し、前記ドリフト領域上にボディ領域を形成する工程と、前記半導体基板の前記表面に第１マスク層を成膜する工程であって、前記第１マスク層は、前記半導体基板の前記表面の第１範囲を被膜し、前記半導体基板の前記表面の前記第１範囲とは異なる第２範囲に開口を有する、第１マスク層を成膜する工程と、前記第１マスク層の前記開口から露出する前記半導体基板の前記表面の前記第２範囲に向けて第２導電型不純物をイオン注入し、前記ボディ領域上にボディコンタクト領域を形成する工程と、前記半導体基板の前記表面に第２マスク層を成膜する工程であって、前記第２マスク層は、前記半導体基板の前記表面の前記第２範囲を被膜し、前記半導体基板の前記表面の前記第１範囲に開口を有する、第２マスク層を成膜する工程と、前記第２マスク層の前記開口から露出する前記半導体基板の前記表面の前記第１範囲に向けて第１導電型不純物をイオン注入し、前記ドリフト領域と前記ボディ領域の双方に接する位置にＪＦＥＴ抵抗低減領域を形成する工程と、前記第２マスク層の前記開口から露出する前記半導体基板の前記表面の前記第１範囲に向けて第１導電型不純物をイオン注入し、前記ボディ領域上にソース領域を形成する工程と、前記半導体基板の前記表面の前記第１範囲において、前記ソース領域と前記ボディ領域と前記ＪＦＥＴ抵抗低減領域を貫通するトレンチゲートを形成する工程と、を備えることができる。なお、ＪＦＥＴ抵抗低減領域を形成する工程とソース領域を形成する工程を実施する順序は特に限定されない。 A method of manufacturing a semiconductor device disclosed in the present specification includes a step of preparing a semiconductor substrate in which a drift region of the first conductivity type is exposed on the surface, and ion implantation of impurities of the second conductivity type toward the surface of the semiconductor substrate. Then, a step of forming a body region on the drift region and a step of forming a first mask layer on the surface of the semiconductor substrate, wherein the first mask layer is the first mask layer on the surface of the semiconductor substrate. A step of forming a first mask layer which covers one area and has an opening in a second area different from the first area of the surface of the semiconductor substrate; and exposing from the opening of the first mask layer. Forming a body contact region on the body region by ion-implanting a second conductivity type impurity toward the second region of the surface of the semiconductor substrate; and forming a second mask layer on the surface of the semiconductor substrate. In the step of forming a film, the second mask layer covers the second area of the surface of the semiconductor substrate, and has an opening in the first area of the surface of the semiconductor substrate. A step of forming a film, and ion-implanting a first conductivity type impurity toward the first range of the surface of the semiconductor substrate exposed from the opening of the second mask layer to form the drift region and the body region. Forming a JFET resistance reduction region at a position in contact with both, and ion-implanting a first conductivity type impurity toward the first range of the surface of the semiconductor substrate exposed from the opening of the second mask layer, Forming a source region on the body region; forming a trench gate penetrating the source region, the body region, and the JFET resistance reducing region in the first range of the surface of the semiconductor substrate; Can be provided. The order of performing the step of forming the JFET resistance reduction region and the step of forming the source region is not particularly limited.

上記製造方法によると、前記ＪＦＥＴ抵抗低減領域は、前記ソース領域の下方に選択的に形成され、前記ボディコンタクト領域の下方には形成されない。このため、前記ＪＦＥＴ抵抗低減領域をイオン注入で形成するときに形成される結晶欠陥は、前記ボディコンタクト領域の下方に形成されない。これにより、前記ボディコンタクト領域の下方に多量の結晶欠陥が形成されることが抑えられる。さらに、上記製造方法によると、前記ソース領域と前記ＪＦＥＴ抵抗低減領域を共通の第２マスク層を用いて形成することができる。これにより、上記製造方法では、製造コストが抑えられる。 According to the above manufacturing method, the JFET resistance reducing region is selectively formed below the source region and is not formed below the body contact region. Therefore, crystal defects formed when the JFET resistance reduction region is formed by ion implantation are not formed below the body contact region. This suppresses formation of a large number of crystal defects below the body contact region. Further, according to the above manufacturing method, the source region and the JFET resistance reducing region can be formed using the common second mask layer. As a result, the manufacturing cost can be suppressed in the above manufacturing method.

本実施形態の半導体装置の要部断面図を模式的に示す。1 schematically shows a cross-sectional view of a main part of a semiconductor device of this embodiment. 本実施形態の半導体装置の製造過程の要部断面図を模式的に示す。FIG. 3 is a schematic sectional view showing an essential part of a manufacturing process of the semiconductor device of this embodiment. 本実施形態の半導体装置の製造過程の要部断面図を模式的に示す。FIG. 3 is a schematic sectional view showing an essential part of a manufacturing process of the semiconductor device of this embodiment. 本実施形態の半導体装置の製造過程の要部断面図を模式的に示す。FIG. 3 is a schematic sectional view showing an essential part of a manufacturing process of the semiconductor device of this embodiment. 本実施形態の半導体装置の製造過程の要部断面図を模式的に示す。FIG. 3 is a schematic sectional view showing an essential part of a manufacturing process of the semiconductor device of this embodiment. 本実施形態の半導体装置の製造過程の要部断面図を模式的に示す。FIG. 3 is a schematic sectional view showing an essential part of a manufacturing process of the semiconductor device of this embodiment. 本実施形態の半導体装置の製造過程の要部断面図を模式的に示す。FIG. 3 is a schematic sectional view showing an essential part of a manufacturing process of the semiconductor device of this embodiment. 本実施形態の半導体装置の製造過程の要部断面図を模式的に示す。FIG. 3 is a schematic sectional view showing an essential part of a manufacturing process of the semiconductor device of this embodiment. 本実施形態の半導体装置の製造過程の要部断面図を模式的に示す。FIG. 3 is a schematic sectional view showing an essential part of a manufacturing process of the semiconductor device of this embodiment. 本実施形態の半導体装置の製造過程の要部断面図を模式的に示す。FIG. 3 is a schematic sectional view showing an essential part of a manufacturing process of the semiconductor device of this embodiment.

図１に示されるように、半導体装置１は、ＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）と称されるパワー半導体素子であり、半導体基板１０、半導体基板１０の裏面を被覆するドレイン電極２２、半導体基板１０の表面を被覆するソース電極２４及び半導体基板１０の表層部に設けられているトレンチゲート３０を備えている。トレンチゲート３０は、半導体基板１０の表面に対して直交する方向から観測したときに、例えばストライプ状に配置されている。 As shown in FIG. 1, a semiconductor device 1 is a power semiconductor element called a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and includes a semiconductor substrate 10, a drain electrode 22 that covers the back surface of the semiconductor substrate 10, and a semiconductor substrate. A source electrode 24 covering the surface of the semiconductor substrate 10 and a trench gate 30 provided in the surface layer portion of the semiconductor substrate 10 are provided. The trench gates 30 are arranged, for example, in a stripe shape when observed from a direction orthogonal to the surface of the semiconductor substrate 10.

半導体基板１０は、炭化珪素（ＳｉＣ）を材料とする基板であり、ｎ+型のドレイン領域１１、ｎ型のドリフト領域１２、ｐ型の電界緩和領域１３、ｎ+型のＪＦＥＴ抵抗低減領域１４、ｐ型のボディ領域１５、ｐ+型のボディコンタクト領域１６及びｎ+型のソース領域１７を有している。 The semiconductor substrate 10 is a substrate made of silicon carbide (SiC), and includes an n + type drain region 11, an n type drift region 12, a p type electric field relaxation region 13, and an n + type JFET resistance reduction region 14. , P type body region 15, p + type body contact region 16 and n + type source region 17.

ドレイン領域１１は、半導体基板１０の裏層部に配置されており、半導体基板１０の裏面に露出する。ドレイン領域１１は、後述するドリフト領域１２がエピタキシャル成長するための下地基板でもある。ドレイン領域１１は、半導体基板１０の裏面を被膜するドレイン電極２２にオーミック接触している。 The drain region 11 is arranged in the back layer portion of the semiconductor substrate 10 and is exposed on the back surface of the semiconductor substrate 10. The drain region 11 is also a base substrate for the epitaxial growth of the drift region 12 described later. The drain region 11 is in ohmic contact with the drain electrode 22 that coats the back surface of the semiconductor substrate 10.

ドリフト領域１２は、ドレイン領域１１上に設けられている。ドリフト領域１２は、エピタキシャル成長技術を利用して、ドレイン領域１１の表面から結晶成長して形成される。ドリフト領域１２の不純物濃度は、半導体基板１０の厚み方向に一定である。 The drift region 12 is provided on the drain region 11. The drift region 12 is formed by crystal growth from the surface of the drain region 11 using an epitaxial growth technique. The impurity concentration of the drift region 12 is constant in the thickness direction of the semiconductor substrate 10.

電界緩和領域１３は、トレンチゲート３０の底面を覆うように設けられており、トレンチゲート３０の底面に集中する電界を緩和することができる。この断面では、電界緩和領域１３がドリフト領域１２及びＪＦＥＴ抵抗低減領域１４によってボディ領域１５から隔てられている。しかしながら、図示しない断面において、電界緩和領域１３がボディ領域１５に接続されていてもよい。電界緩和領域１３は、イオン注入技術を利用して、トレンチゲート３０を形成するためのトレンチの底面に向けてアルミニウムをイオン注入し、そのトレンチの底面に形成される。 The electric field relaxation region 13 is provided so as to cover the bottom surface of the trench gate 30, and can alleviate the electric field concentrated on the bottom surface of the trench gate 30. In this cross section, the electric field relaxation region 13 is separated from the body region 15 by the drift region 12 and the JFET resistance reduction region 14. However, the electric field relaxation region 13 may be connected to the body region 15 in a cross section (not shown). The electric field relaxation region 13 is formed on the bottom surface of the trench by ion-implanting aluminum toward the bottom surface of the trench for forming the trench gate 30 by using the ion implantation technique.

ＪＦＥＴ抵抗低減領域１４は、ドリフト領域１２とボディ領域１５の間に設けられており、ドリフト領域１２よりもｎ型不純物の濃度が濃い領域である。ＪＦＥＴ抵抗低減領域１４は、トレンチゲート３０の側面に接しており、半導体基板１０の表面に直交する方向から見たときに（以下、「平面視したときに」という）、ソース領域１７と重複する位置に配置されている。このため、ＪＦＥＴ抵抗低減領域１４は、隣り合うトレンチゲート３０の間において面方向に離間しており、その離間する部分にドリフト領域１２の一部が位置している。換言すると、ＪＦＥＴ抵抗低減領域１４は、ボディコンタクト領域１６の下方に形成されておらず、ボディコンタクト領域１６の下方に対応する部分において面方向に離間しており、その離間する部分にドリフト領域１２の一部が位置している。ＪＦＥＴ抵抗低減領域１４は、イオン注入技術を利用して、半導体基板１０の表面に向けて窒素をイオン注入し、ドリフト領域１２とボディ領域１５の双方に接する位置に形成される。 The JFET resistance reduction region 14 is provided between the drift region 12 and the body region 15 and has a higher concentration of n-type impurities than the drift region 12. The JFET resistance reduction region 14 is in contact with the side surface of the trench gate 30 and overlaps with the source region 17 when viewed from a direction orthogonal to the surface of the semiconductor substrate 10 (hereinafter, referred to as “when viewed in plan”). It is located in a position. Therefore, the JFET resistance reduction region 14 is separated in the surface direction between the adjacent trench gates 30, and a part of the drift region 12 is located in the separated portion. In other words, the JFET resistance reduction region 14 is not formed below the body contact region 16 and is separated in the plane direction in the portion corresponding to the lower portion of the body contact region 16, and the drift region 12 is located in the separated portion. Part of is located. The JFET resistance reduction region 14 is formed at a position in contact with both the drift region 12 and the body region 15 by ion-implanting nitrogen toward the surface of the semiconductor substrate 10 using an ion implantation technique.

ボディ領域１５は、ドリフト領域１２及びＪＦＥＴ抵抗低減領域１４上に設けられており、半導体基板１０の表層部に配置されている。ボディ領域１５は、トレンチゲート３０の側面に接している。ボディ領域１５は、イオン注入技術を利用して、半導体基板１０の表面に向けてアルミニウムをイオン注入し、半導体基板１０の表層部に形成される。 The body region 15 is provided on the drift region 12 and the JFET resistance reduction region 14, and is arranged in the surface layer portion of the semiconductor substrate 10. The body region 15 is in contact with the side surface of the trench gate 30. The body region 15 is formed in the surface layer portion of the semiconductor substrate 10 by ion-implanting aluminum toward the surface of the semiconductor substrate 10 using an ion implantation technique.

ボディコンタクト領域１６は、ボディ領域１５上に設けられており、半導体基板１０の表層部に配置されており、半導体基板１０の表面に露出しており、ボディ領域１５よりもｐ型不純物の濃度が濃い領域である。ボディコンタクト領域１６は、半導体基板１０の表面を被膜するソース電極２４にオーミック接触している。ボディコンタクト領域１６は、イオン注入技術を利用して、半導体基板１０の表面に向けてアルミニウムをイオン注入し、半導体基板１０の表層部に形成される。 The body contact region 16 is provided on the body region 15, is disposed on the surface layer portion of the semiconductor substrate 10, is exposed on the surface of the semiconductor substrate 10, and has a p-type impurity concentration lower than that of the body region 15. It is a dark area. The body contact region 16 is in ohmic contact with the source electrode 24 that coats the surface of the semiconductor substrate 10. The body contact region 16 is formed in the surface layer portion of the semiconductor substrate 10 by ion-implanting aluminum toward the surface of the semiconductor substrate 10 using an ion implantation technique.

ソース領域１７は、ボディ領域１５上に設けられており、半導体基板１０の表層部に配置されており、半導体基板１０の表面に露出する。ソース領域１７は、ボディ領域１５によってドリフト領域１２及びＪＦＥＴ抵抗低減領域１４から隔てられている。ソース領域１７は、トレンチゲート３０の側面に接している。ソース領域１７は、半導体基板１０の表面を被膜するソース電極２４にオーミック接触している。ソース領域１７は、イオン注入技術を利用して、半導体基板１０の表面に向けて窒素をイオン注入し、半導体基板１０の表層部に形成される。 The source region 17 is provided on the body region 15, is disposed on the surface layer portion of the semiconductor substrate 10, and is exposed on the surface of the semiconductor substrate 10. Source region 17 is separated from drift region 12 and JFET resistance reduction region 14 by body region 15. The source region 17 is in contact with the side surface of the trench gate 30. The source region 17 is in ohmic contact with the source electrode 24 that coats the surface of the semiconductor substrate 10. The source region 17 is formed in the surface layer portion of the semiconductor substrate 10 by ion-implanting nitrogen toward the surface of the semiconductor substrate 10 using an ion implantation technique.

トレンチゲート３０は、半導体基板１０の表面から深部に向けて伸びており、ゲート絶縁膜３２及びゲート電極３４を有している。トレンチゲート３０は、ソース領域１７とボディ領域１５とＪＦＥＴ抵抗低減領域１４を貫通してドリフト領域１２に達している。ゲート絶縁膜３２は、酸化シリコンである。ゲート電極３４は、ゲート絶縁膜３２で被覆されており、不純物を含むポリシリコンである。 The trench gate 30 extends from the surface of the semiconductor substrate 10 toward the deep part, and has a gate insulating film 32 and a gate electrode 34. The trench gate 30 penetrates the source region 17, the body region 15, and the JFET resistance reduction region 14 to reach the drift region 12. The gate insulating film 32 is silicon oxide. The gate electrode 34 is covered with the gate insulating film 32 and is polysilicon containing impurities.

次に、図１を参照し、半導体装置１の動作を説明する。ドレイン電極２２に正電圧が印加され、ソース電極２４が接地され、トレンチゲート３０のゲート電極３４が接地されていると、半導体装置１はオフである。半導体装置１では、電界緩和領域１３がトレンチゲート３０の底面を覆うように設けられている。このため、トレンチゲート３０の底面のゲート絶縁膜３２における電界集中が緩和され、半導体装置１は高い耐圧を有することができる。 Next, the operation of the semiconductor device 1 will be described with reference to FIG. When a positive voltage is applied to the drain electrode 22, the source electrode 24 is grounded, and the gate electrode 34 of the trench gate 30 is grounded, the semiconductor device 1 is off. In the semiconductor device 1, the electric field relaxation region 13 is provided so as to cover the bottom surface of the trench gate 30. Therefore, the electric field concentration in the gate insulating film 32 on the bottom surface of the trench gate 30 is relaxed, and the semiconductor device 1 can have a high breakdown voltage.

ドレイン電極２２に正電圧が印加され、ソース電極２４が接地され、トレンチゲート３０のゲート電極３４にソース電極２４よりも正となる閾値電圧以上の電圧が印加されていると、半導体装置１はオンである。このとき、ソース領域１７とＪＦＥＴ抵抗低減領域１４を隔てるボディ領域１５のうちのトレンチゲート３０の側面に対向する部分に反転層が形成される。ソース領域１７から供給される電子は、その反転層を経由してＪＦＥＴ抵抗低減領域１４に達する。ＪＦＥＴ抵抗低減領域１４に達した電子は、ＪＦＥＴ抵抗低減領域１４を経由してドリフト領域１２に流れる。このようなＪＦＥＴ抵抗低減領域１４が設けられていると、電界緩和領域１３からドリフト領域１２内に伸びてくる空乏層を迂回するように電流が流れることができる。このため、このような空乏層による抵抗の増加、即ち、ＪＦＥＴ抵抗の増加が抑えられる。 When a positive voltage is applied to the drain electrode 22, the source electrode 24 is grounded, and a voltage equal to or higher than the threshold voltage which is more positive than the source electrode 24 is applied to the gate electrode 34 of the trench gate 30, the semiconductor device 1 is turned on. Is. At this time, an inversion layer is formed in a portion of the body region 15 that separates the source region 17 and the JFET resistance reduction region 14 from the side face of the trench gate 30. The electrons supplied from the source region 17 reach the JFET resistance reduction region 14 via the inversion layer. The electrons that have reached the JFET resistance reduction region 14 flow into the drift region 12 via the JFET resistance reduction region 14. When such a JFET resistance reduction region 14 is provided, a current can flow so as to bypass the depletion layer extending from the electric field relaxation region 13 into the drift region 12. Therefore, an increase in resistance due to such a depletion layer, that is, an increase in JFET resistance is suppressed.

次に、半導体装置１の製造方法を説明する。まず、図２に示されるように、ドレイン領域１１とドリフト領域１２が積層した半導体基板１０を準備する。この半導体基板１０は、エピタキシャル成長技術を利用して、ドレイン領域１１からドリフト領域１２を結晶成長して形成される。 Next, a method for manufacturing the semiconductor device 1 will be described. First, as shown in FIG. 2, the semiconductor substrate 10 in which the drain region 11 and the drift region 12 are stacked is prepared. The semiconductor substrate 10 is formed by crystal growth of the drift region 12 from the drain region 11 using an epitaxial growth technique.

次に、図３に示されるように、イオン注入技術を利用して、半導体基板１０の表面に向けてアルミニウムをイオン注入し、半導体基板１０の表層部にボディ領域１５を形成する。なお、このイオン注入に先立って、ボディ領域１５を形成する範囲外の半導体基板１０の表面にマスクを成膜してもよい。このイオン注入は、アルミニウムを厚み方向に多段で注入し、ボディ領域１５のｐ型の不純物濃度が厚み方向に概ね一定となるように実施される。ボディ領域１５のｐ型の不純物濃度は、約４×１０17ｃｍ-3となるように調整されている。 Next, as shown in FIG. 3, using the ion implantation technique, aluminum is ion-implanted toward the surface of the semiconductor substrate 10 to form the body region 15 in the surface layer portion of the semiconductor substrate 10. A mask may be formed on the surface of the semiconductor substrate 10 outside the area where the body region 15 is formed, prior to the ion implantation. This ion implantation is performed so that aluminum is implanted in multiple stages in the thickness direction so that the p-type impurity concentration in the body region 15 is substantially constant in the thickness direction. The p-type impurity concentration of the body region 15 is adjusted to be about 4×10 17 cm −3 .

次に、図４に示されるように、フォトリソグラフィー技術を利用して、半導体基板１０の表面に第１マスク層４２を成膜する。第１マスク層４２は、半導体基板１０の表面の第１範囲１０Ａを被膜し、第２範囲１０Ｂに開口を有している。後述するように、第１範囲１０Ａは、ＪＦＥＴ抵抗低減領域１４とソース領域１７を形成する位置に対応しており、第２範囲１０Ｂは、ボディコンタクト領域１６を形成する位置に対応している。 Next, as shown in FIG. 4, the first mask layer 42 is formed on the surface of the semiconductor substrate 10 by using the photolithography technique. The first mask layer 42 covers the first area 10A on the surface of the semiconductor substrate 10 and has openings in the second area 10B. As will be described later, the first range 10A corresponds to the position where the JFET resistance reduction region 14 and the source region 17 are formed, and the second range 10B corresponds to the position where the body contact region 16 is formed.

次に、図５に示されるように、イオン注入技術を利用して、第１マスク層４２から露出する半導体基板１０の表面に向けてアルミニウムをイオン注入し、ボディ領域１５上であって半導体基板１０の表面に露出する位置にボディコンタクト領域１６を形成する。ボディコンタクト領域１６のｐ型の不純物濃度は、最大濃度が約１×１０20ｃｍ-3となるように調整されている。イオン注入後に、第１マスク層４２を除去する。 Next, as shown in FIG. 5, using the ion implantation technique, aluminum is ion-implanted toward the surface of the semiconductor substrate 10 exposed from the first mask layer 42, and the aluminum is ion-implanted on the body region 15 and on the semiconductor substrate. A body contact region 16 is formed at a position exposed on the surface of 10. The p-type impurity concentration of the body contact region 16 is adjusted so that the maximum concentration is about 1×10 20 cm −3 . After the ion implantation, the first mask layer 42 is removed.

次に、図６に示されるように、フォトリソグラフィー技術を利用して、半導体基板１０の表面に第２マスク層４４を成膜する。第２マスク層４４は、半導体基板１０の表面の第２範囲１０Ｂを被膜し、第１範囲１０Ａに開口を有している。 Next, as shown in FIG. 6, the second mask layer 44 is formed on the surface of the semiconductor substrate 10 by using the photolithography technique. The second mask layer 44 covers the second area 10B on the surface of the semiconductor substrate 10 and has an opening in the first area 10A.

次に、図７に示されるように、イオン注入技術を利用して、第２マスク層４４から露出する半導体基板１０の表面に向けて窒素をイオン注入し、ドリフト領域１２とボディ領域１５の双方に接する位置にＪＦＥＴ抵抗低減領域１４を形成する。この例では、ＪＦＥＴ抵抗低減領域１４は、ドリフト領域１２とボディ領域１５の界面のうちのドリフト領域１２側に形成されているが、この例に代えて、ボディ領域１５側に形成されてもよく、ドリフト領域１２とボディ領域１５の双方の側に形成されてもよい。ＪＦＥＴ抵抗低減領域１４のｎ型の不純物濃度は、最大濃度が約１×１０15ｃｍ-3となるように調整されている。 Next, as shown in FIG. 7, nitrogen is ion-implanted toward the surface of the semiconductor substrate 10 exposed from the second mask layer 44 by using the ion-implantation technique, so that both the drift region 12 and the body region 15 are exposed. A JFET resistance reduction region 14 is formed at a position in contact with. In this example, the JFET resistance reduction region 14 is formed on the drift region 12 side of the interface between the drift region 12 and the body region 15, but instead of this example, it may be formed on the body region 15 side. It may be formed on both sides of the drift region 12 and the body region 15. The n-type impurity concentration of the JFET resistance reduction region 14 is adjusted so that the maximum concentration is about 1×10 15 cm −3 .

次に、図８に示されるように、イオン注入技術を利用して、第２マスク層４４から露出する半導体基板１０の表面に向けて窒素をイオン注入し、ボディ領域１５上であって半導体基板１０の表面に露出する位置にソース領域１７を形成する。ソース領域１７のｎ型の不純物濃度は、最大濃度が約１×１０20ｃｍ-3となるように調整されている。イオン注入後に、第１マスク層４２を除去する。なお、この例では、ＪＦＥＴ抵抗低減領域１４を形成した後にソース領域１７を形成したが、この例に代えて、ソース領域１７を形成した後にＪＦＥＴ抵抗低減領域１４を形成してもよい。 Next, as shown in FIG. 8, nitrogen is ion-implanted toward the surface of the semiconductor substrate 10 exposed from the second mask layer 44 by using the ion-implantation technique, so that the semiconductor substrate is on the body region 15 and on the semiconductor substrate. A source region 17 is formed at a position exposed on the surface of 10. The n-type impurity concentration of the source region 17 is adjusted so that the maximum concentration is about 1×10 20 cm −3 . After the ion implantation, the first mask layer 42 is removed. In this example, the source region 17 is formed after the JFET resistance reduction region 14 is formed, but instead of this example, the JFET resistance reduction region 14 may be formed after the source region 17 is formed.

次に、図９に示すように、ドライエッチング技術を利用して、半導体基板１０の表面の第１範囲１０ＡにトレンチＴＲを形成する。トレンチＴＲは、半導体基板１０の表面からソース領域１７とボディ領域１５とＪＦＥＴ抵抗低減領域１４を貫通してドリフト領域１２に達するように形成される。なお、トレンチＴＲは、ソース領域１７とボディ領域１５を貫通していればよく、その底面がＪＦＥＴ抵抗低減領域１４内に位置するように形成されてもよい。 Next, as shown in FIG. 9, a trench TR is formed in the first area 10A on the surface of the semiconductor substrate 10 by using a dry etching technique. Trench TR is formed so as to reach drift region 12 from the surface of semiconductor substrate 10 through source region 17, body region 15 and JFET resistance reduction region 14. It is sufficient that trench TR penetrates source region 17 and body region 15, and the trench TR may be formed so that the bottom surface thereof is located in JFET resistance reduction region 14.

次に、図１０に示されるように、イオン注入技術を利用して、トレンチＴＲの底面に露出するドリフト領域１２に向けてアルミニウムをイオン注入し、ドリフト領域１２上であってトレンチＴＲの底面に露出する電界緩和領域１３を形成する。なお、このイオン注入に先立って、トレンチＴＲの側面にアルミニウムが導入されるのを抑えるために、トレンチＴＲの側面に保護膜を成膜してもよい。 Next, as shown in FIG. 10, using an ion implantation technique, aluminum is ion-implanted toward the drift region 12 exposed on the bottom surface of the trench TR, and on the drift region 12 and on the bottom surface of the trench TR. The exposed electric field relaxation region 13 is formed. Prior to this ion implantation, a protective film may be formed on the side surface of trench TR in order to suppress the introduction of aluminum to the side surface of trench TR.

次に、ＣＶＤ技術を利用して、そのトレンチＴＲ内にゲート絶縁膜３２を堆積する。次に、ＣＶＤ技術を利用して、ゲート電極３４をトレンチ内に充填する。最後に、半導体基板１０の裏面にドレイン電極２２を成膜し、半導体基板１０の表面にソース電極２４を被膜すると、半導体装置１が完成する。 Next, using the CVD technique, the gate insulating film 32 is deposited in the trench TR. Next, the gate electrode 34 is filled in the trench using the CVD technique. Finally, the drain electrode 22 is formed on the back surface of the semiconductor substrate 10, and the source electrode 24 is coated on the front surface of the semiconductor substrate 10, whereby the semiconductor device 1 is completed.

上記製造方法によると、ＪＦＥＴ抵抗低減領域１４は、ソース領域１７の下方に選択的に形成され、ボディコンタクト領域１６の下方には形成されない。このため、ＪＦＥＴ抵抗低減領域１４をイオン注入で形成するときに形成される結晶欠陥は、ボディコンタクト領域１６の下方に形成されない。例えば、ＪＦＥＴ抵抗低減領域１４がボディコンタクト領域１６の下方にも形成された場合、ＪＦＥＴ抵抗低減領域１４とボディ領域１５とボディコンタクト領域１６の各々をイオン注入で形成するときに形成される結晶欠陥が、ボディコンタクト領域１６の下方に多量に存在することとなる。このような多量の結晶欠陥は、リーク電流の原因となる可能性がある。一方、上記製造方法では、ＪＦＥＴ抵抗低減領域１４がボディコンタクト領域１６の下方に形成されないので、ボディコンタクト領域１６の下方に多量の結晶欠陥が形成されることが抑えられる。さらに、上記製造方法によると、ソース領域１７とＪＦＥＴ抵抗低減領域１４を共通の第２マスク層４４を用いて形成することができる。これにより、上記製造方法では、製造コストが抑えられる。 According to the above manufacturing method, the JFET resistance reduction region 14 is selectively formed below the source region 17 and is not formed below the body contact region 16. Therefore, crystal defects formed when the JFET resistance reduction region 14 is formed by ion implantation are not formed below the body contact region 16. For example, when the JFET resistance reduction region 14 is also formed below the body contact region 16, crystal defects formed when the JFET resistance reduction region 14, the body region 15, and the body contact region 16 are formed by ion implantation. However, a large amount of them exist below the body contact region 16. Such a large amount of crystal defects may cause a leak current. On the other hand, in the above manufacturing method, since the JFET resistance reduction region 14 is not formed below the body contact region 16, it is possible to suppress the formation of a large number of crystal defects below the body contact region 16. Further, according to the above manufacturing method, the source region 17 and the JFET resistance reducing region 14 can be formed using the common second mask layer 44. As a result, the manufacturing cost can be suppressed in the above manufacturing method.

以上、本発明の具体例を詳細に説明したが、これらは例示に過ぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。また、本明細書または図面に説明した技術要素は、単独であるいは各種の組合せによって技術的有用性を発揮するものであり、出願時請求項記載の組合せに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成し得るものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。 Specific examples of the present invention have been described above in detail, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. Further, the technical elements described in the present specification or the drawings exert technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technique illustrated in the present specification or the drawings can achieve a plurality of purposes at the same time, and achieving one of the purposes has technical utility.

１ ：半導体装置
１０ ：半導体基板
１１ ：ドレイン領域
１２ ：ドリフト領域
１３ ：電界緩和領域
１４ ：ＪＦＥＴ抵抗低減領域
１５ ：ボディ領域
１６ ：ボディコンタクト領域
１７ ：ソース領域
２２ ：ドレイン電極
２４ ：ソース電極
３０ ：トレンチゲート
３２ ：ゲート絶縁膜
３４ ：ゲート電極 1: semiconductor device 10: semiconductor substrate 11: drain region 12: drift region 13: electric field relaxation region 14: JFET resistance reduction region 15: body region 16: body contact region 17: source region 22: drain electrode 24: source electrode 30: Trench gate 32: Gate insulating film 34: Gate electrode

Claims (1)

第１導電型のドリフト領域が表面に露出する半導体基板を準備する工程と、
前記半導体基板の前記表面に向けて第２導電型不純物をイオン注入し、前記ドリフト領域上にボディ領域を形成する工程と、
前記半導体基板の前記表面に第１マスク層を成膜する工程であって、前記第１マスク層は、前記半導体基板の前記表面の第１範囲を被膜し、前記半導体基板の前記表面の前記第１範囲とは異なる第２範囲に開口を有する、第１マスク層を成膜する工程と、
前記第１マスク層の前記開口から露出する前記半導体基板の前記表面の前記第２範囲に向けて第２導電型不純物をイオン注入し、前記ボディ領域上にボディコンタクト領域を形成する工程と、
前記半導体基板の前記表面に第２マスク層を成膜する工程であって、前記第２マスク層は、前記半導体基板の前記表面の前記第２範囲を被膜し、前記半導体基板の前記表面の前記第１範囲に開口を有する、第２マスク層を成膜する工程と、
前記第２マスク層の前記開口から露出する前記半導体基板の前記表面の前記第１範囲に向けて第１導電型不純物をイオン注入し、前記ドリフト領域と前記ボディ領域の双方に接する位置にＪＦＥＴ抵抗低減領域を形成する工程と、
前記第２マスク層の前記開口から露出する前記半導体基板の前記表面の前記第１範囲に向けて第１導電型不純物をイオン注入し、前記ボディ領域上にソース領域を形成する工程と、
前記半導体基板の前記表面の前記第１範囲において、前記ソース領域と前記ボディ領域を貫通するトレンチゲートを形成する工程と、を備える、半導体装置の製造方法。 A step of preparing a semiconductor substrate in which a drift region of the first conductivity type is exposed on the surface;
Ion-implanting a second conductivity type impurity toward the surface of the semiconductor substrate to form a body region on the drift region;
Forming a first mask layer on the surface of the semiconductor substrate, the first mask layer covering a first area of the surface of the semiconductor substrate, and forming a first mask layer on the surface of the semiconductor substrate. Forming a first mask layer having an opening in a second range different from the first range;
Forming a body contact region on the body region by ion-implanting a second conductivity type impurity toward the second region of the surface of the semiconductor substrate exposed from the opening of the first mask layer;
Forming a second mask layer on the surface of the semiconductor substrate, the second mask layer covering the second area of the surface of the semiconductor substrate, and forming the second mask layer on the surface of the semiconductor substrate. A step of forming a second mask layer having an opening in the first range,
A first conductivity type impurity is ion-implanted toward the first range of the surface of the semiconductor substrate exposed from the opening of the second mask layer, and a JFET resistor is provided at a position in contact with both the drift region and the body region. Forming a reduced region,
Forming a source region on the body region by ion-implanting a first conductivity type impurity toward the first region of the surface of the semiconductor substrate exposed from the opening of the second mask layer;
Forming a trench gate that penetrates the source region and the body region in the first area of the surface of the semiconductor substrate.
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