JP7006389B2 - Semiconductor devices and methods for manufacturing semiconductor devices - Google Patents

Description

The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

A semiconductor having a wider bandgap than silicon (Si) (hereinafter referred to as a wide bandgap semiconductor) has a maximum electric field strength larger than that of silicon, and thus can realize high withstand voltage, low on-resistance, low loss, high temperature operation, and the like. Expected as a material. When a semiconductor device using a wide bandgap semiconductor has a high withstand voltage, a high voltage is applied not only to the active region where current flows when it is on, but also to the edge termination region surrounding the active region, and the electric field is concentrated. do.

The withstand voltage of a semiconductor device is determined by the impurity concentration, thickness, electric field strength, etc. of each part of the semiconductor device, but the fracture tolerance determined by the unique features of the semiconductor is equal from the active region to the edge termination region. Therefore, when an electric field is concentrated in the edge termination region and an electric load exceeding the fracture capacity of the edge termination region is applied, the semiconductor device may be destroyed in the edge termination region. That is, the withstand voltage of the semiconductor device is rate-determined by the fracture resistance in the edge termination region.

As a structure for improving the withstand voltage of the entire semiconductor device by relaxing and dispersing the electric field in the edge termination region, a junction termination (JTE: Junction Termination Extension) structure arranged in the edge termination region and a field limiting ring (FLR: Field) are used. Pressure-resistant structures such as a Limiting Ring) structure are known. A general JTE structure will be described by taking the case where the semiconductor material is silicon carbide (SiC) as an example.

FIG. 11 is a cross-sectional view showing a withstand voltage structure of a conventional semiconductor device. The conventional semiconductor device shown in FIG. 11 includes an active region 110 in which a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is arranged on a semiconductor substrate (semiconductor chip) 150 made of silicon carbide, and a JTE. It includes an edge termination region 120 in which the structure 140 is arranged. Reference numeral 130 is a region (hereinafter referred to as an intermediate region) between the active region 110 and the edge termination region 120.

The vertical MOSFET in the active region 110 employs a trench gate structure that is structurally easy to obtain low on-resistance characteristics. The trench gate structure is a structure (hereinafter referred to as a MOS gate) 110a having a gate electrode embedded in a trench 107 formed at a predetermined depth from the front surface of the semiconductor substrate 150 via a gate insulating film. The semiconductor substrate 150 is formed by epitaxially growing silicon carbide layers 151 and 152, which are n ^- type drift regions 102 and p-type base regions 104, on an n ⁺ -type starting substrate 101 made of silicon carbide.

By removing the p-type silicon carbide layer 152 over the entire area of the edge termination region 120, the edge termination region 120 is made lower than the active region 110 (recessed to the drain side) on the front surface of the semiconductor substrate 150. 121 is formed. In the edge termination region 120, a plurality of p-type regions (here, 2) in which the n ^- type silicon carbide layer 151 is exposed on the bottom surface 121a of the step 121 and the impurity concentration is lowered so as to be arranged on the outside (chip end side). A JTE structure 140 is provided in which (reference numerals 141 and 142 are attached from the active region 110 side) are arranged adjacent to each other.

These two p-type regions (hereinafter referred to as the first and second JTE regions) 141 and 142 are selectively provided in the portions of the n ^- type silicon carbide layer 151 that are exposed to the bottom surface 121a of the step 121, respectively. .. The first JTE region 141 is in contact with the p ⁺ type region 111 extending from the active region 110 on the bottom surface 121a of the step 121. The pressure resistant structure is configured by this JTE structure 140. The n ^- type drift region 102 is a portion of the n ^- type silicon carbide layer 151 other than the n-type current diffusion region 103, the p ⁺ type regions 111 to 113, and the first and second JTE regions 141 and 142.

Further, in the trench gate structure, since a channel (n-type inverted layer) is formed in the vertical direction (depth direction) along the side wall of the trench 107, it is arranged in a flat plate shape on the front surface of the semiconductor substrate. It is easier to shorten the channel than a planar gate structure having a MOS gate, and it is possible to shorten the channel by reducing the thickness of the p-type base region 104. However, the gate threshold voltage drops due to the influence of the depletion layer extending into the p-type base region 104 from the drain side and the source side when the MOSFET is turned on (increased short-channel effect).

Suppression of the short-channel effect can be achieved by adopting a halo structure. The halo structure is a p-type base from the drain side and the source side when the MOSFET is turned on by selectively providing a p ⁺ type region (so-called halo region) inside the p-type base region 104 apart from the trench 107. It is a structure that suppresses the depletion layer extending in the region 104. A method of manufacturing a conventional semiconductor device having a general halo structure will be described. FIG. 12 is a cross-sectional view showing a state in which a conventional semiconductor device is being manufactured.

As shown in FIG. 12, first, in the active region 110, a predetermined semiconductor region (each portion arranged adjacent to the trench 107 constituting the MOS gate 110a, etc.) is formed on the front surface side of the semiconductor substrate 150. do. In the edge termination region 120, a semiconductor region such as the first and second JTE regions 141 and 142 and a step 121 on the front surface of the semiconductor substrate 150 are formed on the front surface side of the semiconductor substrate 150. Next, in the active region 110, a trench 107 constituting the MOS gate 110a is formed at a predetermined depth from the front surface of the semiconductor substrate 150.

Next, p-type impurities such as aluminum (Al) are ion-implanted into both side walls of the trench 107 from an oblique direction at a predetermined injection angle with respect to the front surface of the semiconductor substrate 150 (hereinafter referred to as oblique ion implantation). 161). By this oblique ion implantation 161, the p ⁺ type region 114 constituting the halo structure is selectively provided inside the p-type base region 104 at a self-alignment on the side wall of the trench 107 and a predetermined distance from the side wall of the trench 107. Form. FIG. 12 shows a case where a p ⁺ type region 114 in contact with the n ⁺ type source region 105 is formed.

Further, as a planar gate MOSFET that suppresses the short-channel effect, a device has been proposed in which a p-type halo region that suppresses the spread of impurities from the source to the channel formation region is provided below the n ^- type source region ( For example, see Patent Document 1 (paragraph 0234) below.).

Further, as a trench gate-type MOSFET that suppresses the short-channel effect, a device is proposed in which a region containing p-type impurities at a high impurity concentration is provided inside the p-type base region, away from the gate insulating film (gate trench). (For example, see Patent Document 2 below (paragraphs 0079,0090, FIGS. 10 and 12).).

Japanese Unexamined Patent Publication No. 2013-012669 Japanese Unexamined Patent Publication No. 2015-153893

In the above-mentioned conventional method for manufacturing a semiconductor device (see FIG. 12), in the oblique ion implantation 161 for forming the p ⁺ type region 114, the portion corresponding to the formation region of the p ⁺ type region 114 is opened for ion implantation. No mask is used. The reason is that the formation region of the p ⁺ type region 114 may be hidden behind the ion implantation mask and the p-type impurities may not be partially implanted. Therefore, the injection angle of the oblique ion implantation 161 may be controlled. This is because it is difficult to align the ion implantation mask and the processing accuracy of the p ⁺ type region 114 is lowered.

However, by performing the oblique ion implantation 161 without using the ion implantation mask, the front surface of the semiconductor substrate 150 is covered over the entire front surface of the semiconductor substrate 150 together with the p ⁺ type region 114 constituting the halo structure. A p ⁺ type region 115 is formed parallel to the front surface of the semiconductor substrate 150 at a predetermined depth. Since the p ⁺ type region 115 is formed not only in the active region 110 but also in the edge termination region 120 as described above, there is a problem that the withstand voltage is lowered in the edge termination region 120 and the withstand voltage of the entire semiconductor device is lowered.

An object of the present invention is to provide a semiconductor device and a method for manufacturing a semiconductor device, which can suppress the short-channel effect and prevent a decrease in withstand voltage in order to solve the above-mentioned problems caused by the prior art. do.

In order to solve the above-mentioned problems and achieve the object of the present invention, the semiconductor device according to the present invention has the following features. A semiconductor substrate made of a semiconductor having a bandgap wider than that of silicon is provided with an active region and a terminal region surrounding the active region. The second conductive layer is a portion exposed on the front surface of the semiconductor substrate in a region other than the terminal region, and is exposed on the front surface of the semiconductor substrate. The first conductive type layer is exposed to the front surface of the semiconductor substrate in the terminal region, and is a portion on the back surface side of the semiconductor substrate in a region other than the terminal region, and is more than the second conductive type layer. It is arranged on the back surface side of the semiconductor substrate in contact with the second conductive type layer. The trench penetrates the second conductive type layer from the front surface of the semiconductor substrate in the depth direction and reaches the first conductive type layer. A gate electrode is provided inside the trench via a gate insulating film. Inside the second conductive type layer, a first semiconductor region of the first conductive type is selectively provided along the side wall of the trench. A second conductive type second semiconductor region is selectively provided on the back surface side of the semiconductor substrate with respect to the first semiconductor region, along the side wall of the trench and in contact with the first semiconductor region. .. Inside the second conductive type layer, a second conductive type third semiconductor region is selectively provided in contact with the first semiconductor region and the second semiconductor region. The third semiconductor region faces the side wall of the trench with the second semiconductor region interposed therebetween. The third semiconductor region has a higher impurity concentration than the second semiconductor region. Inside the second conductive type layer, a fourth semiconductor region of the second conductive type is selectively provided at a position deeper than the front surface of the semiconductor substrate. The fourth semiconductor region extends along the front surface of the semiconductor substrate. The fourth semiconductor region has a higher impurity concentration than the second semiconductor region. A pressure resistant structure is provided on the front surface side of the semiconductor substrate in the terminal region. The first electrode is electrically connected to the first semiconductor region. The second electrode is provided on the back surface of the semiconductor substrate. The fourth semiconductor region extends from the active region side to the terminal region side and terminates inside the terminal region.

Further, in the semiconductor device according to the present invention, in the above-described invention, the withstand voltage structure is arranged adjacent to the surface layer of the front surface of the semiconductor substrate in a direction parallel to the front surface of the semiconductor substrate. It is characterized by having a plurality of second conductive type fifth semiconductor regions whose impurity concentration is lowered so that they are arranged on the outside.

Further, in order to solve the above-mentioned problems and achieve the object of the present invention, the semiconductor device according to the present invention has the following features. A semiconductor substrate made of a semiconductor having a bandgap wider than that of silicon is provided with an active region and a terminal region surrounding the active region. The second conductive layer is a portion exposed on the front surface of the semiconductor substrate in a region other than the terminal region, and is exposed on the front surface of the semiconductor substrate. The first conductive type layer is exposed to the front surface of the semiconductor substrate in the terminal region, and is a portion on the back surface side of the semiconductor substrate in a region other than the terminal region, and is more than the second conductive type layer. It is arranged on the back surface side of the semiconductor substrate in contact with the second conductive type layer. The trench penetrates the second conductive type layer from the front surface of the semiconductor substrate in the depth direction and reaches the first conductive type layer. A gate electrode is provided inside the trench via a gate insulating film. Inside the second conductive type layer, a first semiconductor region of the first conductive type is selectively provided along the side wall of the trench. A second conductive type second semiconductor region is selectively provided on the back surface side of the semiconductor substrate with respect to the first semiconductor region, along the side wall of the trench and in contact with the first semiconductor region. .. Inside the second conductive type layer, a second conductive type third semiconductor region is selectively provided in contact with the first semiconductor region and the second semiconductor region. The third semiconductor region faces the side wall of the trench with the second semiconductor region interposed therebetween. The third semiconductor region has a higher impurity concentration than the second semiconductor region. Inside the second conductive type layer, a fourth semiconductor region of the second conductive type is selectively provided at a position deeper than the front surface of the semiconductor substrate. The fourth semiconductor region extends along the front surface of the semiconductor substrate. The fourth semiconductor region has a higher impurity concentration than the second semiconductor region. A pressure resistant structure is provided on the front surface side of the semiconductor substrate in the terminal region. The first electrode is electrically connected to the first semiconductor region. The second electrode is provided on the back surface of the semiconductor substrate. The pressure-resistant structure is arranged adjacent to the surface layer of the front surface of the semiconductor substrate in a direction parallel to the front surface of the semiconductor substrate, and the impurity concentration is lowered as it is arranged outside. It has a second conductive type fifth semiconductor region. The fourth semiconductor region extends from the active region side to the terminal region and terminates inside the innermost fifth semiconductor region.

Further, in order to solve the above-mentioned problems and achieve the object of the present invention, the semiconductor device according to the present invention has the following features. A semiconductor substrate made of a semiconductor having a bandgap wider than that of silicon is provided with an active region and a terminal region surrounding the active region. The second conductive layer is a portion exposed on the front surface of the semiconductor substrate in a region other than the terminal region, and is exposed on the front surface of the semiconductor substrate. The first conductive type layer is exposed to the front surface of the semiconductor substrate in the terminal region, and is a portion on the back surface side of the semiconductor substrate in a region other than the terminal region, and is more than the second conductive type layer. It is arranged on the back surface side of the semiconductor substrate in contact with the second conductive type layer. The trench penetrates the second conductive type layer from the front surface of the semiconductor substrate in the depth direction and reaches the first conductive type layer. A gate electrode is provided inside the trench via a gate insulating film. Inside the second conductive type layer, a first semiconductor region of the first conductive type is selectively provided along the side wall of the trench. A second conductive type second semiconductor region is selectively provided on the back surface side of the semiconductor substrate with respect to the first semiconductor region, along the side wall of the trench and in contact with the first semiconductor region. .. Inside the second conductive type layer, a second conductive type third semiconductor region is selectively provided in contact with the first semiconductor region and the second semiconductor region. The third semiconductor region faces the side wall of the trench with the second semiconductor region interposed therebetween. The third semiconductor region has a higher impurity concentration than the second semiconductor region. Inside the second conductive type layer, a fourth semiconductor region of the second conductive type is selectively provided at a position deeper than the front surface of the semiconductor substrate. The fourth semiconductor region extends along the front surface of the semiconductor substrate. The fourth semiconductor region has a higher impurity concentration than the second semiconductor region. A pressure resistant structure is provided on the front surface side of the semiconductor substrate in the terminal region. The first electrode is electrically connected to the first semiconductor region. The second electrode is provided on the back surface of the semiconductor substrate. The pressure-resistant structure has a second conductive type fifth semiconductor region provided on the surface layer of the front surface of the semiconductor substrate. The fourth semiconductor region extends from the active region side to the terminal region. A plurality of portions extending to the terminal region of the fourth semiconductor region are arranged at predetermined intervals in the direction from the active region side to the outside.

Further, in the semiconductor device according to the present invention, in the above-described invention, the first second conductive type region is selectively provided inside the first conductive type layer, apart from the second semiconductor region. .. The first second conductive region covers the bottom surface of the trench. A second second conductive type region is selectively provided inside the first conductive type layer between the adjacent trenches, apart from the trench. The first conductive type region extends from the active region toward the terminal region and is adjacent to the inside of the fifth semiconductor region.

Further, in order to solve the above-mentioned problems and achieve the object of the present invention, the method for manufacturing a semiconductor device according to the present invention is a semiconductor having a gate structure in which a gate electrode is embedded in a trench via a gate insulating film. It is a method for manufacturing an apparatus and has the following features. First, a first step of epitaxially growing a first conductive layer on the surface of a starting substrate made of a semiconductor having a bandgap wider than that of silicon is performed. Next, by epitaxially growing the second conductive type layer on the first conductive type layer, the semiconductor having the front surface on the second conductive type layer side as the front surface and the front surface on the starting substrate side as the back surface. The second step of manufacturing the substrate is performed. Next, in the active region, a third step of forming the trench at a predetermined depth that penetrates the second conductive type layer in the depth direction and reaches the first conductive type layer is performed. A first conductive type first semiconductor region is selectively formed inside the second conductive type layer along the side wall of the trench, and the semiconductor is more than the first semiconductor region of the second conductive type layer. The fourth step of leaving the portion on the back surface side of the substrate as the second semiconductor region of the second conductive type is performed. Next, a fifth step is performed in which the second conductive type layer is removed in the terminal region surrounding the active region, and the first conductive type layer is exposed on the front surface of the semiconductor substrate. Next, in the terminal region, a sixth step of forming a pressure resistant structure on the front surface side of the semiconductor substrate is performed. Next, a seventh step of forming an oxide film covering the front surface of the semiconductor substrate is performed at least in the terminal region. Next, using the oxide film as a mask, second conductive impurities are applied to the front surface of the semiconductor substrate and the side wall of the trench at a predetermined injection angle from an oblique direction with respect to the front surface of the semiconductor substrate. The eighth step of ion implantation is performed. In the eighth step, the second conductive layer is in contact with the first semiconductor region and the second semiconductor region, and faces the side wall of the trench with the second semiconductor region interposed therebetween. 2 The second conductive type third semiconductor region having a higher impurity concentration than the semiconductor region is selectively formed. Along with the formation of the third semiconductor region, the third semiconductor layer extends along the front surface of the semiconductor substrate at a position deeper than the front surface of the semiconductor substrate inside the second conductive type layer. The second conductive type fourth semiconductor region having a higher impurity concentration than the two semiconductor regions is selectively formed. The fourth semiconductor region extends from the active region side to the terminal region side and is terminated inside the terminal region.

Further, in order to solve the above-mentioned problems and achieve the object of the present invention, the method for manufacturing a semiconductor device according to the present invention is a semiconductor having a gate structure in which a gate electrode is embedded in a trench via a gate insulating film. It is a method for manufacturing an apparatus and has the following features. First, a first step of epitaxially growing a first conductive layer on the surface of a starting substrate made of a semiconductor having a bandgap wider than that of silicon is performed. Next, by epitaxially growing the second conductive type layer on the first conductive type layer, the semiconductor having the front surface on the second conductive type layer side as the front surface and the front surface on the starting substrate side as the back surface. The second step of manufacturing the substrate is performed. Next, in the active region, a third step of forming the trench at a predetermined depth that penetrates the second conductive type layer in the depth direction and reaches the first conductive type layer is performed. A first conductive type first semiconductor region is selectively formed inside the second conductive type layer along the side wall of the trench, and the semiconductor is more than the first semiconductor region of the second conductive type layer. The fourth step of leaving the portion on the back surface side of the substrate as the second semiconductor region of the second conductive type is performed. Next, a fifth step is performed in which the second conductive type layer is removed in the terminal region surrounding the active region, and the first conductive type layer is exposed on the front surface of the semiconductor substrate. Next, in the terminal region, a sixth step of forming a pressure resistant structure on the front surface side of the semiconductor substrate is performed. Next, a seventh step of forming an oxide film covering the front surface of the semiconductor substrate is performed at least in the terminal region. Next, using the oxide film as a mask, second conductive impurities are applied to the front surface of the semiconductor substrate and the side wall of the trench at a predetermined injection angle from an oblique direction with respect to the front surface of the semiconductor substrate. The eighth step of ion implantation is performed. In the sixth step, as the withstand voltage structure, impurities are arranged on the surface layer of the front surface of the semiconductor substrate adjacent to each other in a direction parallel to the front surface of the semiconductor substrate, and are arranged outside. A plurality of second conductive type fifth semiconductor regions having a low concentration are selectively formed. In the eighth step, the second conductive layer is in contact with the first semiconductor region and the second semiconductor region, and faces the side wall of the trench with the second semiconductor region interposed therebetween. 2 The second conductive type third semiconductor region having a higher impurity concentration than the semiconductor region is selectively formed. Along with the formation of the third semiconductor region, the third semiconductor layer extends along the front surface of the semiconductor substrate at a position deeper than the front surface of the semiconductor substrate inside the second conductive type layer. The second conductive type fourth semiconductor region having a higher impurity concentration than the two semiconductor regions is selectively formed. The fourth semiconductor region extends from the active region side to the terminal region and is terminated inside the innermost fifth semiconductor region.

Further, in order to solve the above-mentioned problems and achieve the object of the present invention, the method for manufacturing a semiconductor device according to the present invention is a semiconductor having a gate structure in which a gate electrode is embedded in a trench via a gate insulating film. It is a method for manufacturing an apparatus and has the following features. First, a first step of epitaxially growing a first conductive layer on the surface of a starting substrate made of a semiconductor having a bandgap wider than that of silicon is performed. Next, by epitaxially growing the second conductive type layer on the first conductive type layer, the semiconductor having the front surface on the second conductive type layer side as the front surface and the front surface on the starting substrate side as the back surface. The second step of manufacturing the substrate is performed. Next, in the active region, a third step of forming the trench at a predetermined depth that penetrates the second conductive type layer in the depth direction and reaches the first conductive type layer is performed. A first conductive type first semiconductor region is selectively formed inside the second conductive type layer along the side wall of the trench, and the semiconductor is more than the first semiconductor region of the second conductive type layer. The fourth step of leaving the portion on the back surface side of the substrate as the second semiconductor region of the second conductive type is performed. Next, a fifth step is performed in which the second conductive type layer is removed in the terminal region surrounding the active region, and the first conductive type layer is exposed on the front surface of the semiconductor substrate. Next, in the terminal region, a sixth step of forming a pressure resistant structure on the front surface side of the semiconductor substrate is performed. Next, a seventh step of forming an oxide film covering the front surface of the semiconductor substrate is performed at least in the terminal region. Next, using the oxide film as a mask, second conductive impurities are applied to the front surface of the semiconductor substrate and the side wall of the trench at a predetermined injection angle from an oblique direction with respect to the front surface of the semiconductor substrate. The eighth step of ion implantation is performed. In the sixth step, as the withstand voltage structure, a second conductive type fifth semiconductor region provided on the surface layer of the front surface of the semiconductor substrate is formed. In the eighth step, the second conductive layer is in contact with the first semiconductor region and the second semiconductor region, and faces the side wall of the trench with the second semiconductor region interposed therebetween. 2 The second conductive type third semiconductor region having a higher impurity concentration than the semiconductor region is selectively formed. Along with the formation of the third semiconductor region, the third semiconductor layer extends along the front surface of the semiconductor substrate at a position deeper than the front surface of the semiconductor substrate inside the second conductive type layer. The second conductive type fourth semiconductor region having a higher impurity concentration than the two semiconductor regions is selectively formed. The fourth semiconductor region extends from the active region side to the terminal region. A plurality of portions extending to the terminal region of the fourth semiconductor region are arranged at predetermined intervals in the direction from the active region side to the outside.

Further, in the method for manufacturing a semiconductor device according to the present invention, in the above-mentioned invention, in the seventh step, a plurality of openings are formed in the oxide film so as to be separated from each other in the direction from the active region side to the outside. The eighth step is characterized in that a portion extending to the terminal region of the fourth semiconductor region is formed on the surface layer exposed to the opening on the front surface of the semiconductor substrate.

According to the semiconductor device and the method for manufacturing the semiconductor device according to the present invention, it is possible to suppress the short-channel effect and prevent the withstand voltage from being lowered.

It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 1. FIG. It is sectional drawing which shows the state in the manufacturing process of the semiconductor device which concerns on Embodiment 1. FIG. It is sectional drawing which shows the state in the manufacturing process of the semiconductor device which concerns on Embodiment 1. FIG. It is sectional drawing which shows the state in the manufacturing process of the semiconductor device which concerns on Embodiment 1. FIG. It is sectional drawing which shows the state in the manufacturing process of the semiconductor device which concerns on Embodiment 1. FIG. It is sectional drawing which shows the state in the manufacturing process of the semiconductor device which concerns on Embodiment 2. FIG. It is sectional drawing which shows the state in the manufacturing process of the semiconductor device which concerns on Embodiment 3. FIG. It is sectional drawing which shows the state in the manufacturing process of the semiconductor device which concerns on Embodiment 4. FIG. It is a characteristic diagram which shows the p-type impurity concentration profile in the cutting line AA'in FIG. It is a characteristic diagram which shows the p-type impurity concentration profile in the cutting line AA'in FIG. It is sectional drawing which shows the withstand voltage structure of the conventional semiconductor device. It is sectional drawing which shows the state in the manufacturing process of the conventional semiconductor device.

Hereinafter, preferred embodiments of the semiconductor device and the method for manufacturing the semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that the electron or hole is a large number of carriers in the layer or region marked with n or p, respectively. Further, + and-attached to n and p mean that the concentration of impurities is higher and the concentration of impurities is lower than that of the layer or region to which it is not attached, respectively. In the following description of the embodiment and the accompanying drawings, the same reference numerals are given to the same configurations, and duplicate description will be omitted.

(Embodiment 1)
The semiconductor device according to the first embodiment is configured by using a semiconductor having a bandgap wider than that of silicon (referred to as a wide bandgap semiconductor). The structure of the semiconductor device according to the first embodiment will be described by exemplifying a case where, for example, silicon carbide (SiC) is used as the wide bandgap semiconductor. FIG. 1 is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment. FIG. 1 shows from the outermost unit cell (on the end side of the chip (semiconductor substrate 50)) of the plurality of unit cells (constituent units of the element) arranged in the active region 10 to the chip end. The active region 10 is a region in which a current flows when the semiconductor device is in the ON state.

The semiconductor device according to the first embodiment shown in FIG. 1 includes an active region 10 in which a vertical MOSFET is arranged and an edge termination region 20 in which a JTE structure 40 is arranged on a semiconductor substrate (semiconductor chip) 50 made of silicon carbide. To prepare for. The edge termination region 20 is a region between the active region 10 and the side surface of the chip (semiconductor substrate 50), and is on the substrate front surface (front surface of the semiconductor substrate 50) side of the n ^- type drift region 2. This is a region where the electric field is relaxed and the withstand voltage (withstand voltage) is maintained. The withstand voltage is the voltage limit at which the semiconductor device does not malfunction or break. Reference numeral 30 is a region (intermediate region) between the active region 10 and the edge termination region 20.

For the vertical MOSFET in the active region 10, for example, a general trench gate structure that is structurally easy to obtain low on-resistance characteristics is adopted. The trench gate structure is a structure (hereinafter referred to as a MOS gate) 10a having a gate electrode 9 embedded in a trench 7 formed at a predetermined depth from the front surface of the semiconductor substrate 50 via a gate insulating film 8. be. The active region 10 is a region sandwiched between the centers of the outermost trench 7a. A p-type base region 4, an n ⁺ -type source region 5, and a p ⁺⁺ -type contact region 6 of a vertical MOSFET are selectively provided between adjacent trenches 7 (mesa region).

Specifically, the semiconductor substrate 50 is formed by epitaxially growing n ^- type drift regions 2 and p-type base regions 4 on n ⁺ -type starting substrates 1 made of silicon carbide, respectively. The trench 7 penetrates the p-type silicon carbide layer 52 in the depth direction from the front surface (the surface on the n ^- type silicon carbide layer 51 side) of the semiconductor substrate 50 and reaches the n ^- type silicon carbide layer 51. The depth direction is the direction from the front surface to the back surface of the semiconductor substrate 50. The surface layer of the n ^- type silicon carbide layer 51 on the p-type silicon carbide layer 52 side is in contact with the p-type silicon carbide layer 52 (p-type base region 4) and has an n-type region (hereinafter referred to as an n-type current diffusion region). ) 3 is selectively provided.

The n-type current diffusion region 3 is a so-called current diffusion layer (CSL) that reduces the spread resistance of carriers. The n-type current diffusion region 3 is uniformly provided in the active region 10 in the direction parallel to the front surface of the semiconductor substrate 50 so as to cover the inner wall (side wall and bottom surface) of the trench 7, for example. The n-type current diffusion region 3 may extend from the active region 10 to the intermediate region 30 and be terminated at the intermediate region 30. The portion of the n ^- type silicon carbide layer 51 other than the n-type current diffusion region 3, the first to 3p ⁺ type regions 11 to 13, the first and second JTE regions 41 and 42 and the n ⁺ type stopper region 43, which will be described later ^, is n-. The type drift region 2.

Inside the n-type current diffusion region 3, first to 3p ⁺ type regions 11 to 13 are selectively provided, respectively. The first p ⁺ type region 11 is arranged at a position deeper on the drain side (drain electrode 18 side) than the interface between the p-type base region 4 and the n-type current diffusion region 3, and separated from the p-type base region 4. Cover the bottom surface of the trench 7. The first p ⁺ type region 11 may cover the bottom surface of the trench 7 and the entire bottom surface corner portion. The bottom corner portion of the trench 7 is a boundary between the bottom surface and the side wall of the trench 7.

The first p ⁺ type region 11 (hereinafter referred to as the outermost first p ⁺ type region 11a) covering the bottom surface of the outermost trench 7a extends to the step 21 described later and is exposed to the bottom surface 21a of the step 21. There is. The bottom surface 21a of the step 21 is a front surface of the semiconductor substrate 50 newly formed in the edge end region 20 by forming the step 21. The exposure to the bottom surface 21a of the step 21 means that the surface layer of the bottom surface 21a of the step 21 is arranged so as to be in contact with the field oxide film 22 described later. The outermost first p ⁺ type region 11a extends outward from, for example, the n-type current diffusion region 3 and the third p ⁺ type region 13.

The second p ⁺ type region 12 is provided between adjacent trenches 7 (mesa region) apart from the first p ⁺ type region 11 and the trench 7, and is in contact with the p-type base region 4. In the second p ⁺ type region 12, for example, a portion 12a arranged at substantially the same depth as the first p ⁺ type region 11 and a portion 12b in contact with the p-type base region 4 are arranged adjacent to each other in the depth direction. It may have a two-layer structure. When the second p ⁺ type region 12 has a two-layer structure with the portions 12a and 12b, these portions 12a and 12b may have the same width and impurity concentration, for example.

The third p ⁺ type region 13 extends from the outermost trench 7a to the step 21 described later between the outermost first p ⁺ type region 11a and the p-type silicon carbide layer 52, and extends to the side wall 21b of the step 21. It is exposed. The side wall 21b of the step 21 is a side surface of the p-type silicon carbide layer 52 newly formed by forming the step 21, and is a front surface of the semiconductor substrate 50. The exposure on the side wall 21b of the step 21 means that the surface layer of the side wall 21b of the step 21 is arranged so as to be in contact with the field oxide film 22.

The third p ⁺ type region 13 extends outward from, for example, the n-type current diffusion region 3. Further, the third p ⁺ type region 13 is in contact with the outermost first p ⁺ type region 11a and the p-type silicon carbide layer 52. That is, in the intermediate region 30, the outermost peripheral first p ⁺ type region 11a, third p ⁺ type region 13 and p-type silicon carbide layer 52 are deeply formed on the surface layer of the front surface of the semiconductor substrate 50 from the drain side. A p-shaped region adjacent to each other in the direction is provided.

The first to 3p ⁺ type regions 11 to 13 may be selectively provided inside the n ^- type silicon carbide layer 51 without providing the n-type current diffusion region 3. It suffices if the pn junction between the first and second p ⁺ type regions 11 and 12 and the n-type current diffusion region 3 (or n ^- type drift region 2) is formed at a position deeper on the drain side than the bottom surface of the trench 7. The depth position of the surface of the first, second p ⁺ type regions 11 and 12 on the drain side can be variously changed according to the design conditions.

For example, the drain-side surfaces of the first and second p ⁺ -type regions 11 and 12 may be located inside the n-type current diffusion region 3 or the n ^- type drift region 2 on the drain side of the bottom surface of the trench 7. However, it may be located at the interface between the n-type current diffusion region 3 and the n ^- type drift region 2. The pn junction between the first and second p ⁺ type regions 11 and 12 and the n-type current diffusion region 3 (or n ^- type drift region 2) is located on the drain side of the bottom surface of the trench 7, so that the bottom surface of the trench 7 is formed. It is possible to prevent a high electric field from being applied to the gate insulating film 8 along the portion along the line.

Inside the p-type silicon carbide layer 52, an n ⁺ type source region 5 and a p ⁺⁺ type contact region 6 are selectively provided so as to be in contact with each other. The n ⁺ type source region 5 is in contact with the gate insulating film 8 on the side wall of the trench 7 and faces the gate electrode 9 via the gate insulating film 8 on the side wall of the trench 7. The drain-side surfaces of the n ⁺ -type source region 5 and the p ⁺⁺ -type contact region 6 are terminated inside the p-type silicon carbide layer 52. The p ⁺⁺ type contact region 6 faces the second p ⁺ type region 12 in the depth direction. For example, the p ⁺⁺ type contact region 6 may penetrate the p type silicon carbide layer 52 in the depth direction and reach the second p ⁺ type region 12.

Further, inside the p-type silicon carbide layer 52, a fourth p ⁺ type region 14 is provided near the side wall of the trench 7 at a predetermined distance from the side wall of the trench 7 and substantially parallel to the side wall of the trench 7. ing. The 4th p ⁺ type region 14 is in contact with the n ⁺ type source region 5 and is not in contact with the n type current diffusion region 3 and the 1st and 2nd p ⁺ type regions 11 and 12. The portion of the p-type base region 4 between the side wall of the trench 7 and the fourth p ⁺ type region 14 is a region (n-type inverted layer) is formed along the side wall of the trench 7 when the MOSFET is turned on. Hereinafter referred to as a channel area).

The fourth p ⁺ type region 14 is composed of a pn junction between the p-type base region 4 and the n ⁺ type source region 5 and a pn junction between the p-type base region 4 and the n-type current diffusion region 3 when the MOSFET is turned on. These are so-called HALO regions that suppress the depletion layer extending into the p-type base region 4, respectively. By providing the 4th p ⁺ type region 14, even if the thickness (= channel length) of the channel region is reduced in order to reduce the on-resistance, it is possible to suppress the increase in the short-channel effect when the MOSFET is turned on. , It is possible to suppress a decrease in the gate threshold voltage.

Further, inside the p-type silicon carbide layer 52, a fifth p ⁺ type region is formed at a predetermined depth from the front surface of the semiconductor substrate 50, parallel to the front surface of the semiconductor substrate 50, and separated from the trench 7. 15 is provided. The fifth p ⁺ type region 15 is provided, for example, between the adjacent fourth p ⁺ type regions 14 across the p ⁺⁺ type contact region 6 in the same mesa region, and the p type base region 4 and the n ⁺ type source region are provided. It touches 5 and the p ⁺⁺ type contact area 6. The fifth p ⁺ type region 15 is arranged only in the active region 10 and the intermediate region 30, not in the edge termination region 20.

The outermost 5p ⁺ type region 15 (hereinafter referred to as the outermost 5p ⁺ type region 15a) is parallel to the side wall 21b and the bottom surface 21a of the step 21 from the active region 10 side, respectively, and the bottom surface 21a of the step 21. It extends to a position facing in the depth direction. The outermost 5p ⁺ type region 15a is arranged at a predetermined depth from the bottom surface 21a and the side wall 21b of the step 21, and is not exposed to the bottom surface 21a and the side wall 21b of the step 21. The outermost end of the outermost 5p ⁺ type region 15a is terminated at the intermediate region 30.

The portion of the p-type silicon carbide layer 52 other than the n ⁺ type source region 5, the p ⁺⁺ type contact region 6 and the fourth and fifth p ⁺ type regions 14 and 15 is the p type base region 4. The interlayer insulating film 16 is provided on the entire front surface of the semiconductor substrate 50 in the active region 10 so as to cover the gate electrode 9 embedded in the trench 7. All gate electrodes 9 are electrically connected to the gate electrode pad (not shown) through a contact hole opened in the interlayer insulating film 16 at a portion (for example, near the boundary between the edge termination region 20 and the intermediate region 30) (not shown). Is connected.

The source electrode 17 is in contact with the n ⁺ type source region 5 and the p ⁺⁺ type contact region 6 via a contact hole opened in the interlayer insulating film 16, and is electrically connected to these regions. Further, the source electrode 17 is electrically insulated from the gate electrode 9 by the interlayer insulating film 16. The source electrode 17 may extend on the field oxide film 22. A drain electrode 18 is provided on the back surface of the semiconductor substrate 50 (the back surface of the n ⁺ type starting substrate 1 which is an n ⁺ type drain region) from the active region 10 to the edge termination region 20.

In the edge termination region 20, the p-type silicon carbide layer 52 is removed over the entire edge termination region 20, so that the edge termination region 20 is made lower than the active region 10 on the front surface of the semiconductor substrate 50 (drain). A step 21 (recessed to the side) is formed. The p-type silicon carbide layer 52 may be removed from the edge end region 20 to the outer portion of the intermediate region 30, and the step 21 may extend from the edge end region 20 to the intermediate region 30. That is, the side wall 21b of the step 21 may be located in the intermediate region 30.

As described above, the outermost first p ⁺ type region 11a extending from the active region 10 side is exposed on the active region 10 side of the bottom surface 21a of the step 21. The bottom corner portion 21c of the step 21 is covered with the outermost first p ⁺ type region 11a. The bottom corner portion 21c of the step 21 is a boundary between the bottom surface 21a of the step 21 and the side wall 21b. The n ^- type drift region 2 is exposed outside the outermost first p ⁺ type region 11a of the bottom surface 21a of the step 21.

On the surface layer of the portion of the n ^- type drift region 2 exposed to the bottom surface 21a of the step 21, a plurality of p-type regions (here, two; hereinafter, the active region 10) whose impurity concentration is lowered so as to be arranged outside. A JTE structure 40 is provided in which the first and second JTE regions 41 and 42 (referred to as the first and second JTE regions 41 and 42) are arranged adjacent to each other. The first and second JTE regions 41 and 42 have a lower impurity concentration than the outermost first p ⁺ type region 11a. The first JTE region 41 is arranged outside the outermost first p ⁺ type region 11a and is adjacent to the outermost first p ⁺ type region 11a.

The second JTE region 42 is arranged outside the first JTE region 41 and is adjacent to the first JTE region 41. The pressure resistant structure is configured by the JTE structure 40. When the MOSFET is off, a depletion layer extending outward from the pn junction between the p-type base region 4 and the n-type current diffusion region 3 spreads in both the first and second JTE regions 41 and 42. The withstand voltage in the edge end region 20 is ensured by the pn junction between the first and second JTE regions 41 and 42 and the n ^- type drift region 2.

Further, on the surface layer of the portion of the n ^- type drift region 2 exposed to the bottom surface 21a of the step 21, the n ⁺ type stopper region 43 is selected outside the second JTE region 42 and separated from the second JTE region 42. It is provided as a target. The n ⁺ type stopper region 43 is exposed on the side surface (that is, the chip end portion) of the semiconductor substrate 50. In the edge termination region 20 and the intermediate region 30, the front surface of the semiconductor substrate 50 is covered with the field oxide film 22.

Next, a method of manufacturing the semiconductor device according to the first embodiment will be described. 2 to 5 are cross-sectional views showing a state in which the semiconductor device according to the first embodiment is in the process of being manufactured. First, as shown in FIG. 2, an n ⁺ type starting board 1 serving as an n ⁺ type drain region is prepared. Next, the n ^- type silicon carbide layer 51 is epitaxially grown on the front surface of the n ⁺ type starting substrate 1. Next, the first to 3p ⁺ type regions 11 to 13 and the n-type current diffusion region 3 are selectively formed at a predetermined depth inside the n ^- type silicon carbide layer 51 by a general method (ion implantation or the like). Form.

Next, the p-type silicon carbide layer 52 is epitaxially grown on the n ^- type silicon carbide layer 51. As a result, the silicon carbide substrate (semiconductor wafer) 50 in which the n ^- type silicon carbide layer 51 and the p-type silicon carbide layer 52 are sequentially deposited on the n ⁺ type starting substrate 1 is formed. Next, a trench 7 is formed that penetrates the p-type silicon carbide layer 52 in the depth direction and reaches the first p ⁺ type region 11 inside the n-type current diffusion region 3. Next, the n ⁺ type source region 5 and the p ⁺⁺ type contact region 6 are selectively formed at predetermined positions inside the p-type silicon carbide layer 52 by a general method (ion implantation or the like). The portion of the p-type silicon carbide layer 52 other than the n ⁺ type source region 5 and the p ⁺⁺ type contact region 6 is the p-type base region 4.

Next, as shown in FIG. 3, the p-type silicon carbide layer 52 is removed by etching over the entire area of the edge termination region 20 to expose the n ^- type silicon carbide layer 51, whereby the front surface of the semiconductor substrate 50 is exposed. A step 21 is formed on the surface. As a result, the outermost first p ⁺ type region 11a is exposed on the active region 10 side of the bottom surface 21a of the step 21 and the bottom corner portion 21c of the step 21. The p-type base region 4 and the third p ⁺ -type region 13 are exposed on the side wall 21b of the step 21. At this time, for example, by forming the step 21 by isotropic etching, the angle θ1 of the side wall 21b of the step 21 with respect to the bottom surface 21a may be obtuse.

Next, as shown in FIG. 4, the n ^- type silicon carbide layer 51 is first placed at a predetermined position on the surface layer of the portion exposed on the bottom surface 21a of the step 21 by a general method (ion implantation or the like). 2 JTE regions 41 and 42 and n ⁺ type stopper regions 43 are selectively formed, respectively. Parts of the n ^- type silicon carbide layer 51 other than the 1st to 3p ⁺ type regions 11 to 13, the n-type current diffusion region 3, the 1st and 2nd JTE regions 41 and 42, and the n ⁺ type stopper region 43 are n ^- type drift. It becomes the area 2.

Next, as shown in FIG. 5, an oxide film mask 61 that covers the bottom surface 21a of the step 21 is formed in the edge end region 20. That is, the opening of the oxide film mask 61 is exposed from the active region 10 to the bottom corner portion 21c of the step 21. Next, p-type impurities such as aluminum (Al) are ion-implanted (diagonal ion implantation) into both side walls of the trench 7 from an oblique direction at a predetermined injection angle ± θ2 with respect to the front surface of the semiconductor substrate 50. 62. A plurality of (multiple stages) of oblique ion implantation 62 under different conditions may be performed on both side walls of the trench 7.

By this oblique ion implantation 62, the fourth p ⁺ type region 14 is selectively formed inside the p-type base region 4 so as to be self-aligned on the side wall of the trench 7 and separated from the side wall of the trench 7 by a predetermined distance. The distance of the 4th p ⁺ type region 14 from the side wall of the trench 7 can be adjusted by the implantation angle θ2 of the oblique ion implantation 62 and the acceleration energy. Further, by this oblique ion implantation 62, together with the 4p ⁺ type region 14, the surface layer of the front surface of the semiconductor substrate 50 at the opening of the oxide film mask 61 has a predetermined depth from the front surface of the semiconductor substrate 50. In addition, the fifth p ⁺ type region 15 is formed parallel to the front surface of the semiconductor substrate 50.

FIG. 5 shows a state in which oblique ion implantation 62 is performed at a predetermined injection angle (+ θ2) on one side wall (right side wall) of the trench 7, and is injected into the other side wall (left side wall) of the trench 7. The state in which the oblique ion implantation 62 is performed at an angle (−θ2) is omitted from the illustration (the same applies to FIGS. 6 to 8). In the state where the oblique ion implantation 62 is performed on the other side wall of the trench 7, the "arrow from the upper left to the lower right" indicating the oblique ion implantation 62 in FIG. 5 is changed to the "arrow from the upper right to the lower left". Will be.

At 62 o'clock of this oblique ion implantation, the fifth p ⁺ type region 15 is formed so as to extend to the side wall of the trench 7. Therefore, after the oblique ion implantation 62, the portion of the n ⁺ type source region 5 along the side wall of the trench 7 and the portion inverted into a p-type by the oblique ion implantation 62 is the front surface of the semiconductor substrate 50. It is inverted into an n ⁺ type by ion implantation from a direction in which the implantation angle is 0 degrees or more and 60 degrees or less with respect to the surface.

Next, heat treatment (activation annealing) for activating impurities is performed on all the regions formed by ion implantation. All the regions formed by ion implantation are n-type current diffusion region 3, n ⁺ type source region 5, p ⁺⁺ type contact region 6, 1st to 5p ⁺ type regions 11 to 15, 1st and 2nd JTE regions 41. , 42 and n ⁺ type stopper region 43. Next, the gate insulating film 8, the gate electrode 9, the interlayer insulating film 16, the contact hole, the source electrode 17, and the drain electrode 18 are formed by a general method. After that, the MOSFET shown in FIG. 1 is completed by dicing (cutting) the semiconductor wafer and individualizing it into individual chips.

As described above, according to the first embodiment, the edge termination region is covered with the oxide film mask, and the oblique ion implantation for forming the fourth p ⁺ type region constituting the halo structure is performed. Therefore, the 5p ⁺ type region formed together with the 4th p ⁺ type region by oblique ion implantation and arranged parallel to the front surface of the semiconductor substrate at a predetermined depth from the front surface of the semiconductor substrate is an edge. Not formed in the termination area. As a result, the potential in the edge termination region does not fluctuate from the potential obtained only by, for example, the JTE structure. The 4p ⁺ type region constituting the halo structure can be formed by the oblique ion implantation to suppress the short channel effect, and the withstand voltage reduction in the edge termination region due to the oblique ion implantation can be prevented.

(Embodiment 2)
Next, the structure of the semiconductor device according to the second embodiment will be described. FIG. 6 is a cross-sectional view showing a state in which the semiconductor device according to the second embodiment is in the process of being manufactured. The difference between the semiconductor device according to the second embodiment and the semiconductor device according to the first embodiment is that the width of the outermost 5p ⁺ type region 15c extending from the active region 10 side to the outside is narrowed. .. In the second embodiment, the outermost 5p ⁺ type region 15c is provided so as not to reach the step 21 from the active region 10 side.

As shown in FIG. 6, in the method for manufacturing a semiconductor device according to the second embodiment, in the method for manufacturing the semiconductor device according to the first embodiment, the oxide film mask 63 used for the oblique ion implantation 62 is attached to the bottom surface 21a of the step 21. And it may be formed so as to cover the side wall 21b.

As described above, according to the second embodiment, even when the width extending from the active region side to the outside of the outermost 5p ⁺ type region is narrowed, the same effect as that of the first embodiment can be obtained. Obtainable.

(Embodiment 3)
Next, the structure of the semiconductor device according to the third embodiment will be described. FIG. 7 is a cross-sectional view showing a state in which the semiconductor device according to the third embodiment is in the process of being manufactured. The difference between the semiconductor device according to the third embodiment and the semiconductor device according to the first embodiment is that the outer end of the outermost 5p ⁺ type region 15d is extended to the edge termination region 20 to extend the JTE structure 40. It is a point terminated inside the first JTE region 41 of.

As shown in FIG. 7, in the method for manufacturing a semiconductor device according to the third embodiment, in the method for manufacturing a semiconductor device according to the first embodiment, the oxide film mask 64 used for the oblique ion implantation 62 is JTE from the chip end portion. It may be formed so as to cover a part of the first JTE region 41 of the structure 40 on the chip end side. That is, at the time of oblique ion implantation 62, the opening of the oxide film mask 64 is exposed from the active region 10 to a part of the first JTE region 41 on the active region 10 side.

As described above, according to the third embodiment, the same effects as those of the first and second embodiments can be obtained. Further, according to the third embodiment, the outer end portion of the outermost 5p ⁺ type region is terminated inside the JTE region on the most active region side constituting the JTE structure. As a result, the impurity concentration in the JTE region on the most active region side constituting the JTE structure can be increased. Therefore, if the width of the edge termination region is not changed, the withstand voltage of the edge termination region can be improved, and if the withstand voltage of the edge termination region is not changed, the edge termination region can be shortened.

(Embodiment 4)
Next, the structure of the semiconductor device according to the fourth embodiment will be described. FIG. 8 is a cross-sectional view showing a state in which the semiconductor device according to the fourth embodiment is in the process of being manufactured. The difference between the semiconductor device according to the fourth embodiment and the semiconductor device according to the first embodiment is that the field limiting ring is a floating p ⁺ type region in the outer portion 15f of the outermost fifth p ⁺ type region 15e. It is a point that constitutes (FLR).

Specifically, in the fourth embodiment, the p-type region 44 is provided in place of the JTE structure on the surface layer of the portion of the n ^- type drift region 2 exposed to the bottom surface 21a of the step 21. The p-type region 44 is arranged outside the outermost first p ⁺ type region 11a and is adjacent to the outermost first p ⁺ type region 11a. The outermost fifth p ⁺ type region 15e extends from the active region 10 side to the inside of the p-type region 44, and is terminated outside the p-type region 44, for example.

The outermost portion 15f of the outermost 5p ⁺ type region 15e is separated into a plurality of parts inside the p type region 44. The distance between the separated parts 15f-1 to 15f-4 in the outer part 15f of the outermost 5p ⁺ type region 15e may be wide enough to be arranged on the outside. Separated portions 15f-1 to 15f-4 of the outermost portion 15f of the outermost 5p ⁺ type region 15e constitute a field limiting ring.

The method for manufacturing a semiconductor device according to the fourth embodiment is the method for manufacturing the semiconductor device according to the first embodiment, in which the oxide film mask 65 used for the oblique ion implantation 62 is attached to the outermost outermost 5p ⁺ type region 15e. The openings 65-1 to 65-4 corresponding to the formed regions of the separated portions 15f-1 to 15f-4 of the portion 15f may be formed.

As described above, according to the fourth embodiment, even when the field limiting ring is configured in the outer portion of the outermost 5p ⁺ type region 15e, the same effect as that of the first to third embodiments is obtained. Can be obtained.

(Example)
Next, the p-type impurity concentration profile of the 5th p ⁺ type region 15 formed by the oblique ion implantation 62 was verified. 9 and 10 are characteristic diagrams showing the p-type impurity concentration profile in the cutting line AA'of FIG. 1. 9 and 10 show the p-type impurity concentration profile in the depth direction from the front surface of the semiconductor substrate 50 in the 5p ⁺ type region 15a on the outermost circumference. The horizontal axis of FIGS. 9 and 10 is the depth from the front surface of the semiconductor substrate 50, and the vertical axis is the doping concentration of the 5p ⁺ type region 15a on the outermost circumference.

9 and 10 show the outermost 5p ⁺ type region 15a in the method of manufacturing the semiconductor device according to the first embodiment described above, when the implantation angles θ2 of the oblique ion implantation 62 are 45 degrees and 60 degrees, respectively. It is a doping concentration profile of a p-type impurity. In each of the samples shown in FIGS. 9 and 10, a fifth p ⁺ type region 15 is formed by performing two-stage oblique ion implantation 62 on each of the side walls of the trench 7.

Of the two-stage oblique ion implantation 62, the first-stage oblique ion implantation 62 had an aluminum dopant, an acceleration energy of 320 keV, and a dose amount of 3.5 × 10 ¹² / cm ² . In the second-stage oblique ion implantation 62, the dopant was aluminum, the acceleration energy was 260 keV, and the dose amount was 2.5 × 10 ¹² / cm ² .

From the results shown in FIGS. 9 and 10, it was confirmed that the impurity concentration near the front surface of the semiconductor substrate 50 was increased to about 1.0 × 10 ¹⁷ / cm ³ by the oblique ion implantation 62. In the present invention, it is necessary to prevent the impurity concentration in the vicinity of the front surface of the semiconductor substrate 50 in the edge termination region 20 from being uniformly about 1.0 × 10 ¹⁷ / cm ³ over the entire edge termination region 20. Can be done. Therefore, it has been confirmed that the present invention is useful in preventing a decrease in withstand voltage in the edge termination region 20.

In the above, the present invention can be variously modified without departing from the spirit of the present invention, and in each of the above-described embodiments, for example, the dimensions of each part, the impurity concentration, and the like are set variously according to the required specifications and the like. The present invention is also applicable to wide bandgap semiconductors other than silicon carbide (for example, gallium (Ga)). Further, the present invention is similarly established even if the conductive type (n type, p type) is inverted.

As described above, the semiconductor device and the method for manufacturing the semiconductor device according to the present invention are useful for a MOS type semiconductor device having a trench gate structure having a halo structure.

1 n ⁺ type starting substrate 2 n ^- type drift region 3 n type current diffusion region 4 p type base region 5 n ⁺ type source region 6 p ⁺⁺ type contact region 7, 7a trench 8 gate insulating film 9 gate electrode 10 active region 11, 11a 1st p ⁺ type region 12 2nd p ⁺ type region 12a, 12b Part of 2nd p ⁺ type region 13 3rd p ⁺ type region 14 4th p ⁺ type region 15 5th p ⁺ type region 15a, 15c to 15e Outermost 5p ⁺ type region 15f Outer part of the outermost 5p ⁺ type region 15f-1 to 15f-4 Each part constituting the field limiting ring outside the outermost 5p ⁺ type region 16 Interlayer insulating film 17 Source electrode 18 Drain electrode 20 Edge end region 21 Step on the front surface of the semiconductor substrate 21a Bottom of the step 21b Side wall of the step 21c Bottom corner of the step 22 Field oxide film 30 Intermediate region 40 JTE structure 41 1st JTE region 42 No. 2JTE region 43 n ⁺ type stopper region 44 p type region 50 semiconductor substrate 51 n ^- type silicon carbide layer 52 p type silicon carbide layer 61, 63-65 oxide film mask 62 Diagonal to form the 4th and 5th p ⁺ type regions Ion injection 65-1 to 65-4 Opening of oxide film mask θ1 Angle with respect to the bottom surface of the side wall of the step θ2 Injection angle of diagonal ion injection

Claims (9)

A semiconductor substrate made of a semiconductor with a wider bandgap than silicon,
The active region provided on the semiconductor substrate and
A terminal region that surrounds the active region and
The second conductive layer, which is a portion exposed on the front surface of the semiconductor substrate in a region other than the terminal region,
In the terminal region, it is exposed on the front surface of the semiconductor substrate, and is a portion on the back surface side of the semiconductor substrate in a region other than the terminal region, and is on the back surface side of the semiconductor substrate rather than the second conductive type layer. The first conductive type layer arranged in contact with the second conductive type layer and
A trench that penetrates the second conductive layer from the front surface of the semiconductor substrate in the depth direction and reaches the first conductive layer.
A gate electrode provided inside the trench via a gate insulating film,
A first semiconductor region of the first conductive type selectively provided along the side wall of the trench inside the second conductive type layer.
A second conductive type second semiconductor region selectively provided on the back surface side of the semiconductor substrate with respect to the first semiconductor region along the side wall of the trench and in contact with the first semiconductor region.
The second semiconductor, which is selectively provided inside the second conductive layer in contact with the first semiconductor region and the second semiconductor region and faces the side wall of the trench with the second semiconductor region interposed therebetween. The second conductive type third semiconductor region, which has a higher impurity concentration than the region,
Inside the second conductive type layer, the second conductive layer is selectively provided at a position deeper on the back surface side than the front surface of the semiconductor substrate and extends along the front surface of the semiconductor substrate. The second conductive type fourth semiconductor region, which has a higher impurity concentration than the semiconductor region,
A pressure-resistant structure provided on the front surface side of the semiconductor substrate in the terminal region,
The first electrode electrically connected to the first semiconductor region and
The second electrode provided on the back surface of the semiconductor substrate and
Equipped with
A semiconductor device characterized in that the fourth semiconductor region extends from the active region side to the terminal region side and is terminated inside the terminal region. The pressure-resistant structure is arranged adjacent to the surface layer of the front surface of the semiconductor substrate in a direction parallel to the front surface of the semiconductor substrate, and the impurity concentration is lowered as it is arranged outside. The semiconductor device according to claim 1, wherein the semiconductor device has a second conductive type fifth semiconductor region. A semiconductor substrate made of a semiconductor with a wider bandgap than silicon,
The active region provided on the semiconductor substrate and
A terminal region that surrounds the active region and
The second conductive layer, which is a portion exposed on the front surface of the semiconductor substrate in a region other than the terminal region,
In the terminal region, it is exposed on the front surface of the semiconductor substrate, and is a portion on the back surface side of the semiconductor substrate in a region other than the terminal region, and is on the back surface side of the semiconductor substrate rather than the second conductive type layer. The first conductive type layer arranged in contact with the second conductive type layer and
A trench that penetrates the second conductive layer from the front surface of the semiconductor substrate in the depth direction and reaches the first conductive layer.
A gate electrode provided inside the trench via a gate insulating film,
A first semiconductor region of the first conductive type selectively provided along the side wall of the trench inside the second conductive type layer.
A second conductive type second semiconductor region selectively provided on the back surface side of the semiconductor substrate with respect to the first semiconductor region along the side wall of the trench and in contact with the first semiconductor region.
The second semiconductor, which is selectively provided inside the second conductive layer in contact with the first semiconductor region and the second semiconductor region and faces the side wall of the trench with the second semiconductor region interposed therebetween. The second conductive type third semiconductor region, which has a higher impurity concentration than the region,
Inside the second conductive type layer, the second conductive layer is selectively provided at a position deeper on the back surface side than the front surface of the semiconductor substrate and extends along the front surface of the semiconductor substrate. The second conductive type fourth semiconductor region, which has a higher impurity concentration than the semiconductor region,
A pressure-resistant structure provided on the front surface side of the semiconductor substrate in the terminal region,
The first electrode electrically connected to the first semiconductor region and
The second electrode provided on the back surface of the semiconductor substrate and
Equipped with
The pressure-resistant structure is arranged adjacent to the surface layer of the front surface of the semiconductor substrate in a direction parallel to the front surface of the semiconductor substrate, and the impurity concentration is lowered as it is arranged outside. It has a second conductive type fifth semiconductor region and has a second conductive type fifth semiconductor region.
A semiconductor device characterized in that the fourth semiconductor region extends from the active region side to the terminal region and is terminated inside the innermost fifth semiconductor region. A semiconductor substrate made of a semiconductor with a wider bandgap than silicon,
The active region provided on the semiconductor substrate and
A terminal region that surrounds the active region and
The second conductive layer, which is a portion exposed on the front surface of the semiconductor substrate in a region other than the terminal region,
In the terminal region, it is exposed on the front surface of the semiconductor substrate, and is a portion on the back surface side of the semiconductor substrate in a region other than the terminal region, and is on the back surface side of the semiconductor substrate rather than the second conductive type layer. The first conductive type layer arranged in contact with the second conductive type layer and
A trench that penetrates the second conductive layer from the front surface of the semiconductor substrate in the depth direction and reaches the first conductive layer.
A gate electrode provided inside the trench via a gate insulating film,
A first semiconductor region of the first conductive type selectively provided along the side wall of the trench inside the second conductive type layer.
A second conductive type second semiconductor region selectively provided on the back surface side of the semiconductor substrate with respect to the first semiconductor region along the side wall of the trench and in contact with the first semiconductor region.
The second semiconductor, which is selectively provided inside the second conductive layer in contact with the first semiconductor region and the second semiconductor region and faces the side wall of the trench with the second semiconductor region interposed therebetween. The second conductive type third semiconductor region, which has a higher impurity concentration than the region,
Inside the second conductive type layer, the second conductive layer is selectively provided at a position deeper on the back surface side than the front surface of the semiconductor substrate and extends along the front surface of the semiconductor substrate. The second conductive type fourth semiconductor region, which has a higher impurity concentration than the semiconductor region,
A pressure-resistant structure provided on the front surface side of the semiconductor substrate in the terminal region,
The first electrode electrically connected to the first semiconductor region and
The second electrode provided on the back surface of the semiconductor substrate and
Equipped with
The pressure-resistant structure has a second conductive type fifth semiconductor region provided on the surface layer of the front surface of the semiconductor substrate.
The fourth semiconductor region extends from the active region side to the terminal region.
A semiconductor device characterized in that a plurality of portions extending to the terminal region of the fourth semiconductor region are arranged at predetermined intervals in a direction from the active region side to the outside. A first conductive type region that is selectively provided inside the first conductive type layer separately from the second semiconductor region and covers the bottom surface of the trench.
A second conductive type region selectively provided inside the first conductive type layer between the adjacent trenches and separated from the trench.
Further prepare
The semiconductor device according to claim 3 or 4, wherein the first second conductive region extends from the active region toward the terminal region and is adjacent to the inside of the fifth semiconductor region. A method for manufacturing a semiconductor device having a gate structure in which a gate electrode is embedded in a trench via a gate insulating film.
The first step of epitaxially growing a first conductive layer on the surface of a starting substrate made of a semiconductor having a bandgap wider than that of silicon.
By epitaxially growing the second conductive type layer on the first conductive type layer, a semiconductor substrate having the front surface on the second conductive type layer side as the front surface and the front surface on the starting substrate side as the back surface is produced. The second step to do and
A third step of forming the trench at a predetermined depth that penetrates the second conductive layer in the active region and reaches the first conductive layer.
A first conductive type first semiconductor region is selectively formed inside the second conductive type layer along the side wall of the trench, and the semiconductor is more than the first semiconductor region of the second conductive type layer. The fourth step of leaving the portion on the back surface side of the substrate as the second semiconductor region of the second conductive type,
A fifth step of removing the second conductive layer in the terminal region surrounding the active region and exposing the first conductive layer on the front surface of the semiconductor substrate.
In the terminal region, a sixth step of forming a pressure resistant structure on the front surface side of the semiconductor substrate, and
A seventh step of forming an oxide film covering the front surface of the semiconductor substrate at least in the terminal region.
Using the oxide film as a mask, ion-implants the second conductive impurity into the front surface of the semiconductor substrate and the side wall of the trench at a predetermined injection angle from an oblique direction with respect to the front surface of the semiconductor substrate. Eighth step and
Including
In the eighth step,
Impurities inside the second conductive layer, which are in contact with the first semiconductor region and the second semiconductor region and face the side wall of the trench with the second semiconductor region interposed therebetween, more than the second semiconductor region. In addition to selectively forming the second conductive type third semiconductor region with high concentration,
Inside the second conductive type layer, the impurity concentration is higher than that of the second semiconductor region extending along the front surface of the semiconductor substrate at a position deeper than the front surface of the semiconductor substrate. The second conductive type fourth semiconductor region is selectively formed, and the second conductive type fourth semiconductor region is selectively formed.
A method for manufacturing a semiconductor device, characterized in that the fourth semiconductor region extends from the active region side to the terminal region side and is terminated inside the terminal region. A method for manufacturing a semiconductor device having a gate structure in which a gate electrode is embedded in a trench via a gate insulating film.
The first step of epitaxially growing a first conductive layer on the surface of a starting substrate made of a semiconductor having a bandgap wider than that of silicon.
By epitaxially growing the second conductive type layer on the first conductive type layer, a semiconductor substrate having the front surface on the second conductive type layer side as the front surface and the front surface on the starting substrate side as the back surface is produced. The second step to do and
A third step of forming the trench at a predetermined depth that penetrates the second conductive layer in the active region and reaches the first conductive layer.
A first conductive type first semiconductor region is selectively formed inside the second conductive type layer along the side wall of the trench, and the semiconductor is more than the first semiconductor region of the second conductive type layer. The fourth step of leaving the portion on the back surface side of the substrate as the second semiconductor region of the second conductive type,
A fifth step of removing the second conductive layer in the terminal region surrounding the active region and exposing the first conductive layer on the front surface of the semiconductor substrate.
In the terminal region, a sixth step of forming a pressure resistant structure on the front surface side of the semiconductor substrate, and
A seventh step of forming an oxide film covering the front surface of the semiconductor substrate at least in the terminal region.
Using the oxide film as a mask, ion-implants the second conductive impurity into the front surface of the semiconductor substrate and the side wall of the trench at a predetermined injection angle from an oblique direction with respect to the front surface of the semiconductor substrate. Eighth step and
Including
In the sixth step, as the withstand voltage structure, impurities are arranged on the surface layer of the front surface of the semiconductor substrate adjacent to each other in a direction parallel to the front surface of the semiconductor substrate, and are arranged outside. A plurality of second conductive type fifth semiconductor regions having a low concentration are selectively formed.
In the eighth step,
Impurities inside the second conductive layer, which are in contact with the first semiconductor region and the second semiconductor region and face the side wall of the trench with the second semiconductor region interposed therebetween, more than the second semiconductor region. In addition to selectively forming the second conductive type third semiconductor region with high concentration,
Inside the second conductive type layer, the impurity concentration is higher than that of the second semiconductor region extending along the front surface of the semiconductor substrate at a position deeper than the front surface of the semiconductor substrate. The second conductive type fourth semiconductor region is selectively formed, and the second conductive type fourth semiconductor region is selectively formed.
A method for manufacturing a semiconductor device, characterized in that the fourth semiconductor region extends from the active region side to the terminal region and is terminated inside the innermost fifth semiconductor region. A method for manufacturing a semiconductor device having a gate structure in which a gate electrode is embedded in a trench via a gate insulating film.
The first step of epitaxially growing a first conductive layer on the surface of a starting substrate made of a semiconductor having a bandgap wider than that of silicon.
By epitaxially growing the second conductive type layer on the first conductive type layer, a semiconductor substrate having the front surface on the second conductive type layer side as the front surface and the front surface on the starting substrate side as the back surface is produced. The second step to do and
A third step of forming the trench at a predetermined depth that penetrates the second conductive layer in the active region and reaches the first conductive layer.
A first conductive type first semiconductor region is selectively formed inside the second conductive type layer along the side wall of the trench, and the semiconductor is more than the first semiconductor region of the second conductive type layer. The fourth step of leaving the portion on the back surface side of the substrate as the second semiconductor region of the second conductive type,
A fifth step of removing the second conductive layer in the terminal region surrounding the active region and exposing the first conductive layer on the front surface of the semiconductor substrate.
In the terminal region, a sixth step of forming a pressure resistant structure on the front surface side of the semiconductor substrate, and
A seventh step of forming an oxide film covering the front surface of the semiconductor substrate at least in the terminal region.
Using the oxide film as a mask, ion-implants the second conductive impurity into the front surface of the semiconductor substrate and the side wall of the trench at a predetermined injection angle from an oblique direction with respect to the front surface of the semiconductor substrate. Eighth step and
Including
In the sixth step, as the withstand voltage structure, a second conductive type fifth semiconductor region provided on the surface layer of the front surface of the semiconductor substrate is formed.
In the eighth step,
Impurities inside the second conductive layer, which are in contact with the first semiconductor region and the second semiconductor region and face the side wall of the trench with the second semiconductor region interposed therebetween, more than the second semiconductor region. In addition to selectively forming the second conductive type third semiconductor region with high concentration,
Inside the second conductive type layer, the impurity concentration is higher than that of the second semiconductor region extending along the front surface of the semiconductor substrate at a position deeper than the front surface of the semiconductor substrate. The second conductive type fourth semiconductor region is selectively formed, and the second conductive type fourth semiconductor region is selectively formed.
The fourth semiconductor region extends from the active region side to the terminal region.
A method for manufacturing a semiconductor device, characterized in that a plurality of portions extending to the terminal region of the fourth semiconductor region are arranged at predetermined intervals in a direction from the active region side to the outside. In the seventh step, a plurality of openings are formed in the oxide film so as to be separated from each other in the direction from the active region side to the outside.
The eighth step is characterized in that a portion extending to the terminal region of the fourth semiconductor region is formed on a surface layer exposed to the opening on the front surface of the semiconductor substrate. Item 8. The method for manufacturing a semiconductor device according to Item 8.

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