JP7151446B2 - Semiconductor device manufacturing method - Google Patents

Description

The technology disclosed in this specification relates to a method of manufacturing a semiconductor device having a trench gate.

Patent document 1 discloses a semiconductor device having a trench gate with a curved shoulder. In a semiconductor device having such a trench gate, electric field concentration at the shoulder is relaxed, and gate-source leakage current is reduced.

JP 2016-82096 A

In Patent Document 1, an n-type drift region, a p-type body region, and an n-type source region are arranged in this order along the depth direction of a semiconductor substrate. A manufacturing method is disclosed in which, after forming the trenches extending in the depth direction, annealing is performed to curve the shoulders of the trenches. In this manufacturing method, annealing is performed to melt the shoulder of the trench and curve the shoulder of the trench.

However, an n-type source region is located at the shoulder of the trench. Therefore, if a part of the melted n-type source region flows down along the side surface of the trench and reaches the p-type body region exposed on the side surface of the trench, it may cause problems in the channel operation of the semiconductor device. .

The present specification provides a manufacturing method capable of curving the shoulder portion of the trench while suppressing the occurrence of defects in the channel operation of the semiconductor device.

In the method of manufacturing a semiconductor device disclosed in the present specification, a drift region of a first conductivity type, a body region of a second conductivity type, and a source region of a first conductivity type are arranged in this order along the depth direction of a semiconductor substrate. forming a trench extending in the depth direction through the source region and the body region from the surface of the semiconductor substrate in the step of covering at least a portion of the body region exposed on the side surface of the trench forming a protective film in the trench so as to expose a shoulder portion of the trench; and performing an annealing treatment while the side surface of the trench is covered with the protective film so as to be exposed from the protective film. and curving the shoulder of the trench. Here, as long as the drift region, the body region, and the source region are arranged in this order along the depth direction of the semiconductor substrate, another semiconductor region may be interposed between these regions. For example, between the drift region and the body region, a JFET resistance reduction region having a higher first conductivity type impurity concentration than the drift region may be interposed.

According to the above manufacturing method, at least part of the body region exposed on the side surface of the trench is covered with the protective film when the annealing treatment is performed. Therefore, the part of the source region melted by the annealing process is prevented from running down to the part of the body region covered with the protective film. Thereby, the semiconductor device can perform stable channel operation by the part of the body region. As described above, according to the manufacturing method described above, the shoulder portion of the trench can be curved while suppressing the occurrence of defects in the channel operation of the semiconductor device.

1 schematically shows a cross-sectional view of a main part of a semiconductor device according to an embodiment; FIG. FIG. 4 schematically shows cross-sectional views of essential parts of the manufacturing process of the semiconductor device of the present embodiment. FIG. 4 schematically shows cross-sectional views of essential parts of the manufacturing process of the semiconductor device of the present embodiment. FIG. 4 schematically shows cross-sectional views of essential parts of the manufacturing process of the semiconductor device of the present embodiment. FIG. 4 schematically shows cross-sectional views of essential parts of the manufacturing process of the semiconductor device of the present embodiment. FIG. 4 schematically shows cross-sectional views of essential parts of the manufacturing process of the semiconductor device of the present embodiment. FIG. 4 schematically shows cross-sectional views of essential parts of the manufacturing process of the semiconductor device of the present embodiment. FIG. 4 schematically shows cross-sectional views of essential parts of the manufacturing process of the semiconductor device of the present embodiment. FIG. 4 schematically shows cross-sectional views of essential parts of the manufacturing process of the semiconductor device of the present embodiment. FIG. 4 schematically shows cross-sectional views of essential parts of the manufacturing process of the semiconductor device of the present embodiment.

As shown in FIG. 1, a semiconductor device 1 is a power semiconductor element called a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and includes a semiconductor substrate 10, a drain electrode 22 covering a back surface 10a of the semiconductor substrate 10, a semiconductor A source electrode 24 covering the surface 10 b of the substrate 10 and a trench gate 30 provided on the surface layer of the semiconductor substrate 10 are provided. The trench gates 30 are arranged, for example, in stripes when viewed from a direction orthogonal to the surface 10b of the semiconductor substrate 10 .

The semiconductor substrate 10 is a substrate made of silicon carbide (SiC), and includes an n ⁺ type drain region 11 , an n type drift region 12 , a p type electric field relaxation region 13 , and an n ⁺ type JFET resistance reduction region 14 . , p-type body regions 15 , p ⁺ -type body contact regions 16 and n ⁺ -type source regions 17 .

The drain region 11 is arranged in the back layer portion of the semiconductor substrate 10 and exposed to the back surface of the semiconductor substrate 10 . The drain region 11 is also a base substrate for epitaxial growth of the drift region 12, which will be described later. The drain region 11 is in ohmic contact with a drain electrode 22 covering the back surface of the semiconductor substrate 10 .

Drift region 12 is provided on drain region 11 . The drift region 12 is formed by crystal growth from the surface of the drain region 11 using an epitaxial growth technique. The impurity concentration of drift region 12 is constant in the thickness direction of semiconductor substrate 10 .

The electric field relaxation region 13 is provided so as to cover the bottom surface of the trench gate 30 and can relax the electric field concentrated on the bottom surface of the trench gate 30 . In this cross-section, field relief region 13 is separated from body region 15 by drift region 12 and JFET resistance reduction region 14 . However, electric field relaxation region 13 may be connected to body region 15 in a cross section not shown. The electric field relaxation region 13 is formed on the bottom surface of the trench by ion-implanting aluminum toward the bottom surface of the trench for forming the trench gate 30 using an ion implantation technique.

The JFET resistance reduction region 14 is provided between the drift region 12 and the body region 15 , separates the drift region 12 and the body region 15 , and has a higher n-type impurity concentration than the drift region 12 . The JFET resistance reduction region 14 extends from the side of one trench gate 30 to the side of the other trench gate 30 between adjacent trench gates 30 . The JFET resistance reduction region 14 is formed at a position in contact with both the drift region 12 and the body region 15 by implanting nitrogen ions toward the surface of the semiconductor substrate 10 using an ion implantation technique.

The body region 15 is provided on the JFET resistance reduction region 14 and arranged in the surface layer portion of the semiconductor substrate 10 . Body region 15 is in contact with the side surface of trench gate 30 . The body region 15 is formed in the surface layer portion of the semiconductor substrate 10 by implanting aluminum ions toward the surface of the semiconductor substrate 10 using an ion implantation technique.

The body contact region 16 is provided on the body region 15 , is arranged in the surface layer portion of the semiconductor substrate 10 , is exposed to the surface of the semiconductor substrate 10 , and has a p-type impurity concentration higher than that of the body region 15 . It is a dark area. Body contact region 16 is in ohmic contact with source electrode 24 covering surface 10 b of semiconductor substrate 10 . The body contact region 16 is formed in the surface layer portion of the semiconductor substrate 10 by implanting aluminum ions toward the surface of the semiconductor substrate 10 using an ion implantation technique.

The source region 17 is provided on the body region 15 , is arranged in the surface layer portion of the semiconductor substrate 10 , and is exposed to the surface 10 b of the semiconductor substrate 10 . Source region 17 is separated from JFET resistance reduction region 14 by body region 15 . Source region 17 abuts the side surface of trench gate 30 . Source region 17 is in ohmic contact with source electrode 24 covering surface 10 b of semiconductor substrate 10 . The source region 17 is formed in the surface layer portion of the semiconductor substrate 10 by implanting nitrogen ions toward the surface of the semiconductor substrate 10 using an ion implantation technique.

The shoulder portion 30a of the trench gate 30 is curved at the position where the source region 17 is provided. The shoulder portion 30 a of the trench gate 30 is a portion where the surface 10 b of the semiconductor substrate 10 and the side surface of the trench gate 30 intersect, and corresponds to the opening of the trench gate 30 on the surface 10 b of the semiconductor substrate 10 . When the shoulder portion 30a of the trench gate 30 is curved in this way, the electric field concentration at the shoulder portion 30a is relaxed, and the leakage current between the gate and the source is reduced.

The trench gate 30 extends from the surface 10b of the semiconductor substrate 10 along the depth direction (vertical direction on the paper surface) of the semiconductor substrate 10 and has a gate insulating film 32 and a gate electrode 34 . Trench gate 30 extends through source region 17 , body region 15 , and JFET resistance reduction region 14 to drift region 12 . The gate insulating film 32 is silicon oxide. The gate electrode 34 is covered with the gate insulating film 32 and made of polysilicon containing impurities.

Next, operation of the semiconductor device 1 will be described with reference to FIG. The semiconductor device 1 is off when a positive voltage is applied to the drain electrode 22, the source electrode 24 is grounded, and the gate electrode 34 of the trench gate 30 is grounded. In the semiconductor device 1 , the electric field relaxation region 13 is provided so as to cover the bottom surface of the trench gate 30 . Therefore, electric field concentration in the gate insulating film 32 on the bottom surface of the trench gate 30 is alleviated, and the semiconductor device 1 can have a high breakdown voltage.

When a positive voltage is applied to the drain electrode 22, the source electrode 24 is grounded, and a voltage equal to or higher than the threshold voltage, which is more positive than the source electrode 24, is applied to the gate electrode 34 of the trench gate 30, the semiconductor device 1 is turned on. is. At this time, an inversion layer is formed in a portion of the body region 15 that separates the source region 17 and the JFET resistance reduction region 14 and faces the side surface of the trench gate 30 . Electrons supplied from the source region 17 reach the JFET resistance reduction region 14 via the inversion layer. Electrons that have reached the JFET resistance reduction region 14 flow into the drift region 12 via the JFET resistance reduction region 14 . When such a JFET resistance reduction region 14 is provided, current can flow so as to bypass the depletion layer extending from the electric field relaxation region 13 into the drift region 12 . Therefore, an increase in resistance due to such a depletion layer, that is, an increase in JFET resistance is suppressed. As described above, the semiconductor device 1 has a structure suitable for a miniaturized structure in which the pitch width of the trench gates 30 is narrow.

Next, a method for manufacturing the semiconductor device 1 will be described. First, as shown in FIG. 2, a semiconductor substrate in which the drain region 11, the drift region 12, the JFET resistance reduction region 14, the body region 15, and the source region 17 are arranged in this order along the depth direction of the semiconductor substrate 10. Prepare 10. The drain region 11 is exposed on the back surface 10 a of the semiconductor substrate 10 and the source region 17 is exposed on the front surface 10 b of the semiconductor substrate 10 . A body contact region 16 is also formed between the source regions 17 in the surface layer portion of the semiconductor substrate 10 . This semiconductor substrate 10 uses an epitaxial growth technique to crystal-grow the drain region 11 and the drift region 12, and then uses an ion implantation technique to add n-type impurities and p-type impurities toward the surface 10b of the semiconductor substrate 10. to form JFET resistance reduction region 14 , body region 15 , body contact region 16 and source region 17 .

Next, as shown in FIG. 3, a resist film 42 is patterned on the front surface 10b of the semiconductor substrate 10 using a photolithographic technique. The resist film 42 is patterned so that part of the source region 17 is exposed through the opening. Next, a dry etching technique is used to form a trench TR extending along the depth direction of the semiconductor substrate 10 from the surface 10b of the semiconductor substrate 10 exposed through the opening of the resist film 42 . Trench TR is formed to reach drift region 12 from surface 10 b of semiconductor substrate 10 through source region 17 , body region 15 and JFET resistance reduction region 14 . Trench TR may be formed so as to pass through source region 17 and body region 15 and have its bottom surface positioned within JFET resistance reduction region 14 .

Next, as shown in FIG. 4, using an ion implantation technique, aluminum is ion-implanted toward drift region 12 exposed at the bottom surface of trench TR so that aluminum is ion-implanted onto drift region 12 and onto the bottom surface of trench TR. An exposed electric field relaxation region 13 is formed. Prior to this ion implantation, a protective film may be formed on the side surface of trench TR in order to prevent aluminum from being introduced into the side surface of trench TR.

Next, as shown in FIG. 5, a film forming technique is used to form a carbon cap film 44 so as to cover the surface 10b of the semiconductor substrate 10 and the side and bottom surfaces of the trench TR. After forming the carbon cap film 44, an activation annealing process is performed to activate various semiconductor regions formed by ion implantation. By forming the carbon cap film 44 prior to the activation annealing treatment, surface roughness due to sublimation or the like on the surface 10b of the semiconductor substrate 10 and the side and bottom surfaces of the trench TR can be suppressed.

Next, as shown in FIG. 6, the carbon cap film 44 is removed using an etching technique.

Next, as shown in FIG. 7, a film forming technique is used to form a protective film 46 so as to fill trench TR. The protective film 46 is a material having a melting point that does not melt at the temperature of the annealing treatment described below. In this example, the material of the protective film 46 is carbon. As a method for forming the protective film 46, a CVD method such as a thermal CVD method or a plasma CVD method may be used, or a PVC method such as a vacuum deposition method or a sputtering method may be used.

Next, as shown in FIG. 8, a dry etching technique is used to remove the protective film 46 formed on the surface 10b of the semiconductor substrate 10 and the protective film 46 filling the trenches TR. Remove some. Protective film 46 in trench TR is etched back from surface 10b of semiconductor substrate 10 to a depth of about 100 nm. The upper surface of protective film 46 in trench TR is adjusted within the depth range where source region 17 exists. Therefore, the entirety of body region 15 exposed on the side surface of trench TR is covered with protective film 46 . Thus, shoulder portion 30a where surface 10b of semiconductor substrate 10 intersects the side surface of trench TR is not covered with protective film 46 and is exposed to the outside.

Next, as shown in FIG. 9, an annealing technique is used to curve shoulder portion 30a of trench TR. The temperature of this annealing step is equal to or higher than the temperature at which a portion of source region 17 located at shoulder portion 30a of trench TR is melted, and is equal to or lower than the temperature at which protective film 46 is not melted. In this example, silicon carbide is used as the material of semiconductor substrate 10 . Therefore, when the temperature of the annealing step exceeds the melting point (1414° C.) of silicon, silicon constituting silicon carbide melts, and shoulder portion 30a of trench TR is curved. Specifically, this annealing step is performed under an inert gas atmosphere at approximately 1700°C. As a result, a portion of source region 17 located at shoulder portion 30a of trench TR is melted, and shoulder portion 30a of trench TR is curved. At this time, trench TR is filled with protective film 46 , so that part of melted source region 17 is prevented from flowing down to body region 15 . For example, if trench TR is not filled with protective film 46 , there is a concern that part of melted source region 17 may flow over body region 15 and into JFET resistance reduction region 14 . In such a case, source region 17 and JFET resistance reduction region 14 are connected through a portion of drooping source region 17 to allow normal channel operation (i.e. switching on and off based on the desired threshold voltage). ) may not be possible. In this manufacturing method, trench TR is filled with protective film 46, so that such a situation can be prevented from occurring.

Next, as shown in FIG. 10, etching technology is used to remove protective film 46 filling trench TR. Next, using the CVD technique, gate insulating film 32 is deposited in trench TR. Next, the CVD technique is used to fill the trench with the gate electrode 34 . Finally, the drain electrode 22 is formed on the back surface of the semiconductor substrate 10, and the source electrode 24 is formed on the surface of the semiconductor substrate 10, whereby the semiconductor device 1 is completed.

In the manufacturing method described above, protective film 46 filled in trench TR covers the entire body region 15 exposed on the side surface of trench TR. Instead of this example, protective film 46 may cover at least part of body region 15 exposed on the side surface of trench TR. For example, when the body region 15 is formed by ion implantation, the protective film 46 is provided so as to cover at least the side surface with a depth corresponding to the peak position of the impurity concentration of the body region 15 that determines the threshold voltage. good too. Further, when the body region 15 is formed by crystal growth or by multistage ion implantation, the impurity concentration of the body region 15 is substantially constant in the depth direction. is arbitrary in the depth direction. In this case, protective film 46 may cover at least part of body region 15 exposed on the side surface of trench TR.

Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. In addition, the technical elements described in this specification or in the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques exemplified in this specification or drawings can simultaneously achieve a plurality of purposes, and achieving one of them has technical utility in itself.

Reference Signs List 1: semiconductor device 10: semiconductor substrate 11: drain region 12: drift region 13: electric field relaxation region 14: JFET resistance reduction region 15: body region 16: body contact region 17: source region 22: drain electrode 24: source electrode 30: Trench gate 30a: shoulder portion 32: gate insulating film 34: gate electrode

Claims (1)

A drift region of a first conductivity type, a body region of a second conductivity type, and a source region of a first conductivity type are arranged in this order along the depth direction of the semiconductor substrate. forming a trench extending in the depth direction through the body region;
forming a protective film in the trench so as to cover at least a portion of the body region exposed on the side surface of the trench and expose a shoulder portion of the trench;
and performing annealing in an inert gas atmosphere while the side surfaces of the trench are covered with the protective film to melt and curve the shoulder portion of the trench exposed from the protective film. , a method for manufacturing a semiconductor device.

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