CN116646391A - Trench power device and manufacturing method thereof - Google Patents
Trench power device and manufacturing method thereof Download PDFInfo
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- CN116646391A CN116646391A CN202310920524.1A CN202310920524A CN116646391A CN 116646391 A CN116646391 A CN 116646391A CN 202310920524 A CN202310920524 A CN 202310920524A CN 116646391 A CN116646391 A CN 116646391A
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- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 6
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention relates to a manufacturing method of a trench power device, which comprises the steps of providing a substrate and an epitaxy arranged on the substrate, forming a first window on a first hard mask layer, and injecting P-type impurities into the first window to form a P-type body region and a P-type compression ring; removing the first hard mask layer, depositing a second hard mask layer above the silicon oxide layer, forming a second window in the second hard mask layer, injecting high-energy N-type impurities into the second window, and forming a JFET doping region below the P-type body region by the high-energy N-type impurities; injecting N-type impurities into the second window to form an N+ source region in the P-type body region; depositing a silicon oxide or silicon nitride dielectric layer and etching back on the second window to form a side wall structure; etching epitaxy through a second window under the shielding of the second hard mask layer and the side wall structure to form a groove; and etching the interlayer dielectric layer through a photomask to form a third window, injecting P-type impurities into the third window to form P+ ohmic contact, and activating the P+ ohmic contact by adopting furnace tube annealing or rapid thermal annealing.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a trench power device and a manufacturing method thereof.
Background
In the prior art, the trench type device is a common structure in the power MOSFET device, and has wide application range and relatively mature process technology. Under the condition of smaller and smaller differentiation, how to control the production cost and simultaneously improve the performance of devices to the maximum extent, and providing a product with characteristics becomes a problem facing the industry.
The conventional trench power device is fabricated by etching a trench in a prepared epitaxial layer, forming a gate oxide layer and gate polysilicon, forming a P-type Body region (Body) by ion implantation and forming an n+ source region on the P-type Body region, depositing an interlayer dielectric layer (ILD) and opening a wiring hole, depositing front side metal and back side etching, back side thinning and back side metallization. In the process, the n+ source region must be defined by a mask to define a corresponding implantation pattern, resulting in high production cost. And, when the reduction in thickness is limited, it is difficult to further reduce the on-resistance of the device. Therefore, it is necessary to improve the manufacturing process of the trench power device, reduce the manufacturing cost of the device, optimize the on-resistance, and improve the cost performance of the device.
Disclosure of Invention
The first object of the present invention is to provide a method for manufacturing a trench power device, which aims to solve the problem of high manufacturing cost caused by the need of using a photomask for multiple times in the manufacturing process of generating a trench of the trench power device, improve the problem of gate-source leakage and optimize the on-resistance of the trench power device.
In order to solve the above technical problems, a method for manufacturing a trench power device is provided, including:
providing a substrate and an epitaxy arranged on the substrate, thermally oxidizing a silicon oxide layer above the epitaxy, and depositing a first hard mask layer above the silicon oxide layer;
the first hard mask layer is provided with a first window, and P-type impurities are injected into the first window to form a P-type body region and a P-type compression ring;
removing the first hard mask layer, depositing a second hard mask layer above the silicon oxide layer, forming a second window in the second hard mask layer, implanting high-energy N-type impurities into the second window, and forming a JFET doping region below the P-type body region by the high-energy N-type impurities;
implanting N-type impurities into the second window to form an N+ source region in the P-type body region;
depositing a silicon oxide or silicon nitride dielectric layer and etching back to the second window to form a side wall structure;
etching the epitaxy through the second window under the shielding of the second hard mask layer and the side wall structure to form a groove;
forming a gate oxide layer in the groove, depositing gate polysilicon in the groove, and etching the gate polysilicon back;
depositing an interlayer dielectric layer on the gate polysilicon, and flattening by adopting furnace tube annealing;
and etching the interlayer dielectric layer through a photomask to form a third window, injecting P-type impurities into the third window to form P+ ohmic contact, and activating the P+ ohmic contact by adopting furnace tube annealing or rapid thermal annealing.
Further, the implanting P-type impurities into the first window to form a P-type body region and a P-type compression-resistant ring comprises:
and injecting P-type impurities into the epitaxy by utilizing the first window of the first hard mask layer, wherein the P-type impurities in the end ring region injection window are subjected to high-temperature annealing and pushing to form a P-type compression ring, and the P-type impurities in the active region injection window are subjected to high-temperature annealing and pushing to form a P-type body region.
Further, implanting high energy N-type impurities in the second window, and forming JFET doped regions under the P-type body regions by the high energy N-type impurities comprises:
the high-energy N-type impurity passes through the P-type body region, and the JFET doping region is formed below the P-type body region.
Further, implanting N-type impurities into the second window to form an n+ source region in the P-type body region includes:
and implanting N-type impurities into the upper layer of the P-type body region in the first window, and forming the N+ source region in the upper layer region of the P-type body region.
Further, under the shielding of the second hard mask layer and the side wall structure, after etching the epitaxy through the second window to form a trench, forming a gate oxide layer in the trench, depositing gate polysilicon in the trench, and etching back the gate polysilicon, wherein the method further comprises the steps of:
and after the groove is completed, removing the side wall and the second hard mask layer through a wet process.
Further, etching the interlayer dielectric layer through a photomask to form a third window, implanting P-type impurities into the third window to form p+ ohmic contact, and activating the p+ ohmic contact by using furnace tube annealing or rapid thermal annealing comprises:
providing the photomask to define a grid electrode and a source electrode wiring hole, etching and removing a dielectric film in the source electrode wiring hole, and etching and quantifying bulk silicon in the source electrode wiring hole to a depth of between 0.3 and 0.5 um.
Further, etching the interlayer dielectric layer through the photomask to form a third window, injecting P-type impurities into the third window to form p+ ohmic contact, and activating the p+ ohmic contact by adopting furnace tube annealing or rapid thermal annealing further comprises the following steps:
depositing front metal on the P+ ohmic contact and reversely etching to form a source region electrode, and depositing front metal on the interlayer dielectric layer and reversely etching to form a ring region metal field plate;
and thinning the back substrate, and metallizing the substrate to form a drain electrode.
A second object of the present invention is to provide a trench power device, which aims to solve the problem of trench manufacturing in the trench power device.
In order to solve the above technical problem, a trench power device is provided, including: the epitaxial structure comprises a substrate, an epitaxial layer, an interlayer dielectric layer, source electrode metal and field plate metal, wherein the epitaxial layer is connected with the substrate, the epitaxial layer comprises an active region, a terminal ring region, an N+ source region, a groove, gate polysilicon and a P+ source region, the active region is formed on one side containing a cell, the terminal ring region is arranged outside the active region and is arranged on the same side of the epitaxial layer as the active region, the N+ source region is formed in the active region, the groove penetrates through the N+ source region and the P-type Body region (Body) in the active region, the gate polysilicon is formed in the groove, and the P+ source region is positioned below the N+ source region to form P+ ohmic contact; the interlayer dielectric layer is positioned on the polysilicon; the source metal covers the interlayer dielectric layer, is embedded into the N+ source region and is abutted against the P+ source region; the field plate metal and the source electrode metal are arranged at intervals.
And further, forming the groove in the window of the middle part of the N+ source region through shielding of the second hard mask layer and the side wall structure.
Further, the trench power device further includes a drain metal, the drain being located on the substrate.
The implementation of the embodiment of the invention has the following beneficial effects:
1. the manufacturing method of the trench power device in the embodiment provides a substrate and an epitaxy arranged on the substrate, wherein a silicon oxide layer is thermally oxidized above the epitaxy, and a first hard mask layer is deposited above the silicon oxide layer; the first hard mask layer is provided with a first window, and P-type impurities are injected into the first window to form a P-type body region and a P-type compression ring; removing the first hard mask layer, depositing a second hard mask layer above the silicon oxide layer, forming a second window in the second hard mask layer, injecting high-energy N-type impurities into the second window, and forming a JFET doping region below the P-type body region by the high-energy N-type impurities; injecting N-type impurities into the second window to form an N+ source region in the P-type body region; depositing a silicon oxide or silicon nitride dielectric layer and etching back to the first window to form a side wall structure; etching epitaxy through a second window under the shielding of the second hard mask layer and the side wall structure to form a groove; forming a gate oxide layer in the groove, depositing gate polysilicon in the groove, and etching the gate polysilicon back; depositing an interlayer dielectric layer on the gate polysilicon, and flattening by adopting furnace tube annealing; and etching the interlayer dielectric layer through a photomask to form a third window, injecting P-type impurities into the third window to form P+ ohmic contact, and activating the P+ ohmic contact by adopting furnace tube annealing or rapid thermal annealing. Under the shielding of the second hard mask layer and the side wall structure, the groove is formed through etching epitaxy through the second window, so that the use of a photomask for etching the groove can be reduced, the dependence on a precise photoetching machine is further reduced, and the technical problem of high production cost of a groove power device in the prior art is solved.
2. In the trench power device in this embodiment, the side wall structure can define the opening position of the trench and protect the n+ source regions on the left and right sides, so that the n+ source regions are prevented from being synchronously etched during trench etching. In addition, from the beginning of defining an N+ injection window to the end of trench etching, the continuity and compactness are maintained in the front-back process, so that a side wall structure with good shape retention can be obtained, and further, the etching of a good trench morphology is facilitated.
3. The trench power device in this embodiment includes a substrate, an epi, an interlayer dielectric layer, a source metal and a field plate metal, where the epi includes an active region, a terminal ring region, an n+ source region, a trench, a gate polysilicon and a p+ source region, and since a Body region and an n+ source region are formed before trench etching, the difference between junction depths of the n+ source region and the Body region after trench etching is the channel length, and no subsequent high temperature process is required, no process disturbance is generated to the junction depths, so that a more stable turn-on voltage can be obtained.
4. In the manufacturing method of the trench power device in the embodiment, because the n+ source region and the P-type body region are formed in advance of etching the trench, compared with the n+ implantation performed after the gate oxidation in the conventional process, the n+ heavily doped implantation does not cause potential damage to the gate oxide layer near the opening position of the trench, thereby being beneficial to improving the gate source leakage.
5. In the method for manufacturing the trench power device in this embodiment, in the second window, the high-energy N-type impurity is injected, and the N-type JFET doped regions with higher concentration are formed by diffusion at two sides of the bottom trench, so that the on-resistance of the device is reduced while the breakdown voltage is not reduced.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method of implementing the present invention;
fig. 2-16 are schematic structural diagrams of a trench power device in steps of a method according to an embodiment of the present invention;
fig. 17 is a schematic structural diagram of a trench power device of the present invention.
Wherein: 100. a trench power device; 110. a substrate; 120. epitaxy; 1201. a silicon oxide layer; 121. a P-type body region; 122. a P-type pressure-resistant ring; 123. an n+ source region; 124. a groove; 125. gate polysilicon; 126. a P+ source region; 127. a JFET doped region; 130. an interlayer dielectric layer; 131. a third window; 140. a source metal; 150. a field plate metal; 160A, a first hard mask layer; 161. a first window; 160B, a second hard mask layer; 162. a second window; 170. a side wall structure; 180. a drain metal; 190. an active region; 200. and a terminal ring region.
Detailed Description
In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "fixed to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
Example 1
Referring to fig. 1 to 16, an embodiment of the present invention provides a method for manufacturing a trench power device 100, including:
s101, providing a substrate 110 and an epitaxy 120 arranged on the substrate 110, thermally oxidizing a silicon oxide layer 1201 above the epitaxy 120, and depositing a first hard mask layer 160A above the silicon oxide layer 1201;
s103, forming a first window 161 on the first hard mask layer 160A, and implanting P-type impurities (boron or boron compound) into the first window 161 to form a P-type body region 121 and a P-type compression-resistant ring 122;
s105, removing the first hard mask layer 160A, depositing a second hard mask layer 160B above the silicon oxide layer 1201, forming a second window 162 on the second hard mask layer 160B, implanting high-energy N-type impurities into the second window 162, and forming a JFET doping region 127 under the P-type body region 121 by the high-energy N-type impurities;
s107, implanting N-type impurities (arsenic or phosphorus) into the second window 162 to form an N+ source region 123 in the P-type body region 121;
s109, depositing a silicon oxide layer 1201 or a silicon nitride dielectric layer and etching back in the second window 162 to form a side wall structure 170;
s111, under the shielding of the second hard mask layer 160B and the side wall structure 170, etching the epitaxy 120 through the second window 162 to form a groove 124;
s113, forming a gate oxide layer in the groove 124, depositing gate polysilicon 125 in the groove 124, and etching back the gate polysilicon 125;
s115, depositing an interlayer dielectric layer 130 on the gate polysilicon 125, and flattening the interlayer dielectric layer by adopting furnace tube annealing;
s117, etching the interlayer dielectric layer 130 through a photomask to form a third window 131, implanting P-type impurities (boron or boron compounds) into the third window 131 to form P+ ohmic contact, and activating the P+ ohmic contact by furnace tube annealing or rapid thermal annealing.
In the above manufacturing method provided by the embodiment of the present invention, the trench 124 is formed by etching the epi 120 through the second window 162 under the shielding of the second hard mask layer 160B and the sidewall structure 170, so that the use of a photomask for etching the trench 124 can be reduced, the dependence on a precise photoetching machine is further reduced, and the technical problem of high production cost of the trench power device 100 in the prior art is overcome.
In one possible embodiment, implanting P-type impurities in first window 161 to form P-type body region 121 and P-type withstand voltage ring 122 includes:
p-type impurities are implanted into the epitaxy 120 through the first window 161 of the first hard mask layer 160A, wherein the P-type impurities in the window are formed by high-temperature annealing the P-type impurities in the terminal ring region 200, and the P-type impurities in the window are formed by high-temperature annealing the P-type impurities in the active region 190. In a specific operation, boron is implanted into the first window 161, after the epitaxy 120 is annealed at a high temperature and pushed, the P-type impurity in the first window 161 forms a P-type voltage-resistant Ring 122, which is also called Body Ring, and the P-type impurity in the active region 190 is implanted into the window to form a P-type Body region 121, which is also called Body region.
In one possible embodiment, implanting high energy N-type impurities in the second window 162 and forming the JFET doping region 127 under the P-type body region 121 includes:
the high energy N-type impurity passes through the P-type body region 121, and the JFET doping region 127 is formed under the P-type body region 121. In a specific operation, the N-type JFET doped region 127 with higher concentration is formed by high-energy N-type impurity implantation in the second window 162 and diffusion at two sides of the bottom trench 124, so that the on-resistance of the trench power device 100 is reduced while the breakdown voltage is not reduced; it should be noted that, because the high-energy N-type impurity is implanted, the depth of the implantation is deeper (0.5 um to 1.5 um), the peak value of the implanted impurity is far away from the surface of the silicon oxide layer 1201, so that the diffusion is mainly followed by longitudinal movement, the transverse movement is smaller, the dose of the high-energy N-type JFET is between 1e12 and 7e12, the energy is 400kev to 1.5mev, the high-energy N-type JFET belongs to light doping implantation, and the JFET doping region 127 is far away from the surface of the silicon oxide layer 1201 by high-temperature junction pushing, and is formed deep in the epi 120 relative to the n+ source region 123.
In one possible embodiment, implanting N-type impurities (arsenic or phosphorus) within the second window 162 to form the n+ source region 123 includes:
an N-type impurity (arsenic or phosphorus) is implanted into the upper layer of the P-type body region 121 in the second window 162, and an n+ source region 123 is formed in the upper layer region of the P-type body region 121. In a specific operation, n+ source region 123 is formed by implanting N-type impurity (arsenic or phosphorus) into a partial region of P-type body region 121 through second window 162, such that n+ source region 123 is located in P-type body region 121 to form a PN junction; it should be noted that the N-type impurity implantation dose is between 1e15 and 1e16, the energy is 60kev to 120kev, and the n+ source region 123 is formed on the epi 120 near the surface of the silicon oxide layer 1201 by high-temperature junction pushing but at a lower annealing temperature.
In one possible embodiment, after forming the trench 124 by etching the epi 120 through the second window 162 under the shielding of the second hard mask layer 160B and the sidewall structure 170, forming a gate oxide layer in the trench 124, depositing the gate polysilicon 125 in the trench 124, and etching back the gate polysilicon 125, the method further includes the steps of:
after the trench 124 is completed in S113, the sidewall 170 and the second hard mask layer 160B are removed by a wet process. In a specific operation, after the trench 124 is etched, the sidewall structure 170 and the second hard mask layer 160B need to be removed, and the sidewall structure 170 and the second hard mask layer 160B may be dissolved or dissolved and loosened to be separated from the epi 120 by wet immersion etching, so as to complete the removal of the sidewall structure 170 and the second hard mask layer 160B.
In one possible implementation, the third window 131 is formed by etching the interlayer dielectric layer 130 through a photomask, the P-type impurity (boron or boron compound) is implanted into the third window 131 to form a p+ ohmic contact, and activating the p+ ohmic contact by using furnace tube annealing or rapid thermal annealing includes:
providing a photomask to define a grid electrode and a source electrode wiring hole, etching to remove a dielectric film in the source electrode wiring hole, and etching a quantitative body silicon in the source electrode wiring hole to a depth of between 0.3um and 0.5 um. In a specific operation, a photomask is used to locate the wiring hole between the gate and the source, then the dielectric film in the source wiring hole is removed by etching, and then the depth of bulk silicon of the quantitative P-type body region 121 is etched in the source wiring hole to be between 0.3um and 0.5um, preferably to be 0.4um, so as to implant P-type impurities (boron or boron compound) through the third window 131.
In one possible implementation, the third window 131 is formed by etching the interlayer dielectric layer 130 through a photomask, the P-type impurity (boron or boron compound) is implanted into the third window 131 to form a p+ ohmic contact, and the step of activating the p+ ohmic contact by using furnace tube annealing or rapid thermal annealing further comprises:
s119, depositing front metal on the P+ ohmic contact and reversely etching to form a source region electrode, and depositing front metal on the interlayer dielectric layer 130 and reversely etching to form a ring region metal field plate;
s121, thinning the substrate 110 far from the epi 120, and metallizing the substrate 110 on that side to form a drain.
Example two
The embodiments are relatively different in implementing a claimed subject matter:
referring to fig. 17, a second embodiment of the present invention provides a trench power device 100, including: the substrate 110, the epitaxy 120, the interlayer dielectric layer 130, the source metal 140 and the field plate metal 150, the epitaxy 120 is connected with the substrate 110, the epitaxy 120 comprises an active region 190, a terminal ring region 200, an n+ source region 123, a trench 124, gate polysilicon 125 and a p+ source region 126, in specific applications, the active region 190 is formed on one side containing a cell, the terminal ring region 200 is arranged outside the active region 190 and on the same side as the active region 190, the n+ source region is formed in the active region 190, the trench penetrates the n+ source region 123 and the P-type Body region, the P-type Body region is also called Body region, the gate polysilicon 125 is formed in the trench 124, and the p+ source region 126 is positioned below the n+ source region 123 to form p+ ohmic contact; an interlayer dielectric layer 130 is located over the polysilicon; source metal 140 covers interlayer dielectric layer 130 and n+ source region 123 and abuts p+ source region 126; the field plate metal 150 is spaced apart from the source metal 140. Notably, the trenches extend through the n+ source region 123 and the P-type Body region (Body), so that the etching of the n+ source region 123 and the etching of the trench 124 are completed simultaneously, and the use of a photomask for etching the trench 124 is reduced, thereby reducing the production cost of the trench power device 100.
In one possible embodiment, the epitaxy 120 is an N-type epitaxy 120 or a P-type epitaxy 120, and if an N-type epitaxy 120 is used, an n+ source region 123 is formed in the active region 190, and a p+ source region 126 is located below the n+ source region 123 to form a p+ ohmic contact; if a P-type epitaxial 120 substrate is used, P+ source region 126 is formed in active region 190 and N+ source region 123 is located below P+ source region 126 to form an N+ ohmic contact.
In one possible embodiment, the trench 124 is formed in the window in the middle portion of the n+ source region 123 by shielding by the second hard mask layer 160B and the sidewall structure 170. In a specific application, the sidewall structure 170 is attached to the sidewall of the second hard mask layer 160B, where the sidewall structure 170 forms a concave window, and the two sides of the window are arc tops and connected to the hard mask layer 160, and the trench 124 is etched in the n+ source region 123 and the P-type body region 121 through the window of the sidewall structure 170, and the sidewall structure 170 can define the position of the trench 124 and protect the required n+ source region 123, so that the n+ source region 123 is prevented from being etched synchronously when the trench 124 is etched.
In one possible embodiment, trench power device 100 further includes drain metal 180, which is connected to substrate 110 away from epi 120. In particular applications, the Drain metal 180 and the Source metal 140 are Gate (also called Gate), source (S), drain (Drain-D) field effect transistor (Field Effect Transistor abbreviation (FET)) referred to as field effect transistor.
The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (10)
1. A method of manufacturing a trench power device, comprising:
providing a substrate and an epitaxy arranged on the substrate, thermally oxidizing a silicon oxide layer above the epitaxy, and depositing a first hard mask layer above the silicon oxide layer;
the first hard mask layer is provided with a first window, and P-type impurities are injected into the first window to form a P-type body region and a P-type compression ring;
removing the first hard mask layer, depositing a second hard mask layer above the silicon oxide layer, forming a second window in the second hard mask layer, implanting high-energy N-type impurities into the second window, and forming a JFET doping region below the P-type body region by the high-energy N-type impurities;
implanting N-type impurities into the second window to form an N+ source region in the P-type body region;
depositing a silicon oxide layer or a silicon nitride dielectric layer and etching back to the second window to form a side wall structure;
etching the epitaxy through the second window under the shielding of the second hard mask layer and the side wall structure to form a groove;
forming a gate oxide layer in the groove, depositing gate polysilicon in the groove, and etching the gate polysilicon back;
depositing an interlayer dielectric layer on the gate polysilicon, and flattening by adopting furnace tube annealing;
and etching the interlayer dielectric layer through a photomask to form a third window, injecting P-type impurities into the third window to form P+ ohmic contact, and activating the P+ ohmic contact by adopting furnace tube annealing or rapid thermal annealing.
2. The method of manufacturing a trench power device of claim 1, wherein implanting P-type impurities in the first window to form a P-type body region and a P-type compressive ring comprises:
and injecting P-type impurities into the epitaxy by utilizing the first window of the first hard mask layer, wherein the P-type impurities in the end ring region injection window are subjected to high-temperature annealing and pushing to form a P-type compression ring, and the P-type impurities in the active region injection window are subjected to high-temperature annealing and pushing to form a P-type body region.
3. The method of manufacturing a trench power device of claim 2, wherein implanting high energy N-type impurities in the second window and forming the high energy N-type impurities with JFET doped regions under the P-type body region comprises:
the high-energy N-type impurity passes through the P-type body region, and the JFET doping region is formed below the P-type body region.
4. The method of manufacturing a trench power device as defined in claim 3 wherein implanting N-type impurities into said second window to form n+ source regions in said P-type body region comprises:
and implanting N-type impurities into the upper layer of the P-type body region in the first window, and forming the N+ source region in the upper layer region of the P-type body region.
5. The method for manufacturing a trench power device according to any one of claims 1-4, wherein after etching the trench through the second window under the shielding of the second hard mask layer and the sidewall structure, forming a gate oxide layer in the trench, depositing gate polysilicon in the trench, and etching back the gate polysilicon, further comprises the steps of:
and after the groove is completed, removing the side wall and the second hard mask layer through a wet process.
6. The method for manufacturing a trench power device according to claim 1, wherein etching the interlayer dielectric layer through a photomask to form a third window, implanting P-type impurities into the third window to form a p+ ohmic contact, and activating the p+ ohmic contact by using furnace tube annealing or rapid thermal annealing comprises:
providing the photomask to define a grid electrode and a source electrode wiring hole, etching and removing a dielectric film in the source electrode wiring hole, and etching and quantifying bulk silicon in the source electrode wiring hole to a depth of between 0.3 and 0.5 um.
7. The method of manufacturing a trench power device according to claim 6, wherein etching the interlayer dielectric layer through the mask to form a third window, implanting P-type impurities into the third window to form a p+ ohmic contact, and activating the p+ ohmic contact by using furnace tube annealing or rapid thermal annealing further comprises the steps of:
depositing front metal on the P+ ohmic contact and reversely etching to form a source region electrode, depositing front metal on the interlayer dielectric layer and reversely etching to form a source region metal and a ring region metal field plate;
and thinning the back substrate, and metallizing the substrate to form a drain electrode.
8. A trench power device comprising: the epitaxial structure comprises a substrate, an epitaxial layer, an interlayer dielectric layer, source electrode metal and field plate metal, and is characterized in that the epitaxial layer is connected with the substrate, the epitaxial layer comprises an active region, a terminal ring region, an N+ source region, a groove, gate polysilicon and a P+ source region, the epitaxial layer is arranged on the substrate, the active region and the terminal ring region are separated and formed on the epitaxial layer, the N+ source region is formed in the active region, the groove penetrates through the N+ source region and the Body region in the active region, the gate polysilicon is formed in the groove, and the P+ source region is positioned below the N+ source region to form P+ ohmic contact; the interlayer dielectric layer is arranged on the gate polysilicon; the source metal is covered on the interlayer medium, embedded into the N+ source region and abutted against the P+ source region; the field plate metal and the source electrode metal are arranged at intervals.
9. The trench power device of claim 8 wherein the trench is formed in a window in a middle portion of the n+ source region by shielding from a second hard mask layer and a sidewall structure.
10. The trench power device of claim 8 or 9, further comprising a drain metal, the drain being located on the back side of the substrate.
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