JP2001094095A - Silicon carbide semiconductor device and fabrication method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a guard ring structure in which a high breakdown strength can be attained even if the number of guard rings is decreased. SOLUTION: The outermost circumferential p+ type well region 21a in a plurality of p+ type well regions 21 has a region of deeper junction than those located closer to the cell region side than the outermost circumferential p+ type well region 21a. Since a region of deep junction is provided in the outermost circumferential p+ type well region 21a, concentration of field is relaxed and a high breakdown strength can be attained even if the number of guard rings is small. Since the number of rings can be decreased for attaining a desired breakdown strength and the interval between well regions can be increased, a mask for forming a p+ type well region can be formed stably and the well regions can be prevented from coming into contact with each other.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a silicon carbide semiconductor device, and more particularly to an insulated gate type field effect transistor, particularly a vertical power MOSFET for high power and a Schottky diode for high power.

[0002]

2. Description of the Related Art Japanese Unexamined Patent Publication No. Hei 8-167713 discloses a guard ring structure for weakening the electric field in a cell region in which a power MOSFET is formed without bias. FIG. 12 shows a semiconductor device employing this guard ring structure.

The conventional semiconductor device shown in FIG. 12 employs a guard ring structure when silicon (Si) is used. As shown in FIG. 12, the p-type base region 1 is provided on the surface of the n ⁻ -type epitaxial layer 102.
The n ⁺ -type source region 104 is formed in the surface layer of the base region 103. Then, an MO that performs drain current switching using the surface layer portion of the base region 103 between the n ⁺ type source region 104 and the n ⁻ type epitaxial layer 102 as a channel region.
The SFET is a unit cell.

A p-type well region 105 is formed in the outer peripheral region of the cell region in which a plurality of such unit cells are formed, and is separated from the cell region by a predetermined distance. This p-type well region 105 is a guard ring. The p-type well layer 105 is formed in a ring shape so as to surround the cell region, and the electric field extends outward from the cell region without bias, so that the electric field concentration is reduced and a predetermined breakdown voltage is provided. Plays a role.

[0005]

In order to obtain a desired breakdown voltage with the guard ring having the above-described structure, it is necessary to form the p-type well region 105 in a number equal to or more than the number of rings corresponding to the desired breakdown voltage.

However, as the number of rings increases, it becomes necessary to reduce the distance between adjacent p-type well regions 105. In particular, when silicon carbide is used, the impurity concentration is set to be two orders of magnitude higher than that of silicon due to the desire to lower on-resistance compared to silicon based on the feature that the critical electric field strength is one order higher than that of silicon. Since a drift layer is formed and the depletion layer does not extend when a reverse bias voltage is applied, the interval between guard rings must be narrowed.

FIG. 13 shows the distance between guard rings (p-type well region 105) with respect to the number of rings at which a desired breakdown voltage is obtained.
) Indicates an appropriate value. As shown in this figure, the above-mentioned interval becomes narrower as the number of rings increases. For example, when the number of rings becomes five, the interval becomes 1 μm or less. It is difficult to design a mask dimension for forming the p-type well region 105 at such a narrow interval, and the mask itself cannot be formed stably. For example, an opening is formed in the mask on a region where the p-type well region 105 is to be formed.
Since the space between them is small, adjacent openings are connected to each other, and the p-type well regions 105 are formed in contact with each other.

The present invention has been made in view of the above problems, and has as its object to provide a silicon carbide semiconductor device having a guard ring structure capable of obtaining a high breakdown voltage even if the number of guard rings is reduced, and a method of manufacturing the same. .

[0009]

In order to achieve the above object, the following technical means are employed.

[0010] In the invention according to claims 1 to 8,
The outermost peripheral well region (21a) located at the outermost periphery of the plurality of well regions (21) has a deeper junction depth than that of the plurality of well regions located closer to the cell region than the outermost peripheral well region. It is characterized by having a formed region.

As described above, by providing a region having a deep junction depth in the outermost peripheral well region, the electric field at the outermost peripheral portion can be reduced, and a high breakdown voltage can be obtained even with a small number of rings. Therefore, the number of rings for obtaining a desired withstand voltage can be reduced, and the distance between the well regions can be widened. Therefore, a mask for forming the well regions can be formed stably, and the well regions are not in contact with each other. It is possible to prevent such troubles as to occur. For example, as described in claim 7, the interval between the well regions can be set to about 2 to 3 μm.

According to the third aspect of the present invention, in the outermost peripheral well region, the region where the junction depth is deep is
It is characterized in that the impurity concentration is lower than in other well regions.

As described above, by forming the region having a deeper junction depth in the outermost peripheral well region with a low concentration, the outermost peripheral well region and the semiconductor layer can be formed into an inclined junction. A higher breakdown voltage can be achieved.

According to a fourth aspect of the present invention, the outer peripheral side of the outermost peripheral well region may have a deeper junction depth than the inner peripheral side. The junction depth may be deeper on the inner peripheral side than on the outer peripheral side of the well region. Further, as described in claim 5, the outermost peripheral well region may be configured such that the junction depth becomes deeper in order toward the outer peripheral direction of the outermost peripheral well region.

According to a fifth aspect of the present invention, the outermost well region of the plurality of well regions is formed wider than the other well regions, and the junction depth of the widened portion of the outermost well region is set. It may be deeper.

The invention according to claims 13 to 18 corresponds to the method for manufacturing a silicon carbide semiconductor device according to claims 1 to 12.

According to the present invention, in the region where the junction depth is reduced, the step of performing ion implantation of an inert ion species (for example, C (carbon)) and the region where the junction depth is reduced are provided. And a step of ion-implanting a second conductivity type impurity into a region where the junction depth is increased, and a step of performing a heat treatment to activate the implanted second conductivity type impurity.

As described above, by implanting the inert ion species into the region of the outermost peripheral well region where the junction depth is shallower, the inert ion species enter the vacancies of the carbon site and become inactive in the semiconductor layer. Crystal defects can be repaired. For this reason, in the portion where the inert ion species is implanted, the second conductivity type impurity is unlikely to be thermally diffused, so that the junction depth is reduced, and in the portion where the inert ion species is not implanted, the second impurity is implanted. The conductivity type impurities are easily diffused by heat, and the junction depth is formed deep.

According to the fifteenth aspect of the present invention, in addition to the effect of the fourteenth aspect, the base region forming step and the well region forming step are performed at the same time, and the base region and the junction depth are deep. After arranging a first mask (61) having an opening on the well region excluding the region, a step of performing ion implantation of inactive ion species, and a step of performing ion implantation on the base region and the well region including the region where the junction depth is deep. After arranging the opening second mask (62), the method includes a step of ion-implanting a second conductivity type impurity and a step of performing a heat treatment to activate the implanted second conductivity type impurity. Features.

As described above, the base region and the well region can be formed simultaneously. Then, by implanting an inactive ion species into each of the well region and the base region constituting the guard ring, lattice defects (C vacancies) can be repaired. Since the diffusion can be suppressed, the intervals between the well regions are hardly reduced by the thermal diffusion, and the intervals can be accurately defined.

According to a sixteenth aspect of the present invention, the second mask in the second-conductivity-type impurity implantation step is such that the opening of the first mask in the inactive ion species implantation step is extended to a region where the junction depth is deep. Can be expanded.

Further, since the same mask is used except for a portion having a deep junction depth, the second conductivity type impurity and the inactive ion species can be accurately overlapped without mask shift, and a portion having a deep junction depth can be obtained. Otherwise, thermal diffusion of the second conductivity type impurity can be suppressed.

According to the twentieth aspect, C (carbon) is used as an inert ion species. Since the lattice defect (C vacancy) has the same size as the C element, C is most likely to enter. Therefore, by filling the lattice defects (C vacancies) with the implanted carbon, it can be repaired more easily than other inactive ion species. This allows
For example, the amount of implantation of ion species required for repairing lattice defects can be reduced as compared with the case where another element is used.

The reference numerals in parentheses of the above means indicate the correspondence with specific means described in the embodiments described later.

[0025]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a first embodiment of the present invention. (First Embodiment) Vertical power MO shown in this embodiment
The SFET is shown in FIG. Based on this figure, vertical power MO
The SFET will be described.

The vertical power MOSFET has an n ⁺ -type substrate 1 made of silicon carbide and an n ⁻ -type silicon carbide epitaxial layer (hereinafter referred to as an n ⁻ -type epi layer) 2 grown thereon. The cell region and the outer peripheral region surrounding the cell region are formed.

The cell area is composed of a plurality of MOSFETs. In the present embodiment, a planar MOSFET is employed as the MOSFET.

A plurality of p ⁺ -type base regions 3 made of silicon carbide and having a predetermined depth are formed in the surface portion of n ⁻ -type epi layer 2 in the cell region. Among them, the p ⁺ -type base region 3a (hereinafter, referred to as the extraction base region 3a) located at the outermost periphery of the cell region serves as a cell for extracting carriers (holes), and is located on the inner periphery side. What is located is one that works as a MOSFET.

In the p ⁺ type base region 3 which functions as a MOSFET, an n ⁺ type source region 4 shallower than the base region 3 is formed in a predetermined region of the surface layer.

Further, p⁺Upper surface of the mold base region 3 and
n⁺A gate insulating film (silicon)
An oxide film 7 is formed. Further, the gate insulating film 7
A gate electrode layer 8 made of polysilicon is formed on
The gate electrode layer 8 is made of LTO (Low Te).
insulating oxide 9)
Covered. A source electrode 10 is formed thereon.
And the source electrode 10 is n ⁺Type source region 4 and p⁺Type
It is in contact with base region 3. Also, n⁺Back side of mold substrate 1
Is formed with a drain electrode 11.

On the other hand, the outer peripheral portion region, n ^- -type p for junction formed so as to surround the cell region at the surface layer portion of the epitaxial layer 2
^{It comprises a +} -type layer 20 and a plurality of p ⁺ -type well regions 21 formed so as to surround the bonding p ⁺ -type layer 20 several times in the surface layer portion of the n ⁻ -type epi layer 2.

The joining p ⁺ -type region 20 has a predetermined length and extends outward from the extraction base region 3a.
It is electrically connected to the source electrode 10 in a cross section different from that of FIG. The gate electrode layer 8 is formed on the p ⁺ -type junction region 20 with a thick insulating film 23 interposed therebetween. The gate electrode layer 8 is electrically connected to the gate electrode 24 via the insulating film 9.

The p ⁺ -type well regions 21 constitute a guard ring, and a plurality of p ⁺ -type well regions 21 are formed at predetermined intervals D from the junction p ⁺ -type regions 20. Of the p ⁺ -type well regions 21, the outermost one (hereinafter referred to as the outermost p ⁺ -type well region) 21 a is configured to be wider than the p ⁺ -type well region 21 located further inside. The outer peripheral side has a stepped shape in which the joining depth is made deeper than the inner peripheral side. The outermost p ⁺ -type well region 21a has a lower concentration at a portion where the junction depth is deeper on the outer side than at a portion where the junction depth is shallower on the inner side.

For example, the width Wx on the outer peripheral side of the outermost peripheral p ⁺ -type well region 21a is set to 1 to 7 μm. The innermost side of the outermost p ⁺ -type well region 21a has an impurity concentration of 1 × 10 ^{17 to} 5 × 10 ¹⁸ cm ⁻³ and a junction depth of 0.5 to 10 × 10 ¹⁸ cm ^−3.
The impurity concentration is 5 × 10 ^{15 to} 5 × 10 ¹⁷ cm ⁻³ on the outer peripheral side, and the junction depth Hx is 1.
It is about 0 to 3 μm.

The interval D between the p ⁺ -type well regions 21
Is determined by the width Wx on the outer peripheral side of the outermost peripheral p ⁺ -type well region 21a and the impurity concentration, but is within about 2 to 3 μm.

The portion of the p ⁺ -type junction region 20 and the p ⁺ -type well region 21 other than the outermost periphery of the outermost p ⁺ -type well region 21a and the p ⁺ -type base region 3 have the same depth, The same impurity concentration (for example, 1 × 10 ^{17 to} 5 × 10 ¹⁸⁾
(impurity concentration of cm ⁻³ ), and inactive regions are implanted into these regions.

In the MOSFET configured as described above, the outer peripheral side of the outermost p ⁺ -type well region 21a of the p ⁺ -type well region 21 forming the guard ring is made deeper in the junction depth, and n ⁻ The following effects can be obtained by extending the lower part of the mold epi layer 2.

FIG. 2 shows the vertical power MOSFET shown in FIG.
The result of having investigated the withstand voltage of T is shown. As can be seen from the equipotential lines shown in this figure, the outermost p ⁺ -type well region 21a
Is made to have a layer thickness, so that the equipotential line once becomes n ⁻
After being lowered to the lower side of the mold epi layer 2, it is terminated on the outer periphery side of the outermost periphery p ⁺ -type well region 21. For this reason, the region where the equipotential lines terminate is not locally biased but spreads over a wide range, so that the electric field concentration is reduced and a high breakdown voltage can be achieved.

In the present embodiment, the impurity concentration on the outer peripheral side of the outermost p ⁺ -type well region 21a is lower than that on the inner peripheral side. Therefore, the outermost p ⁺ -type well region 21a and the n ^-- type epi layer 2 are inclined junctions, that is, junctions in which the impurity concentration changes gradually.
A higher breakdown voltage can be achieved as compared with a step-type junction in which the impurity concentration changes rapidly.

As described above, a desired breakdown voltage can be obtained even if the number of guard rings is small, so that it is not necessary to reduce the distance between the rings of the guard ring structure, and the mask for forming the guard ring structure can be used. It can be formed stably. In addition, since the number of rings can be reduced, the device can be miniaturized.

Also, since a high breakdown voltage can be achieved by such a structure, normally, even if the field plate extending from the outermost position of the guard ring toward the outer periphery of the cell region is eliminated, the same as the field plate can be obtained. The effect of can be obtained. In addition, the field plate is
So as to be in contact with the outermost p ⁺ -type well region 21a, and is intended to be extended toward the outermost p ⁺ -type well region 21a to the outside of the cell region.

For reference, FIG. 3 shows experimental results obtained by examining the withstand voltage of the MOSFET according to the present embodiment employing the above-described guard ring structure and the withstand voltage of the MOSFET employing the conventional guard ring structure.

This figure shows the withstand voltage when the width Wx on the outer peripheral side of the outermost p ⁺ -type well region 21a is displaced at 1 μm intervals from 1 to 7 μm when the number of rings is 3 in this embodiment. It is a thing which investigated. In addition, in the figure, as a comparative example, the number of rings is 1 to 4
The withstand voltage in the case of is also shown.

As shown in this figure, when the guard ring structure according to the present embodiment is employed, the breakdown voltage with respect to the number of rings is improved as compared with the case where the conventional guard ring structure is employed. By adopting the guard ring structure of the present embodiment, even if the number of rings is 3, for example, it is possible to obtain a withstand voltage when the number of rings is 4 or more in the conventional guard ring structure. It is possible.

Next, the vertical power MOSF shown in FIG.
The manufacturing process of the ET will be described with reference to FIGS.

[Step shown in FIG. 4A] First, a low-resistance n ⁺ -type silicon carbide semiconductor substrate 1 is prepared, and a high-resistance n ⁻ -type epi layer 2 is epitaxially grown on the n ⁺ -type substrate 1. .

[Step shown in FIG. 4B] Each p ⁺ -type well region 21 excluding the outer periphery of the p ⁺ -type base region 3, the junction p ⁺ -type layer 20, and the outermost p ⁺ -type well region 21a (Carbon) is ion-implanted using a mask material 61 having an upper opening. As a result, C enters the vacancies at the carbon sites, and the vacancies are almost eliminated, and the crystal defects formed in the n ⁻ -type epi layer 2 are repaired.

[Step shown in FIG. 4C] Subsequently, the opening of the mask material 61 is widened so as to open at the upper part on the outer peripheral side of the outermost p ⁺ -type well region 21a.
And At this time, the mask material 62 includes the p ⁺ -type base region 3, the bonding p ⁺ -type layer 20, and each p ⁺ -type well region 21.
Is open.

Then, B (boron) ions are implanted using the mask material 62. As a result, B is implanted over C in each of the p ⁺ -type well regions 21 except for the outer periphery of the p ⁺ -type base region 3, the junction p ⁺ -type layer 20, and the outermost peripheral p ⁺ -type well region 21a. In this state, only B is implanted on the outer peripheral side of the outermost p ⁺ -type well region 21a.

The conditions for ion implantation of C and B are as follows:
The junction depth is set to be equal, and the dose is set so that C is about 10 times B than B, for example. For example, B is 3
Multi-stage implantation of 0 to 400 keV, total dose about 8.0 ×
A rectangular profile having an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ and a depth of 0.7 μm is formed, and C is 30 to ⁴ cm ^2.
Multi-stage implantation of 00 keV, total dose about 8 × 10 ¹⁵ cm
⁻² , impurity concentration 1 × 10 ²⁰ cm ⁻³ , depth 0.7 μm
Is formed.

At this time, since each p ⁺ -type well region 21 constituting the guard ring structure has the above-described structure, the interval between each p ^-- type well region 21 is set to a relatively large value of 2 to 3 μm. be able to. For this reason, the interval between the p ⁺ -type well regions 21 can be set in consideration of the variation in the etching amount when opening the mask.

[Step shown in FIG. 5 (a)]
Activate the injected B. At this time, as described above, in the region where B is implanted with C overlaid, C
The crystal defect is repaired, so that the amount of thermal diffusion of B is very small and activated at almost the implanted position. Therefore, the p ⁺ type base region 3 and the junction p ⁺ type layer 2
In each of the p ⁺ -type well regions 21 except for 0 and the outermost peripheral side of the outermost p ⁺ -type well region 21a, the p ⁺ -type well regions 21 are formed in a shape when B is implanted, and are formed at a high concentration. On the other hand, B
In the region into which only B is implanted, the amount of thermal diffusion of B is large, and the region is activated in a state where it is spread as a whole. However, since thermal diffusion of B is suppressed in the direction of the region where the crystal defect has been repaired, B does not diffuse much in the inner peripheral direction of the outermost p ⁺ -type well region 21a, and the outermost p ⁺ -type well region It diffuses in the outer peripheral direction and the depth direction of 21a. Therefore, the outermost circumference p
^The junction depth is deeper on the outer peripheral side of the ⁺ -type well region 21a than on the inner peripheral side, and is formed at a low concentration.

[Step shown in FIG. 5 (b)] An n-type impurity is ion-implanted, and an n ⁺ -type source region 4 is provided in a predetermined region of the p ⁺ -type base region 3 and a contact region is provided in a predetermined region of the outer peripheral region. An n ⁺ -type layer 40 is formed.

Subsequently, through a photolithography process,
An oxide film (Si) having a predetermined thickness is formed on the p ^- type region 20 for bonding.
O ₂ ) 23 are formed.

[Step shown in FIG. 5C] A thermal oxide film 7 is formed on the entire surface of the wafer by thermal oxidation. This thermal oxide film 7 constitutes a gate oxide film. Then, after depositing polysilicon or the like, patterning is performed to form the gate electrode layer 8.

[Step shown in FIG. 6] An interlayer insulating film 9 is formed on the wafer including the gate insulating film 7.

Thereafter, after forming a contact hole in the interlayer insulating film 9, an aluminum wiring is patterned to form a gate electrode 24, a source electrode 10, and an electrode 22 constituting a field plate. And the gate electrode 2
4, passivation film 13 is formed on source electrode 10 and electrode 22, and n ⁺ -type silicon carbide semiconductor substrate 1
A drain electrode 11 is formed on the back side of the semiconductor device to complete the vertical power MOSFET shown in FIG.

(Other Embodiments) In the above embodiment, the inner peripheral side of the outermost p ⁺ -type well region 21a has the same structure as the other p ⁺ -type well regions 21. Although the junction depth is increased, a configuration as shown in FIGS. 7 to 10 may be employed.

In FIG. 7, the outermost p ⁺ -type well region 21a
Is shown as a whole in which the concentration is reduced and the junction depth is increased. In this case, the outermost p ⁺ -type well region 21
What is necessary is just to make it easy to thermally diffuse, without performing ion implantation of C to a. In addition, if the space between the outermost p ⁺ -type well region 21a and the p ⁺ -type well region 21 located inside the outermost p ⁺ -type well region 21a is set in consideration of the thermal diffusion amount of B,
Even if B in the outermost p ⁺ -type well region 21a is thermally diffused, the interval between the p ⁺ -type well regions 21 can be made constant.

[0060] In FIG. 8, in order toward the outer circumference of the outermost p ⁺ -type well region 21a, with the junction depth of the outermost p ⁺ -type well region 21a is set to be deeper stepwise, staged 2 shows a case where the density is reduced in order. For example, the outermost p ⁺ -type well region 21a
The region A located on the inner peripheral side of the substrate has a junction depth of 0.5 to 3.0 μm.
m, doping concentration 1 × 10 ^{17 to} 5 × 10 ¹⁸ cm ^-3
And a region B located on the outer peripheral side from the region A has a junction depth of about 1 to 3.0 μm and a doping concentration of 1 × 10 ¹⁶ to 1
× is about 10 ¹⁸ cm ^-3, can select the region C located on the outer peripheral side of the region B junction depth 1.5~3μm about, the doping concentration 5 × 10 ¹⁵ about ~5 × 10 ¹⁷ cm ^-3.

FIG. 9 shows the case where the junction depth is made deeper and the concentration is lower on the inner peripheral side of the outermost p ⁺ -type well region 21a. In this case, the outermost circumference p ⁺
C ions may not be implanted on the inner peripheral side of the mold well region 21a, but C ions may be implanted on the outer peripheral side, so that B can be easily diffused on the inner peripheral side. If the space between the outermost p ⁺ -type well region 21a and the p ⁺ -type well region 21 located inside the outermost p ⁺ -type well region 21a is set in consideration of the amount of thermal diffusion of B, the B ⁺ Can be made to have a constant interval between the p ⁺ -type well regions 21 even when the thermal diffusion is performed.

[0062] In FIG. 10, the inner circumferential side junction depth of the outermost p ⁺ -type well region 21a is configured as a deep low concentration, allowed overhang toward the inner periphery of the outermost p ⁺ -type well region 21a Thus, a case is shown in which the contact is made to be in contact with the p ⁺ -type well region 21 located one inside the outermost peripheral p ⁺ -type well region 21a. In this case, the mask opening may be configured such that the outermost peripheral p ⁺ -type well region 21a and the p ⁺ -type well region 21 located inside the outermost p ⁺ -type well region 21 are connected to the case shown in FIG.

In the above embodiment, the vertical power MOSFE
Although a description has been given of a case where a guard ring structure is employed for T, the present invention is not limited to this, and it is needless to say that the present invention can be applied to a device having a guard ring structure. For example, the present invention may be applied to a guard ring structure surrounding a Schottky diode. FIG. 11 shows an example of this application.

As shown in FIG. 11, n ⁺
With type epi layer 2 is formed, n ^{- -} on the mold substrate 1 n Schottky electrode 31 which is Schottky connected to the surface of the type epi layer 2 is disposed further on the back surface of the n ⁺ -type substrate 1 A Schottky diode having a cathode electrode 32 is provided.

As described above, even in the case where the Schottky diode is formed in the cell region, the guard ring structure in each of the above embodiments can be adopted. In this case, the wiring electrode 10 is ohmically connected to the p ⁺ -type layer 20 by the ohmic electrode 33.

[Brief description of the drawings]

FIG. 1 is a planer type power MOS according to a first embodiment.
FIG. 3 is a cross-sectional view showing an FET.

FIG. 2 is a diagram showing a result of examining a breakdown voltage of the MOSFET shown in FIG. 1;

FIG. 3 shows a MOSFET shown in FIG. 1 and a conventional MOSFET.
It is a figure which shows the result of having investigated the withstand voltage with respect to the number of rings.

FIG. 4 is a view showing a manufacturing process of the MOSFET shown in FIG. 1;

FIG. 5 is a view showing a manufacturing step of the MOSFET following FIG. 4;

FIG. 6 is a view showing a manufacturing step of the MOSFET following the step shown in FIG. 5;

FIG. 7 is a planer type power MOS according to another embodiment.
FIG. 3 is a cross-sectional view showing an FET.

FIG. 8 is a planer type power MOS according to another embodiment.
FIG. 3 is a cross-sectional view showing an FET.

FIG. 9 is a planer type power MOS according to another embodiment.
FIG. 3 is a cross-sectional view showing an FET.

FIG. 10 is a planer type power MO according to another embodiment.
FIG. 3 is a cross-sectional view illustrating an SFET.

FIG. 11 is a cross-sectional view illustrating a Schottky diode according to another embodiment.

FIG. 12 shows a conventional M employing a guard ring structure.
FIG. 3 is a cross-sectional view of an OSFET.

FIG. 13 is a diagram showing an appropriate interval of each guard ring with respect to the number of rings of the guard ring structure in FIG.

[Explanation of symbols]

Reference numerals 1 ... n ⁺ type substrate, 2 ... n ^- type epi layer, 3 ... p ⁺ type base region, 4 ... n ⁺ type source region, 7 ... gate insulating film, 8 ...
Gate electrode layer, 9 insulating film, 10 source electrode, 11 ...
Drain electrode, 20: junction p ⁺ type region, 21: p ⁺ type well region, 21a: outermost periphery p ⁺ type well region, 22:
Electrodes, 24 ... Gate electrode.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 658A

Claims (20)

[Claims] A first conductivity type low-resistance semiconductor substrate (1) made of silicon carbide; a first semiconductor layer (2) formed on the semiconductor substrate and having a higher resistance than the semiconductor substrate; A current is generated by applying a voltage to a gate electrode layer (8) provided on the base region and including a second conductivity type base region (3) formed on a surface portion of the first semiconductor layer. An FET that performs a switching operation is a unit cell, and a cell region having a plurality of the unit cells is formed to surround the cell region at a predetermined distance from the cell region at an outer peripheral portion of the cell region. Multiple second
A conductive type well region (21); and a gate electrode (2) electrically connected to the gate electrode layer.
4) and a source electrode (1) electrically connected to the base region.
0), and a drain electrode (11) electrically connected to the back surface side of the semiconductor substrate, and an outermost peripheral well region (21a) located at the outermost periphery of the plurality of well regions includes A silicon carbide semiconductor device, comprising: a well region having a junction depth greater than that of the well region located closer to the cell region than the outermost well region. 2. A semiconductor substrate (1) of a first conductivity type made of silicon carbide and having a low resistance, a first semiconductor layer (2) formed on the semiconductor substrate and having a higher resistance than the semiconductor substrate, A Schottky electrode formed on a surface portion of the first semiconductor layer and making Schottky contact with the first semiconductor layer; and an outer peripheral portion of the Schottky electrode formed to surround the Schottky electrode. A plurality of second conductivity type well regions; and a cathode electrode electrically connected to the back surface of the semiconductor substrate, and an outermost peripheral well located at an outermost periphery of the plurality of well regions. The region (21a) has a region in which the junction depth of the plurality of well regions is formed deeper than that of the plurality of well regions located closer to the cell region than the outermost well region. Silicon carbide semiconductor device . 3. The region of the outermost peripheral well region where the junction depth is deeper than the one of the plurality of well regions that is located closer to the cell region than the outermost peripheral well region. 3. The silicon carbide semiconductor device according to claim 1, wherein the concentration is low. 4. The outermost peripheral well region has a junction depth formed deeper on an outer peripheral side than on an inner peripheral side of the outermost peripheral well region. The silicon carbide semiconductor device according to one of the above. 5. An outermost well region of the plurality of well regions is configured to be wider than other well regions.
5. The silicon carbide semiconductor device according to claim 1, wherein a widened portion of the outermost peripheral well region forms a region where the junction depth is increased. 6. 6. The semiconductor device according to claim 1, wherein the outermost peripheral well region is formed such that a junction depth is gradually increased toward an outer peripheral direction of the outermost peripheral well region. Silicon carbide semiconductor device. 7. The semiconductor device according to claim 1, wherein the intervals between the plurality of well regions are substantially equal, and the intervals are approximately 2 μm to 3 μm.
4. The silicon carbide semiconductor device according to any one of the above. 8. The outer peripheral well region, wherein a junction depth is formed deeper on an inner peripheral side than on an outer peripheral side of the outermost peripheral well region. The silicon carbide semiconductor device according to one of the above. 9. The outermost peripheral well region is formed such that the inner peripheral side where the junction depth is increased protrudes in the direction of the well region located one inner periphery from the outermost peripheral well region. 9. The silicon carbide semiconductor device according to claim 8, wherein said silicon carbide semiconductor device is in contact with said well region located on said inner periphery. 10. A semiconductor substrate (1) of a first conductivity type made of silicon carbide and having a low resistance, a first semiconductor layer (2) formed on the semiconductor substrate and having a higher resistance than the semiconductor substrate, By applying a voltage to a gate electrode layer (8) provided on the base region and including a second conductivity type base region (3) formed in a surface layer portion of the first semiconductor layer, the current is reduced. An FET which performs a switching operation is a unit cell, and a cell region having a plurality of the unit cells is formed so as to surround the cell region at a predetermined distance from the cell region at an outer peripheral portion of the cell region. At least one well region of the second conductivity type and a gate electrode electrically connected to the gate electrode layer;
4) and a source electrode (1) electrically connected to the base region.
0), and a drain electrode (11) electrically connected to the back surface side of the semiconductor substrate, and an outermost peripheral well region (21a) located at the outermost periphery of the at least one well region has a junction depth A silicon carbide semiconductor device having a region formed deeper and a region having a junction depth shallower than a region having a larger junction depth. 11. A low-resistance semiconductor substrate of a first conductivity type made of silicon carbide (1), a first semiconductor layer (2) formed on the semiconductor substrate and having a higher resistance than the semiconductor substrate, A Schottky electrode formed on a surface portion of the first semiconductor layer and making Schottky contact with the first semiconductor layer; and an outer peripheral portion of the Schottky electrode formed to surround the Schottky electrode. At least one well region of the second conductivity type (21); and a cathode electrode () electrically connected to the back surface of the semiconductor substrate. The outer peripheral well region (21a) has a region where the junction depth is formed deeper and a region where the junction depth is made shallower than the region where the junction depth is deeper. Semiconductor device. 12. The outermost peripheral well region may be formed on either the outer peripheral side or the inner peripheral side of the outermost peripheral well region.
The silicon carbide semiconductor device according to claim 10, wherein a junction depth is partially formed to be deep. 13. A step of forming a first conductivity type semiconductor layer (2) made of silicon carbide having a higher resistance than the semiconductor substrate on a main surface of the first conductivity type semiconductor substrate (1) made of silicon carbide. Forming a plurality of second conductivity type base regions (3) having a predetermined depth in predetermined regions of a surface portion of the semiconductor layer; and forming a guard ring so as to surround the base regions. Forming at least one second conductivity type well region (21); and forming a first conductivity type source region (4) having a junction depth shallower than the base region in a predetermined region of a surface layer portion in the base region. A) forming a gate electrode layer on the base region between the source region and the semiconductor layer; and a source electrode in contact with the base region and the source region. And the step of forming And, the well region forming step, the outermost well region positioned in the outermost periphery of the at least one well region (2
A method of manufacturing a silicon carbide semiconductor device, comprising: forming 1a) in a region having a deeper junction depth and a region having a lower junction depth than the region having a deeper junction depth. 14. The method according to claim 14, wherein the step of forming the well region includes the step of ion-implanting an inactive ion species in the region where the junction depth is small; 2. The method according to claim 1, further comprising the steps of: ion-implanting a second conductivity type impurity; and performing a heat treatment to activate the implanted second conductivity type impurity.
3. The method for manufacturing a silicon carbide semiconductor device according to item 3. 15. A first mask (61) in which the base region forming step and the well region forming step are performed simultaneously, and an opening is formed on the base region and on the well region excluding the region having a large junction depth. After disposing, ion implanting an inactive ion species; and disposing a second mask (62) that opens on the base region and the well region including the region where the junction depth is deep, 2. The method according to claim 1, further comprising the steps of: ion-implanting a second conductivity type impurity; and performing a heat treatment to activate the implanted second conductivity type impurity.
5. The method for manufacturing a silicon carbide semiconductor device according to item 4. 16. The second mask in the step of implanting impurities of the second conductivity type is such that an opening of the first mask in the step of implanting inert ion species is extended to a region where the junction depth is deep. The method for manufacturing a silicon carbide semiconductor device according to claim 15, wherein: 17. A step of forming a first conductivity type semiconductor layer (2) made of silicon carbide having a higher resistance than the semiconductor substrate on a main surface of the first conductivity type semiconductor substrate (1) made of silicon carbide. Forming a Schottky electrode forming a Schottky connection with the semiconductor layer in a predetermined region of a surface portion of the semiconductor layer; and forming a guard ring so as to surround the Schottky electrode. At least one well region (21)
Forming the outermost well region (2) located at the outermost periphery of the at least one well region in the well region forming step.
A method of manufacturing a silicon carbide semiconductor device, comprising: forming 1a) in a region having a deeper junction depth and a region having a lower junction depth than the region having a deeper junction depth. 18. The method according to claim 18, wherein the step of forming the well region includes the step of implanting an inert ion species in the region where the junction depth is shallow, and the step of forming the region where the junction depth is shallow and the region where the junction depth is deep. 2. The method according to claim 1, further comprising the steps of: ion-implanting a second conductivity type impurity; and performing a heat treatment to activate the implanted second conductivity type impurity.
8. The method for manufacturing a silicon carbide semiconductor device according to item 7. 19. In the second conductivity type impurity implantation step,
19. The method of manufacturing a silicon carbide semiconductor device according to claim 13, wherein B (boron) is used as the second conductivity type impurity. 20. The inactive ion species implantation step,
20. The method of manufacturing a silicon carbide semiconductor device according to claim 14, wherein C (carbon) is used as an inert ion species.