JPH04239778A - Field-effect transistor and its manufacture - Google Patents

Abstract

PURPOSE:To increase the withstand voltage value of a field-effect transistor and to reduce the forward voltage, by using silicon carbide semiconductors solving the problem that thermal diffusion of impurities to silicon carbides is difficult. CONSTITUTION:The first and second semiconductor regions composed of one and the other conductivity type silicon carbides are laminated doping impurities at the time of epitaxial growth, the third semiconductor region is formed into one conductivity type in a part of the surface of the second semiconductor region by ion implantation. And a recession is dug from the third semiconductor region until it reaches the first semiconductor region, and a gate is fitted into it after its surface is covered with a gate insulating film. Besides, source and drain terminals are drawn out from the first and third semiconductor regions, and a gate terminal is drawn out from the gate respectively.

Description

Description: FIELD OF THE INVENTION The present invention relates to a field effect transistor using a silicon carbide semiconductor, particularly suitable for high voltage and large current applications, and a method for manufacturing the same. [Prior Art] All so-called power transistors, which are suitable for applications that handle high voltages and large currents, have traditionally used silicon semiconductors, and the main ones that have been put into practical use to date include the well-known There are bipolar transistors, field effect transistors, and insulated gate bipolar transistors. The most basic performances required of power transistors in general include low forward voltage when turned on, high input impedance, and high switching speed. When looking at transistors, each has advantages and disadvantages. That is, both bipolar transistors and field effect transistors have high switching speeds, but while the former has the advantage of low forward voltage,
The latter has the disadvantage of low input impedance, while the latter has the advantage of high input impedance, but has the disadvantage of high forward voltage. These intermediate insulated gate bipolar transistors have low forward voltage and high input impedance, but have the disadvantage of slow switching speed. For this reason, various efforts have been made to solve these problems and improve the performance of power transistors, but these improvements naturally have limits based on the basic performance values of semiconductor materials. At present, it is thought that we are already approaching the theoretical limit of the performance of transistors using silicon semiconductors, and silicon carbide is attracting attention as one of the new semiconductor materials that can overcome this limit. As is well known, silicon carbide is a semiconductor with a wider bandgap than silicon, and is attracting attention as a material for semiconductor devices suitable for environments with high radiation levels and high-noise locations such as around car engines. However,
Recently, wafers with considerably high crystallinity have become available (for example, R.F. Davis et al; Mat
．． Res. Soc. Symp. Proc. , V
ol. 162, l990, p. 463)
, the feasibility of semiconductor devices using it is being studied (for example, K. Shenai et al.
IEEE Trans. on Elect. Dev
．． , Vol. 36, No. 9, 1989,
p. 1181). In addition to the above-mentioned feature of a wide bandgap, silicon carbide has a higher electric field strength than silicon, which causes a carrier multiplication effect within its crystal, and therefore has a higher dielectric breakdown voltage, but has a lower resistance value. Since it is still not always easy to create a semiconductor layer with a semiconductor layer therein, a field effect type transistor is more suitable than a bipolar type as a transistor using silicon carbide. Regarding effect transistors. In addition,
Although almost no prior art regarding this type of transistor is known, R. F. Davis, HFPC Ma
y (1989) Proceedings; p. 8
1. As a result of prototyping a horizontal field effect transistor,
There are reports that transistor characteristics similar to those of silicon semiconductors can be obtained. However, as is well known, field effect transistors with such a horizontal structure are disadvantageous when used for large currents, and they are also disadvantageous when increasing voltage resistance by taking advantage of silicon carbide's inherent ability to withstand high electric field strength. Therefore, it is desirable to adopt a vertical structure for high voltage and large current even in field effect transistors using silicon carbide semiconductors. Although the vertical structure of a silicon carbide field effect transistor suitable for such electric power is not yet known, a typical vertical structure when using a silicon semiconductor is briefly explained below with reference to FIG. 4 for reference. do. A vertical field effect transistor for large currents is generally made up of a large number of small transistors connected in parallel, and FIG. 4 shows one unit in such a composite structure in the case of an n-channel type. A drain connection layer 41 is diffused with a strong n-type from the back side of an n-type substrate 40, and a polycrystalline silicon gate 43 is formed on the surface via a gate oxide film 42.
Then, using this as a mask, impurities are ion-implanted and thermally diffused to form a deep p-type well 44 and a strong n-type shallow source layer 45, with their peripheral edges forming gates as shown in the figure. Make it so that it goes under the 43. Further, after covering the gate 43 with an insulating film 46, an aluminum electrode film 47 is provided thereon, and the electrode film 47 is also attached to the drain connection layer 41 on the back side. As shown in the figure, such a vertical field effect transistor 50 has an electrode film 47 connecting the well 44 and the source layer 45 on the surface as a source terminal S, and an electrode film 47 connected to the drain connection layer 41 as a drain terminal. The electrode film 46 connected to the terminal D and the gate 43 is used as the gate terminal G, and the gate voltage applied to the terminal G controls channel formation on the surface of the lower part of the gate 43 of the well 44, thereby forming a source terminal. S and drain terminal D
The gap between the two is cut off or made conductive. The current i during conduction flows vertically inside the substrate 40 and the like as shown in the figure, so it is called a vertical type. [0010] However, it is difficult to apply the vertical structure as shown in FIG. 4 to a field effect transistor using silicon carbide as it is. This is because the temperature required for diffusion of impurities to form a semiconductor layer is about 1000°C in the case of silicon, while in silicon carbide it is about 2000°C.
℃ or higher, and in reality there is no practical equipment that can thermally diffuse impurities at such high temperatures. In addition, it takes a very long time to diffuse impurities into a considerable depth such as the well 44 in FIG. This is because the above is almost impossible to implement. Another problem is that field effect transistors have the disadvantage that their forward voltage is inherently high as mentioned above, and although silicon carbide can be used to increase the withstand voltage, it is difficult to handle large currents. If the forward voltage when flowing is too high, its practicality may be significantly reduced. In order to lower the forward voltage, it is necessary to increase the impurity concentration in the semiconductor layer to lower its specific resistance value, but it is difficult to eliminate this drawback if impurity diffusion is difficult as described above. Based on the current situation, the present invention solves the problem of silicon carbide, in which thermal diffusion of impurities is difficult, and makes use of the features of field effect transistors such as high switching speed and high input impedance, while achieving even higher breakdown voltage. It is an object of the present invention to provide a field effect transistor with a vertical structure using silicon carbide, which can improve the forward voltage of the transistor, and a method of manufacturing the same. [Means for Solving the Problems] According to the field effect transistor of the present invention, a first semiconductor region made of silicon carbide of one conductivity type, and a first semiconductor region made of silicon carbide of the other conductivity type overlapped therewith. a third semiconductor region made of one conductivity type in a part of the surface of the second semiconductor region; A dug recess, a gate insulating film covering the surface of the recess, and a gate region formed in the recess through the gate oxide film are provided, and a pair of semiconductor regions are formed from the first and third semiconductor regions. This is achieved by leading out the source/drain terminals and the gate terminal from the gate region. [0014] In general, the first semiconductor region in the above structure may be used as a drain layer, the second semiconductor region may be used as a well or substrate, and the third semiconductor region may be used as a source layer. It is preferable that the second semiconductor region is an epitaxial layer of silicon carbide grown on a substrate made of silicon carbide of a conductivity type, and the second semiconductor region is an epitaxial layer of silicon carbide further grown thereon.
In this case, it is preferable to use a silicon carbide single crystal with a high impurity concentration as the substrate. Furthermore, the third semiconductor region may be a very shallow semiconductor layer that is simply activated by introducing impurities into the surface of the second semiconductor region. Furthermore, it is advantageous that the second semiconductor region and the third semiconductor region are short-circuited to each other at their surfaces by an electrode film for leading out the terminal. It is also desirable that the field effect transistor of the present invention has a composite structure in which small transistors are integrated, as in the case of using a silicon semiconductor. In field effect transistors for high voltage applications, a guard ring or a channel stopper layer is usually provided to prevent dielectric breakdown along the semiconductor surface, but when using a silicon carbide semiconductor, it is difficult to diffuse impurities for this purpose, so a second semiconductor region is used instead. It is advantageous to cut a mesa-etched trench from the periphery of the semiconductor region to the first semiconductor region. When the field effect transistor has the above-mentioned composite structure, the mesa etching groove may be provided so as to surround a plurality of small transistors in common. According to the method for manufacturing a field effect transistor of the present invention, the step of epitaxially growing a first semiconductor region of silicon carbide of one conductivity type on a substrate of silicon carbide of one conductivity type; a step of epitaxially growing a second semiconductor region of silicon carbide of the other conductivity type on the surface of the second semiconductor region; a step of digging a recess in a part of the surface of the second semiconductor region so as to reach the first semiconductor region; a step of covering the surface of the area with a gate insulating film; a step of forming a gate region so as to fit into the recess through the gate insulating film;
A step of implanting impurity ions into the peripheral area of the recess in the surface of the second semiconductor region to form a third semiconductor region of one conductivity type, and a step of forming a third semiconductor region of one conductivity type,
The above object is achieved through the steps of providing a drain electrode film and a gate electrode film connected to the gate region. In the epitaxial growth process of the first and second semiconductor regions in the above structure, these semiconductor regions may be grown in a vapor phase by CVD using a raw material gas containing silane, methane, etc. It is advantageous to use a reactive ion etching method in the digging process. In addition, in the process of coating the gate insulating film, it is preferable to form a silicon oxide film by oxidizing the surface of the recess, and in the process of forming the gate region in the recess, polycrystalline silicon is grown using the CVD method. It is advantageous to let them do so. In the step of forming the third semiconductor region, as described above, it is difficult to thermally diffuse impurities after ion implantation, so the implanted impurities are activated by high-temperature heat treatment to form a layer of, for example, about 0.1 μm. It is sufficient to create a shallow third semiconductor region. Furthermore, it is not particularly necessary to carry out the step of forming the third semiconductor region after providing the gate region, and it may be carried out before the step of digging a recess for the gate region. Note that using aluminum as the p-type impurity and nitrogen as the n-type impurity for the silicon carbide semiconductor imparts impurity levels as narrow as possible to each of the semiconductor regions and improves the characteristics of the field effect transistor. preferred above. [Operation] In the field effect transistor and the manufacturing method thereof according to the present invention, the first and second semiconductor regions referred to in the structure described in the previous section are formed of an epitaxial layer of silicon carbide, and impurities are introduced from the beginning during the epitaxial growth. A portion of the second semiconductor region that is in contact with the gate insulating film on the side surface of the recess as a so-called buried structure in which the gate region is placed in a recess dug so as to penetrate through the second semiconductor region and reach the first semiconductor region. By using the channel forming surface as the channel forming surface, it is not necessary to diffuse impurities into the first and second semiconductor regions later, thereby solving the problem of silicon carbide in which thermal diffusion of impurities is difficult. Furthermore, the present invention improves the withstand voltage of a field effect transistor by setting the electric field strength in the first semiconductor region high by utilizing the feature of silicon carbide having a high allowable maximum electric field strength, and also increases the electric field strength. By optimizing the thickness of the first semiconductor region in accordance with the set value of , it is possible to reduce the forward voltage of the field effect transistor. The reason why this forward voltage can be reduced will be explained below using some equations. In the field effect transistor of the present invention, a channel is formed in the second semiconductor region as described above, and if its on-resistance is R, it is the sum of the resistance Rc of this channel and the resistance R1 in the first semiconductor region. , R=Rc+R1

1), but several hundred V
In the above high voltage field effect transistor, the channel resistance R
Since c is about 1% of the resistance R1 of the first semiconductor region,
In reality, the resistance R may be determined only by the resistance R1. Similarly, all the voltages applied when the field effect transistor is turned off may be applied to the first semiconductor region, and if the withstand voltage value of the field effect transistor is V, it can be expressed by the following equation. V=Emd-qN1d2
/2ε
2) However, Em is the electric field strength in the first semiconductor region, that is, the maximum allowable electric field strength of silicon carbide, and d is the first
The thickness of the semiconductor region, q is the electron charge, N1 is the impurity concentration of the first semiconductor region, and ε is the dielectric constant of silicon carbide.The internal electric field strength distribution when the depletion layer extends into the first semiconductor region is well known. It was assumed that the slope changes linearly with the slope determined by the impurity concentration, as shown in the figure. Now, since the resistance R1 of the first semiconductor region in equation 1) when on is proportional to its thickness d and inversely proportional to the impurity concentration N1, if the on-resistance R is equal to this resistance R1, its reciprocal is It is expressed by the following formula. 1/R=A・μN1/d

3) However, A is a proportionality constant and μ is the mobility of electrons in silicon carbide. Now, when we insert the impurity concentration N1 obtained from equation 2) into equation 3), we get 1/R=A・(2εμ
/q) (Em/d2 -V/d3) 4
) is obtained. Letting the right side of this equation 4) be a function of the thickness d of the first semiconductor region, and finding the thickness that minimizes the left side, we get:
d=3V/2Em

5), and if the forward voltage of the field effect transistor when the thickness of the first semiconductor region is set to this optimum value d is Vf, then by inserting the thickness d from equation 5) into equation 4), the following equation can be obtained. It will be done. Vf∝R∝V2 /εμ
Em3
6) As can be seen from the above, by optimizing the thickness d of the first semiconductor region according to the maximum electric field strength Em of silicon carbide as shown in equation 5) above, the forward voltage Vf of the field effect transistor can be reduced. can be reduced in inverse proportion to the cube of the maximum electric field strength Em, as shown in equation 6). The maximum electric field strength Em of silicon carbide is 3x1016V/c
m, about 1 more than silicon's 3.7x1015V/cm
It can be seen that the forward voltage Vf can be significantly reduced because it is an order of magnitude higher. Further, the thickness d of the first semiconductor region can be made as thin as about one-eighth of that in the case of silicon. Note that since the electron mobility μ in equation 6) is lower in silicon carbide than in silicon, the above effect is somewhat diminished, but the forward voltage can still be reduced to about 1/20th. [Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view of an embodiment of a field-effect transistor according to the present invention, FIG. 2 is a cross-sectional view showing an embodiment of the manufacturing method of the field effect transistor at each main step leading to the completed state shown in FIG. 1, and FIG.
1 is a cross-sectional view and a top view of a field effect transistor with a composite structure. In these embodiments, all field effect transistors are of n-channel type. For the field effect transistor 30 shown in FIG. 1, in this embodiment, silicon carbide doped with a predetermined impurity concentration of the same n-type is formed on a substrate 10 of a single crystal of silicon carbide doped strongly n-type. A three-layer structure of silicon carbide is used, in which a first semiconductor region 11 made of an epitaxial layer and a second semiconductor region 12 made of similar silicon carbide doped with an opposite p-type impurity concentration are stacked one after another. A shallow third semiconductor region 13 is formed in the center of the surface of the second semiconductor region by ion-implanting nitrogen or the like as an n-type impurity at a high dose. For example, when the field effect transistor 30 has a breakdown voltage of 1000V, the thickness of the first semiconductor region 11 is approximately 10 μm, the thickness of the second semiconductor region 12 is 1 to 2 μm, and the depth of the third semiconductor region 13 is approximately 0.5 μm. be done. Furthermore, the recess 14 is further extended from the center of the third semiconductor region 13.
is dug through the second semiconductor region 12 to reach the first semiconductor region 11, and a thin gate insulating film 21 is applied to cover the surface thereof. The gate 23 in this embodiment is made of polycrystalline silicon made to fill the recess 14. In the field effect transistor 30 of FIG. 1, the second semiconductor region 12 is a p-type well, and the third semiconductor region 1 is a p-type well.
3 constitutes an n-type source region, and the first semiconductor region 11 and the substrate 10 thereunder constitute an n-type drain region, and insulating films 24 are attached to the front and back surfaces in order to lead out connection terminals from these, respectively. An electrode film 25 is provided at a predetermined location within the window opened therein to make conductive contact. As shown, the second
The surfaces of the semiconductor region 12 and the third semiconductor region 13 are short-circuited by this electrode film 25, and a source terminal S is led out from the electrode film 25. A drain terminal D is led out from the electrode film 25 which is in conductive contact with the substrate 10, and a gate terminal G is led out from the electrode film 25 which is in conductive contact with the gate 23. This field effect transistor 30 is an n-channel type in which a channel formation region is a portion of the p-type second semiconductor region 12 facing the gate 23 with the gate insulating film 21 interposed therebetween. By controlling this channel formation by applying a voltage to the source terminal S and the drain terminal D, it is possible to cut off or conduct the connection between the source terminal S and the drain terminal D. It is a vertical type in which current flows vertically within the substrate 10 and the first semiconductor region 11 when conducting, and when cut off, the current flows vertically within the substrate 10 and the first semiconductor region 11.
A depletion layer extends inside. As mentioned above, the maximum electric field strength of silicon carbide in the first semiconductor region 11 is high and its thickness can be made approximately one order of magnitude thinner than in the case of silicon. Therefore, the field effect transistor 30 according to the present invention is suitable for high breakdown voltage applications and has a high maximum electric field strength. Directional voltage can be reduced by more than an order of magnitude. Furthermore, the features of field effect transistors, such as high input impedance and high switching speed, are utilized as they are in the case of the present invention, and are comparable to those of silicon. In addition, silicon carbide has the advantage of being easy to cool because its thermal conductivity is about three times higher than that of silicon. Note that in a field effect transistor for large current use, it is advantageous to adopt a composite structure as shown in FIG. Although the field effect transistor of the present invention is suitable for high breakdown voltages as described above, it is difficult to diffuse impurities into the surface of the second semiconductor region 12 in order to provide a guard ring or a channel stopper on the surface, as in the case of silicon. Since it is difficult to do so, it is desirable to provide mesa etching grooves 15 in the peripheral portion as shown in FIG. 1 instead. It is best to use dry etching using a fluorine-based reactive gas for this mesa etching, and by selecting isotropic etching conditions, the mesa etching groove 15 is formed into a second groove with an inclination of about 45 degrees as shown in the figure. At least the first
After digging to reach the semiconductor region 11, the etched surface is covered with an insulating film 24 of silicon oxide or silicon nitride, and each chip is isolated to form the state shown in the figure. Next, a method for manufacturing a field effect transistor according to the present invention will be explained with reference to FIG. In the figure (a), an n-type first semiconductor region 11 and a p-type second semiconductor region 12, both made of silicon carbide, are formed on an n-type silicon carbide substrate 10 with a thickness of several hundred μm as described above. The epitaxial growth is shown to have a thickness of approximately 10 μm and a thickness of 1 to 2 μm, respectively. The epitaxial growth of these semiconductor regions 11 and 12 may be carried out by vapor phase growth using, for example, a CVD method using a source gas containing silane, methane, etc., and impurities may be mixed into this source gas for vapor phase growth. By placing the silicon carbide on the substrate, silicon carbide to be epitaxially grown can be doped with impurities at a desired concentration. For this purpose, nitrogen is most suitable as the n-type impurity, and aluminum is most suitable as the p-type impurity. FIG. 2(b) shows the process of digging the recess 14. Although chemical etching is also possible for this digging, it is better to use a dry etching method, particularly a reactive ion etching method, to dig the recess 14 under anisotropic etching conditions so that the side surface shape is approximately right angle as shown in the figure. is advantageous. The width of this recess 14 is desirably narrow, for example, 2 to 3 μm, so that it can be easily filled with polycrystalline silicon or the like in the next step. Although not shown in the figure, this digging etching is of course performed using a photoresist film or the like as a mask. FIG. 2C shows the growth process of the gate insulating film 21 and the polycrystalline silicon 22 for the gate. The easiest way to form the gate insulating film 21 is to use a thermal oxide film as in the case of silicon, and even in the case of silicon carbide, a silicon oxide film can be formed into the gate insulating film 21 by short-term thermal oxidation in an atmosphere containing oxygen. It can be applied with a suitable film thickness of, for example, 0.05 to 0.1 μm. Next, the polycrystalline silicon 22 is grown by a low pressure CVD method using silane as a raw material gas until it fills the inside of the recess 14, resulting in the state shown in the figure. Furthermore, this polycrystalline silicon 22 is etched by a dry etching method using, for example, CF4 as a reaction gas to form a recess 14 as shown in FIG. 2(d).
The gate insulating film 21 remaining on the surface other than the recess 14 is removed by short-time chemical etching using dilute hydrofluoric acid or the like. FIG. 2(d) shows the step of forming the third semiconductor region 13. For this purpose, an ion implantation method is used, and after covering unnecessary parts with a mask (not shown), nitrogen is applied at 100kV.
The n-type third semiconductor region 13 is implanted into the peripheral area of the gate 23 on the surface of the second semiconductor region 12 to a depth of, for example, about 0.1 μm with a high dose under an acceleration voltage of about 0.5 μm.
Incorporate. Since thermal diffusion of introduced impurities is difficult in silicon carbide, the impurities are only activated by heat treatment at a high temperature of about 1100° C. thereafter. Even if the third semiconductor region 13 is very shallow in this way, it can sufficiently fulfill its role as a source region. Thereafter, as explained in FIG. 1, the mesa etching groove 15 is dug and the insulating film 24 is
After coating and disposing the electrode film 25, the completed state shown in FIG. 1 is obtained. FIG. 3 shows an embodiment in which the present invention is applied to a field effect transistor 31 having a composite structure. Figure 3(a) is a cross-sectional view, and Figure 3(b) is a top view of a part of it.
a) corresponds to the cross section taken along the line X-X in FIG. 2(b). The gates 23 in the three recesses 14 in FIG. 3(a) are actually cross sections of the gates 23 having a continuous mesh pattern shown in FIG. 3(b). Recess 14 in case of composite structure
It is advantageous to form the gate 23 in such a net-like or comb-like pattern; for convenience of illustration, only two meshes are shown in FIG. It is said to be a net-like pattern with hundreds of eyes. The recess 14 having such a pattern forms the second semiconductor region 1 as shown in FIG.
2 to reach the first semiconductor region 11 is the same as in the previous embodiment, and the third semiconductor region is dug through the recess 1 to reach the first semiconductor region 11.
4 to the outside and the inside of the mesh. As shown in FIG. 3(b), the gate 23 has an extending portion 23a extending outward from the mesh pattern, and a gate terminal G is led out from the electrode film 25 that is in conductive contact with the extending portion 23a. The electrode film 25 for the source terminal S is formed so as to cover the entire mesh pattern of the gate 23.
), it is insulated from the gate 23 by the insulating film 24. Second semiconductor region 12 and third semiconductor region 13
The surface of the source terminal S is short-circuited by the electrode film 25 for the source terminal S, as in the previous embodiment. Mesa etching groove 1
5 is dug into the periphery of the chip of the field effect transistor 31 so as to surround the entire composite structure from the outside, and its surface is protected by the insulating film 24. Drain terminal D
In this example, the electrode film 25 is provided so as to cover the entire back surface of the chip, as shown in FIG. The field effect transistor 31 with the composite structure shown in FIG. 3 is suitable for large currents, and can easily be configured with a rating of several tens of A to over 100 A. It can be built inside. [0038] The present invention is not limited to the embodiments described above, but can be implemented in appropriate aspects or various forms. The conductivity type, thickness, etc. of each semiconductor region in the embodiments are merely examples, and should be appropriately set according to the voltage, current, etc. conditions under which the field effect transistor is used. Further, in the manufacturing method illustrated in FIG. 2, the third semiconductor region is formed after the recess is formed, but the recess may be formed after the third semiconductor region is formed. As described above, in the field effect transistor of the present invention, the first and second semiconductor regions of silicon carbide are stacked with one conductivity type and the other conductivity type, and the third semiconductor region is stacked with the second conductivity type.
One conductivity type is formed in a part of the surface of the semiconductor region, a recess is dug from within the range of the third semiconductor region to reach the first semiconductor region, the surface is covered with a gate insulating film, and the recess is formed in the recess. In the manufacturing method, first and second semiconductor regions of silicon carbide of one conductivity type and the other conductivity type are epitaxially grown on a substrate of silicon carbide of one conductivity type, and the gate is formed in the second semiconductor region. A recess is dug from a part of the surface until it reaches the first semiconductor region, the surface is covered with a gate insulating film, a gate region is formed in the recess, and impurity ions are implanted around the recess. By forming three semiconductor regions of one conductivity type, the following effects can be obtained. (a) The first and second semiconductor regions are made of silicon carbide doped with impurities during epitaxial growth, and the gate is fitted into the recess to form a channel in the second semiconductor region. Furthermore, it is possible to eliminate the need to diffuse impurities later into the second semiconductor region, solve the problem of difficulty in thermally diffusing impurities into silicon carbide, and provide a highly practical field effect transistor. (b) By utilizing the feature of silicon carbide, which has a high allowable maximum electric field strength, and giving the first semiconductor region the role of withstanding high electric field strength, an electric field effect with a much higher breakdown voltage value than that of silicon type can be achieved. Can configure transistors. (c) By optimizing the thickness and impurity concentration in the first semiconductor region according to the set value of the electric field strength, the forward voltage of the field effect transistor can be reduced by more than one order of magnitude compared to the conventional one. . (d) Since internal heat generation can be easily dissipated by utilizing the high thermal conductivity of silicon carbide, the chip size of the field effect transistor can be reduced in conjunction with the reduction of the forward voltage, and its operation can be reduced. Reliability can be improved. The present invention utilizes the advantages of high switching speed and input impedance of field effect transistors while overcoming the limitations of using silicon to create a power source with high withstand voltage and low forward voltage as described above. This makes it possible for the first time to put practical field effect transistors into practical use using silicon carbide.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing one embodiment of a field effect transistor using a silicon carbide semiconductor according to the present invention.

FIG. 2 shows electric fields in the main steps of the method of manufacturing a field-effect transistor according to the present invention, which corresponds to FIG. 1, and shown in FIGS. FIG. 2 is a cross-sectional view of a wafer for effect transistors.

FIG. 3 shows an embodiment in which the present invention is applied to a field effect transistor having a composite structure, with a cross-sectional view in FIG. 3(a) and a partial top view in FIG. 3(b).

FIG. 4 is a cross-sectional view showing, for reference, a structural example of a conventional field effect transistor using a silicon semiconductor.

[Explanation of symbols]

10 Silicon carbide substrate 11 First semiconductor region or drain region 12 Second semiconductor region or well region 1
3 Third semiconductor region or source region 14
Recess 15 Mesa etching groove 21 Gate insulating film 22 Polycrystalline silicon 23 Gate 25 Electrode film 30 Field effect transistor 31
Composite structure field effect transistor D Drain terminal G Gate terminal S Source terminal

Claims (3)

[Claims] 1. A first semiconductor region made of silicon carbide of one conductivity type, a second semiconductor region made of silicon carbide of the other conductivity type overlaid thereon, and a portion of the surface of the second semiconductor region. a third semiconductor region made of one conductivity type in the range of the third semiconductor region; a recess dug from within the third semiconductor region to reach the first semiconductor region; and a recess that covers the surface of the recess. comprising a gate insulating film and a gate region formed in a recess through the gate oxide film;
A field effect transistor characterized in that a pair of source/drain terminals connected to a semiconductor region and a gate terminal connected to a gate region are derived. 2. The transistor according to claim 1,
A field effect transistor characterized in that a mesa etching groove is dug from the periphery of the second semiconductor region to the first semiconductor region. 3. A step of epitaxially growing a first semiconductor region made of silicon carbide of one conductivity type on a substrate made of silicon carbide of one conductivity type, and growing silicon carbide of the other conductivity type on the first semiconductor region. a step of epitaxially growing a second semiconductor region, a step of digging a recess within a part of the surface of the second semiconductor region so as to reach the first semiconductor region, and a step of forming a gate insulating film on the surface of the recess. A covering step;
A process of forming a gate region so as to fit into the recess through a gate insulating film, and implanting impurity ions into the peripheral area of the recess on the surface of the second semiconductor region to form the third semiconductor region with one conductivity type. 1. A field effect transistor comprising: a manufacturing step; and a step of providing source/drain electrode films connected to first and third semiconductor regions and gate electrode films connected to a gate region. Production method.