JP2005086140A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem that the concentration of an electric field occurs at an upper end of a polysilicon gate electrode in the conventional power MOSFET, resulting in the reduction in a breakdown resistance of a gate insulating film. <P>SOLUTION: An n-type impurity is diffused on the upper part of a first gate electrode composed of p-type polysilicon in a trench to form a second gate electrode. Since joint surfaces of the first and the second gate electrode are joined in the form of a pn junction, a depletion layer spreads. Thus, the concentration of the electric field can be relaxed. Consequently, a breakdown resistance of a gate insulating film of a trench type power MOSFET can be improved. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

The present invention relates to a structure of a vertical MOSFET having a trench structure and a manufacturing method thereof.

  In a conventional vertical MOSFET, a polysilicon gate electrode is embedded in a trench, and a source electrode is formed thereon via an interlayer insulating film.

  The structure of such a vertical MOSFET will be described with reference to FIG. 13, taking a p-channel type as an example.

  In the semiconductor substrate 111 having an n − type channel layer 112 on the surface and a p − type drain region 111 a and a p + type drain region 111 b below the n − type channel layer 112, a large number of trenches 113 extend over the n − type channel layer 112 and p −. A depth reaching the mold drain region 111a is formed. A gate oxide film 114 is formed on the surface of the trench 113, and a gate electrode 115 made of polycrystalline silicon or the like is embedded in the gate oxide film 114. On the surface of the channel layer 112, an n + -type body contact region 117 is disposed substantially in the middle of the adjacent trench 113. A p + -type source region 118 is provided adjacent to the body contact region 117 and the trench 113. An NSG layer 122 and a BPSG layer 120 are disposed on the gate electrode 115, and a metal electrode 123 such as aluminum is provided on the entire surface of the cell region. The NSG layer 122 and the BPSG layer 120 serve as an interlayer insulating film 121 to insulate and isolate the gate electrode 115 and the metal electrode 123. The metal electrode 123 is configured to make ohmic contact with the source region 118 and the body contact region 117.

  A manufacturing process of a conventional p-channel power MOSFET having a trench structure will be described with reference to FIGS.

In FIG. 13, a silicon semiconductor substrate 111 in which a p ⁻ type drain region 111a is stacked on a p ⁺ type drain region 111b is prepared. An n-type impurity is selectively implanted into the planned channel layer 112 and then diffused to form the channel layer 112.

  In FIG. 14, after forming a mask (not shown) with a CVD oxide film of NSG (Non-doped Silicate Glass) on the entire surface by CVD, the silicon semiconductor substrate is anisotropically dry-etched with CF-based gas and HBr-based gas to obtain a channel layer 112. A trench 113 is formed so as to penetrate through to the drain region 111a (FIG. 14A). Thereafter, the entire surface is thermally oxidized to form a gate oxide film 114 (FIG. 14B).

  In FIG. 15, a non-doped polysilicon layer is deposited on the entire surface, and boron is implanted and diffused at a high concentration to increase the conductivity. Thereafter, the polysilicon layer deposited on the entire surface is dry-etched without a mask to form a gate electrode 115 embedded in the trench 113.

In FIG. 16, n-type impurities are selectively ion-implanted using a mask made of a resist film PR to form an n ⁺ -type body contact region 117, and then the resist film PR is removed.

After that, masking is performed to expose the planned source region 118 and gate electrode 115 with a new resist film PR, and impurities are ion-implanted to form a p ⁺ -type source region 118 on the surface of the channel layer 112 adjacent to the trench 113. After that, the resist film PR is removed.

  In FIG. 17, after forming the NSG layer 122 on the entire surface, a BPSG (Boron Phosphorus Silicate Glass) layer is deposited by the CVD method. Further, using the resist film as a mask, the other regions of the BPSG layer, the NSG layer, and the gate oxide film 114 on the substrate surface are removed so as to remain on the gate electrode 115 to form an interlayer insulating film 121.

After that, aluminum is deposited on the entire surface by a sputtering apparatus to form the source electrode 123 that contacts the source region 118 and the body contact region 117, thereby obtaining the final structure shown in FIG. 13 (see, for example, Patent Document 1).
Japanese Patent Laid-Open No. 11-67787 (2nd page, FIG. 8)

  As described above, the gate electrode 115 is in contact with the gate oxide film 114, and the electric field tends to concentrate at the corner portion at the upper end of the gate electrode 115 when the gate is turned on. The gate oxide film 114 is preferably thin in order to improve the switching speed, and it is necessary to provide the gate oxide film 114 as thin as possible within a range corresponding to the drive voltage. For this reason, there has been a problem that the breakdown resistance of the gate oxide film is reduced due to the electric field concentration described above.

  The present invention has been made in view of such problems, and includes a one-conductivity-type semiconductor substrate, a trench provided in the semiconductor substrate, an insulating film covering at least the inner wall of the trench, a first electrode embedded in the trench, The main object is to include a second electrode provided on the first electrode and a one conductivity type region provided adjacent to the trench on the surface of the substrate.

  Another object of the present invention is to provide a semiconductor substrate having a drain region of one conductivity type, a reverse conductivity type channel layer provided on the surface of the drain region, a trench provided in the semiconductor substrate, and at least the inner wall of the trench. An insulating film covering the first electrode, a first electrode embedded in the trench, a second electrode provided on the first electrode, and a channel electrode provided on the surface of the channel layer adjacent to the trench. And a source region of a conductivity type.

  Another object of the present invention is to provide a semiconductor substrate having a drain region of one conductivity type, a reverse conductivity type channel layer provided on the surface of the drain region, a trench provided in the semiconductor substrate, and at least the inner wall of the trench. A first electrode made of one conductivity type semiconductor material embedded in the trench, and a second electrode made of a reverse conductivity type semiconductor material provided on the first gate electrode A source region of one conductivity type provided adjacent to the trench on the surface of the channel layer, and a body contact region of opposite conductivity type provided on the surface of the channel layer between the source regions. It is in.

  Another object of the present invention is to have a silicon oxide film containing a reverse conductivity type impurity covering at least the first and second electrodes.

  Another object of the present invention is to deplete the junction surface between the first electrode and the second electrode.

  Another object of the present invention is to embed the second electrode in the trench.

  Another object of the present invention is to provide the second electrode at a depth less than or equal to the source region.

  Another object of the present invention is to provide a step of forming a trench on the surface of the one-conductivity-type semiconductor substrate, a step of forming an insulating film covering at least the inner wall of the trench, and a first electrode embedded in the trench. Forming a second electrode provided on the first electrode, and forming a one-conductivity type region adjacent to the trench on the surface of the substrate. .

  Another object of the present invention is to form a reverse conductivity type channel layer on the one conductivity type drain region of the semiconductor substrate surface, and to form a trench that penetrates the channel layer and reaches the drain region; Forming an insulating film on the inner wall of the trench; forming a first electrode embedded in the trench; forming a source region of one conductivity type on the surface of the channel layer adjacent to the trench; And forming a second electrode on the first gate electrode, and forming an interlayer insulating film covering at least the trench.

  Another object of the present invention is to form a reverse conductivity type channel layer on the one conductivity type drain region of the semiconductor substrate surface, and to form a trench that penetrates the channel layer and reaches the drain region; A step of forming an insulating film on the inner wall of the trench; a step of forming a first electrode by embedding a semiconductor material containing one conductivity type impurity in the trench; and one conductivity on the surface of the channel layer adjacent to the trench. A step of forming a source region of a mold, a step of forming a second electrode of a reverse conductivity type on the first electrode, and a step of forming an interlayer insulating film covering at least the trench. There is.

  Another object of the present invention is to form a silicon oxide film containing a reverse conductivity type impurity over at least the first electrode, and the second electrode includes the reverse conductivity type impurity as the first conductivity type. It is to be formed by diffusing over the electrode.

  Another object of the present invention is to form the second electrode by diffusing a reverse conductivity type impurity above the first electrode.

  Another object of the present invention is that the reverse conductivity type impurity is ion-implanted under the condition that the depth of the reverse conductivity type impurity implantation region is not more than the thickness of the insulating film.

  As described above, the present invention forms the second gate electrode 16 of the reverse conductivity type on the upper layer of the first gate electrode 15 of one conductivity type in the structure of the trench vertical MOSFET and the manufacturing method thereof. is there. Thereby, the junction surface of the first gate electrode 15 and the second gate electrode 16 forms a pn junction, and a depletion layer is formed by the built-in voltage.

  Since the electric field is also received in this depletion layer region, the electric field concentration at the corner of the upper end of the second gate electrode 16 is alleviated and the breakdown resistance of the device is improved.

  An embodiment of the present invention will be described with reference to FIGS. 1 to 12 by taking a p-channel trench power MOSFET as an example.

  FIG. 1 shows a cross-sectional view of the structure of a power MOSFET according to the present invention.

  The trench power MOSFET includes a drain region 11, a channel layer 12, a trench 13, a gate oxide film 14, a first gate electrode 15, a second gate electrode 16, an interlayer insulating film 21, and a source region. 18, body contact region 17, and source electrode 23.

The semiconductor substrate 11 is, for example, provided with a p ⁻ type drain region 11a on a p ⁺ type silicon semiconductor substrate 11b. The channel layer 12 selectively ionizes n − type impurities on the surface of the drain region 11a. It is a diffusion layer diffused after implantation. A channel region (not shown) is formed in a region adjacent to the trench 13 of the channel layer 12.

  The trench 13 is formed by anisotropic dry etching of the semiconductor substrate 11 and penetrates the channel layer 12 to reach the drain region 11a. In general, trenches 13 are formed in a grid pattern or stripe pattern in a planar pattern on a semiconductor substrate. A gate oxide film 14 is provided on the inner wall of the trench 13, and polysilicon into which impurities are introduced is buried to provide a first gate electrode 15 and a second gate electrode 16.

  The gate oxide film 14 is formed at least on the inner wall of the trench 13 in contact with the channel layer 12 to a thickness of, for example, about 600 mm depending on the driving voltage. Since the gate oxide film 14 is an insulating film, it has a MOS structure sandwiched between the first gate electrode 15 and the second gate electrode 16 provided in the trench 13 and the silicon substrate.

  The first gate electrode 15 is made of polysilicon buried in the trench 13, and p-type impurities are introduced into the polysilicon to reduce the resistance.

  The second gate electrode 16 is formed by diffusing an n-type impurity on the first gate electrode 15 embedded in the trench 13 and is provided at a depth equal to or less than the depth of the source region 18. As will be described in detail later, the junction surface of the second gate electrode 16 and the first gate electrode 15 becomes a pn junction, and a depletion layer spreads by the built-in voltage, and the electric field concentration at the upper end of the gate electrode can be relaxed by this depletion layer . As will be described in detail later, it is preferable that the depletion layer region be as deep as possible. However, if it is too deep, there is a problem such as an increase in gate resistance.

  The junction surfaces of the first gate electrode 15 and the second gate electrode form a pn junction.

  The interlayer insulating film 21 covers at least the first and second gate electrodes 15 and 16 and is composed of a silicon oxide film 19 containing n-type impurities and a BPSG film 20 stacked thereon. The silicon oxide film 19 is, for example, a PSG (Phosphorous Silicate Glass) film, diffuses phosphorus on the first gate electrode 15 by heat treatment after film formation, and the second gate electrode 16 on the first gate electrode 15. Form. As will be described later, by forming the second gate electrode 16 by diffusing impurities from the PSG film 19, impurities can be added only on the first gate electrode 15 without affecting the impurity concentration of the adjacent source region 18. Can diffuse.

  Further, the second gate electrode 16 may be optimized by ion implantation conditions, and impurities may be implanted / diffused on the first gate electrode 15 by ion implantation. In that case, the NSG film 22 may be used instead of the PSG film 19, and the BPSG film 20 is further laminated to form the interlayer insulating film 21.

  The PSG film 19 or the NSG film 22 is provided with a thickness of about 2000 mm, and the BPSG film is provided with a thickness of several thousand mm.

The source region 18 is a p + type impurity region provided on the surface of the channel layer 12 along the trench 13 adjacent to the trench 13. Body contact region 17 is an n ⁺ -type impurity region provided on the surface of channel layer 12 between adjacent source regions. The body contact region 17 is provided for stabilizing the substrate potential.

  The source electrode 23 in contact with the source region 18 and the body contact region 17 is composed of a barrier metal layer such as titanium nitride and an upper aluminum layer.

  Here, a MOSFET having the structure of the present embodiment will be described with reference to FIG. 2 in comparison with a MOSFET having a conventional structure. 2A is a cross-sectional view of the MOSFET, FIG. 2B is an electric field distribution diagram at the upper end of the gate electrode, and FIG. 2C is a graph of evaluation of electric field concentration.

  This measurement reproduces the gate-on state in which the gate bias is applied to the gate electrode at −20 V and the source electrode is at the GND potential, and the thickness of the gate oxide film is 600 mm.

  2A shows an electric field distribution diagram of the corner portion (a1) at the upper end of the gate electrode 115 having the conventional structure and the corner portion (a2) at the upper end of the second gate electrode 16 having the structure according to the present embodiment. 2 (B). Further, in FIG. 2C, the amount of electric field concentration in the channel region (gate electrode intermediate portion) indicated by b1 and b2 in FIG. 2A was also evaluated.

  As shown in FIGS. 2B and 2C, the electric field concentration is 3.3 MV / cm in both the channel regions (b1 and b2 regions), whereas in the conventional structure, the corner portion at the upper end of the gate electrode 115 is formed. In (a1 region), the strongest portion is 6 MV / cm, and it can be seen that the electric field is distributed in a shape close to a circle so as to surround the corner portion. In addition, the electric field is distributed so as to surround the corner portion even when the electric field strength gradually decreases.

  In this conventional structure, if the gate oxide film is about 600 mm in design, it can withstand a gate voltage of about 48 V to 50 V which is an electric field of about 8 MV / cm, which is the maximum electric field strength of the oxide film. However, in the measured value of the conventional structure, the electric field concentration is 6 MV / cm at 20 V (gate bias -20 V). Actually, there are other factors, but if the ratio is simply calculated for comparison, the gate bias is about −26 V ((8/6) × (−20)) when the conventional structure is 8 MV / cm. become. Further, in the experiment, when the gate voltage is increased to 29 V, the gate oxide film may break down, and it is supported that the breakdown tolerance cannot be secured with the electric field concentration of 6 MV / cm.

  On the other hand, in the structure of the present embodiment, the region with the highest electric field intensity surrounding the corner portion (a2 region) is wider than the a1 region. Further, it can be seen that the region of the electric field intensity that is three steps lower than that spreads downward.

  This is because a depletion layer is formed by a built-in voltage at the pn junction interface, which is the junction between the first gate electrode 15 and the second gate electrode 16. That is, since the electric field is also received in the depletion layer region below the corner part a2, the electric field concentrated at the corner part spreads downward, and the electric field distribution around the corner part a2 becomes gentle. Also, it can be seen that the equal electric field distribution becomes gentle and relaxed above the a2 region.

  As described above, in this embodiment, the electric field spreads from the opening of the trench 13 to the depletion layer region positioned further downward, so that the electric field concentration near the upper corner of the second gate electrode 16 can be reduced. In other words, it can be considered that the electric field distribution spreads downward and the electric field concentration can be more relaxed if the depletion layer region is made as deep as possible. However, if the depletion layer region is too deep, there is a problem such as an increase in gate resistance.

  As a result, in the structure of this embodiment, the electric field concentration amount is 4.3 MV / cm as in 2 (C), which is lower than the conventional electric field concentration amount of 6 MV / cm. Further, when the case of 8 MV / cm is calculated in the structure of the present embodiment in the same manner as described above, it can withstand up to about 37 V ((8 / 4.3) × (−20)). Also in the experiment, it was possible to secure a breakdown resistance of 29 V or higher, which was the gate oxide film in the conventional structure, and to improve the breakdown resistance of the device.

  A method of manufacturing the above semiconductor device will be described with reference to FIGS. 3 to 12 and FIG. 1, taking a p-channel type MOSFET having a trench structure as an example.

  According to one embodiment of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a channel layer of opposite conductivity type on a drain region of one conductivity type on a semiconductor substrate surface; and forming a trench that penetrates the channel layer and reaches the drain region. A step of forming an insulating film on the inner wall of the trench, a step of forming a first electrode embedded in the trench, and a source region of one conductivity type on the surface of the channel layer adjacent to the trench. , Forming a second electrode on the first gate electrode, and forming an interlayer insulating film covering at least the trench.

  First, a first embodiment of the present invention will be described with reference to FIGS. 3 to 8 and FIG.

  First step (see FIG. 3): a step of forming a channel layer of reverse conductivity type on a drain region of one conductivity type on the surface of the semiconductor substrate, and forming a trench that penetrates the channel layer and reaches the drain region.

  As shown in FIG. 3A, a semiconductor substrate 11 in which a p− type drain region 11a is provided on a p + type silicon semiconductor substrate 11b is prepared. An oxide layer (not shown) is formed on the surface of the substrate 11, a guard ring region (not shown) is formed in the periphery of the chip, and then an annular layer (not shown) is formed on the outer periphery of the chip.

  Next, an n − type diffusion layer that becomes the channel layer 12 is formed on the entire surface of the region (cell region) where the MOSFET cell is disposed by, for example, ion implantation. This is formed by forming an oxide film over the entire surface, then providing an opening in a portion to be a cell region of the oxide film, and ion-implanting phosphorus which is an n-type impurity, for example.

  Next, as shown in FIG. 3B, a trench 13 that penetrates the channel layer 12 and reaches the drain region 11a is formed. The trench 13 is formed by forming a mask (not shown) having an opening by a photolithography process in a portion that becomes a cell region of an oxide film (NSG film or the like) formed on the entire surface, and then using a CF-based gas and an HBr-based gas for the substrate 11. It is formed by anisotropic dry etching.

  Second step (FIG. 4): a step of forming an insulating film on the inner wall of the trench.

  In order to remove the defective layer due to the formation of the trench 13 in the silicon substrate 11, an oxide layer (not shown) is first formed in the trench 13 by dummy oxidation. Then, by removing the oxide film layer, the defect layer accompanying the trench formation is removed.

  Then, the entire oxide layer in the cell region is removed, and then gate oxidation is performed, thereby forming a gate insulating film 14 inside the trench 13 as shown in FIG. The gate insulating film is provided with a film thickness of several hundreds of squares depending on the driving voltage.

  Third step (FIG. 5): a step of forming a first electrode embedded in the trench.

  Next, a polycrystalline silicon film is deposited on the entire surface by CVD, thereby filling the inside of the trench 13 with polycrystalline silicon. Then, the polycrystalline silicon film is doped with a p-type impurity such as boron to make the polycrystalline silicon film conductive. Next, the polycrystalline silicon is etched back by, for example, isotropic gas etching. Then, the etching of the polycrystalline silicon is stopped at the stage where the oxide film on the surface where the gate oxide film 14 is extended is exposed, so that the first p + polysilicon buried in the trench 13 as shown in FIG. A gate electrode 15 is formed.

  Fourth step (FIG. 6): A step of forming a source region of one conductivity type on the surface of the channel layer adjacent to the trench.

  Next, as shown in FIG. 6A, first, an n + type body contact region 17 is formed in order to stabilize the potential of the substrate 11. In this process, an opening of a resist mask is formed by a photolithography process in a portion to become the body contact region 17, and, for example, phosphorus is ion-implanted to form the n + type body contact region 17.

  Next, as shown in FIG. 6B, an opening of a resist mask is formed again in a portion that becomes the source region 18 by a photolithography process, and p + type source region 18 is formed by ion implantation of, for example, boron.

  Fifth step (FIG. 7): a step of forming a second electrode on the first gate electrode.

  Next, as shown in FIG. 7A, a silicon oxide film (for example, PSG film) 19 containing an n-type impurity is deposited on the entire surface of the substrate by about 2000 mm. In this case, for example, a PSG film 19 having a P (phosphorus) concentration of 1.2 wt% to 8 wt% is formed by a CVD method. Further, the BPSG film 20 is deposited on the entire upper layer by several thousand Å. The PSG film 19 is in contact with the surface of the first gate electrode 15.

  Next, for example, heat treatment is performed at 900 ° C. for about 30 minutes to diffuse P in the PSG film to the surface of the first gate electrode 15, and as shown in FIG. A second gate electrode 16 is formed.

  Here, the source region 18 is covered with an oxide film extending from the gate oxide film 14 to the substrate surface. That is, if the second gate electrode is formed by diffusion from the PSG film 19 as in this step, the on-resistance loss can be suppressed without affecting the carrier concentration of the source region 18 due to P diffusion.

  Sixth step: (FIG. 8): A step of forming an interlayer insulating film covering at least the trench.

  Next, a mask that exposes a part of the source region 18 and the body contact region 17 on the surface of the substrate 11 is formed by a photolithography process, and an opening is provided by etching the PSG film 19 and the BPSG film 20. As a result, the interlayer insulating film 21 is formed so as to cover the first gate electrode 15 and the second gate electrode 16 in the trench 13.

  Then, a metal material such as aluminum is deposited on the entire surface of the substrate by sputtering, patterned by a photoresist process, and alloyed to form a metal electrode that becomes a source electrode on the entire surface of the cell region as shown in FIG. Layer 23 is formed. Further, a passivation film (not shown) is deposited on the entire surface of the chip, and a backing electrode (not shown) is formed on the back surface of the semiconductor substrate 11b, thereby completing a vertical MOSFET at the wafer stage.

  Next, a second embodiment of the manufacturing method of the present invention will be described with reference to FIGS.

  The second gate electrode 16 is a polysilicon layer in which impurities having a conductivity opposite to that of the first gate electrode 15 are diffused, and can also be formed by ion implantation.

  Since the first to third steps are the same as those in the first embodiment, description thereof is omitted. That is, the first gate electrode 15 embedded in the trench 13 is formed by the first to third steps as shown in FIGS. 3 to 5.

  Fourth step (FIG. 9): A step of forming a source region of one conductivity type on the surface of the channel layer adjacent to the trench.

  As shown in FIG. 9, first, an n + type body contact region 17 is formed in order to stabilize the potential of the substrate 11. In this process, an opening of a resist mask is formed by a photolithography process in a portion to become the body contact region 17, and, for example, phosphorus is ion-implanted to form the n + type body contact region 17.

  Next, a resist mask opening is formed again in a portion to be the source region 18 by a photolithography process, and p + type source region 18 is formed by ion implantation of boron, for example.

  Fifth step (FIG. 10): a step of forming a second electrode on the first gate electrode.

  Next, as shown in FIG. 10A, an n + type impurity such as phosphorus is ion-implanted over the entire surface of the first gate electrode. The ion implantation conditions at this time are set so that the depth of the ion implantation region is equal to or less than the thickness of the gate oxide film 14. This is to perform ion implantation only on the first gate electrode 15 and prevent ions from being implanted into the source region 17. As a result, loss of on-resistance is suppressed without affecting the carrier concentration of the source region 18.

  Specifically, this ion implantation condition is given by t> Rp + σ where t is the thickness of the gate oxide film 14, Rp is the projected range of ions in the gate oxide film 14, and σ is the distribution of ion distribution. . For example, when n + type impurities are phosphorus and the thickness of the gate oxide film is 600 mm, ion implantation energy of 40 KeV may be used.

  Next, as shown in FIG. 10B, a silicon oxide film (for example, PSG film) 19 containing a reverse conductivity type impurity is deposited on the entire surface of the substrate by about 2000 mm by CVD. In the case of the PSG film 19, p-type impurities can be further diffused on the first gate electrode. Further, since the ions have already been implanted, the NSG film 22 may be deposited instead of the PSG film 19. Subsequently, several thousands of BPSG film 20 is deposited by CVD.

  Next, for example, heat treatment is performed at 900 ° C. for about 30 minutes. As a result, an n + -type impurity is diffused on the first gate electrode 15 to form a second gate electrode 16 as well as a reflow heat treatment for flattening the BPSG film 20.

  Alternatively, the second gate electrode 16 may be formed by diffusing impurities by ion treatment after ion implantation, and then the PSG film 19 and the BPSG film 20 may be formed. However, since the CVD method requires a reflow process, it is preferable to perform the reflow of the BPSG film 20 and the formation of the second gate electrode 16 as described above without increasing the number of manufacturing processes.

  Sixth step: (FIG. 11): A step of forming an interlayer insulating film covering at least the trench.

  The PSG film 19 (or NSG film 22) and the BPSG film 20 deposited on the entire surface are etched by forming a mask so that a part of the source region 18 and the body contact region 17 on the substrate surface are exposed by a photolithography process. Opening is provided. Accordingly, the interlayer insulating film 21 is formed so as to cover the first gate electrode 15 and the second gate electrode 16 in the trench 13.

  Then, a metal material such as aluminum is deposited on the entire surface of the substrate by sputtering, patterned by a photoresist process, and alloyed to form a source electrode on the entire surface of the cell region as shown in FIG. The electrode layer 23 is formed. Further, a passivation film is deposited on the entire surface of the chip, and a backing electrode is formed on the back surface of the semiconductor substrate 11b, thereby completing a vertical MOSFET at the wafer stage.

  Further, as shown in FIG. 12, the body contact region 17 and the second gate electrode 16 may be formed in the same process.

  In the state where the first gate electrode 15 is formed as shown in FIG. 5 by the first to third steps, a resist mask opening is formed in a portion to become the source region 18 by a photolithography step, and boron is ion-implanted, for example. Thus, a p + type source region 18 is formed (FIG. 12A).

  Thereafter, as shown in FIG. 12B, an n + type body contact region 17 and a second gate electrode 16 for stabilizing the potential of the substrate 11 are formed simultaneously.

  First, a resist mask opening is formed on the portion to be the body contact region 17 and the first gate electrode 15 by a photolithography process. Thereafter, for example, phosphorus is ion-implanted.

  Further, as shown in FIG. 12C, the PGS film 19 (or NSG film 22) and the BPSG film 20 are deposited and reflow heat treatment is performed. As a result, the body contact region 17 is formed, and at the same time, the n + -type impurity is diffused into the polysilicon layer above the first gate electrode 15 to form the second gate electrode. Thereafter, as shown in FIG. 11, an interlayer insulating film 20 is formed.

  As described above, in the embodiment of the present invention, the p-channel type power MOSFET has been described as an example. However, it is a matter of course that an n-channel type MOSFET having a reversed conductivity type can be similarly implemented. Further, it can be applied to an IGBT in which a bipolar transistor and a power MOSFET are monolithically combined in one chip, and the same effect can be obtained.

It is sectional drawing explaining the semiconductor device of this invention, and its manufacturing method. It is a figure explaining the difference of this invention and the conventional characteristic. It is sectional drawing explaining the manufacturing method of the semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the conventional semiconductor device. It is sectional drawing explaining the manufacturing method of the conventional semiconductor device. It is sectional drawing explaining the conventional semiconductor device and its manufacturing method. It is sectional drawing explaining the manufacturing method of the conventional semiconductor device. It is sectional drawing explaining the manufacturing method of the conventional semiconductor device.

Explanation of symbols

11 semiconductor substrate 11a drain region 11b p + type silicon semiconductor substrate 12 channel layer 13 trench 14 gate oxide film 15 first gate electrode 16 second gate electrode 17 body contact region 18 source region 19 PSG film 20 BPSG film 21 interlayer insulation film 23 Source electrode 111 Semiconductor substrate 111a Drain region 111b p + type silicon semiconductor substrate 112 Channel layer 113 Trench 114 Gate oxide film 115 Gate electrode 117 Body contact region 118 Source region 120 BPSG film 121 Interlayer insulating film 122 NSG film 123 Source electrode

Claims (13)

One conductivity type semiconductor substrate;
A trench provided in the semiconductor substrate;
An insulating film covering at least the inner wall of the trench;
A first electrode embedded in the trench;
A second electrode provided on the first electrode;
One conductivity type region provided adjacent to the trench on the substrate surface;
A semiconductor device comprising: A semiconductor substrate having a drain region of one conductivity type;
A reverse conductivity type channel layer provided on the surface of the drain region;
A trench provided in the semiconductor substrate;
An insulating film covering at least the inner wall of the trench;
A first electrode embedded in the trench;
A second electrode provided on the first electrode;
A source region of one conductivity type provided adjacent to the trench on the surface of the channel layer;
A semiconductor device comprising: A semiconductor substrate having a drain region of one conductivity type;
A reverse conductivity type channel layer provided on the surface of the drain region;
A trench provided in the semiconductor substrate;
An insulating film covering at least the inner wall of the trench;
A first electrode made of a semiconductor material of one conductivity type embedded in the trench;
A second electrode made of a semiconductor material of a reverse conductivity type provided on the first gate electrode;
A source region of one conductivity type provided adjacent to the trench on the surface of the channel layer;
And a reverse conductivity type body contact region provided on the surface of the channel layer between the source regions. 4. The semiconductor device according to claim 2, further comprising a silicon oxide film containing a reverse conductivity type impurity covering at least the first and second electrodes. 4. The semiconductor device according to claim 1, wherein a joint surface between the first electrode and the second electrode is depleted. 5. The semiconductor device according to claim 1, wherein the second electrode is embedded in the trench. The semiconductor device according to claim 2, wherein the second electrode is provided at a depth less than or equal to that of the source region. Forming a trench in the surface of one conductivity type semiconductor substrate;
Forming an insulating film covering at least the inner wall of the trench;
Forming a first electrode embedded in the trench;
Forming a second electrode provided on the first electrode;
Forming one conductivity type region adjacent to the trench on the substrate surface;
A method for manufacturing a semiconductor device, comprising: Forming a reverse conductivity type channel layer on the one conductivity type drain region of the semiconductor substrate surface, and forming a trench that penetrates the channel layer and reaches the drain region;
Forming an insulating film on the inner wall of the trench;
Forming a first electrode embedded in the trench;
Forming a source region of one conductivity type on the surface of the channel layer adjacent to the trench;
Forming a second electrode on the first gate electrode;
Forming an interlayer insulating film covering at least the trench;
A method for manufacturing a semiconductor device, comprising: Forming a reverse conductivity type channel layer on the one conductivity type drain region of the semiconductor substrate surface, and forming a trench that penetrates the channel layer and reaches the drain region;
Forming an insulating film on the inner wall of the trench;
Burying a semiconductor material containing one conductivity type impurity in the trench to form a first electrode;
Forming a source region of one conductivity type on the surface of the channel layer adjacent to the trench;
Forming a second electrode of reverse conductivity type on the first electrode;
Forming an interlayer insulating film covering at least the trench;
A method for manufacturing a semiconductor device, comprising: A silicon oxide film containing a reverse conductivity type impurity is formed covering at least the first electrode, and the second electrode is formed by diffusing the reverse conductivity type impurity above the first electrode. 11. The method for manufacturing a semiconductor device according to claim 9, wherein the semiconductor device is manufactured. 11. The method of manufacturing a semiconductor device according to claim 8, wherein the second electrode is formed by diffusing a reverse conductivity type impurity on the upper portion of the first electrode. 11. 13. The method of manufacturing a semiconductor device according to claim 12, wherein the reverse conductivity type impurity is ion-implanted under a condition that a depth of the implantation region of the reverse conductivity type impurity is equal to or less than the thickness of the insulating film.

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