JP2005116649A - Vertical gate semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a vertical gate semiconductor device forming a source region and a body contact region without using a resist pattern, capable of conducting a miniaturization without increasing the contact resistance of the source region. <P>SOLUTION: The vertical gate semiconductor device has a silicon substrate 100, a semiconductor layer 110 composed of a drain region 111 and well regions 112, a vertical type gate electrode 120, an insulating film 130, and insulating substances 140. The semiconductor device further has an aluminum film 150 brought into contact with the source region 113 on side faces of trench grooves and brought into contact with the body contact region 114 on side faces of the trench grooves and the surface of the semiconductor layer 110 and a barrier metal 160. The well region 112 has the first conductivity type source regions 113 formed at a region not contacted with the surface of the semiconductor layer 110 on the side wall of the trench groove in the upper section of the well region 112, and the second conductivity type body contact region 114 formed on the surface of the semiconductor layer 110 in the upper section of the well region 112. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having a vertical gate electrode and a method for manufacturing the same.

  In recent years, with the reduction in power consumption, higher functionality, and higher speed in electronic devices, the accompanying semiconductor devices are also required to have lower power consumption and higher speed. In general, a semiconductor device used in a DC-DC converter of an electronic device is also required to have a small on-resistance characteristic of a transistor in order to meet these requirements. One way to reduce the on-resistance of a transistor is to increase the density of transistors arranged per unit area. Specifically, the gate electrode of the semiconductor device is arranged in the vertical direction. As a semiconductor device to which this method is applied, there is a vertical gate semiconductor device. This is a semiconductor device in which a gate electrode is arranged in a vertical direction, a source region is formed so as to face the top of the gate electrode, and a drain region is formed so as to face the bottom of the gate electrode.

  By the way, in the vertical gate semiconductor device, since the gate electrode is arranged vertically, the uppermost surface of the vertical gate electrode and the silicon surface where the source region exists are on the same plane. For this reason, when connecting an electrode to the source region or body contact region, the upper part of the vertical gate electrode must be covered with a convex insulating film to prevent conduction between the source region or body contact region and the vertical gate electrode. There is a problem that must be.

  As a prior art for solving such a problem, there is a technique described in Patent Document 1. In the vertical gate semiconductor device arranged in parallel, by retreating the uppermost surface of the vertical gate electrode from the silicon surface where the source region exists, and filling the insulating film on the vertical gate electrode, It solves the above problems.

Hereinafter, a conventional vertical gate semiconductor device will be described with reference to FIG.
As shown in the sectional view of the vertical gate semiconductor device in FIG. 17, the vertical gate semiconductor device includes a silicon substrate 1700 that is a first conductivity type semiconductor substrate, and a semiconductor layer 1710 formed on the silicon substrate 1700. The vertical gate electrode 1720 is formed in the trench groove of the semiconductor layer 1710 and the uppermost surface is below the surface of the semiconductor layer 1710 where the source region 1713 exists, and the insulating film filled in the upper part of the vertical gate electrode 1720 1730, a vertical gate electrode 1720, a drain region 1711, a well region 1712, and a source region 1713 are all composed of an insulating material 1740 adjacent to the vertical surface, an aluminum film 1750 as a wiring material, and a barrier metal 1760. Is done.

  Here, the semiconductor layer 1710 includes a first conductivity type drain region 1711 formed on the silicon substrate 1700 by an epitaxial growth method, and a second conductivity type well having a polarity opposite to the first conductivity type formed above the drain region 1711. The well region 1712 includes a first conductivity type source region 1713 and a second conductivity type body contact region 1714 formed on the surface of the semiconductor layer 1710 above the well region 1712.

In addition, the upper portion of the vertical gate electrode 1720 is opposed to the source region 1713 and the bottom portion of the vertical gate electrode 1720 is opposed to the drain region 1711.
In the vertical gate semiconductor device having the above configuration, the insulating film 1730 prevents conduction between the source region 1713 or the body contact region 1714 and the vertical gate electrode 1720, so that an electrode is formed in the source region or the body contact region. The step of covering the upper part of the vertical gate electrode with an insulating film, which is performed at the time of connection, can be omitted. In addition, since the top surface of the insulating film 1730 and the silicon surface where the source region 1713 exists are substantially on the same plane and have a flat surface with respect to the mask process, the vertical gate semiconductor device is manufactured. Can be facilitated.
Japanese Patent No. 266221

However, in the conventional technique described in Patent Document 1, since the source region and the body contact region are both formed on the surface of the semiconductor layer, two different resist mask patterns are used in forming the source region and the body contact region. There is a problem that each region must be formed by using.
In the prior art described in Patent Document 1, when the distance between the vertical gate electrodes is shortened along with the downsizing of the vertical gate semiconductor device, the contact area between the electrode and the source region is reduced, and the contact resistance is reduced. There is a problem of increasing. At this time, since the body contact region is in a relation of inversion of the source region, the contact area between the electrode and the source region can be increased by reducing the area of the body contact region, but the area of the body contact region is reduced. As a result, the well region cannot be grounded, and a new problem arises that the parasitic bipolar transistor becomes easy to operate. For example, in a vertical gate semiconductor device in which vertical gate electrodes having a width of 0.2 μm are arranged at intervals of 0.2 μm, when an interval between the vertical gate electrodes is to be shortened by 0.1 μm, Is 0.1 μm, and the source region formed here is very small.

In view of the above problems, it is a first object of the present invention to provide a vertical gate semiconductor device capable of forming a source region and a body contact region without using a resist pattern, and a manufacturing method thereof. .
It is a second object of the present invention to provide a vertical gate semiconductor device that can be reduced in size without increasing the contact resistance of the source region, and a method for manufacturing the same.

  In order to achieve the above object, a vertical gate semiconductor device of the present invention has a trench groove, a semiconductor layer formed on a semiconductor substrate, a gate oxide film formed on the inner wall of the trench groove, and the trench A vertical gate semiconductor device comprising a gate electrode embedded in a trench, wherein the semiconductor layer has a drain region of a first conductivity type, and is opposite to the first conductivity type formed above the drain region. The trench groove penetrates the well region, the well region has an overlap with the gate electrode, and does not contact the surface of the semiconductor layer on the side wall of the trench groove. A source region of the first conductivity type formed in a region; and a body contact region of a second conductivity type formed on the surface of the semiconductor layer in contact with the source region. To. The present invention also includes a well region and a drain region having a body contact region and a source region, having a trench groove, a semiconductor layer formed on a semiconductor substrate, and a gate oxide formed on the inner wall of the trench groove. A method for manufacturing a vertical gate semiconductor device, comprising: a film; a gate electrode embedded in the trench groove; and an insulating film formed in the trench groove on the gate electrode. Forming a drain region below the semiconductor layer, forming a well region above the semiconductor layer, and forming an insulating oxide film on the surface of the semiconductor layer where the well region is formed. And after penetrating the insulating oxide film and the well region, forming a trench groove in the semiconductor layer, forming a gate oxide film on the inner wall of the trench groove, and A second step of depositing a gate electrode material inside the trench, and a third step of forming the gate electrode by removing the gate electrode material so that a concave shape is formed above the trench groove on the surface of the semiconductor layer. A first conductivity type impurity is implanted into the trench groove in an oblique direction with respect to the surface of the semiconductor layer using the insulating oxide film as a mask, and a portion of the well region on the side wall of the trench groove is A third step of forming a source region; a fourth step of depositing an insulating film on the gate electrode; and removing the insulating oxide film to introduce an impurity of a second conductivity type opposite to the first conductivity type. And a fifth step of forming the body contact region in a part of the well region by injecting into the surface of the semiconductor layer. It may be.

  As a result, the source region and the body contact region are implanted into the trench groove obliquely with respect to the surface of the semiconductor layer by implanting the first conductivity type impurity using the insulating oxide film for forming the trench groove as a mask. A vertical gate semiconductor device capable of forming a source region and a body contact region without using a resist pattern and a method of manufacturing the same are realized because it is formed by implanting two conductivity type impurities into the surface of a semiconductor layer. Can do.

  The semiconductor layer surface has a concave shape above the trench groove, and the vertical gate semiconductor device further includes an insulating film formed in the trench groove on the gate electrode, and the body contact The region may be in contact with the electrode on the side surface of the trench groove and the surface of the semiconductor layer, and the source region may be in contact with the electrode on the side surface of the trench groove. Here, the vertical gate semiconductor device further includes electrodes formed in the trench groove and on the surface of the semiconductor layer, and the manufacturing method of the vertical gate semiconductor device further includes the trench on the surface of the semiconductor layer. A sixth step of removing the insulating film so that a concave shape is formed in the upper part of the trench and the source region of the trench trench sidewall is exposed; and the trench trench sidewall and the surface of the semiconductor layer that appear by the removal And depositing an electrode member to form an electrode inside the trench and on the surface of the semiconductor layer.

  This ensures a sufficient contact area between the electrode and the source region without reducing the area of the body contact region even when the distance between the gate electrodes is reduced along with the downsizing of the vertical gate semiconductor device. Therefore, a vertical gate semiconductor device that can be downsized without increasing the contact resistance of the source region can be realized. At the same time, since a sufficient contact area between the electrode and the body contact region can be ensured, a vertical gate semiconductor device that suppresses the operation of the parasitic bipolar transistor and a manufacturing method thereof can be realized.

  According to the vertical gate semiconductor device of the present invention, the source region and the body contact region are inclined with respect to the surface of the semiconductor layer by using the insulating oxide film for forming the trench groove as a mask. After being implanted into the trench groove, an impurity of the second conductivity type opposite to the first conductivity type is implanted into the surface of the semiconductor layer, so that the source region and the body contact region are formed without using a resist pattern. The effect is that a vertical gate semiconductor device that can be realized can be realized. Further, according to the vertical gate semiconductor device of the present invention, the electrode and the source can be obtained without reducing the area of the body contact region even if the distance between the gate electrodes is reduced due to the downsizing of the vertical gate semiconductor device. Since a sufficient contact area with the region can be secured, there is an effect that a vertical gate semiconductor device that can be downsized without increasing the contact resistance of the source region can be realized. . In addition, according to the vertical gate semiconductor device of the present invention, a sufficient contact area between the electrode and the body contact region can be ensured, so that occurrence of a voltage difference in the well that may occur during transistor operation is suppressed. Thus, the vertical gate semiconductor device that suppresses the operation of the parasitic bipolar transistor can be realized.

  Therefore, according to the present invention, it is possible to provide a vertical gate semiconductor device in which a source region and a body contact region can be formed without using a resist pattern, and the size can be reduced without increasing the contact resistance of the source region. It becomes possible and its practical value is extremely high.

Hereinafter, a vertical gate semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a cross-sectional view of the vertical gate semiconductor device of the present embodiment.
The vertical gate semiconductor device of this embodiment forms a source region and a body contact region without using a resist pattern, and can be downsized without increasing the contact resistance of the source region. An object of the present invention is to realize a device, which is formed in a silicon substrate 100 which is a first conductivity type semiconductor substrate, a semiconductor layer 110 formed on the silicon substrate 100, and a trench groove in the semiconductor layer 110. A vertical gate electrode 120 whose uppermost surface is below the surface of the semiconductor layer 110 where the body contact region 114 exists, and a semiconductor whose uppermost surface is present on the body contact region 114. An insulating film 130 below the surface of the layer 110 and a vertical gate electrode 120 are formed, and the drain An insulating material 140 which region 111 and the well region 112 adjacent to the vertical surface composed of aluminum film 150 and the barrier metal 160. as a wiring material.

  Here, the semiconductor layer 110 has a first conductivity type drain region 111 formed in the silicon substrate 100 by an epitaxial growth method and a trench having a polarity opposite to that of the first conductivity type formed above the drain region 111. The well region 112 includes a second conductive type well region 112, and the well region 112 has an overlap on the vertical gate electrode 120 in a region not contacting the surface of the semiconductor layer 110 on the side wall of the trench groove above the well region 112. It has a first conductivity type source region 113 formed and a second conductivity type body contact region 114 formed in a region in contact with the source region 113 on the surface of the semiconductor layer 110 above the well region 112.

The aluminum film 150 is in contact with the source region 113 on the side surface of the trench groove, and is in contact with the body contact region 114 on the side surface of the trench groove and the surface of the semiconductor layer 110.
The upper part of the vertical gate electrode 120 exists so as to face the source region 113, and the bottom part of the vertical gate electrode 120 exists so as to face the drain region 111.

  Next, a method for manufacturing a vertical gate semiconductor device having the above structure will be described with reference to cross-sectional views shown in FIGS. The same elements as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted here.

First, as shown in FIG. 2, a first conductivity type epitaxial layer is formed on the silicon substrate 100, and a second conductivity type well region is formed thereon to form a drain region 111 and a well region 112. Thereafter, a silicon oxide film 200 of 50 to 500 nm is formed on the surface of the well region 112 by thermal oxidation.
Next, as shown in FIG. 3, a resist pattern 300 is formed on the silicon oxide film 200, and the silicon oxide film 200 is etched using the resist pattern 300.

  Next, as shown in FIG. 4, after removing the resist pattern 300, the well pattern 112 reaches the drain region 111 by dry etching using the patterned silicon oxide film 200 as a mask. Forms a trench groove 400 having a thickness of 0.8 to 3.0 μm. Here, the dry etching of the silicon oxide film 200 is performed so that the silicon oxide film 200 exists in a sufficient thickness on the well region 112 even after the dry etching in a portion where the silicon oxide film 200 is not dry-etched. It is.

Next, as shown in FIG. 5, in order to remove the damaged layer on the side wall and bottom of the trench groove 400, a silicon oxide film 500 having a thickness of 20 to 100 nm is formed on the inner wall of the trench groove 400 by thermal oxidation.
Next, as shown in FIG. 6, the silicon oxide film 500 on the inner wall of the trench groove 400 is removed by wet etching.

Next, as shown in FIG. 7, an insulating material 140, which is an oxide film having a thickness of 8 to 100 nm, is formed on the inner wall of the trench groove 400.
Next, as shown in FIG. 8, a polysilicon film 800 doped with a first conductivity type impurity serving as a gate electrode material is deposited in the trench groove 400 and on the surface of the silicon oxide film 200. At this time, a polysilicon film 800 is deposited on the surface of the silicon oxide film 200 with a thickness of 300 to 800 nm. The polysilicon film 800 may be doped with impurities of the first conductivity type by ion implantation and annealing after deposition, even if the impurities are not doped at the time of deposition.

  Next, as shown in FIG. 9, the surface of the silicon oxide film 200 and a part of the polysilicon film 800 inside the trench groove 400 are removed by whole surface etching, and the remaining polysilicon film 800 is used as the vertical gate electrode 120. . Here, the etching of the polysilicon film 800 inside the trench 400 is performed from the surface of the silicon oxide film 200 to 200 to 800 nm below.

  Next, as shown in FIG. 10, the first conductivity type is obliquely formed with respect to the surface of the silicon oxide film 200 (in the direction of the arrow in the figure) so that the first conductivity type impurity is implanted into the well region 112. The first conductivity type source region 113 having an overlap on the upper part of the vertical gate electrode 120 is formed on the sidewall of the trench groove 400 by injecting the impurity. At this time, since the surface of the well region 112 is masked by the silicon oxide film 200, the first conductivity type impurity is not implanted into the surface of the well region 112, and the source region 113 is not formed. Note that the source region 113 may be formed not by ion implantation but by vapor phase diffusion.

  Next, as shown in FIG. 11, a silicon oxide film 1100 is deposited with a thickness of 400 to 800 nm on the vertical gate electrode 120 inside the trench groove 400 and on the surface of the silicon oxide film 200.

  Next, as shown in FIG. 12, the silicon oxide films 200, 1100 are formed until the top surface of the silicon oxide film 1100 above the vertical gate electrode 120 and the surface of the well region 112 coincide with each other by planarization etchback using a resist. Remove. As a result, the trench trench 400 is filled with the silicon oxide film 1100 and the vertical gate electrode 120. Note that the silicon oxide films 200 and 1100 may be removed by other planarization methods including a CMP method instead of the planarization etchback using a resist. In the planarization etchback, a silicon oxide film 200 having a thickness smaller than that of the silicon oxide film 1100 remaining on the vertical gate electrode 120 may remain on the surface of the well region 112.

  Next, as shown in FIG. 13, a body contact region 114 is formed by implanting a second conductivity type impurity into the surface of the well region 112 (injection in the direction of the arrow in FIG. 13). At this time, since the silicon oxide film 1100 is formed on the vertical gate electrode 120, the second conductivity type impurity is not implanted into the vertical gate electrode 120. The body contact region 114 may be formed not by ion implantation but by vapor phase diffusion.

  Next, as shown in FIG. 14, a silicon oxide film 1400 to be an interlayer insulating film is deposited on the surface of the well region 112 to a thickness of 500 to 1000 nm, and then a resist pattern 1410 is formed on the silicon oxide film 1400. To do.

  Next, as shown in FIG. 15, the silicon oxide film 1400 is dry-etched using a resist pattern 1410 to form a contact hole, and then a part of the silicon oxide film 1100 above the vertical gate electrode 120 is formed by dry etching. Then, a part of the insulating material 140 is removed, and the insulating film 130 is formed. Here, in the etching of the silicon oxide film 1100 and the insulating material 140 on the vertical gate electrode 120, the trench groove 400 portion is concaved on the surface of the well region 112, and the source region 113 on the sidewall of the trench groove 400 is exposed. In other words, the process is performed from the surface of the well region 112 to 100 to 300 nm below.

Next, as shown in FIG. 16, an aluminum film 150 and a barrier metal 160 are deposited and patterned on the surface of the silicon oxide film 1400, the source region 113 of the well region 112, the surface of the body contact region 114, and the surface of the insulating film 130. .
As described above, according to the vertical gate semiconductor device of the present embodiment, the body contact region 114 is formed on the surface of the semiconductor layer 110, and the source region 113 is formed in a region not in contact with the surface of the semiconductor layer 110 on the side wall of the trench. The Therefore, after the impurity of the first conductivity type is implanted into the trench groove obliquely with respect to the surface of the semiconductor layer using the insulating oxide film for forming the trench groove as a mask, the second conductivity opposite to the first conductivity type is then obtained. Since the source region and the body contact region can be formed by injecting the impurity of the type into the surface of the semiconductor layer, the vertical gate semiconductor device of this embodiment has the source region and the body contact region without using a resist pattern. It is possible to realize a vertical gate semiconductor device capable of forming

  Further, according to the vertical gate semiconductor device of this embodiment, the source region 113 is in contact with the electrode on the side surface of the trench groove. Therefore, even if the distance between the vertical gate electrodes becomes shorter as the vertical gate semiconductor device becomes smaller, a sufficient contact area between the electrode and the source region is ensured without reducing the area of the body contact region. Therefore, the vertical gate semiconductor device of this embodiment can realize a vertical gate semiconductor device that can be reduced in size without increasing the contact resistance of the source region. At the same time, since the body contact region is in contact with the electrode on the surface of the semiconductor layer where the source region is not formed, a sufficient contact area between the electrode and the body contact region can be ensured, so that the vertical gate of this embodiment The semiconductor device can suppress the occurrence of a voltage difference in the well that may occur during transistor operation, and can realize a vertical gate semiconductor device that suppresses the operation of a parasitic bipolar transistor.

  The present invention can be used for a vertical gate semiconductor device, and in particular, can be used for electronic equipment such as a DC-DC converter.

It is sectional drawing of the vertical gate semiconductor device of embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the vertical gate semiconductor device of the embodiment. It is sectional drawing for demonstrating the manufacturing method of the vertical gate semiconductor device of the embodiment. It is sectional drawing for demonstrating the manufacturing method of the vertical gate semiconductor device of the embodiment. It is sectional drawing for demonstrating the manufacturing method of the vertical gate semiconductor device of the embodiment. It is sectional drawing for demonstrating the manufacturing method of the vertical gate semiconductor device of the embodiment. It is sectional drawing for demonstrating the manufacturing method of the vertical gate semiconductor device of the embodiment. It is sectional drawing for demonstrating the manufacturing method of the vertical gate semiconductor device of the embodiment. It is sectional drawing for demonstrating the manufacturing method of the vertical gate semiconductor device of the embodiment. It is sectional drawing for demonstrating the manufacturing method of the vertical gate semiconductor device of the embodiment. It is sectional drawing for demonstrating the manufacturing method of the vertical gate semiconductor device of the embodiment. It is sectional drawing for demonstrating the manufacturing method of the vertical gate semiconductor device of the embodiment. It is sectional drawing for demonstrating the manufacturing method of the vertical gate semiconductor device of the embodiment. It is sectional drawing for demonstrating the manufacturing method of the vertical gate semiconductor device of the embodiment. It is sectional drawing for demonstrating the manufacturing method of the vertical gate semiconductor device of the embodiment. It is sectional drawing for demonstrating the manufacturing method of the vertical gate semiconductor device of the embodiment. It is sectional drawing of the conventional vertical gate semiconductor device.

Explanation of symbols

100, 1700 Silicon substrate 110, 1710 Semiconductor layer 111, 1711 Drain region 112, 1712 Well region 113, 1713 Source region 114, 1714 Body contact region 120, 1720 Vertical gate electrode 130, 1730 Insulating film 140, 1740 Insulating material 150, 1750 Aluminum film 160, 1760 Barrier metal 200, 500, 1100, 1400 Silicon oxide film 300, 1410 Resist pattern 400 Trench groove 800 Polysilicon film

Claims (4)

A vertical gate semiconductor device having a trench groove, comprising a semiconductor layer formed on a semiconductor substrate, a gate oxide film formed on the inner wall of the trench groove, and a gate electrode embedded in the trench groove. And
The semiconductor layer includes a first conductivity type drain region and a second conductivity type well region opposite to the first conductivity type formed above the drain region;
The trench groove penetrates the well region,
The well region has an overlap with the gate electrode, and is in contact with the source region, the source region of the first conductivity type formed in a region not in contact with the surface of the semiconductor layer on the sidewall of the trench groove, and the semiconductor A vertical gate semiconductor device comprising: a body contact region of a second conductivity type formed on the surface of the layer. The semiconductor layer surface has a concave shape at the top of the trench groove,
The vertical gate semiconductor device further includes:
An insulating film formed in the trench groove on the gate electrode;
The body contact region is in contact with the electrode at the trench groove side surface and the semiconductor layer surface,
The vertical gate semiconductor device according to claim 1, wherein the source region is in contact with the electrode on a side surface of the trench. A well region having a body contact region and a source region and a drain region, having a trench groove, a semiconductor layer formed on a semiconductor substrate, a gate oxide film formed on the inner wall of the trench groove, and the trench groove A method of manufacturing a vertical gate semiconductor device comprising a gate electrode embedded therein and an insulating film formed inside the trench groove on the gate electrode,
After forming the semiconductor layer on the semiconductor substrate, a drain region is formed below the semiconductor layer, the well region is formed above, and an insulating oxide film is formed on the surface of the semiconductor layer where the well region is formed. A first step;
A second step of penetrating the insulating oxide film and the well region, forming a trench groove in the semiconductor layer, forming a gate oxide film on an inner wall of the trench groove, and depositing a gate electrode material in the trench groove; ,
A third step of removing the gate electrode material so as to form a concave shape above the trench groove on the surface of the semiconductor layer and forming a gate electrode;
Impurities of the first conductivity type are implanted into the trench groove in an oblique direction with respect to the surface of the semiconductor layer using the insulating oxide film as a mask, and the source region is formed in a part of the well region on the trench groove side wall. A third step of forming;
A fourth step of depositing an insulating film on the gate electrode;
A fifth step of removing the insulating oxide film and implanting a second conductivity type impurity opposite to the first conductivity type into the surface of the semiconductor layer to form the body contact region in a part of the well region. A method of manufacturing a vertical gate semiconductor device. The vertical gate semiconductor device further includes an electrode formed in the trench groove and on the surface of the semiconductor layer,
The method for manufacturing the vertical gate semiconductor device further includes:
A sixth step of removing the insulating film so that a concave shape is formed in the upper portion of the trench groove on the surface of the semiconductor layer and the source region of the sidewall of the trench groove is exposed;
7. A seventh step of depositing an electrode member on the side wall of the trench groove and the surface of the semiconductor layer appearing by the removal, and forming an electrode inside the trench groove and on the surface of the semiconductor layer. The manufacturing method of the vertical gate semiconductor device of description.

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