CN113972265A - Method for improving LDMOS (laterally diffused metal oxide semiconductor) process technology of strip field plate - Google Patents
Method for improving LDMOS (laterally diffused metal oxide semiconductor) process technology of strip field plate Download PDFInfo
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- CN113972265A CN113972265A CN202010718128.7A CN202010718128A CN113972265A CN 113972265 A CN113972265 A CN 113972265A CN 202010718128 A CN202010718128 A CN 202010718128A CN 113972265 A CN113972265 A CN 113972265A
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- field plate
- oxide layer
- ldmos
- improving
- depositing
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- 238000000034 method Methods 0.000 title claims abstract description 62
- 230000008569 process Effects 0.000 title claims abstract description 33
- 229910044991 metal oxide Inorganic materials 0.000 title description 2
- 150000004706 metal oxides Chemical class 0.000 title description 2
- 239000004065 semiconductor Substances 0.000 title description 2
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 18
- 238000000151 deposition Methods 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 230000002035 prolonged effect Effects 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 230000004075 alteration Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
Abstract
The invention relates to a method for improving an LDMOS process technology of a strip field plate, which comprises the following steps: providing a substrate and forming a grid electrode on the substrate; depositing a first oxide layer on the grid; depositing a field plate on the first oxide layer; depositing a second oxide layer on the field plate; covering a photoresist on the second oxide layer, developing, and etching the second oxide layer; etching the field plate; forming the LDMOS with a field plate. Through the method for improving the LDMOS process technology of the strip field plate, the problem of too large step height of the field plate is solved by depositing or adding the oxide layer after the field plate is deposited, and the added oxide layer can be used as a hard mask to protect the region of the field plate needing to be left, so that the etching time can be prolonged to ensure that no residue exists.
Description
Technical Field
The present invention relates to an improvement of an LDMOS process, and more particularly, to a method of improving an LDMOS process of a strip field plate.
Background
At present, different from the conventional LDMOS, the source-drain region electric field when the channel is opened can be reduced by matching the field plate technology in the LDMOS process requirements, so that the breakdown voltage is improved. In the LDMOS with a field plate, in the prior art, an oxide layer is usually deposited as an isolation layer after a gate is defined, then the field plate is deposited, and then the field plate is directly etched after photoresist development is performed on the field plate to obtain the LDMOS with the field plate.
Referring to fig. 1, fig. 1 illustrates the prior art situation in more detail: fig. 1 shows a schematic outline of an LDMOS with a field plate prepared by a conventional process, as shown in the figure, after the field plate 4 is etched, a residual field plate 5 left without being etched is left between two gates 2, which may cause defects shown in the residual field plate 5, mainly, after an oxide layer 3 is deposited, a deep recess may be generated, which may cause a residual photoresist to become a mask (mask) during a subsequent etching process because the recess is deep and narrow and the photoresist is not easily removed during a photoresist developing process, so that the residual photoresist may not be removed during the subsequent etching process, and the field plate/oxide layer/gate underneath may not be etched during the subsequent etching process, so that the residual field plate/oxide layer/gate remains to become a defect.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide a method for improving the LDMOS process technology of a strip field plate, the invention deposits an oxide layer on the field plate after the field plate is deposited so as to improve the problem of too large step height of the field plate, then covers a photoresist on the oxide layer and develops the photoresist according to the required area, and then etches the oxide layer deposited again on the field plate firstly and then etches the field plate, thereby completely etching the field plate and realizing no residue of the field plate between grids.
In order to solve the technical problems, the invention adopts the following technical scheme:
according to an aspect of the present invention, there is provided a method for improving an LDMOS process of a strip field plate, the method comprising the steps of:
(1) providing a substrate and forming a grid electrode on the substrate;
(2) depositing a first oxide layer on the grid;
(3) depositing a field plate on the first oxide layer;
(4) depositing a second oxide layer on the field plate;
(5) covering a photoresist on the second oxide layer, developing, and etching the second oxide layer;
(6) etching the field plate;
(7) forming the LDMOS with a field plate.
In one embodiment of the present invention, the substrate in step (1) is made of a silicon, germanium or silicon carbide material.
In one embodiment of the present invention, the gate formed in step (1) is a polysilicon gate (poly gate), wherein the gate comprises a gate polysilicon layer and a gate silicon oxide layer under the gate polysilicon layer.
In one embodiment of the invention, the number of the grid electrodes is two or more, and the grid electrodes are distributed on the substrate at intervals.
In one embodiment of the present invention, the thickness of the first oxide layer in step (2) is
In one embodiment of the invention, the field plate in step (3) is made of polysilicon (poly).
In one embodiment of the present invention, the thickness of the second oxide layer in step (4) is
In one embodiment of the invention, the second oxide layer has a thickness of
In one embodiment of the present invention, a step of removing the photoresist is further included between step (6) and step (7).
According to another aspect of the present invention, there is provided an LDMOS with a band field plate manufactured by the above-mentioned improved LDMOS with a band field plate manufacturing method.
By adopting the technical scheme, compared with the prior art, the invention has the following advantages:
in the method for improving the LDMOS process technology of the strip field plate, the invention redeposits or adds the oxide layer on the field plate after the field plate is deposited, thereby improving the problem of too large step height of the field plate, the added oxide layer can be used as a hard mask to protect the region of the field plate needing to be left, and the etching time can be prolonged so as to ensure that no residue exists.
Drawings
The above and/or additional aspects and advantages of the present invention will become more apparent and readily appreciated from the following description of the embodiments taken in conjunction with the accompanying drawings, in which:
fig. 1 shows a schematic diagram of the LDMOS with a field plate prepared by a conventional process;
FIG. 2 is a schematic diagram of the LDMOS profile of the strip field plate according to the present invention to meet the process requirements;
FIG. 3 is a flow chart of a method of improving LDMOS process of the strip field plate according to the present invention;
fig. 4 is a schematic diagram of an LDMOS process for an improved strip field plate according to the present invention.
Description of the reference numerals
1 substrate, 2 grid, 3 first oxide layer, 4 field plate, 5 residual field plate, 6 second oxide layer and 7 photoresist
Detailed Description
It should be understood that the embodiments of the invention shown in the exemplary embodiments are illustrative only. Although only a few embodiments of the present invention have been described in detail above, those skilled in the art will readily appreciate that many modifications are possible without materially departing from the teachings of the present subject matter. Accordingly, all such modifications are intended to be included within the scope of this invention. Other substitutions, modifications, changes and omissions may be made in the design, operating conditions and parameters and the like of the following exemplary embodiments without departing from the spirit of the present invention.
The invention provides a method for improving an LDMOS process technology of a strip field plate, which comprises the following steps: providing a substrate and forming a grid electrode on the substrate; depositing a first oxide layer on the grid; depositing a field plate on the first oxide layer; depositing a second oxide layer on the field plate; covering a photoresist on the second oxide layer, developing, and etching the second oxide layer; etching the field plate; forming the LDMOS with a field plate.
In the above manufacturing method, the substrate is made of a silicon, germanium, or silicon carbide material.
In the above manufacturing method, the formed gate is a polysilicon gate, wherein the gate includes a gate polysilicon layer and a gate silicon oxide layer under the gate polysilicon layer.
In the above manufacturing method, the number of the gates is two or more, and the gates are distributed on the substrate at intervals.
In the above preparation method, the thickness of the first oxide layer is
In the above fabrication method, the field plate is made of polysilicon.
In the above preparation method, the thickness of the second oxide layer is
Preferably, the second oxide layer has a thickness of
In the above manufacturing method, the method further includes a step of removing the photoresist.
In addition, the invention also provides the LDMOS with the field plate, which is prepared by adopting the method for improving the LDMOS process technology of the field plate.
The technical solution of the present invention will be described in detail with reference to the accompanying fig. 2 to 4.
Referring to fig. 2, fig. 2 is a schematic diagram of a profile of the LDMOS of the strip field plate according to the present invention, which meets the requirements of the manufacturing process, that is, the LDMOS of the strip field plate prepared by the improved process/method of the present invention has no field plate residue between the gates 2, that is, there is no residual field plate 5 between the gates 2 in fig. 1, compared with the LDMOS of the strip field plate prepared by the conventional preparation process of fig. 1.
Referring to fig. 3-4, fig. 3 and 4 are a flow chart and a schematic diagram of a method for improving the LDMOS process of the strip field plate according to the present invention. The method 300 of the present invention starts at block 301, where a substrate 1 is provided and a gate 2 is formed on the substrate 1, then proceeds to block 302, where the step of depositing a first oxide layer 3 on the gate 2 is performed, then proceeds to block 303, completing the deposition of a field plate 4 on the first oxide layer 3, the method 300 proceeds to block 304, depositing a second oxide layer 6 on the field plate 4, then to block 305, covering the second oxide layer 6 with a photoresist 7 and developing, etching the second oxide layer 6, then to block 306, etching the field plate 4, and finally to block 307, removing the photoresist 7 to obtain a desired LDMOS with field plate.
The invention is improved on the basis of the existing LDMOS process technology, an oxide layer is deposited on the field plate after the field plate is deposited so as to solve the problem that the step height of the field plate is too large, then, aiming at the required area, a photoresist is covered on the oxide layer and is developed, then, the oxide layer deposited on the field plate again is etched, and then, the field plate is etched. In the improved process or method, the invention improves the problem that the step height of the field plate is too large by depositing or adding an oxide layer on the field plate after the field plate is deposited, and the added oxide layer can be used as a hard mask to protect the region of the field plate needing to be left, so that the etching time can be prolonged to ensure that no residue exists.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; it is intended that the following claims be interpreted as including all such alterations, modifications, and equivalents as fall within the true spirit and scope of the invention.
Claims (10)
1. A method for improving LDMOS process technology of a strip field plate is characterized by comprising the following steps:
(1) providing a substrate and forming a grid on the substrate;
(2) depositing a first oxide layer on the grid;
(3) depositing a field plate on the first oxide layer;
(4) depositing a second oxide layer on the field plate;
(5) covering a photoresist on the second oxide layer, developing, and etching the second oxide layer;
(6) etching the field plate;
(7) forming the LDMOS with a field plate.
2. The method for improving the LDMOS process of claim 1, wherein the substrate in step (1) is made of a silicon, germanium or silicon carbide material.
3. The method of claim 1, wherein the gate formed in step (1) is a polysilicon gate, wherein the gate comprises a gate polysilicon layer and a gate silicon oxide layer under the gate polysilicon layer.
4. The method for improving LDMOS process of claim 1, wherein the number of the gates is two or more, and the gates are distributed on the substrate at intervals.
5. The method for improving LDMOS process of claim 1, wherein the first oxide layer in step (2) has a thickness of
6. The method for improving LDMOS process of claim 1, wherein the field plate in step (3) is made of polysilicon.
7. The method for improving LDMOS process of claim 1, wherein the thickness of the second oxide layer in step (4) is set to be equal to
8. The method of claim 7, wherein the thickness of the second oxide layer is set to be
9. The method for improving the LDMOS process of the strip field plate as claimed in claim 1, further comprising a step of removing the photoresist between the step (6) and the step (7).
10. An LDMOS with a strip field plate manufactured by the method for improving the LDMOS process of a strip field plate as claimed in any one of the claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010718128.7A CN113972265B (en) | 2020-07-23 | 2020-07-23 | Method for improving LDMOS (laterally diffused metal oxide semiconductor) manufacturing process with field plate |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010718128.7A CN113972265B (en) | 2020-07-23 | 2020-07-23 | Method for improving LDMOS (laterally diffused metal oxide semiconductor) manufacturing process with field plate |
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| CN113972265A true CN113972265A (en) | 2022-01-25 |
| CN113972265B CN113972265B (en) | 2023-07-04 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020072159A1 (en) * | 2000-12-07 | 2002-06-13 | Eiji Nishibe | Semiconductor device and manufacturing method thereof |
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| US20180219093A1 (en) * | 2014-11-25 | 2018-08-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methodology and structure for field plate design |
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| CN111063737A (en) * | 2019-11-25 | 2020-04-24 | 上海华虹宏力半导体制造有限公司 | LDMOS device and technological method |
| CN111092123A (en) * | 2019-12-10 | 2020-05-01 | 杰华特微电子（杭州）有限公司 | Lateral double-diffused transistor and manufacturing method thereof |
| CN111200006A (en) * | 2018-11-19 | 2020-05-26 | 无锡华润上华科技有限公司 | Lateral double-diffusion metal oxide semiconductor field effect transistor and preparation method thereof |
-
2020
- 2020-07-23 CN CN202010718128.7A patent/CN113972265B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20020072159A1 (en) * | 2000-12-07 | 2002-06-13 | Eiji Nishibe | Semiconductor device and manufacturing method thereof |
| CN101777497A (en) * | 2010-01-12 | 2010-07-14 | 上海宏力半导体制造有限公司 | Production method of power MOS field-effect tube |
| US20150048448A1 (en) * | 2013-08-15 | 2015-02-19 | Vanguard International Semiconductor Corporation | Semiconductor device and method for forming the same |
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| US20180219093A1 (en) * | 2014-11-25 | 2018-08-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methodology and structure for field plate design |
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